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JHDL - http://www.jhdl.org/
JHDL is a method of describing (programmatically, in JAVA) the components and connections in a digital logic circuit. |
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RHDL - http://www.aracnet.com/~ptkwt/ruby_stuff/RHDL/
RHDL (Ruby Hardware Description Language) is an HDL based on the Ruby programming language. |
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MyHDL - http://www.jandecaluwe.com/Tools/MyHDL/Overview.html
MyHDL is a Python package for using Python as a hardware description and verification language. |
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Hydra Computer HDL - http://www.dcs.gla.ac.uk/~jtod/Hydra/
Hydra is an HDL based on the functional programming language Haskell. |
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Perlilog - http://www.opencores.org/projects.cgi/web/perlilog/overview
As the name implies, Perilog uses a mix of Perl and Verilog to construct parametric hardware designs. |