CA1052463A - Spc telecommunication system - Google Patents
Spc telecommunication systemInfo
- Publication number
- CA1052463A CA1052463A CA228,756A CA228756A CA1052463A CA 1052463 A CA1052463 A CA 1052463A CA 228756 A CA228756 A CA 228756A CA 1052463 A CA1052463 A CA 1052463A
- Authority
- CA
- Canada
- Prior art keywords
- instruction
- register
- address
- registers
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/223—Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/226—Microinstruction function, e.g. input/output microinstruction; diagnostic microinstruction; microinstruction format
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
Abstract
ABSTRACT OF THE DISCLOSURE
A Stored Program Controlled telecommunication system comprises test points, operating points,data storage registers connected to each other through a data bus, a phase generator and an access signal generator. The registers include instruction registers for storage of instructions, and an address register for storage of address numbers identifying the instructions. The address register is provided with a stepping input for raising its content with one unit. The phase generator produces phase signals by which the processing cycles of the instructions are divided into phases. The access signal generator is controlled by the phase signal, the address numbers and the instructions. For producing access signals in order to control the test points, operating points and registers, the access signal generator includes logic arrangements. A first logic decodes the content of the address register during the beginning phase of the respective cycle and accesses the instruction register associated with the respective address number during the other phases of the cycle. A second logic activates the stepping input during a middle phase of each cycle. A third logic allows transfer of an address number from one of the registers to the address register only during the end phase of the respective cycle.
A fourth logic carrying out an AND-function has its inputs activated during the end phase of a cycle for accessing one of the test points and by the one binary state of this test point, and its output connected to the stepping input.
A Stored Program Controlled telecommunication system comprises test points, operating points,data storage registers connected to each other through a data bus, a phase generator and an access signal generator. The registers include instruction registers for storage of instructions, and an address register for storage of address numbers identifying the instructions. The address register is provided with a stepping input for raising its content with one unit. The phase generator produces phase signals by which the processing cycles of the instructions are divided into phases. The access signal generator is controlled by the phase signal, the address numbers and the instructions. For producing access signals in order to control the test points, operating points and registers, the access signal generator includes logic arrangements. A first logic decodes the content of the address register during the beginning phase of the respective cycle and accesses the instruction register associated with the respective address number during the other phases of the cycle. A second logic activates the stepping input during a middle phase of each cycle. A third logic allows transfer of an address number from one of the registers to the address register only during the end phase of the respective cycle.
A fourth logic carrying out an AND-function has its inputs activated during the end phase of a cycle for accessing one of the test points and by the one binary state of this test point, and its output connected to the stepping input.
Description
The present invention relates to a SPC (Stored Program Controlled) telecommunication sys~em in which test points, opera-ting points and data storage registers which are connected to each other through a data bus are controlled by means of access -~
signals that are produced in accordance with control instructions identified by means of instruction address numbers. In the system, the execution of a control function consists of a number of sequentially processed control instructions being initiated by the aid of a start instruction address number associated with the first control instruction of the control function, the start instruction address number being stored in one of the data storage registers of the telecommunication system. , Known SPC telecommunication systems, as for example "D-10 Electronic Switching System", published in the journal "Japan Telecommunications Review - Vol. 13: No~ 3 and 4 and Vol. 14: No. 1", consist of an exchange and a computer. The ;
computer is formed by a memory part and by a processor. The memory part comprises a program store, a data store and registers which form a transfer unit that stores the operation instructions received from the computer for transferring to the exchange and stores state information received from the exchange for transfer to the computer respectively. The processor comprises a number of datastorage registers, an arithmetic unit and a control unit which includes a micro instruction generator with a micro program store and controls the processing of instructions stored in the program store.
However, such a system comprising a computer does not manage with only so called effective instructions which are intended to control the function units of the exchange. Rather, it demands considerably so called ineffective instructions in order to control the computer itself. Furthermore, the computer demands the use of its own program language from which an average ~ ; ' .
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telecommunication expert cannot be expected to separate the original telecommunication control functions. The result becomes, finally, a rather confused and very complex system, the opera-tion, maintenance and extension of which are combined with large costs.
The present invention, the characteristics of which appear from the claims, proceeds from an arbitrary automatic exchange which is controlled by means of control elements that `~
are used as identifiers, code receivers, code senders and markers.
The purpose of the invention is to achieve a SPC system without use of a computer program language. In such a system, the in-effective instructions are avoided as far as possible. This is achieved by inserting in the function units of the exchange simple computer technical aid means that do not require changing existing approved control principles in connection with a ;
concentration of the control of the system by means of a computer.
The computer technical means comprise data storage registers and logic arrangements controlled by time phase signals for producing access signals in order to address and activate the data storage registers. The registers are connected to each ;~
other through a data bus as well as the operating points and test points of the system.
The invention will now be more particularly described with reference to an embodiment thereof shown, by way of example, in the accompanying drawings, in which:
Fig. 1 is a block diagram of a SPC system according to the invention; and Fig. 2 is a block diagram showing how a marker carried out a path selection in a SPC exchange according to the invention.
In Fig. 1 a telecommunication system E~ is indicated by means of its operating points OP, test points TP and data storage registers REG. An example of an operating point is the
signals that are produced in accordance with control instructions identified by means of instruction address numbers. In the system, the execution of a control function consists of a number of sequentially processed control instructions being initiated by the aid of a start instruction address number associated with the first control instruction of the control function, the start instruction address number being stored in one of the data storage registers of the telecommunication system. , Known SPC telecommunication systems, as for example "D-10 Electronic Switching System", published in the journal "Japan Telecommunications Review - Vol. 13: No~ 3 and 4 and Vol. 14: No. 1", consist of an exchange and a computer. The ;
computer is formed by a memory part and by a processor. The memory part comprises a program store, a data store and registers which form a transfer unit that stores the operation instructions received from the computer for transferring to the exchange and stores state information received from the exchange for transfer to the computer respectively. The processor comprises a number of datastorage registers, an arithmetic unit and a control unit which includes a micro instruction generator with a micro program store and controls the processing of instructions stored in the program store.
However, such a system comprising a computer does not manage with only so called effective instructions which are intended to control the function units of the exchange. Rather, it demands considerably so called ineffective instructions in order to control the computer itself. Furthermore, the computer demands the use of its own program language from which an average ~ ; ' .
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telecommunication expert cannot be expected to separate the original telecommunication control functions. The result becomes, finally, a rather confused and very complex system, the opera-tion, maintenance and extension of which are combined with large costs.
The present invention, the characteristics of which appear from the claims, proceeds from an arbitrary automatic exchange which is controlled by means of control elements that `~
are used as identifiers, code receivers, code senders and markers.
The purpose of the invention is to achieve a SPC system without use of a computer program language. In such a system, the in-effective instructions are avoided as far as possible. This is achieved by inserting in the function units of the exchange simple computer technical aid means that do not require changing existing approved control principles in connection with a ;
concentration of the control of the system by means of a computer.
The computer technical means comprise data storage registers and logic arrangements controlled by time phase signals for producing access signals in order to address and activate the data storage registers. The registers are connected to each ;~
other through a data bus as well as the operating points and test points of the system.
The invention will now be more particularly described with reference to an embodiment thereof shown, by way of example, in the accompanying drawings, in which:
Fig. 1 is a block diagram of a SPC system according to the invention; and Fig. 2 is a block diagram showing how a marker carried out a path selection in a SPC exchange according to the invention.
In Fig. 1 a telecommunication system E~ is indicated by means of its operating points OP, test points TP and data storage registers REG. An example of an operating point is the
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one end of a relay winding. If a voltage is supplied to this winding end, the relay functions and this constitutes an operating course in the telecommunication system. In order to adjust the telecommunication system to the high data processing rates a bistable flip-flop, for example, is suitable. The output of the bistable flip-flop is connected to tha winding end and the input of the flip-flop constitutes the operating point. An example of a test point is a subscriber's line, the loop resistance of which is either high or low. If bistable 10 flip-flops are used, their outputs are used as test points. By inserting data storage registers in the function units of the telecommunication system, in many cases a saving of relay sets is achieved. For example, the operating state of a group selector of the telecommunication system can advantageously be indicated by means of a register Rl. Thus, the binary content of each bit position of the register indicates busy and idle states, respectively, of a predetermined path through the selector. The installation of further registers R2 in order to transfer, for further evaluation, said state of the group selector to another 20 function unit of the telecommunication system such as a marker is not di~ficult for an ordinary telecommunication expert, even if he is not a data processing expert. In Fig. 1 a data bus DB
is shown which connects all the registers to each other. However, it is not shown how the individual bit pOSitiOIIS in tha state registers Rl, and how the operating and test points OP, TP, respectively, are connected to the proper telecommunication ele-ments of the system, since these connections are determined by the individual embodiment of the telecommunication system and are not considered necessary for understanding the present invention.
One condition for the control of the system by means of a stored program is that each o~eratingpoint, each test point and each register can be accessed by means of an associated access .
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signal which is applied to a corresponding access gate. Accord-ing to Fig. 1 the access signals are sent from an access signal generator ASG. And by means of the access gates, a *Ve voltage that is necessary for operation is supplied to the operating points, and the existing state of the accessed test point to a common output 0 of the telecommunication system so that the access signals of the registers distinguish whether the access signal controls data reception or data transmission of the register.
Control by means of a stored program is further achie-ved by provision of a number of instruetion registers IR and at least one instruction address register IAR having access gates.
Each instruction register includes in binary coded form a control instruction for controlling an arbitrary complicated system that operates with three different instruction types, namely ;
test instruetions, operating instructions and transport instruc~
tions.
A test instruction is intended to access a test point j~
for the above mentioned transfer of the binary state to the common output 0. Aceordingly, a test instruction eomprises the address of the test point, the state of which will be tested.
An operating instruetion is intended to access and ;
operate, respectively, an operating point, the result of which '~
is that such an instruction at least includes the address of the operating point. In a modification of the operating instructions, ;
they furthermore comprise the address of a test point. The modification provides that the operating point is maintained activated until the test point changes to a predetermined binary state.
A transport instruction is intended to transport data from one registex to another through the data bus and correspond-ing access gates. The result is -that a normal transport "' ' '' . .' ' ' ;,;''', ' ' " ' ,' ~: '' ' . .'' ",, :
instruction includes the addresses of both the sending and ~;
receiving registers. There are registers R2 which are accessed due to the one instruction for reception and due to the other instruction for sending data. If, however, a transport instruc-tion addresses one of the registers Rl that stores system states, this register is always accessed only for sending data to the data bus DB. Also in the instruction registers, data reception from the data bus is impossible therefore the instructions stored therein are unchangeably written and may be read only.
For data transport from one of the instruction registers IR ~
to one of the registers REG in the telecommunication system or ~ i to the instruction address register IAR, the register IAR is used as a consequence of the condition that the instruction register itself is the sending register, a transport instruction which includes partly the data d which are to be transported and partly the addresses a for the receiving register. Thus, when the foregoing condition concern data transports the result is that even the instruction registers and the instruction address register with its corresponding access gates are connect-ed to the data bus DB.
The addresses appearing in the different instructions are transferred to the access signal generator ASG which decodes ~;~
the addresses and produces the access signals as. Besides the ;
instruction registers, the instruction address register IAR
also distinguishes from other registers of the telecommunication system so that its content is transferred not only to the data bus DB for transport to another register but, moreover, to the access signal generator ASG. The instruction address register IAR iS only arranged in order to store an instruction address number which is associated with one of the instruction registers.
The access signal generator ASG decodes the instruction address numbers and produces thereby the access signals asi for the .. . . . . ................... . ................ . ........... . .
, . ' , : .
address parts a stored in the instruction registers. Fuxthermore, the instruction address register IAR distinguishes from all other registers so that it is provided with a stepping forward input ST, the activation of which provides that the stored address number is raised with a binary counter unit.
Each instruction is processed step by step. Thus, a processing cycle is divided into at least three time phases, a beginning, a middle, and an end phase which are controlled by means of a phase generator PG, that sends corresponding time 1~ phase signals 01,02,~3to the access signal generator ASG. The ;
access signal generator ASG includes a first logic arrangement Ll which decodes the content of the instruction address register during the beginning phases and transmits during the other time phases the access signal asi for the instruction register that is identified by means of a respective instruction address number.
In this manner the access signal generator ASG has for its dis-posal during the other time phases in a respective processing cycle the address content of the accessed instruction register.
The access signals as for activating the operating ~ `
and test points and for connecting all the registers including the instruction registers and the instruction address register IAR to the data bus DB are produced by means of further logic arrangements of the access signal generator ASG during suitable time phases. As counting is required with building up processes, it is advantageous to access the registers which receive data first during the end phases. Conversely, the registers which will send data to the data bus DB and the operating and test points are accessed as quickly as possible.
The working manner of the access signal generator ASG
is described in more detail in the following description with reference to an embodiment shown in Fig. 2. In the diagram of Fig. 1, the conversion of the addresses a received from the -- 6 _ , . , ~ , instruction registers to the access signals as is indicated only by means of a dotted line for purposes of clarity. In the above-mentioned first logic arrangement Ll, the time phase control is indicated by means of a gate Gl activated during the beginning phases. Through the gate Gl the instruction address numbers are written in an intermediate register R3, the output of which is connected to an address decoder DECl. For all other registers the time phase control is indicated for the instruction address register IAR by means of a logic arrangement L3 which is activated for transferring data to the data bus DB -during the middle and the end phases and for reception of data from the data bus during the end phases.
The execution of a control function, which consists of a number of control instructions, in principle proceeds in the following manner: When nothing has to be changed in the operation state of the telecommunication system the phase generator PG sends no time phase signals and the instruction address register IAR includes the address number for a transport -~instruction, an opening instruction which comprises as a sender address the address of a predetermined register in the tele-communication system, a start register SR, and as a receiver ;
address the address of the instruction address register IAR.
In order to understand the present invention, it is not necessary to explain the method according to which an instruction address `
number is written into the start register, by means of which address number the first control instruction of the present control function is to be accessed. One can install several phase generators and their respective instruction reglsters, instruction address registers and access signal generators, if the invention is to be utilized in order to process all controlfunctions appearing in a teIecommunication system. In this case, each phase generator is allotted an unchangeable process -- 1 ....
', , ~' ', ' ' ' ' ' ', .. .. . ..... .
, ,'; '' ,, ' :' of determined control functions which affect a limited number of operating points and test points. However, a suitable utilizing of the registers REG makes the cooperation of the phase generators possible. In such cases a start register cooperating with a first phase generator even belongs to the registers cooperating -with a second phase generator. When the second phase generator has, for example, finished a control function with a data trans- `~
port to this start register, a control function is ordered, the execution of which is controlled by the first phase generator.
On the other hand there is in each telecommunication system, irrespective of whether data processing aids are used at the execution of all control functions or only a part thereof, at least one control function, the execution of which is demanded by an operation state change in the telecommunication system.
If, for example, a subscriber changes the loop state of its line, an instruction address number is thereby written into a start register SR. By means of the address number, the first control ~ -instruction in the control function is accessed in order to scan all the lines.
An address number stored in the start register SR
releases the start of the phase generator PG. During the begin-ning phase in the first processing cycle, the above mentioned opening instruction is accessed, thereby achieving transport of the address number stored in the start register SR through the data bus DB to the instruction address register IAR, where the address number is written during the end phase of the first pro-cessing cycle. The result is that the first control instruction of the ordered control function is accessed at the beginning of the following processing cycle. It is assumed that this first control instruction concerns the operation of an operating point which consequently is accessed according to the above descrip-tion and is activated by the access signal generator ASG. The ' .. .......
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second control instruction in the control function which is initiated in this way is accessed by means of the above mentioned stepping input ST of the instruction address register IAR, which input is acti~ated by means of an OR-gate L2 during the middle phase in each processing cycle. In this manner, for all processing cycles following after each other instruction addresses are obtained, the numbers of the instruction addresses being raised each time with one counting unit. And, therewith access signals asi are obtained for control instructions which are to be processed after each other. Also during the middle phase, in the processing cycle for said opening instruction such an address number raise was carried out. However, this raise was abolished at the reception of the instruction address number belonging to the first control instruction during each respective end phase. According to the foregolng principle the address number raise is abolished in case the instruction address regis-ter is accessed as a receiving register in consequence of a transport instruction.
This property will be used when, in connection with a test instruction, the continued execution of a control function depends on the binary state of the accessed test point. The output 0 of the telecommunication system previously mentioned, and which is common to all test points, is connected to an AND-gate L4 which is activated during the end phases and the output of which is connected through said OR-gate L2 to the stepping input ST of the instruction address register IAR. In this manner, it depends on the binary state of the test point whether the content of the instruction address register IAR, during a respective processing cycle, is raised once or twice with a counter unit. The address number raised with one counter unit in comparison with a test instruction address number is often allotted to a transport instruction due to which a new ' " ' ^' : " ' ' ' '. "~' "; ' .' '. ' ~
. . . . . . .
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instruction address number is transported through said data bus DB to the instruction address register IAR. This operation is continued after a test instruction with one of two possible instruction sequences. ~hen the proper control function of the telecommunication system is executed, a transport instruction is accessed by means oE a normal address number raise during the middle phases. Due to such transport instruction, the instruc-tion address register receives, during the end phase, an instruc-tion address number which is a counter unit smaller than the address number of the above mentioned opening instruction and which is associated with an operating instruction, referred to as a stop instruction. By means of the stop instruction, an operating point OPl is accessed during the end phase and activa- ;~ i tion thereof stops the phase generator PG. Earlier, however, during the middle phase in the instruction address register IAR, the address number associated with the opening instruction has been obtained.
By means of Fig. 2 and an embodiment shown therein a marker M that executes a path selection in an automatic exchange, in the following description some modifications and further progresses, respectively, of the control so far described will now be explained. As parts of ~he marker M, two registers R4 and R5, a clock CL, a counter C, some gates and a shift register SHR are shown, the cooperation of which will be explained in detail below. The start register SR, the instruction address register IAR and the phase generator PG have been already descri-bed in relation to Fig. 1. Instead of a data bus DB the indivi-dual connections for appearing data transports are shown in Fig.
2 in order to more easlly explain the execution of the path -selection control ~unction. Instead of the instruction registers, a read only memory ROM is used equipped with an address decoder DECl and a read register RR.
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.. : , The construction of the access signal generator ASG
depends on the coding form which is chosen for the immediately accessible control instruc*ions stored in the read only memory ROM. The instructions consist of an operator and a variable part op and va. The variable part va includes the addresses for the registers, the test and operating points which are to be controlled and data which are to be transported to one of the registers, respectively. As it already appears from the fore- -going description, the difference between effective and ineffec-tive instructions explained in the introduction is mainly mani-fested in the different transport instructions. The instructions which access the instruction address register IAR either for data reception ordata sending are ineffective due to the fact that they do not promote immediately the proper control of the telecommunication system. The operator part in such ineffective transport instructions is associated in the embodiment shown in Fig. 2 with individual operating code numbers. Besides the code numbers 1, 2 and 3, respectively shown for the effective ;
transport, operating and test instructions, the code numbers 4 and 5 respectively represent the data transport from the start register SR and from the variable part of the read register RR
to the instruction address register IAR. This means that no variable part in combination with the code number 4 is necessary, due to the fact that the code number already defines the sending and the receiving register. This in turn means that in an instr- `
uction with a whole code number 5, the variable part is at the disposal of an instruction address number which is to be transported.
The access signal generator ASG is used for decoding the code numbers and comprises an operator decoder DEC2 which is connected to the operator part of the read register RR; and for decoding the addresses of the register, test and operating - lI -.: ; -.
points of the telecommunication system the generator ASG comprisesa sending, a receiving, an operating and a test decoder DEC3 to DEC6 which, through associated activating gates, are connected to the phase generator PG, to the operator decoder and to the variable part of the read register RR. In a transport instruc- ~ .
tion with the code number 1, for example the one with the address number 22 in the read only memory ROM, the one variable part half comprising _ bit positions is for the sending addresses sa, -and the other part half comprising _ positions is for the receiv-ing addresses ra The insertion of the code number 5 means that the instruction address register IAR as well as the start register comprise. 2-n bit positions and that it is possible to execute control functions with only 22n control instructions when using :
a sufficiently large read only memory ROM, therewith controlling data transports between 2n registers in the telecommunication system. The variable parts of test instructions having the code ` : :
number 3, for example the one with the address number 23 in the read only memory ROM, include only test point addresses ta, so the existing bit positions per se allow an access of 22n test points. If it is assumed that no operating poi.nt needs to be activated longer than to the end of the respective processing cycle, the variable parts of the operating instructions with the :
code number 2, for example the one with the address number 25 in the read only memory ROM, are only used for the operating point addresses a and per se there is also access posssibility for 22n operating points. In the embodiment shown in Fig. 2 it is, how-ever, possible to make the processing cycles of the operating instructions independent of the time phase signals of the phase generator PG. This is achieved when the phase generator PG is provided with a signal extension input SEL and when in such oper-ating instructions with code number 2, for example the one with the address number 26 in the read only memory ROM, the one _ 12 -, .
. .
variable part half comprises the operating point address oa which is decoded by the operating decoder DEC5, and the other variable part half comprises the address ta of a suitable test point. The address ta is decoded by the test decoder DEC6, and the suitable test point changes its binary state when the operating process is finished. An activation of the signal extension input/
resulting in an extension of the time phase signal just transmitted from the phase generator PG, begins by means of a logic arrange~
ment L5 during the middle phase of a respective operating instruc-tion. This condition remains established until the binary stateof the likewise accessed test point has been changed. As such modified operating instructions include two addresses, by one access signal generator ASG, access signals are produced for only 2n operating points and for only 2n test points.
Of the registers R4 and R5, denoted as marker parts, one cooperates with an input selector group and the other with an output selector group. The selector groups SG are included in a number of similar groups and take part in setting up a new telephone connection. It is assumed that it is both at the input side and at the output side already described which paths may be switched in the selector groups in a group, of for example 12 paths, for the new connection without disturbing currently exist-ing connections. Between the corresponding input and output selector groups, all paths in a number of path groups are defined by means of fast installed links. Examination results for a predetermined path group belong to the related links, stored on the one hand at the input side and on the other hand at the output side in the bit positions of the registers R4 and R5. Each link is associated with one of the link numbers O to 11 with one bit position in each of said registers. According to the bit positions in the register R4 at the input side and according to the bit posikions in the register R5 at the output side, it is assumed - ï3 -.
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that the li~ks with the numbers 0 5 8 and ll and the links with the numbers 2 4 5 6 and 8, respectively, will be available for the new connection. The path selection function of the marker M is to determine one path, i.e. one link through which the new connection is to be switched.
The read outlets of said two registers are through an AND-gate arrangement G3 connected to the write inlets of the shift register SHR. For each bit position an ~ND-function is carried ~-out so that positions of the shift register only are activated if lO in both registers R4 and R5 corresponding positions are activated. `~
According to the foregoing example, in the shift register the bit positions are activated which belong to the links with the numbers 5 and 8. The counter C which is provided with a zero input O for zerosetting the content in the counter, counts the shift pulses which are fed to the shift input of the shift register. The zero input of the counter forms an operating point OP2. A first test point TPl indicates, by means of an ;~
OR-gate G4 connected to the bit positions of the shift register, if at least one of the bit positions is activated.
, .
When the binary state of the first test point TPl shows that no link within the path group called for path selection is held available for the new connection, the path selection control function is interrupted. And, by means of other control functions, the selector states at the input side and at the output side for ~ -another path group are examined.
A second test point TP2 is formed of the bit position in the shift register. The contents of the other positions are ~ -shifted to this position in turn concurrently with the shift pulses which are produced by the clock CL and are received at 30 the shift input. By means of an AND-gate G5, activated during respective operating instructions, an operating point OP3, i.e. the counter C and the shift register SHR, obtains long ... . ......
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shift pulses until the second test point TP2 is activated, and it demands 5 shift pulses according to the foregoing example. At the end of the path selection, the counter C comprises the numberof the link through which the new connection is to be switched.
Starting from a stopped phase generator PG and from an instruction address register IAR unactivated in all its bit positions, the execution of the path selection function is initiated according to the example shown in Fig. 2 by writing the instruction address number 22 in the start register S~ that is provided with an OR-gate G6. It is assumed that the data transports to the start register SR as well as to the registers R~ and R5, both cooperating with the selector groups, refer to control functions which belong to the selector groups SG. The ..
OR-gate G6 is connected via a blocking gate G7 to a start input of the phase generator PG which is provided with an output w that is activated as long as the time phase signals are transmittedand which is connected to an inverting input of the blocking gate G7. In this manner the phase generator PG
receives only a short start pulse and it is impossible to open a new control function before the just processed control function is finished. For a better comprehension, the outputs of the operating decoder DEC2 and the operating parts of the accessed control instructions are denoted in Fig. 2 by corresponding operating code numbers 1 to 5. In addition, the outputs of the address decoder DEC1 are denoted by the instruction address numbers 0, 22 to 27, x and max. By means of the time phase signals ~ 2, 0 3 sent from the phase generator PG, the execution of the path selection occurs step by step. In the following list of steps, two digit list numbers are used, the ten digit denoting the running processiny cycle number and the one digits 1, 2 and 3 denoting the beginning, middle and end phases.
The steps referred to are as follows:
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11: The instruction with the operating code number 4 associated with the address number 0 is accessed and stored in the read register RR.
12: The content of the instruction address register IAR is by means of the stepping input ST put on 1 and the code number 4 is decoded by the operating decoder DEC2.
13: The content of the start register SR, i.e. the address ~
number 22 is transported to the instruction address register IAR. --21 The instruction with the operating code number 1 associated with the address number 22 is accessed and stored in the read register RR. ~ ~ `
22: The content of the instruction address register IAR is put on 23, the code number 1 is decoded, and by means of the sending address sa, stored in the variable part of the read register RR
and decoded by the sending decoder DEC3, the register R4 of the `;
marker M is activated to send the binary content 100001001001. ~ `
23: By means of the receiving address ra stored in the variable part of the read register RR and decoded by the receiving decoder DEC4 the shift register SHR of the marker M is activated to receive the binary content 000001001000.
31: The instruction with the code number 3 associated with the ~ `
address number 23 is accessed and stored in the read register RR.
. .
32: The content of the instruction address register IAR is put on 24, the code number 3 is decoded, and by means of the test point address ta 1, stored in the variable part of the read register and decoded by the test decoder DEC6, the first test point TPl of the marker M is activated.
33: The content of the instruction address register IAR is put on 25 by means of activation of the stepping input due to the fact that the accessed test point TPl is activated.
41: The instruction with the code number 2 associated with the address number 25 is accessed and stored in the read register RR.
.
- 16 ~
'~ ` , ` .:
~, . ' ' `'i''' ' ' ' ''" ''' ' ' ';' " " :
: ; : '~` .. ' ' .: i:
~2 and 43: The content of the instruction address register IAR
is put on 26, the code number 2 is decoded and by means of the operating point address oa2, stored in the variable part of the read register RR and decoded by the operating decoder DEC5, the zero input 0 of the counter C is activated as the operating point OP2 of the marker M, i.e. the counter is set to zero.
51: The instruction with the code number 2 associated with the address number 26is accessed and storedin the read register RR.
52: The content of the instruction address register IAR is put on 27, the code number 2 is decoded and by means of the operating point address _ 3, stored in the variable part of the read register RR and decoded by the operating decoder DEC5, the shift input of the shift register is activated as the opPrating point OP3 of the marker M for reception of shift pulses sent - from the clock CL. By means of the test point address ta2 stored in the variable part of the read register RR and decoded by the test decoder DEC6, the second test point TP2 of the marker M is accessed. The middle phase of this processing cycle is extended as a conse~uence of the activation of the signal extension input SEL of the phase generator PG due to the fact that the second test point is unactivated, and, due to the shift pulses, the content of the shift register is shifted until at the content 100100000000, the second test point, changes its binary state, the counter C
counting 5 shift pulses.
61: The instruction with the code number 5 associated with the address number 27 is accessed and stored in the read register RR.
62: The content of the instruction address register IAR is ~-put on 28 and the code number 5 is decoded.
63: The variable part of the read register RR, i.e. the instruction address number max having binary "1" in all bit positions, is transported to the instruction address register IAR~
71: The instruction with the code number 2 associated with the :
.
- ., :
, , . :
~
only binary "1" comprising an address number is accessed and stored in the read register RR.
72: The content consisting of only binary "1" in the instruction address register IAR iS raised with one unit which is equal to a zero setting, the code number 2 is decoded and by means of the operating point address oal stored in the variable part of the read register RR and decoded by the operating decoder DEC5, an operating point OPl is accessed in order to set to zero the start register SR and in order to stop the phase generator PG.
73: Said operating point OP1 is activated. ;~
If all the bit positions of the shift register SHR had been unactivated in the step 23, i.e. if no path within the examined path group had been available ~or the new circuit, the stepping input of the instruction address register IAR would not be activated in the step 33 and one would obtain the following:
41: The instruction with the code number 5 associated with the address number 2~ is accessed and stored in the read register RR.
42: The content of the instruction address register IAR is put on 25 and the code number 5 is decoded.
43: The variable part of the read register RR, i.e. the address number x for an instruction which opens a new instruction sequence, that is not here described, is transported to the instruction address register IAR.
In order to limit the path selection function as far as possible from other control functions, it has been assumed,accord-ing to thé example describedthatthe counter C is started from zero when a new path group is examined. by means of another control function, not described, the address of the selected link is calculated by adding the link number obtained in the counter C to an address number which is associated with the link with the link number zero. At a variant that is not shown the path selection includes said adding function by charging the -- 1~ --counter C, for example, from the selector groups SG, with the address to the link with the number zero, the counter C at the end of the path selection containing the address to the link through which the new circuit is to be switched.
-- 19 -- . , ..
.: . , ,
. ' . ~. . ' ,:
.'' ' ,, ~ ` :
one end of a relay winding. If a voltage is supplied to this winding end, the relay functions and this constitutes an operating course in the telecommunication system. In order to adjust the telecommunication system to the high data processing rates a bistable flip-flop, for example, is suitable. The output of the bistable flip-flop is connected to tha winding end and the input of the flip-flop constitutes the operating point. An example of a test point is a subscriber's line, the loop resistance of which is either high or low. If bistable 10 flip-flops are used, their outputs are used as test points. By inserting data storage registers in the function units of the telecommunication system, in many cases a saving of relay sets is achieved. For example, the operating state of a group selector of the telecommunication system can advantageously be indicated by means of a register Rl. Thus, the binary content of each bit position of the register indicates busy and idle states, respectively, of a predetermined path through the selector. The installation of further registers R2 in order to transfer, for further evaluation, said state of the group selector to another 20 function unit of the telecommunication system such as a marker is not di~ficult for an ordinary telecommunication expert, even if he is not a data processing expert. In Fig. 1 a data bus DB
is shown which connects all the registers to each other. However, it is not shown how the individual bit pOSitiOIIS in tha state registers Rl, and how the operating and test points OP, TP, respectively, are connected to the proper telecommunication ele-ments of the system, since these connections are determined by the individual embodiment of the telecommunication system and are not considered necessary for understanding the present invention.
One condition for the control of the system by means of a stored program is that each o~eratingpoint, each test point and each register can be accessed by means of an associated access .
. : ~
.. . . . , . .. : .
signal which is applied to a corresponding access gate. Accord-ing to Fig. 1 the access signals are sent from an access signal generator ASG. And by means of the access gates, a *Ve voltage that is necessary for operation is supplied to the operating points, and the existing state of the accessed test point to a common output 0 of the telecommunication system so that the access signals of the registers distinguish whether the access signal controls data reception or data transmission of the register.
Control by means of a stored program is further achie-ved by provision of a number of instruetion registers IR and at least one instruction address register IAR having access gates.
Each instruction register includes in binary coded form a control instruction for controlling an arbitrary complicated system that operates with three different instruction types, namely ;
test instruetions, operating instructions and transport instruc~
tions.
A test instruction is intended to access a test point j~
for the above mentioned transfer of the binary state to the common output 0. Aceordingly, a test instruction eomprises the address of the test point, the state of which will be tested.
An operating instruetion is intended to access and ;
operate, respectively, an operating point, the result of which '~
is that such an instruction at least includes the address of the operating point. In a modification of the operating instructions, ;
they furthermore comprise the address of a test point. The modification provides that the operating point is maintained activated until the test point changes to a predetermined binary state.
A transport instruction is intended to transport data from one registex to another through the data bus and correspond-ing access gates. The result is -that a normal transport "' ' '' . .' ' ' ;,;''', ' ' " ' ,' ~: '' ' . .'' ",, :
instruction includes the addresses of both the sending and ~;
receiving registers. There are registers R2 which are accessed due to the one instruction for reception and due to the other instruction for sending data. If, however, a transport instruc-tion addresses one of the registers Rl that stores system states, this register is always accessed only for sending data to the data bus DB. Also in the instruction registers, data reception from the data bus is impossible therefore the instructions stored therein are unchangeably written and may be read only.
For data transport from one of the instruction registers IR ~
to one of the registers REG in the telecommunication system or ~ i to the instruction address register IAR, the register IAR is used as a consequence of the condition that the instruction register itself is the sending register, a transport instruction which includes partly the data d which are to be transported and partly the addresses a for the receiving register. Thus, when the foregoing condition concern data transports the result is that even the instruction registers and the instruction address register with its corresponding access gates are connect-ed to the data bus DB.
The addresses appearing in the different instructions are transferred to the access signal generator ASG which decodes ~;~
the addresses and produces the access signals as. Besides the ;
instruction registers, the instruction address register IAR
also distinguishes from other registers of the telecommunication system so that its content is transferred not only to the data bus DB for transport to another register but, moreover, to the access signal generator ASG. The instruction address register IAR iS only arranged in order to store an instruction address number which is associated with one of the instruction registers.
The access signal generator ASG decodes the instruction address numbers and produces thereby the access signals asi for the .. . . . . ................... . ................ . ........... . .
, . ' , : .
address parts a stored in the instruction registers. Fuxthermore, the instruction address register IAR distinguishes from all other registers so that it is provided with a stepping forward input ST, the activation of which provides that the stored address number is raised with a binary counter unit.
Each instruction is processed step by step. Thus, a processing cycle is divided into at least three time phases, a beginning, a middle, and an end phase which are controlled by means of a phase generator PG, that sends corresponding time 1~ phase signals 01,02,~3to the access signal generator ASG. The ;
access signal generator ASG includes a first logic arrangement Ll which decodes the content of the instruction address register during the beginning phases and transmits during the other time phases the access signal asi for the instruction register that is identified by means of a respective instruction address number.
In this manner the access signal generator ASG has for its dis-posal during the other time phases in a respective processing cycle the address content of the accessed instruction register.
The access signals as for activating the operating ~ `
and test points and for connecting all the registers including the instruction registers and the instruction address register IAR to the data bus DB are produced by means of further logic arrangements of the access signal generator ASG during suitable time phases. As counting is required with building up processes, it is advantageous to access the registers which receive data first during the end phases. Conversely, the registers which will send data to the data bus DB and the operating and test points are accessed as quickly as possible.
The working manner of the access signal generator ASG
is described in more detail in the following description with reference to an embodiment shown in Fig. 2. In the diagram of Fig. 1, the conversion of the addresses a received from the -- 6 _ , . , ~ , instruction registers to the access signals as is indicated only by means of a dotted line for purposes of clarity. In the above-mentioned first logic arrangement Ll, the time phase control is indicated by means of a gate Gl activated during the beginning phases. Through the gate Gl the instruction address numbers are written in an intermediate register R3, the output of which is connected to an address decoder DECl. For all other registers the time phase control is indicated for the instruction address register IAR by means of a logic arrangement L3 which is activated for transferring data to the data bus DB -during the middle and the end phases and for reception of data from the data bus during the end phases.
The execution of a control function, which consists of a number of control instructions, in principle proceeds in the following manner: When nothing has to be changed in the operation state of the telecommunication system the phase generator PG sends no time phase signals and the instruction address register IAR includes the address number for a transport -~instruction, an opening instruction which comprises as a sender address the address of a predetermined register in the tele-communication system, a start register SR, and as a receiver ;
address the address of the instruction address register IAR.
In order to understand the present invention, it is not necessary to explain the method according to which an instruction address `
number is written into the start register, by means of which address number the first control instruction of the present control function is to be accessed. One can install several phase generators and their respective instruction reglsters, instruction address registers and access signal generators, if the invention is to be utilized in order to process all controlfunctions appearing in a teIecommunication system. In this case, each phase generator is allotted an unchangeable process -- 1 ....
', , ~' ', ' ' ' ' ' ', .. .. . ..... .
, ,'; '' ,, ' :' of determined control functions which affect a limited number of operating points and test points. However, a suitable utilizing of the registers REG makes the cooperation of the phase generators possible. In such cases a start register cooperating with a first phase generator even belongs to the registers cooperating -with a second phase generator. When the second phase generator has, for example, finished a control function with a data trans- `~
port to this start register, a control function is ordered, the execution of which is controlled by the first phase generator.
On the other hand there is in each telecommunication system, irrespective of whether data processing aids are used at the execution of all control functions or only a part thereof, at least one control function, the execution of which is demanded by an operation state change in the telecommunication system.
If, for example, a subscriber changes the loop state of its line, an instruction address number is thereby written into a start register SR. By means of the address number, the first control ~ -instruction in the control function is accessed in order to scan all the lines.
An address number stored in the start register SR
releases the start of the phase generator PG. During the begin-ning phase in the first processing cycle, the above mentioned opening instruction is accessed, thereby achieving transport of the address number stored in the start register SR through the data bus DB to the instruction address register IAR, where the address number is written during the end phase of the first pro-cessing cycle. The result is that the first control instruction of the ordered control function is accessed at the beginning of the following processing cycle. It is assumed that this first control instruction concerns the operation of an operating point which consequently is accessed according to the above descrip-tion and is activated by the access signal generator ASG. The ' .. .......
-- ~3 -- ..
.. . .. . . .... . . . .. .. .
', ; , , , ' ' ', ''' ' .' ' ' : ~''.:' "'" , . ~,:
,,, . , . , " , .. . . ..
$~
second control instruction in the control function which is initiated in this way is accessed by means of the above mentioned stepping input ST of the instruction address register IAR, which input is acti~ated by means of an OR-gate L2 during the middle phase in each processing cycle. In this manner, for all processing cycles following after each other instruction addresses are obtained, the numbers of the instruction addresses being raised each time with one counting unit. And, therewith access signals asi are obtained for control instructions which are to be processed after each other. Also during the middle phase, in the processing cycle for said opening instruction such an address number raise was carried out. However, this raise was abolished at the reception of the instruction address number belonging to the first control instruction during each respective end phase. According to the foregolng principle the address number raise is abolished in case the instruction address regis-ter is accessed as a receiving register in consequence of a transport instruction.
This property will be used when, in connection with a test instruction, the continued execution of a control function depends on the binary state of the accessed test point. The output 0 of the telecommunication system previously mentioned, and which is common to all test points, is connected to an AND-gate L4 which is activated during the end phases and the output of which is connected through said OR-gate L2 to the stepping input ST of the instruction address register IAR. In this manner, it depends on the binary state of the test point whether the content of the instruction address register IAR, during a respective processing cycle, is raised once or twice with a counter unit. The address number raised with one counter unit in comparison with a test instruction address number is often allotted to a transport instruction due to which a new ' " ' ^' : " ' ' ' '. "~' "; ' .' '. ' ~
. . . . . . .
... . .
9~
instruction address number is transported through said data bus DB to the instruction address register IAR. This operation is continued after a test instruction with one of two possible instruction sequences. ~hen the proper control function of the telecommunication system is executed, a transport instruction is accessed by means oE a normal address number raise during the middle phases. Due to such transport instruction, the instruc-tion address register receives, during the end phase, an instruc-tion address number which is a counter unit smaller than the address number of the above mentioned opening instruction and which is associated with an operating instruction, referred to as a stop instruction. By means of the stop instruction, an operating point OPl is accessed during the end phase and activa- ;~ i tion thereof stops the phase generator PG. Earlier, however, during the middle phase in the instruction address register IAR, the address number associated with the opening instruction has been obtained.
By means of Fig. 2 and an embodiment shown therein a marker M that executes a path selection in an automatic exchange, in the following description some modifications and further progresses, respectively, of the control so far described will now be explained. As parts of ~he marker M, two registers R4 and R5, a clock CL, a counter C, some gates and a shift register SHR are shown, the cooperation of which will be explained in detail below. The start register SR, the instruction address register IAR and the phase generator PG have been already descri-bed in relation to Fig. 1. Instead of a data bus DB the indivi-dual connections for appearing data transports are shown in Fig.
2 in order to more easlly explain the execution of the path -selection control ~unction. Instead of the instruction registers, a read only memory ROM is used equipped with an address decoder DECl and a read register RR.
_ 1-0 _ . : : ~ .
.. . . . . . ... .
. .
.. : , The construction of the access signal generator ASG
depends on the coding form which is chosen for the immediately accessible control instruc*ions stored in the read only memory ROM. The instructions consist of an operator and a variable part op and va. The variable part va includes the addresses for the registers, the test and operating points which are to be controlled and data which are to be transported to one of the registers, respectively. As it already appears from the fore- -going description, the difference between effective and ineffec-tive instructions explained in the introduction is mainly mani-fested in the different transport instructions. The instructions which access the instruction address register IAR either for data reception ordata sending are ineffective due to the fact that they do not promote immediately the proper control of the telecommunication system. The operator part in such ineffective transport instructions is associated in the embodiment shown in Fig. 2 with individual operating code numbers. Besides the code numbers 1, 2 and 3, respectively shown for the effective ;
transport, operating and test instructions, the code numbers 4 and 5 respectively represent the data transport from the start register SR and from the variable part of the read register RR
to the instruction address register IAR. This means that no variable part in combination with the code number 4 is necessary, due to the fact that the code number already defines the sending and the receiving register. This in turn means that in an instr- `
uction with a whole code number 5, the variable part is at the disposal of an instruction address number which is to be transported.
The access signal generator ASG is used for decoding the code numbers and comprises an operator decoder DEC2 which is connected to the operator part of the read register RR; and for decoding the addresses of the register, test and operating - lI -.: ; -.
points of the telecommunication system the generator ASG comprisesa sending, a receiving, an operating and a test decoder DEC3 to DEC6 which, through associated activating gates, are connected to the phase generator PG, to the operator decoder and to the variable part of the read register RR. In a transport instruc- ~ .
tion with the code number 1, for example the one with the address number 22 in the read only memory ROM, the one variable part half comprising _ bit positions is for the sending addresses sa, -and the other part half comprising _ positions is for the receiv-ing addresses ra The insertion of the code number 5 means that the instruction address register IAR as well as the start register comprise. 2-n bit positions and that it is possible to execute control functions with only 22n control instructions when using :
a sufficiently large read only memory ROM, therewith controlling data transports between 2n registers in the telecommunication system. The variable parts of test instructions having the code ` : :
number 3, for example the one with the address number 23 in the read only memory ROM, include only test point addresses ta, so the existing bit positions per se allow an access of 22n test points. If it is assumed that no operating poi.nt needs to be activated longer than to the end of the respective processing cycle, the variable parts of the operating instructions with the :
code number 2, for example the one with the address number 25 in the read only memory ROM, are only used for the operating point addresses a and per se there is also access posssibility for 22n operating points. In the embodiment shown in Fig. 2 it is, how-ever, possible to make the processing cycles of the operating instructions independent of the time phase signals of the phase generator PG. This is achieved when the phase generator PG is provided with a signal extension input SEL and when in such oper-ating instructions with code number 2, for example the one with the address number 26 in the read only memory ROM, the one _ 12 -, .
. .
variable part half comprises the operating point address oa which is decoded by the operating decoder DEC5, and the other variable part half comprises the address ta of a suitable test point. The address ta is decoded by the test decoder DEC6, and the suitable test point changes its binary state when the operating process is finished. An activation of the signal extension input/
resulting in an extension of the time phase signal just transmitted from the phase generator PG, begins by means of a logic arrange~
ment L5 during the middle phase of a respective operating instruc-tion. This condition remains established until the binary stateof the likewise accessed test point has been changed. As such modified operating instructions include two addresses, by one access signal generator ASG, access signals are produced for only 2n operating points and for only 2n test points.
Of the registers R4 and R5, denoted as marker parts, one cooperates with an input selector group and the other with an output selector group. The selector groups SG are included in a number of similar groups and take part in setting up a new telephone connection. It is assumed that it is both at the input side and at the output side already described which paths may be switched in the selector groups in a group, of for example 12 paths, for the new connection without disturbing currently exist-ing connections. Between the corresponding input and output selector groups, all paths in a number of path groups are defined by means of fast installed links. Examination results for a predetermined path group belong to the related links, stored on the one hand at the input side and on the other hand at the output side in the bit positions of the registers R4 and R5. Each link is associated with one of the link numbers O to 11 with one bit position in each of said registers. According to the bit positions in the register R4 at the input side and according to the bit posikions in the register R5 at the output side, it is assumed - ï3 -.
~t;t~
that the li~ks with the numbers 0 5 8 and ll and the links with the numbers 2 4 5 6 and 8, respectively, will be available for the new connection. The path selection function of the marker M is to determine one path, i.e. one link through which the new connection is to be switched.
The read outlets of said two registers are through an AND-gate arrangement G3 connected to the write inlets of the shift register SHR. For each bit position an ~ND-function is carried ~-out so that positions of the shift register only are activated if lO in both registers R4 and R5 corresponding positions are activated. `~
According to the foregoing example, in the shift register the bit positions are activated which belong to the links with the numbers 5 and 8. The counter C which is provided with a zero input O for zerosetting the content in the counter, counts the shift pulses which are fed to the shift input of the shift register. The zero input of the counter forms an operating point OP2. A first test point TPl indicates, by means of an ;~
OR-gate G4 connected to the bit positions of the shift register, if at least one of the bit positions is activated.
, .
When the binary state of the first test point TPl shows that no link within the path group called for path selection is held available for the new connection, the path selection control function is interrupted. And, by means of other control functions, the selector states at the input side and at the output side for ~ -another path group are examined.
A second test point TP2 is formed of the bit position in the shift register. The contents of the other positions are ~ -shifted to this position in turn concurrently with the shift pulses which are produced by the clock CL and are received at 30 the shift input. By means of an AND-gate G5, activated during respective operating instructions, an operating point OP3, i.e. the counter C and the shift register SHR, obtains long ... . ......
. .. . . :
.:
. ~ ,: . - ' ' ~ , .
shift pulses until the second test point TP2 is activated, and it demands 5 shift pulses according to the foregoing example. At the end of the path selection, the counter C comprises the numberof the link through which the new connection is to be switched.
Starting from a stopped phase generator PG and from an instruction address register IAR unactivated in all its bit positions, the execution of the path selection function is initiated according to the example shown in Fig. 2 by writing the instruction address number 22 in the start register S~ that is provided with an OR-gate G6. It is assumed that the data transports to the start register SR as well as to the registers R~ and R5, both cooperating with the selector groups, refer to control functions which belong to the selector groups SG. The ..
OR-gate G6 is connected via a blocking gate G7 to a start input of the phase generator PG which is provided with an output w that is activated as long as the time phase signals are transmittedand which is connected to an inverting input of the blocking gate G7. In this manner the phase generator PG
receives only a short start pulse and it is impossible to open a new control function before the just processed control function is finished. For a better comprehension, the outputs of the operating decoder DEC2 and the operating parts of the accessed control instructions are denoted in Fig. 2 by corresponding operating code numbers 1 to 5. In addition, the outputs of the address decoder DEC1 are denoted by the instruction address numbers 0, 22 to 27, x and max. By means of the time phase signals ~ 2, 0 3 sent from the phase generator PG, the execution of the path selection occurs step by step. In the following list of steps, two digit list numbers are used, the ten digit denoting the running processiny cycle number and the one digits 1, 2 and 3 denoting the beginning, middle and end phases.
The steps referred to are as follows:
- lS -. . . . .: : ~
.. . ... ' ' ' ; .' . :
.. . , ,. , ., , ~
11: The instruction with the operating code number 4 associated with the address number 0 is accessed and stored in the read register RR.
12: The content of the instruction address register IAR is by means of the stepping input ST put on 1 and the code number 4 is decoded by the operating decoder DEC2.
13: The content of the start register SR, i.e. the address ~
number 22 is transported to the instruction address register IAR. --21 The instruction with the operating code number 1 associated with the address number 22 is accessed and stored in the read register RR. ~ ~ `
22: The content of the instruction address register IAR is put on 23, the code number 1 is decoded, and by means of the sending address sa, stored in the variable part of the read register RR
and decoded by the sending decoder DEC3, the register R4 of the `;
marker M is activated to send the binary content 100001001001. ~ `
23: By means of the receiving address ra stored in the variable part of the read register RR and decoded by the receiving decoder DEC4 the shift register SHR of the marker M is activated to receive the binary content 000001001000.
31: The instruction with the code number 3 associated with the ~ `
address number 23 is accessed and stored in the read register RR.
. .
32: The content of the instruction address register IAR is put on 24, the code number 3 is decoded, and by means of the test point address ta 1, stored in the variable part of the read register and decoded by the test decoder DEC6, the first test point TPl of the marker M is activated.
33: The content of the instruction address register IAR is put on 25 by means of activation of the stepping input due to the fact that the accessed test point TPl is activated.
41: The instruction with the code number 2 associated with the address number 25 is accessed and stored in the read register RR.
.
- 16 ~
'~ ` , ` .:
~, . ' ' `'i''' ' ' ' ''" ''' ' ' ';' " " :
: ; : '~` .. ' ' .: i:
~2 and 43: The content of the instruction address register IAR
is put on 26, the code number 2 is decoded and by means of the operating point address oa2, stored in the variable part of the read register RR and decoded by the operating decoder DEC5, the zero input 0 of the counter C is activated as the operating point OP2 of the marker M, i.e. the counter is set to zero.
51: The instruction with the code number 2 associated with the address number 26is accessed and storedin the read register RR.
52: The content of the instruction address register IAR is put on 27, the code number 2 is decoded and by means of the operating point address _ 3, stored in the variable part of the read register RR and decoded by the operating decoder DEC5, the shift input of the shift register is activated as the opPrating point OP3 of the marker M for reception of shift pulses sent - from the clock CL. By means of the test point address ta2 stored in the variable part of the read register RR and decoded by the test decoder DEC6, the second test point TP2 of the marker M is accessed. The middle phase of this processing cycle is extended as a conse~uence of the activation of the signal extension input SEL of the phase generator PG due to the fact that the second test point is unactivated, and, due to the shift pulses, the content of the shift register is shifted until at the content 100100000000, the second test point, changes its binary state, the counter C
counting 5 shift pulses.
61: The instruction with the code number 5 associated with the address number 27 is accessed and stored in the read register RR.
62: The content of the instruction address register IAR is ~-put on 28 and the code number 5 is decoded.
63: The variable part of the read register RR, i.e. the instruction address number max having binary "1" in all bit positions, is transported to the instruction address register IAR~
71: The instruction with the code number 2 associated with the :
.
- ., :
, , . :
~
only binary "1" comprising an address number is accessed and stored in the read register RR.
72: The content consisting of only binary "1" in the instruction address register IAR iS raised with one unit which is equal to a zero setting, the code number 2 is decoded and by means of the operating point address oal stored in the variable part of the read register RR and decoded by the operating decoder DEC5, an operating point OPl is accessed in order to set to zero the start register SR and in order to stop the phase generator PG.
73: Said operating point OP1 is activated. ;~
If all the bit positions of the shift register SHR had been unactivated in the step 23, i.e. if no path within the examined path group had been available ~or the new circuit, the stepping input of the instruction address register IAR would not be activated in the step 33 and one would obtain the following:
41: The instruction with the code number 5 associated with the address number 2~ is accessed and stored in the read register RR.
42: The content of the instruction address register IAR is put on 25 and the code number 5 is decoded.
43: The variable part of the read register RR, i.e. the address number x for an instruction which opens a new instruction sequence, that is not here described, is transported to the instruction address register IAR.
In order to limit the path selection function as far as possible from other control functions, it has been assumed,accord-ing to thé example describedthatthe counter C is started from zero when a new path group is examined. by means of another control function, not described, the address of the selected link is calculated by adding the link number obtained in the counter C to an address number which is associated with the link with the link number zero. At a variant that is not shown the path selection includes said adding function by charging the -- 1~ --counter C, for example, from the selector groups SG, with the address to the link with the number zero, the counter C at the end of the path selection containing the address to the link through which the new circuit is to be switched.
-- 19 -- . , ..
.: . , ,
Claims (3)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A Stored Program Controlled telecommunication system in which test points, operating points and data storage registers connected to each other through a data bus are controlled by means of access signals which are produced by control instructions identified by means of instruction address numbers, the execution of a control function consisting of a number of sequentially processed control instructions being initiated by the aid of a start instruction address number associated with the first control instruction of the control function, the start instruction address number being stored in one of the data storage registers of the telecommunication system, wherein said data storage registers include a number of instruction registers containing one control instruction each and further include at least one instruction address register for storage of said instruction address numbers provided with a stepping input the activation of which provides that a stored address number is raised with one unit, and said telecommunication system comprises at least one phase generator which produces time phase signals that are used in order to divide each of the processing cycles of the control instructions into phases, and comprises at least one access signal generator controlled by the time phase signals, the instruction address numbers and the control instructions, said access signals being generated at the outputs of the access signal generator which includes a first logic arrangement that decodes the content of the instruction address register during a time phase at the begin of the respective processing cycle and accesses the instruction register associated with the respective address number during the other time phases of the processing cycle, a second logic arrangement by means of which said stepping input is activated during a time phase in the middle of each processing cycle, a third logic arrangement which allows transfer of an instruction address number from one of the registers in the system to the instruction address register only during a time phase at the end of the processing cycles, and a fourth logic arrangement having an AND-function the inputs of which are activated during the time phase at the end of a processing cycle which results in an access signal for accessing one of said test points and by the one binary state of this test point, the output of which is connected to said stepping input in the instruction address register.
2. A telecommunication system according to claim 1, wherein said time phase generator is provided with a signal extension input, the activation of which causes an extension of the time phase signal just sent out, and the telecommunication system comprises a fifth logic arrangement, the inputs of which, during the processing cycle which results in access signals for accessing one of said operating points and one of said test points, are activated by at least one of the last mentioned access signals and by a binary state of the last mentioned test point, the output of which is connected to said signal extension input in the time phase generator.
3. A telecommunication system according to one of claims 1 or 2, wherein said instruction registers comprise at least one memory having an address decoder and a read register and that said first logic arrangement in the access signal generator comprises a gate arrangement, the read register being connected to the access signal generator and to said data bus for decoding and for transport of the instruction stored in the read register, respectively, the gate arrangement connecting the instruction address register to the address decoder of the memory only during the time phases at the beginning of the processing cycles.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SE7407431A SE376354B (en) | 1974-06-06 | 1974-06-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1052463A true CA1052463A (en) | 1979-04-10 |
Family
ID=20321339
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA228,756A Expired CA1052463A (en) | 1974-06-06 | 1975-06-06 | Spc telecommunication system |
Country Status (19)
| Country | Link |
|---|---|
| US (1) | US4002851A (en) |
| JP (1) | JPS5818836B2 (en) |
| AU (1) | AU497191B2 (en) |
| BE (1) | BE829976A (en) |
| BR (1) | BR7503523A (en) |
| CA (1) | CA1052463A (en) |
| DK (1) | DK138298B (en) |
| EG (1) | EG13379A (en) |
| ES (1) | ES438259A1 (en) |
| FI (1) | FI58418C (en) |
| FR (1) | FR2274190A1 (en) |
| GB (1) | GB1462150A (en) |
| HU (1) | HU171888B (en) |
| IN (1) | IN142560B (en) |
| MY (1) | MY7800103A (en) |
| NL (1) | NL7506750A (en) |
| NO (1) | NO137803C (en) |
| SE (1) | SE376354B (en) |
| YU (1) | YU36091B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4487630A (en) * | 1982-10-25 | 1984-12-11 | Cabot Corporation | Wear-resistant stainless steel |
| JPS6130454A (en) * | 1984-07-21 | 1986-02-12 | Motoyasu Tanaka | Environment improving method for living space of automobile |
| US5471526A (en) * | 1994-02-28 | 1995-11-28 | Telefonaktiebolaget L M Ericsson (Publ.) | Tracing with keys and locks on a telecommunication network |
| US20060020413A1 (en) * | 2004-07-26 | 2006-01-26 | Septon Daven W | Methods and apparatus for providing automated test equipment with a means to jump and return in a test program |
| CN113254079B (en) * | 2021-06-28 | 2021-10-01 | 广东省新一代通信与网络创新研究院 | Method and system for realizing self-increment instruction |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR1603447A (en) * | 1968-08-08 | 1971-04-19 | ||
| US3825693A (en) * | 1972-09-25 | 1974-07-23 | Tele Resources Inc | Time division multiplex branch exchange |
-
1974
- 1974-06-06 SE SE7407431A patent/SE376354B/xx not_active IP Right Cessation
-
1975
- 1975-05-19 US US05/578,734 patent/US4002851A/en not_active Expired - Lifetime
- 1975-05-21 IN IN1027/CAL/1975A patent/IN142560B/en unknown
- 1975-05-28 FI FI751555A patent/FI58418C/en not_active IP Right Cessation
- 1975-05-29 GB GB2351475A patent/GB1462150A/en not_active Expired
- 1975-05-29 AU AU81685/75A patent/AU497191B2/en not_active Expired
- 1975-06-03 HU HU75EI00000624A patent/HU171888B/en unknown
- 1975-06-04 YU YU1440/75A patent/YU36091B/en unknown
- 1975-06-04 DK DK252575AA patent/DK138298B/en unknown
- 1975-06-04 BR BR4512/75D patent/BR7503523A/en unknown
- 1975-06-05 FR FR7517658A patent/FR2274190A1/en active Granted
- 1975-06-05 NO NO751996A patent/NO137803C/en unknown
- 1975-06-05 JP JP50068137A patent/JPS5818836B2/en not_active Expired
- 1975-06-05 ES ES438259A patent/ES438259A1/en not_active Expired
- 1975-06-06 BE BE157120A patent/BE829976A/en not_active IP Right Cessation
- 1975-06-06 CA CA228,756A patent/CA1052463A/en not_active Expired
- 1975-06-06 NL NL7506750A patent/NL7506750A/en not_active Application Discontinuation
- 1975-06-07 EG EG329/75A patent/EG13379A/en active
-
1978
- 1978-12-30 MY MY103/78A patent/MY7800103A/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| YU36091B (en) | 1981-11-13 |
| JPS518808A (en) | 1976-01-24 |
| NO137803B (en) | 1978-01-16 |
| HU171888B (en) | 1978-04-28 |
| AU497191B2 (en) | 1978-12-07 |
| FI58418C (en) | 1981-01-12 |
| NO137803C (en) | 1978-05-10 |
| DK252575A (en) | 1975-12-07 |
| AU8168575A (en) | 1976-12-02 |
| MY7800103A (en) | 1978-12-31 |
| SE376354B (en) | 1975-05-12 |
| NL7506750A (en) | 1975-12-09 |
| BR7503523A (en) | 1976-05-25 |
| YU144075A (en) | 1981-02-28 |
| GB1462150A (en) | 1977-01-19 |
| DK138298B (en) | 1978-08-07 |
| JPS5818836B2 (en) | 1983-04-14 |
| EG13379A (en) | 1981-03-31 |
| DK138298C (en) | 1979-01-22 |
| FR2274190A1 (en) | 1976-01-02 |
| FI751555A (en) | 1975-12-07 |
| FR2274190B1 (en) | 1979-03-23 |
| ES438259A1 (en) | 1977-04-16 |
| NO751996L (en) | 1975-12-09 |
| FI58418B (en) | 1980-09-30 |
| BE829976A (en) | 1975-10-01 |
| IN142560B (en) | 1977-07-30 |
| US4002851A (en) | 1977-01-11 |
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