CA1063677A - Spread spectrum demodulator - Google Patents
Spread spectrum demodulatorInfo
- Publication number
- CA1063677A CA1063677A CA259,770A CA259770A CA1063677A CA 1063677 A CA1063677 A CA 1063677A CA 259770 A CA259770 A CA 259770A CA 1063677 A CA1063677 A CA 1063677A
- Authority
- CA
- Canada
- Prior art keywords
- signal
- spread spectrum
- pulses
- phase
- random sequence
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/14—Relay systems
- H04B7/15—Active relay systems
- H04B7/204—Multiple access
- H04B7/216—Code division or spread-spectrum multiple access [CDMA, SSMA]
Abstract
ABSTRACT OF THE DISCLOSURE
Demodulation of a wideband spread spectrum four-phase PSK
(phase shift keyed) modulated carrier signal is accomplished by means of a correlator which phase shifts the modulated carrier signal as a function of a locally generated PN (pseudo-noise) sequence to provide a narrow band two-phase PSK modulated carrier signal. The two-phase modulated signal is fed to a matched filter wherein undesired signal components are removed so as to provide an IF (intermediate frequency) signal. A carrier re-covery phaselock loop demodulates the two phase modulated IF
signal to provide a baseband signal. A timing recovery loop operates upon the baseband signal to provide timing signals for the locally generated PN sequence to synchronize the local PN
sequence with the modulated carrier sequence. A bit timing loop and a sample and hold means operate upon the baseband signal to detect the modulating data to provide an output signal which is a function of the modulating data.
Demodulation of a wideband spread spectrum four-phase PSK
(phase shift keyed) modulated carrier signal is accomplished by means of a correlator which phase shifts the modulated carrier signal as a function of a locally generated PN (pseudo-noise) sequence to provide a narrow band two-phase PSK modulated carrier signal. The two-phase modulated signal is fed to a matched filter wherein undesired signal components are removed so as to provide an IF (intermediate frequency) signal. A carrier re-covery phaselock loop demodulates the two phase modulated IF
signal to provide a baseband signal. A timing recovery loop operates upon the baseband signal to provide timing signals for the locally generated PN sequence to synchronize the local PN
sequence with the modulated carrier sequence. A bit timing loop and a sample and hold means operate upon the baseband signal to detect the modulating data to provide an output signal which is a function of the modulating data.
Description
~ 7i The present invention is related to the ield of spread spectrum communications systems and more particularly to an im-proved spread spectrum demodulator utillzing matched filtering techniques.
Spread spectrum communication systems utilize a transmis-sion bandwidth many time~ as large as the information bandwidth in order to achieve jam re~istance. Additional advantages in~
clude multipath signal rejection and a low probability of detec-tionO A ~pread spe~trum transmitter generates a data modulated ln signal, which signal h~s its energy spread over a frequency band considerably wider than the data rate. Generally a PN sequence `~ is used to modulate the phase of the carrier signal. Within the receiver there is usually provided a matched filter, which filter is designed to have an impulse response which is the time-reverse -~ of the transmitter's ou~put waveform. The matched fllter thus provides a match between the transmitted waveform and the re-ceiver's response. ~tched filters that utilize surface acoustic wave devices (SAW's) have been used in spread spectrum data transmission sy~temsO
Two publicat~ons of interest for purposes of establishing i~ the state of the art are "5urface Acoustic Wave Devices And Ap-pllcations" by D. P. Morgan, Ultrasonics, May 1973, pages 121-128;
and "Surface Acous~ic Wave Device~ And Appllcations (Spread Spectrum Processors)" by B. J. Hunsinger, ~ltrasonic~, November 1973, pages 254~263.
In the spread spectrum demodula~or of the present inv~ntion there is provided a correlator for phase shift~ng a four-phase w~deband PSK modulated signal in response ~o a local ~N sequence in order to provide a two-phase narrow band signal. The two-phase signal i8 applled to a matehed filter, the output of which is an IF signal, The IF signal is then applied to a carrler re~
, covery phaselock loop whereln demodulation takes place to provide .~' ..
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a baseband data slgnal. A bit timing loop and a sample and hold circuit operate upon the baseband data signal to reconstruct the information data. A PN timing recovery loop also receives the IF
signal from the matched filter along with a clocking signal from the bit timing loop to provide a synchronizing sign~l to the local PN sequence generator. Improved demodulation is achieved by positioning the matched filter prior to the carrier recovery phaselock loop and by transmi~ting the wideband signal in four~
phase and by converting it early in the recei~er into a two~ph~se narrow band signalO
More specifically, in the preferred embodiment of the in~en-tion there is provided a carrier signal generator and a modulat-ing device responsive to a binary information sign~l for spread spectrum modulating the generated carrier signal. Additionally~
there is provided an apparatus for transmitting the spread spec-trum modulated carrier signal and an apparatus for receiving and collapsing the spread spectrum of a received spread spectrum modulated earrier signal to provide a non-spread spectrum modu-lated signal. A matched filter responsive to the non-spread spectrum modulated carrier signal provides an intermediate sig-nal which contains the modulation components of ~he binary in-formation ~ignal. A carrler recovery cirruit responsive to the intermediate signal from the matched filter provldes a baseband ~ign~l, An apparatus i5 provided or detecting the blnary in~or-' mation ~ignal from ~he baseband 8ignalO
i From the foregoing it can therefore be seen that it is a primary object of the present ~nvention to provide an improved spread ~pectrum demodulator.
It i~ another object of the present invention to provide a spread spectrum demodulator wherein ~ four-phase wideband signal is changed to a two-phase narrow band ~ignal early in the demodu-lation process.
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'7'7 These and other objects of the present invention will be-come more apparent when taken in conjunction with the following description and drawings where~n like characters indicate like parts and which drawings form a part of the present disclosure.
Fig. 1 illustrates in block diagram form a spread spectrum modulator which may be utilized with the present invention;
Fig. 2 lllustrates in block diagram form the preferred em-bodiment of the invention;
Fig. 3 ~llustrates in block diagram form a matched filter which may be utilized with the preferred embodiment of Figo 2;
:. Fig. 4 illustrates in block diagram form the PN tim~ng re-covery loop control circuitry which may be u~ilized in the pre-ferred embodiment of Fig. 2;
Fig. 5 lllu~trates ~n a detailed block diagram form two of the blocks associated wi~h the preferred embodiment of Fig. 2;
Figo 6 illustrates in block diagram form a carrier recovery : ~ :
phaselock loop whlch may be used in the preferred e~bodiment of . ~g. 2;
Fig. 7 illustrates in block diagram form a portion of the c~rrier recovery phaselock loop shown in Figo 6;
Flgs, 8~ to 8g illustrate waveforms which oczur at selected points in the device shown ~n Fig. 3;
Flg. 9 illustrates waveform~ u~eful in understanding the operation of the preferred embodiment o the inYention shown in Flgo 2, Fig~. lOa to lOc illustrate waveforms whlch occur in Fig. 4;
and ~ .
Figs. lla to lld illustrate ln chart form signal frequency ~
spectrums whlch spectrums are useful in under~tanding the opera- . . .
. 30 tion of ~he inventlon.
In ~igo 1 there i8 disclosed ~he modulatlng por~ion of a data modulated transmission system, of the spread spectrum type, ;,., ' ' .
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which system codes an information slgnal in a par~icular format and utilizes the encoded information signal to spread spectrum modulate a ~arrier signal. A PN sequence generator 10~ in re-sponse to a clock signal, provides a pseudo-random bLnary bit sequence of pulses to an encoder 12. The PN sequence genera tor 10 may be, for example, a multistage shift register having feed-back from selected ones of the multistages. The clock signal controls the shifting of pulses through the stages of the shift register. The pseudo-random binary bit sequen e of pulses is 10 generally taken from the last stage of the shift r~gister.
In a single channel phase shift keyed modula~ed system, a binary signal will control a ph~se modulator in two pha~es; one " .
phase ~or a binary "0" and another phase for a binary "1"~ -Therefore, the sequence of pulse~ from the PN sequence generator 10 are two phase (20) in functionO The particular sequence of bits generate~ by the PN sequence provides the transmitter with a partirular "sig~ature" of its own, that is, a recei~er will not be able to demodulate a data signal that is mixed wl~h ~he "signature" signal unless the "~ignature" sig~al is first known 20 to the receiver.
E~coder 12 converts the 20 pseudo~random binary pulse se-quence into a pseudo-random 40 ~equence. Thls is accomplished by causing every even positioned bit from the p~eudo-sequence to ~ appear at ter~inal ~ and every odd positioned bit to appear at - termin~l C. The slgnal at terminal B will therefore be a binary - sign~l ~2~) the bits o~ which represent the "even" blts o the pseudo-random ~equence; while the signal at termi~al C will be a ~ binary ~ignal (2~), the bits of which represent the "oddl' bits i of the pseudo-random sequence. This particular encoding technique enables a 40 modulation of a carrler 8ign31; therefore the en~
coding ls called a Zp to 40 encodlng. The (binary) data to be transmitted i8 applied, in ~erial form, to the input terminals _ 4 ~
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of EXCLUSIVE-OR gates 13 and 15. The B terminal output of en-coder 12 is applied to an input of the EXCLUSIVE-OR gate 13 with the C terminal output of encoder 12, being applied to an input of the EXCLUSIVE-OR gate 15 0 The output of EXC W SIVE~02 gate 13 will be the serial data input signal gated ~mixed) as a function of the signal appearing at terminal B; with the output signal from the EXCLUSIVE-OR gate 15 being the serial input data signal gated as a function of the signal appearing at terminal CO These two gated ~ignals are used to phase shift key modulate a local carrier signal.
A local oscillator 20 provlde~ a carrier signal, which ear-rier slgnal is ed to a 90 hybrid circuit 22. The hybrid cir-cuite 22 splits the carr~er signal into two slgnals, the phases of which are shifted 90 and 0 with respect to the ph~se of the carrier signal from the local oscillator 200 The 90 signal is fed to an input of a phase modulator 17. The phase modulator 17 also rece~ves as a modula~ing i~put signal th~ output s~gnal from the ~XCLUSIVE-OR gate 130 In response to the modulating signal from th~ EXCLUSIVE-OR gatP 13, phase modulator 17 modu- . .
lates the phase ~f the 90~ phase shifted carrier signal between 90 and 270 according to the level of the modulating signal~ -The 0 phase ~hifted carrier signal i8 applied as an lnput to the phase modulator 19 along with the output slgnal from the ; EXC W SIVE-OR gate 150 The signal from the EXCLUSIVE~OR gate 15 : :
is a modulating signal that modulates the 0 phase shifted car-ri~r signal between ~he phases 0 and 180 a~cording to the level of the modulating signalO The phase modulated output si~nal from the pha~e modulator 17 i~ summed with the pha~e modulated output slgnal from the phase modulator 19 by ~he summer 23 to provide a four-phase ~hase shift keyed modu~ated (PSK) signal. The ~ummer 23 i8 used to obtain a voltage that i~ proportional to the sum of Reveral input voltages. A summing amplifier of the type ~ 5 .. .
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disclosed in "Electronic Analog Computers", by Korn and Korn, McGraw Hill, 1952, page 14, may be used for summer 23. The four-phase PSK modulated carrier signal from summer 23 is fed to a bandpass filter 25, which filter removes ouit of band signal com~
; ponents. The output signal from the bandpass filter 25 is then fed to a transmitter sec~ion 26 for transmission over a communi~
cation link to a receiver.
; In summary, a pseudo random bit sequence is 40 encoded to provide a wideband signal, which signal is comb~ned with a rela-10 tively narrow ba~dwidth digi~al data signal to form modulating signals. The modulating signals are applied to a 40 modulator wherein a carrier signal is phase shift keiyed modulated to pro-vide a spread spectrum signal hav~ng a wideband width and a low :~
power-density.
Recovery of the narrow bandwidth digital data signal from a received spread spectrum sigDal requires a correlation between .; the exact replica of the wideband modulating signals and the re-ceived spread spec~rum signal.
; One ~ype of optimum receiver for a spread spectrum signal is a receiver which utilizes a matched filterO
` A ma~ched filter is deined as a filter having a transer function which is the complex conjugate o~ the spectrum of the signal to which it is matched.
The receiver o~ the present invention utilizes a ma~ched filter of the ~urface wave type to detect the spread spectrum ' 8ig~1-'J~ Referring now to Fig. 2 a receiver 30 receives the modulated four-phase wideband 8ignal and forwards the received signal to a ., bandpa~s filter 31. The bandpass filter removes those undesirable signRl components which all outside of the band of frequencies of interest. The owtput signal from the bandpass filter is fed to a correlator 33 whierein the wldeban~width (spread) of the re-..
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ceived signal is narrowed (collapsed). Within the correlator a 90 hybrid circuit 32 splits the rece~ved PSK four-phase modu-lated wideband signal into two identical signals, one having a 90 phase shift from the received signal and the other having a 0 phase shift. The 0 phase shifted signal is applied to an input of a phase detector 34. The 90 phase shifted signal is applied to an input of a phase detector 36. Phase de~ector 34 also receives, as a local demodulation signal, the signal pre-sent at the terminal Bl~ of a 20 t9 40 encoder 43. The phase detector 36 also receives as a demodulating signal the signal Cl from the 2p to 40 converter 43. Each of the phase detector~ pro-vides an output signal which is a function of the phase correla-tion between the signals received at ~heir inputs. Th~ ~ to 4 converter 43 receives, ~s an input signal, a pseudo-random binary bit sequencP which is genera~ed by a PN generator 35. The se-quence generated by generator 35 is identical to the sequence generated by the P~ sequence generator 10, shown in Fig. 1. The output signals from phase ~etectors 34 and 36 are summed ~ogether in a summing circuit 38 to provide a 20 narrow band IF signal.
The 2~ narrow band signal is th~n applied to a bandp~ss amplifier 37 wherein undesired signal components falling outside of the pass band are removedO The output signal from the bandpass am-plifier 37 is fed to a m2tc~ed ~ilter 39. The matched filter 39 i8 designed to have an impulse response which is the time-r~verse of the transmitted baseband signal. The output signal from the matched filter 39 is fed to an ampli~ier 40 which amplifier adds signal gain. The output signal ~rom ~plifier 40 i5 fed to a PN . :
timing recovery loop 48 and to a carrier recov~ry phaselock loop : 42. The output signal from the carrier recovery phaselock loop 30 i8 directed to a bit timing loop 44 and to a sample and hold cir-cuit 46. The bit timing loop 44 provides an output signal which is a unction of the bit timing and which 5ignal controls the . .
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sampling ~ime of the sample and hold circuit 46. The bit tlm~ng sign~l is also directed to the PN timing recovery loop 48 ~o pro-vide a synchronizing signal for deriving a PN timlng ~ignal. The output of the sample and hold z~rcult 46 is the recovered d~a signalO
. The output signal from the PN timi~g recovery loop 48 is directed to the local PN sequence generator 35 so as to cause the synchronization of the locally generated PN sequence with the se- -: quence contained in the received four-phase PSK wideband signal so as to provide the correla~or 33 with the correct demodulation s igna ls 4 A phase d~ther circu~t 45 recelves a co~trol signal, and the recovered timing (clock~ ~ignal from the PN tim~ng re~overy loop 48; and in response to the control sig~al and the clock ~ig-nal "dithers" the local PN sequence to enable the PN timing re~
covery loop 48 to accurately detec~ the phasing of the PN se-. quence. The term "d~thering" is applied to a signal condition~
.~ where~n a s~gnal is oscillated slightly about a locked or null ! pOS ltionO
.~, ~ 20 In Fig, 3 there i~ shown one preferred embodiment of the matched filter 390 The matched filter is constructed utiliz~ng a number of surace ~ccustic wave (SAW) devices. The present sy~tem requlres an impulse response of lOQ microseconds duration to a 7~MHz RF carrier pulse. The particul~r approach taken ls to divide the prop2gAtion path length into 5 parts, each 20 micro-seconds longO The flrst device is a ~urface wave tapped delay line 51 which receives the signal ~rom the bandpass amplifier 370 '1 The output sign~l from the tapped delay line 51 is fed to four iserially connected fixed delay lines (FDL) labeled FDLl through ~ ~ .
.~30 FDLho The output 8ignal from the tapped de~ay line 51 and each : :
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~iof the fiKed delay lines are connected by means of current :~
;amplifier~ Il to 15, ~o an outpu~ line 57. The amplifiers .. ..
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Al, A2, A3, A4 ~nd A5 connected between success~ve fixed d~lay lines compensate or the insertion losses encountered in each of the delay lines.
F~gso 8a to 8g show the relationships of the waveforms pre sent at the input of the matched filter, the output of each amp-lifier, Al to A5, and ~hP output line 57 of the matched filter.
A CW (continuous wave) burst of energy, Fig. 8a, is applied to the surface wave tapped delay line 51. The ~apped delay line 51 is a 20us long matched fllter th~t delays the CW burst by 10 20us. ~ach of the fixed delay lines ~DLl to FDL4 delay the ~ig-nals at their respective inputs by 20us, (Figs. 8b to 8f). The addition of all the amplifier ou~pu~s at line 57 results in the :
response shown in Fig. 8g, which response is the desired matched filter response of lOOus. A m~re deta~led description of match-ed filters can be found in the publicatio~ entitledj "Cascaded SAW M~tched Filter", by R. S. Gordy et al., l974 Ultrasonics Symposium Proceedings, IEE cat. ~74 C~0 896-ISU, pages 386-3880 ~ ~ .
Referring now to Fig. 4 wherein there is shown one preferred embodiment of a P~ timing recovery loop 48; an envelope detector 60 is connected to receive the signal present at the output of the ~mpl~fier 40 ~n order to provide an output sign~l which is a ~: function of the envelope of the signal at lts ~nput. The detect-ed en~elope signal is fed to a bandp~ss filter 61 for the elimi- -nation of signal co~ponents outside of the pass band of the ilter. The data PSK signal appears ~hen the local PN sequence is within ~l b~ud period of the received PN seque~ce. Fig. 9 illu~trates this relationship. The amplitude of ~he envelope ;
:- signal in ~ig. 9 decrea~es ~ubstantlally as the phase difference between the loca 1 PN sequence and the received PN sequence in- . --creases towards ~l baud period. The filtered sign~l from filter 61 is rectified by a rectifier 62. The rectified signal from rectifier 62 ~8 low pass filtered by the low pass filter 64 to ;~
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provide a D.C. signal which is relatively free of high frequency signal components. The threshold detector 65 prnvides a con- :
trolling outpu~ signal to an FET switch 66, when the level of the D.C. signal from th~ low pass filter 64 is above a predetermined level. Terminal E of said switch is connected to terminal G
under con~rol of th~ signal from the threshold detector 65. The predetermined level is set so that when the same level is reached in the rectifier 62 output, which level occurs when the local PN
sequence is with~n one baud period of the rece~ved PN sequence, the threshold detector will provlde the controlling output sign~l~
When the FET switch 66 is in the position labeled G the signal from the envelope detector 60 is used ~o control a VC0 (voltage : controlled oscillator) 70~ The ~C0 70 provides a squ~re wave (CLOCK~ signal. The rate (frequency) of which is a function of the level of the signal present at the input to the VCO.
The signal from the env,olope detector 60 is also applied to an ~mplifier 72~ the output of which is eonnectable by means of an FET switch 73 to either the input of a summer 75, to the input ~ -of an i~verter 74 or to the open terminal No The waveforms at the output of amplifier 72 for an in-lock condition and an out-of-lock condition c~n be seen ~n Figs. lOg and lOh, respacti~rely. The output of ~he inverter 74 is directed to an input of ~he summer 75O The output signal rom summer 75 shown in Fig. lOi is directed to a compen~ating loop filter 76, :
which fllter i designed to provide closed loop stability to the 8y8tem, The output signal from the loop ilter 76 is d-lrec$ed to the ~ termi~al of the FET switch 66~ The ~ terminal o~ the FET switch i8 connected to a potentiometer 68 which potentiome~er -~
., may be adjusted to provlde a p~rtlcular voltage, of a D.C. level, ;~, 30 which voltage is used to provide a forced change ln the rate of the VC0 output signal. Ter~in~l E of the FET swit~h 66 lg con-nected to the input of the VC0 70 to allow ~he voltage appearing . ~ , .
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on termi~al E to drive the VCO. The output CLOCK signal from VCO 70 is applied ~o the phase di~her circuit 45 and to the clocking input of the PN generator 35~
The bit timing loop circuit 44 of Figo 2 provides a data clock signal to the PN timing recovery loop 48. The rate and the synchronization of the data clock signal corresponds to the data rate of the received PSK carrier modulated signal. The data clock signal $s applied to the input of a div~de~by-four circuit 78. This waveform is shown in Figo lOa. The NOR ga~e : 10 79 receives as one input the data clock sign~l. The NOR gate 79 also receives as an input the noncomplement of the signal cor-responding to the data clock rate t~vlded-by-four, which signal ~s provided by the div~de-by-four circuit 78. The NOR ga~e 80 receives as its other input the complement of the data clock signal divided by four. The complement signal from the divide-by-four c~rcuit is also directed, as a control signal, to the phase dither network 45. This waveform can be seen in Fig. lObo The output signals from the NOR gates 79 and 80 drive one shot ~; multivibrator~ 79a and 80a which send ou~ a n~rrow pulse for . 20 every po~ltive edge input slgnal th~y receive, In comparing . Fig. lOc with ~lg. lOe it c~n be seen that the positive leading edge of each pulse shown in Fig~ lOc causes a narrow pulse at the output of the one shot multivibr~tor as shown in Figo l~a. The ~' same holds true or the pulses shown in Fig. lOd as compared with - the pulses of Fig. lOf. The ou~put pulses fro~ the one shot 79a set the FET swi~ch 73 to terminal H and the output pulsas from one shot 80a set the ~ET switch to terminal I~
In operation, when the clock~ng ~ignal from the VCO 70 is dr~ving the PN generator 35 at a r~te which is synchro~ized to ~ ~
30 the PN sequence co~tai~ed in the PSK Aignal~ the level o~ the ~ :
slgnal detected by the threshold detector 65 is of such a magni-tude that the FET switch 66 is posltioned at the terminal G.
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This position is considered to be the lock position and the sig-nal from the envelope detector 60 passing through amplifier 72, switch 73, summer 75 and loop filter 76, will then control the output signal fr~m the VC0 70. In this lock position, ~ET switch 73 separates the amplitude variations caused by the dithering of the local P~ sequence into two signals which appear at terminals H and I of FET switch 73. The slgnal at terminal H has an ampli-tude which i~ the effect of the local PN being dithered to one direction and the amplitude of t~e signal at terminal I is the effect of the local P~ being dlthered in the opposite dlrection.
Fig. 9 shows amplitude and phase relationships caused by the dithering. The difference voltage of the signals at terminals H and I appears at the output of the ~umm~r 75O This difference voltage is avera~ed in loop filter 76, and the averaged voltage :
ls applied to the VC0 70 control line to direct the VC0 towards a frequency which will correct the phase error between the local and receive PN sequences. In other words, the only c~ange that : ~:
ccurs in the closed loop path, from the envelope detector 60 to .
the VC0 70, occurs when the inverter 74 is toggled ~n and out of 20 the closed loop path by the FET switch 730 Therefore, if at the ;~
input of the ~ummer 75 with the switch 73 in the H position we . .
have, for a locked condition, a signal of ~o2 millivolts, when the switch 73 i8 toggled to I position the summer 75 will re-ceive at its other input a signal of -.2 millivolts. The summer then effectively will see a signal which alternates symmetrical~
ly around a zero reference po~nt 2t a rate determined by the toggllng rate of the FET switch 73. The average voltage of ~his signal will therefore be zero when the ph~se difference between the received PN sequence and the local gener~ted PN sequence is zero. When the VC0 70 receives a zero level signal on its input it does not ~hange ~ ts output slgDal.
The waveform of Fig. lOh shows a change from the wave~orm .
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of Fig. lOg which change is cau~ed by a slight phase error. This phase error causes a change in the amplitude of the signals pass-ed by the summer. For the particular condition shown, the phase errOr is such as to change the ampli~ude of the samples passed when the one shot 79a is actlvated. As a result, the amplitudes ~ -of the negative-going pulses shown in Figo lOi are less than the amplitudes of the positive-going pulses. An averaging of these pulses in the loop fllter 76 will re~ult in a positive sign~l which signal when applied to the VCO 70 will drive the VC0 in a direction which will tend to drive the phase error towards zero.
If the phase error lncreases to a point where lock is complete ly lost then the FET switch 66 does not receive a signa1 of suf-ficient magnitude from the threshold detector 65, and terminal E
is therefore sw~tched to the position lndicated by terminal F.
Lock will be lost when, referring back to Fig. 9, the phase dif-ference between the local PN sequence and the received PN se-quence decreases the amplitude of the envelope detected waveform below the predetermined level set by the threshold detector 65.
In this position the D.C. voltage provided by the potention~ter 68 causes the PN generator 35 to change its output rate to search for a position which will allow the threshold de~ector to be ac~ivated. The Do C~ sweep voltage is coupled from the FET
switch 66 to the input o~ the VC0 70. The D.C. voltage cau~es the VC0 to change its rate in proportion to the level of the ~OC.
voltage. In turn, the output of the V~0 changes the rate of ~he signal provided by the PN generator 35O
Re~erring now to Figo S wher~in the phase dither circuit 45 and the 20 to 4~ converter circuit 43 are 3hown; the clock sig-nal from the PN timing recovery loop 48 is applied to the K
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terminal of an FET switrh 82. Terminal K is toggled between ; terminal L and terminal M by mean~ of a control signal from the PN recovery loop 48. Terminal L of t~e ~ET switch 82 is ... ...
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'7'~' connected ~o an input of an O~ gate 84. Terminal M i6 connected by means of a fixed delay network 83 to the other inpu~ of the OR gate 84. The output of the OR gate 84 is fed to the clocking termlna l of a D -type f lip-f lop 86 . The Q output of f lip-f lop 86 is fed back to the D input. The Q output of flip-flop 86 is con-nected to the clocking input of a D-type flip~flop 87. The Q
output of flip-flop 86 is also connected to the clocking input of a D-type fllp-flop 88. The D inputs of flip~flops 87 and ~8 are o~nected to the output of the PN generator 35. A D-type flip-flop is one in which the signal present a$ the data input D appears at the Q output, after the occurrence of a particular - clocklng transition, and re~ins at the Q output until the occur-rence of the next like clocking transltion. In effect wha~ is occurrlng is that the signal from the PN generator 35 is being controllably ~ated to the output terminals labeled Cl and Bl, ` alternately, so that the two phase P~ sequence is being d~vided `, into two separa~e channels of two phase data. With ~he transi-tion of data being of a binary natura, ~n which each of the two levels represents a dlfference phase. The fact that there are 20 now two signals each havlng ~wo phases essentially converts ~he ~ .
two phase PN sequence into a four phase sequence. The phase dither network periodically introduces a fixed delay into the clock slgnal from the PN timing reco~Jery loop 48 so as to dither ~che slgnals at the terminal~ Cl and Bl, ~..
Referring naw to Yig. 6 wherein the block diagram of ~he c~rrier recovery phaselock loop 42 of Flg. 2 iæ shown; the signal from the ampllf~er 40 is applied to the inputs of phaqe detactors 91 and 94. A voltage controlled oscillator 95 in response to a s control signal from a de~ector and loop ilter circuit 96 pro-. 30 vides a carrier 8ignal to the phase shift ne~work 93. The phaæe ; shift network 93 provides two output sign21s, one o which is shifted ~45 ~n phase with respect to the signal from the YCO 95, ,....................................................................... .
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an~ the other of which is shifted -45 in phase~ The phase de-tectors 91 and 94 each provide an output slgnal, the D.C. level of which is a function of the phase difference between the sig-nal received from the phase shift network 93 and the signal re-ceived rom the amplifier 400 This difference signal is applied as an input to the detector and loop filter circuit 96. The circuit 96 compares these signals to provide the control signal for the VC0 95 which con~rol signsl drives the VC0 in a par-ticular direction so as to minimize the phase difference between the inpu~ ~ign31s to the respective phase detectors. In addi-tion, the detec~or and loop filter circult 96 provides the base- \
band data signal to the bit timing loop 44 and to the sample and hold circuit 46.
In ~lg. 7 there is illustrated a particular detector and loop filter circui~ which may ~e used for the circuit 96 shown ~ ~:
in ~ig. 6. The slgnal~ from the phase detectors 91 and 94 are fed to low pass filters 98 and 99, r~spectively. The filtered output signal from the low pass filter 98 is the baseband data ~ig~19 which signal is fed to the blt timing loop 44 and the ~ample and hold circuit 46 and also to the i~put of a phase de-tec~or 100. The filtered signal from ~h low pass filter 99 is amplitude llmited in a limites 101 to form a square wave signal hav~ng ~ high ~ta~e and a low state. The phase detector 100 re- :
spond3 to the squ~re wave ~ignal from lOl by passing the sig~al ~rom the low pas~ filter 98 when the square wave signal is in its high st~te and by inverting a~d passing the signal from the low pa8~ filter 98 when the square wave signal is in its low state. The ou~put s~gnal from the multiplier 100 is direc~ed to a loop filter 102. The loop filter 102 ha~ a transfer function 30 ~imped~nce characteristic) which i8 desig~ed to equalize the re- -spon~e of the carrier recovery phaselock loop 42 80 as to facil-: itate locking of the signal~ from the phase ~hift network to the ,~
: - 15 -carrier of the received ~gna~ro7 amplifier 40. The equalized signal from the loop filter 102 is applied as ~he control signal to the VC0 95O
Figures lla to lld set forth the generalized waveforms as-sociated wlth spectrums of spread and unspread signals, In Fig.
: 1 ~f the signal transmitted by the transmitter TX26 is not spread in spectrum, it will have a frequency spectrum of the type shown in Figo llaO With spectrum spreading, ~he signal from TX26 will be of the type shown in Fig. llb~ Fig. llc illustrates the sig-nals present at the input of the receiver RX30, shown in Fig~ 2, when a spread spectrum PSK signal i~ received along with a jam-ming signal. The ~amm~ng signal has a frequency which is ~atched to the frequency of the non-spread PSX signal. In normal receiv-er operation the jamming signal would effectlvely prevent intel~
ligent detection of the non-spread PSK ~ignal. Wlth spectrum spreading ~he correlator 33 is able to spread the spectrum of the jamming signal and to collapse the spec~rum of the PSK signal.
The results are ~hown in Fig. lld. The energy of the PSK signal is ~uch that lt ~an be detected even though the jamming signal is presentO
Wh~le the system and apparat~s hereof accomplishes the ob-jects and adYantages mentioned, certain variations may ocour to those skilled in the art and it is contemplated that all such - variatlon~ not departing from the spiri~ and scope o the lnven-tion hereof are to be construed in accordance with the following claims .
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... , ., . .. :: :
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Spread spectrum communication systems utilize a transmis-sion bandwidth many time~ as large as the information bandwidth in order to achieve jam re~istance. Additional advantages in~
clude multipath signal rejection and a low probability of detec-tionO A ~pread spe~trum transmitter generates a data modulated ln signal, which signal h~s its energy spread over a frequency band considerably wider than the data rate. Generally a PN sequence `~ is used to modulate the phase of the carrier signal. Within the receiver there is usually provided a matched filter, which filter is designed to have an impulse response which is the time-reverse -~ of the transmitter's ou~put waveform. The matched fllter thus provides a match between the transmitted waveform and the re-ceiver's response. ~tched filters that utilize surface acoustic wave devices (SAW's) have been used in spread spectrum data transmission sy~temsO
Two publicat~ons of interest for purposes of establishing i~ the state of the art are "5urface Acoustic Wave Devices And Ap-pllcations" by D. P. Morgan, Ultrasonics, May 1973, pages 121-128;
and "Surface Acous~ic Wave Device~ And Appllcations (Spread Spectrum Processors)" by B. J. Hunsinger, ~ltrasonic~, November 1973, pages 254~263.
In the spread spectrum demodula~or of the present inv~ntion there is provided a correlator for phase shift~ng a four-phase w~deband PSK modulated signal in response ~o a local ~N sequence in order to provide a two-phase narrow band signal. The two-phase signal i8 applled to a matehed filter, the output of which is an IF signal, The IF signal is then applied to a carrler re~
, covery phaselock loop whereln demodulation takes place to provide .~' ..
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a baseband data slgnal. A bit timing loop and a sample and hold circuit operate upon the baseband data signal to reconstruct the information data. A PN timing recovery loop also receives the IF
signal from the matched filter along with a clocking signal from the bit timing loop to provide a synchronizing sign~l to the local PN sequence generator. Improved demodulation is achieved by positioning the matched filter prior to the carrier recovery phaselock loop and by transmi~ting the wideband signal in four~
phase and by converting it early in the recei~er into a two~ph~se narrow band signalO
More specifically, in the preferred embodiment of the in~en-tion there is provided a carrier signal generator and a modulat-ing device responsive to a binary information sign~l for spread spectrum modulating the generated carrier signal. Additionally~
there is provided an apparatus for transmitting the spread spec-trum modulated carrier signal and an apparatus for receiving and collapsing the spread spectrum of a received spread spectrum modulated earrier signal to provide a non-spread spectrum modu-lated signal. A matched filter responsive to the non-spread spectrum modulated carrier signal provides an intermediate sig-nal which contains the modulation components of ~he binary in-formation ~ignal. A carrler recovery cirruit responsive to the intermediate signal from the matched filter provldes a baseband ~ign~l, An apparatus i5 provided or detecting the blnary in~or-' mation ~ignal from ~he baseband 8ignalO
i From the foregoing it can therefore be seen that it is a primary object of the present ~nvention to provide an improved spread ~pectrum demodulator.
It i~ another object of the present invention to provide a spread spectrum demodulator wherein ~ four-phase wideband signal is changed to a two-phase narrow band ~ignal early in the demodu-lation process.
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'7'7 These and other objects of the present invention will be-come more apparent when taken in conjunction with the following description and drawings where~n like characters indicate like parts and which drawings form a part of the present disclosure.
Fig. 1 illustrates in block diagram form a spread spectrum modulator which may be utilized with the present invention;
Fig. 2 lllustrates in block diagram form the preferred em-bodiment of the invention;
Fig. 3 ~llustrates in block diagram form a matched filter which may be utilized with the preferred embodiment of Figo 2;
:. Fig. 4 illustrates in block diagram form the PN tim~ng re-covery loop control circuitry which may be u~ilized in the pre-ferred embodiment of Fig. 2;
Fig. 5 lllu~trates ~n a detailed block diagram form two of the blocks associated wi~h the preferred embodiment of Fig. 2;
Figo 6 illustrates in block diagram form a carrier recovery : ~ :
phaselock loop whlch may be used in the preferred e~bodiment of . ~g. 2;
Fig. 7 illustrates in block diagram form a portion of the c~rrier recovery phaselock loop shown in Figo 6;
Flgs, 8~ to 8g illustrate waveforms which oczur at selected points in the device shown ~n Fig. 3;
Flg. 9 illustrates waveform~ u~eful in understanding the operation of the preferred embodiment o the inYention shown in Flgo 2, Fig~. lOa to lOc illustrate waveforms whlch occur in Fig. 4;
and ~ .
Figs. lla to lld illustrate ln chart form signal frequency ~
spectrums whlch spectrums are useful in under~tanding the opera- . . .
. 30 tion of ~he inventlon.
In ~igo 1 there i8 disclosed ~he modulatlng por~ion of a data modulated transmission system, of the spread spectrum type, ;,., ' ' .
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which system codes an information slgnal in a par~icular format and utilizes the encoded information signal to spread spectrum modulate a ~arrier signal. A PN sequence generator 10~ in re-sponse to a clock signal, provides a pseudo-random bLnary bit sequence of pulses to an encoder 12. The PN sequence genera tor 10 may be, for example, a multistage shift register having feed-back from selected ones of the multistages. The clock signal controls the shifting of pulses through the stages of the shift register. The pseudo-random binary bit sequen e of pulses is 10 generally taken from the last stage of the shift r~gister.
In a single channel phase shift keyed modula~ed system, a binary signal will control a ph~se modulator in two pha~es; one " .
phase ~or a binary "0" and another phase for a binary "1"~ -Therefore, the sequence of pulse~ from the PN sequence generator 10 are two phase (20) in functionO The particular sequence of bits generate~ by the PN sequence provides the transmitter with a partirular "sig~ature" of its own, that is, a recei~er will not be able to demodulate a data signal that is mixed wl~h ~he "signature" signal unless the "~ignature" sig~al is first known 20 to the receiver.
E~coder 12 converts the 20 pseudo~random binary pulse se-quence into a pseudo-random 40 ~equence. Thls is accomplished by causing every even positioned bit from the p~eudo-sequence to ~ appear at ter~inal ~ and every odd positioned bit to appear at - termin~l C. The slgnal at terminal B will therefore be a binary - sign~l ~2~) the bits o~ which represent the "even" blts o the pseudo-random ~equence; while the signal at termi~al C will be a ~ binary ~ignal (2~), the bits of which represent the "oddl' bits i of the pseudo-random sequence. This particular encoding technique enables a 40 modulation of a carrler 8ign31; therefore the en~
coding ls called a Zp to 40 encodlng. The (binary) data to be transmitted i8 applied, in ~erial form, to the input terminals _ 4 ~
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~ 6 ~
of EXCLUSIVE-OR gates 13 and 15. The B terminal output of en-coder 12 is applied to an input of the EXCLUSIVE-OR gate 13 with the C terminal output of encoder 12, being applied to an input of the EXCLUSIVE-OR gate 15 0 The output of EXC W SIVE~02 gate 13 will be the serial data input signal gated ~mixed) as a function of the signal appearing at terminal B; with the output signal from the EXCLUSIVE-OR gate 15 being the serial input data signal gated as a function of the signal appearing at terminal CO These two gated ~ignals are used to phase shift key modulate a local carrier signal.
A local oscillator 20 provlde~ a carrier signal, which ear-rier slgnal is ed to a 90 hybrid circuit 22. The hybrid cir-cuite 22 splits the carr~er signal into two slgnals, the phases of which are shifted 90 and 0 with respect to the ph~se of the carrier signal from the local oscillator 200 The 90 signal is fed to an input of a phase modulator 17. The phase modulator 17 also rece~ves as a modula~ing i~put signal th~ output s~gnal from the ~XCLUSIVE-OR gate 130 In response to the modulating signal from th~ EXCLUSIVE-OR gatP 13, phase modulator 17 modu- . .
lates the phase ~f the 90~ phase shifted carrier signal between 90 and 270 according to the level of the modulating signal~ -The 0 phase ~hifted carrier signal i8 applied as an lnput to the phase modulator 19 along with the output slgnal from the ; EXC W SIVE-OR gate 150 The signal from the EXCLUSIVE~OR gate 15 : :
is a modulating signal that modulates the 0 phase shifted car-ri~r signal between ~he phases 0 and 180 a~cording to the level of the modulating signalO The phase modulated output si~nal from the pha~e modulator 17 i~ summed with the pha~e modulated output slgnal from the phase modulator 19 by ~he summer 23 to provide a four-phase ~hase shift keyed modu~ated (PSK) signal. The ~ummer 23 i8 used to obtain a voltage that i~ proportional to the sum of Reveral input voltages. A summing amplifier of the type ~ 5 .. .
~ 3~
disclosed in "Electronic Analog Computers", by Korn and Korn, McGraw Hill, 1952, page 14, may be used for summer 23. The four-phase PSK modulated carrier signal from summer 23 is fed to a bandpass filter 25, which filter removes ouit of band signal com~
; ponents. The output signal from the bandpass filter 25 is then fed to a transmitter sec~ion 26 for transmission over a communi~
cation link to a receiver.
; In summary, a pseudo random bit sequence is 40 encoded to provide a wideband signal, which signal is comb~ned with a rela-10 tively narrow ba~dwidth digi~al data signal to form modulating signals. The modulating signals are applied to a 40 modulator wherein a carrier signal is phase shift keiyed modulated to pro-vide a spread spectrum signal hav~ng a wideband width and a low :~
power-density.
Recovery of the narrow bandwidth digital data signal from a received spread spectrum sigDal requires a correlation between .; the exact replica of the wideband modulating signals and the re-ceived spread spec~rum signal.
; One ~ype of optimum receiver for a spread spectrum signal is a receiver which utilizes a matched filterO
` A ma~ched filter is deined as a filter having a transer function which is the complex conjugate o~ the spectrum of the signal to which it is matched.
The receiver o~ the present invention utilizes a ma~ched filter of the ~urface wave type to detect the spread spectrum ' 8ig~1-'J~ Referring now to Fig. 2 a receiver 30 receives the modulated four-phase wideband 8ignal and forwards the received signal to a ., bandpa~s filter 31. The bandpass filter removes those undesirable signRl components which all outside of the band of frequencies of interest. The owtput signal from the bandpass filter is fed to a correlator 33 whierein the wldeban~width (spread) of the re-..
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ceived signal is narrowed (collapsed). Within the correlator a 90 hybrid circuit 32 splits the rece~ved PSK four-phase modu-lated wideband signal into two identical signals, one having a 90 phase shift from the received signal and the other having a 0 phase shift. The 0 phase shifted signal is applied to an input of a phase detector 34. The 90 phase shifted signal is applied to an input of a phase detector 36. Phase de~ector 34 also receives, as a local demodulation signal, the signal pre-sent at the terminal Bl~ of a 20 t9 40 encoder 43. The phase detector 36 also receives as a demodulating signal the signal Cl from the 2p to 40 converter 43. Each of the phase detector~ pro-vides an output signal which is a function of the phase correla-tion between the signals received at ~heir inputs. Th~ ~ to 4 converter 43 receives, ~s an input signal, a pseudo-random binary bit sequencP which is genera~ed by a PN generator 35. The se-quence generated by generator 35 is identical to the sequence generated by the P~ sequence generator 10, shown in Fig. 1. The output signals from phase ~etectors 34 and 36 are summed ~ogether in a summing circuit 38 to provide a 20 narrow band IF signal.
The 2~ narrow band signal is th~n applied to a bandp~ss amplifier 37 wherein undesired signal components falling outside of the pass band are removedO The output signal from the bandpass am-plifier 37 is fed to a m2tc~ed ~ilter 39. The matched filter 39 i8 designed to have an impulse response which is the time-r~verse of the transmitted baseband signal. The output signal from the matched filter 39 is fed to an ampli~ier 40 which amplifier adds signal gain. The output signal ~rom ~plifier 40 i5 fed to a PN . :
timing recovery loop 48 and to a carrier recov~ry phaselock loop : 42. The output signal from the carrier recovery phaselock loop 30 i8 directed to a bit timing loop 44 and to a sample and hold cir-cuit 46. The bit timing loop 44 provides an output signal which is a unction of the bit timing and which 5ignal controls the . .
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sampling ~ime of the sample and hold circuit 46. The bit tlm~ng sign~l is also directed to the PN timing recovery loop 48 ~o pro-vide a synchronizing signal for deriving a PN timlng ~ignal. The output of the sample and hold z~rcult 46 is the recovered d~a signalO
. The output signal from the PN timi~g recovery loop 48 is directed to the local PN sequence generator 35 so as to cause the synchronization of the locally generated PN sequence with the se- -: quence contained in the received four-phase PSK wideband signal so as to provide the correla~or 33 with the correct demodulation s igna ls 4 A phase d~ther circu~t 45 recelves a co~trol signal, and the recovered timing (clock~ ~ignal from the PN tim~ng re~overy loop 48; and in response to the control sig~al and the clock ~ig-nal "dithers" the local PN sequence to enable the PN timing re~
covery loop 48 to accurately detec~ the phasing of the PN se-. quence. The term "d~thering" is applied to a signal condition~
.~ where~n a s~gnal is oscillated slightly about a locked or null ! pOS ltionO
.~, ~ 20 In Fig, 3 there i~ shown one preferred embodiment of the matched filter 390 The matched filter is constructed utiliz~ng a number of surace ~ccustic wave (SAW) devices. The present sy~tem requlres an impulse response of lOQ microseconds duration to a 7~MHz RF carrier pulse. The particul~r approach taken ls to divide the prop2gAtion path length into 5 parts, each 20 micro-seconds longO The flrst device is a ~urface wave tapped delay line 51 which receives the signal ~rom the bandpass amplifier 370 '1 The output sign~l from the tapped delay line 51 is fed to four iserially connected fixed delay lines (FDL) labeled FDLl through ~ ~ .
.~30 FDLho The output 8ignal from the tapped de~ay line 51 and each : :
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~iof the fiKed delay lines are connected by means of current :~
;amplifier~ Il to 15, ~o an outpu~ line 57. The amplifiers .. ..
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Al, A2, A3, A4 ~nd A5 connected between success~ve fixed d~lay lines compensate or the insertion losses encountered in each of the delay lines.
F~gso 8a to 8g show the relationships of the waveforms pre sent at the input of the matched filter, the output of each amp-lifier, Al to A5, and ~hP output line 57 of the matched filter.
A CW (continuous wave) burst of energy, Fig. 8a, is applied to the surface wave tapped delay line 51. The ~apped delay line 51 is a 20us long matched fllter th~t delays the CW burst by 10 20us. ~ach of the fixed delay lines ~DLl to FDL4 delay the ~ig-nals at their respective inputs by 20us, (Figs. 8b to 8f). The addition of all the amplifier ou~pu~s at line 57 results in the :
response shown in Fig. 8g, which response is the desired matched filter response of lOOus. A m~re deta~led description of match-ed filters can be found in the publicatio~ entitledj "Cascaded SAW M~tched Filter", by R. S. Gordy et al., l974 Ultrasonics Symposium Proceedings, IEE cat. ~74 C~0 896-ISU, pages 386-3880 ~ ~ .
Referring now to Fig. 4 wherein there is shown one preferred embodiment of a P~ timing recovery loop 48; an envelope detector 60 is connected to receive the signal present at the output of the ~mpl~fier 40 ~n order to provide an output sign~l which is a ~: function of the envelope of the signal at lts ~nput. The detect-ed en~elope signal is fed to a bandp~ss filter 61 for the elimi- -nation of signal co~ponents outside of the pass band of the ilter. The data PSK signal appears ~hen the local PN sequence is within ~l b~ud period of the received PN seque~ce. Fig. 9 illu~trates this relationship. The amplitude of ~he envelope ;
:- signal in ~ig. 9 decrea~es ~ubstantlally as the phase difference between the loca 1 PN sequence and the received PN sequence in- . --creases towards ~l baud period. The filtered sign~l from filter 61 is rectified by a rectifier 62. The rectified signal from rectifier 62 ~8 low pass filtered by the low pass filter 64 to ;~
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provide a D.C. signal which is relatively free of high frequency signal components. The threshold detector 65 prnvides a con- :
trolling outpu~ signal to an FET switch 66, when the level of the D.C. signal from th~ low pass filter 64 is above a predetermined level. Terminal E of said switch is connected to terminal G
under con~rol of th~ signal from the threshold detector 65. The predetermined level is set so that when the same level is reached in the rectifier 62 output, which level occurs when the local PN
sequence is with~n one baud period of the rece~ved PN sequence, the threshold detector will provlde the controlling output sign~l~
When the FET switch 66 is in the position labeled G the signal from the envelope detector 60 is used ~o control a VC0 (voltage : controlled oscillator) 70~ The ~C0 70 provides a squ~re wave (CLOCK~ signal. The rate (frequency) of which is a function of the level of the signal present at the input to the VCO.
The signal from the env,olope detector 60 is also applied to an ~mplifier 72~ the output of which is eonnectable by means of an FET switch 73 to either the input of a summer 75, to the input ~ -of an i~verter 74 or to the open terminal No The waveforms at the output of amplifier 72 for an in-lock condition and an out-of-lock condition c~n be seen ~n Figs. lOg and lOh, respacti~rely. The output of ~he inverter 74 is directed to an input of ~he summer 75O The output signal rom summer 75 shown in Fig. lOi is directed to a compen~ating loop filter 76, :
which fllter i designed to provide closed loop stability to the 8y8tem, The output signal from the loop ilter 76 is d-lrec$ed to the ~ termi~al of the FET switch 66~ The ~ terminal o~ the FET switch i8 connected to a potentiometer 68 which potentiome~er -~
., may be adjusted to provlde a p~rtlcular voltage, of a D.C. level, ;~, 30 which voltage is used to provide a forced change ln the rate of the VC0 output signal. Ter~in~l E of the FET swit~h 66 lg con-nected to the input of the VC0 70 to allow ~he voltage appearing . ~ , .
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on termi~al E to drive the VCO. The output CLOCK signal from VCO 70 is applied ~o the phase di~her circuit 45 and to the clocking input of the PN generator 35~
The bit timing loop circuit 44 of Figo 2 provides a data clock signal to the PN timing recovery loop 48. The rate and the synchronization of the data clock signal corresponds to the data rate of the received PSK carrier modulated signal. The data clock signal $s applied to the input of a div~de~by-four circuit 78. This waveform is shown in Figo lOa. The NOR ga~e : 10 79 receives as one input the data clock sign~l. The NOR gate 79 also receives as an input the noncomplement of the signal cor-responding to the data clock rate t~vlded-by-four, which signal ~s provided by the div~de-by-four circuit 78. The NOR ga~e 80 receives as its other input the complement of the data clock signal divided by four. The complement signal from the divide-by-four c~rcuit is also directed, as a control signal, to the phase dither network 45. This waveform can be seen in Fig. lObo The output signals from the NOR gates 79 and 80 drive one shot ~; multivibrator~ 79a and 80a which send ou~ a n~rrow pulse for . 20 every po~ltive edge input slgnal th~y receive, In comparing . Fig. lOc with ~lg. lOe it c~n be seen that the positive leading edge of each pulse shown in Fig~ lOc causes a narrow pulse at the output of the one shot multivibr~tor as shown in Figo l~a. The ~' same holds true or the pulses shown in Fig. lOd as compared with - the pulses of Fig. lOf. The ou~put pulses fro~ the one shot 79a set the FET swi~ch 73 to terminal H and the output pulsas from one shot 80a set the ~ET switch to terminal I~
In operation, when the clock~ng ~ignal from the VCO 70 is dr~ving the PN generator 35 at a r~te which is synchro~ized to ~ ~
30 the PN sequence co~tai~ed in the PSK Aignal~ the level o~ the ~ :
slgnal detected by the threshold detector 65 is of such a magni-tude that the FET switch 66 is posltioned at the terminal G.
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This position is considered to be the lock position and the sig-nal from the envelope detector 60 passing through amplifier 72, switch 73, summer 75 and loop filter 76, will then control the output signal fr~m the VC0 70. In this lock position, ~ET switch 73 separates the amplitude variations caused by the dithering of the local P~ sequence into two signals which appear at terminals H and I of FET switch 73. The slgnal at terminal H has an ampli-tude which i~ the effect of the local PN being dithered to one direction and the amplitude of t~e signal at terminal I is the effect of the local P~ being dlthered in the opposite dlrection.
Fig. 9 shows amplitude and phase relationships caused by the dithering. The difference voltage of the signals at terminals H and I appears at the output of the ~umm~r 75O This difference voltage is avera~ed in loop filter 76, and the averaged voltage :
ls applied to the VC0 70 control line to direct the VC0 towards a frequency which will correct the phase error between the local and receive PN sequences. In other words, the only c~ange that : ~:
ccurs in the closed loop path, from the envelope detector 60 to .
the VC0 70, occurs when the inverter 74 is toggled ~n and out of 20 the closed loop path by the FET switch 730 Therefore, if at the ;~
input of the ~ummer 75 with the switch 73 in the H position we . .
have, for a locked condition, a signal of ~o2 millivolts, when the switch 73 i8 toggled to I position the summer 75 will re-ceive at its other input a signal of -.2 millivolts. The summer then effectively will see a signal which alternates symmetrical~
ly around a zero reference po~nt 2t a rate determined by the toggllng rate of the FET switch 73. The average voltage of ~his signal will therefore be zero when the ph~se difference between the received PN sequence and the local gener~ted PN sequence is zero. When the VC0 70 receives a zero level signal on its input it does not ~hange ~ ts output slgDal.
The waveform of Fig. lOh shows a change from the wave~orm .
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of Fig. lOg which change is cau~ed by a slight phase error. This phase error causes a change in the amplitude of the signals pass-ed by the summer. For the particular condition shown, the phase errOr is such as to change the ampli~ude of the samples passed when the one shot 79a is actlvated. As a result, the amplitudes ~ -of the negative-going pulses shown in Figo lOi are less than the amplitudes of the positive-going pulses. An averaging of these pulses in the loop fllter 76 will re~ult in a positive sign~l which signal when applied to the VCO 70 will drive the VC0 in a direction which will tend to drive the phase error towards zero.
If the phase error lncreases to a point where lock is complete ly lost then the FET switch 66 does not receive a signa1 of suf-ficient magnitude from the threshold detector 65, and terminal E
is therefore sw~tched to the position lndicated by terminal F.
Lock will be lost when, referring back to Fig. 9, the phase dif-ference between the local PN sequence and the received PN se-quence decreases the amplitude of the envelope detected waveform below the predetermined level set by the threshold detector 65.
In this position the D.C. voltage provided by the potention~ter 68 causes the PN generator 35 to change its output rate to search for a position which will allow the threshold de~ector to be ac~ivated. The Do C~ sweep voltage is coupled from the FET
switch 66 to the input o~ the VC0 70. The D.C. voltage cau~es the VC0 to change its rate in proportion to the level of the ~OC.
voltage. In turn, the output of the V~0 changes the rate of ~he signal provided by the PN generator 35O
Re~erring now to Figo S wher~in the phase dither circuit 45 and the 20 to 4~ converter circuit 43 are 3hown; the clock sig-nal from the PN timing recovery loop 48 is applied to the K
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terminal of an FET switrh 82. Terminal K is toggled between ; terminal L and terminal M by mean~ of a control signal from the PN recovery loop 48. Terminal L of t~e ~ET switch 82 is ... ...
~ 13 -.. . .
'7'~' connected ~o an input of an O~ gate 84. Terminal M i6 connected by means of a fixed delay network 83 to the other inpu~ of the OR gate 84. The output of the OR gate 84 is fed to the clocking termlna l of a D -type f lip-f lop 86 . The Q output of f lip-f lop 86 is fed back to the D input. The Q output of flip-flop 86 is con-nected to the clocking input of a D-type flip~flop 87. The Q
output of flip-flop 86 is also connected to the clocking input of a D-type fllp-flop 88. The D inputs of flip~flops 87 and ~8 are o~nected to the output of the PN generator 35. A D-type flip-flop is one in which the signal present a$ the data input D appears at the Q output, after the occurrence of a particular - clocklng transition, and re~ins at the Q output until the occur-rence of the next like clocking transltion. In effect wha~ is occurrlng is that the signal from the PN generator 35 is being controllably ~ated to the output terminals labeled Cl and Bl, ` alternately, so that the two phase P~ sequence is being d~vided `, into two separa~e channels of two phase data. With ~he transi-tion of data being of a binary natura, ~n which each of the two levels represents a dlfference phase. The fact that there are 20 now two signals each havlng ~wo phases essentially converts ~he ~ .
two phase PN sequence into a four phase sequence. The phase dither network periodically introduces a fixed delay into the clock slgnal from the PN timing reco~Jery loop 48 so as to dither ~che slgnals at the terminal~ Cl and Bl, ~..
Referring naw to Yig. 6 wherein the block diagram of ~he c~rrier recovery phaselock loop 42 of Flg. 2 iæ shown; the signal from the ampllf~er 40 is applied to the inputs of phaqe detactors 91 and 94. A voltage controlled oscillator 95 in response to a s control signal from a de~ector and loop ilter circuit 96 pro-. 30 vides a carrier 8ignal to the phase shift ne~work 93. The phaæe ; shift network 93 provides two output sign21s, one o which is shifted ~45 ~n phase with respect to the signal from the YCO 95, ,....................................................................... .
" 1~
' '7~
an~ the other of which is shifted -45 in phase~ The phase de-tectors 91 and 94 each provide an output slgnal, the D.C. level of which is a function of the phase difference between the sig-nal received from the phase shift network 93 and the signal re-ceived rom the amplifier 400 This difference signal is applied as an input to the detector and loop filter circuit 96. The circuit 96 compares these signals to provide the control signal for the VC0 95 which con~rol signsl drives the VC0 in a par-ticular direction so as to minimize the phase difference between the inpu~ ~ign31s to the respective phase detectors. In addi-tion, the detec~or and loop filter circult 96 provides the base- \
band data signal to the bit timing loop 44 and to the sample and hold circuit 46.
In ~lg. 7 there is illustrated a particular detector and loop filter circui~ which may ~e used for the circuit 96 shown ~ ~:
in ~ig. 6. The slgnal~ from the phase detectors 91 and 94 are fed to low pass filters 98 and 99, r~spectively. The filtered output signal from the low pass filter 98 is the baseband data ~ig~19 which signal is fed to the blt timing loop 44 and the ~ample and hold circuit 46 and also to the i~put of a phase de-tec~or 100. The filtered signal from ~h low pass filter 99 is amplitude llmited in a limites 101 to form a square wave signal hav~ng ~ high ~ta~e and a low state. The phase detector 100 re- :
spond3 to the squ~re wave ~ignal from lOl by passing the sig~al ~rom the low pas~ filter 98 when the square wave signal is in its high st~te and by inverting a~d passing the signal from the low pa8~ filter 98 when the square wave signal is in its low state. The ou~put s~gnal from the multiplier 100 is direc~ed to a loop filter 102. The loop filter 102 ha~ a transfer function 30 ~imped~nce characteristic) which i8 desig~ed to equalize the re- -spon~e of the carrier recovery phaselock loop 42 80 as to facil-: itate locking of the signal~ from the phase ~hift network to the ,~
: - 15 -carrier of the received ~gna~ro7 amplifier 40. The equalized signal from the loop filter 102 is applied as ~he control signal to the VC0 95O
Figures lla to lld set forth the generalized waveforms as-sociated wlth spectrums of spread and unspread signals, In Fig.
: 1 ~f the signal transmitted by the transmitter TX26 is not spread in spectrum, it will have a frequency spectrum of the type shown in Figo llaO With spectrum spreading, ~he signal from TX26 will be of the type shown in Fig. llb~ Fig. llc illustrates the sig-nals present at the input of the receiver RX30, shown in Fig~ 2, when a spread spectrum PSK signal i~ received along with a jam-ming signal. The ~amm~ng signal has a frequency which is ~atched to the frequency of the non-spread PSX signal. In normal receiv-er operation the jamming signal would effectlvely prevent intel~
ligent detection of the non-spread PSK ~ignal. Wlth spectrum spreading ~he correlator 33 is able to spread the spectrum of the jamming signal and to collapse the spec~rum of the PSK signal.
The results are ~hown in Fig. lld. The energy of the PSK signal is ~uch that lt ~an be detected even though the jamming signal is presentO
Wh~le the system and apparat~s hereof accomplishes the ob-jects and adYantages mentioned, certain variations may ocour to those skilled in the art and it is contemplated that all such - variatlon~ not departing from the spiri~ and scope o the lnven-tion hereof are to be construed in accordance with the following claims .
, . .
~ ' .
.
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Claims (14)
1. A spread spectrum system comprising: means for generat-ing a carrier signal; modulating means responsive to a binary in-formation signal for spread spectrum modulating said generated local carrier signal; means for transmitting the spread spectrum modulated carrier signal; means for receiving and collapsing the spread spectrum of a received spread spectrum modulated carrier signal to provide a non-spread spectrum modulated carrier signal;
a matched filter responsive to said non-spread spectrum modulated carrier signal for providing an intermediate signal which con-tains the modulation components of the binary information signal;
a carrier recovery circuit responsive to the intermediate signal from said matched filter for providing a baseband signal; and means for detecting the binary information signal from said base-band signal.
a matched filter responsive to said non-spread spectrum modulated carrier signal for providing an intermediate signal which con-tains the modulation components of the binary information signal;
a carrier recovery circuit responsive to the intermediate signal from said matched filter for providing a baseband signal; and means for detecting the binary information signal from said base-band signal.
2. The spread spectrum system according to claim 1 where-in said modulating means is comprised of: generator means for generating a random sequence of pulses; encoding means for phase encoding said pulses; combining means for combining the encoded random pulses with said binary information signal to provide modulating signals; and phase modulating means for modulating said generated carrier signal as a function of said modulating signals.
3. The spread spectrum system according to claim 1 where-in said means for collapsing the spread spectrum of the received spread spectrum modulated carrier signal is comprised of: a local generator means for generating a local random sequence of pulses corresponding to the random sequence of pulses contained in the received signal; correlating means operatively connecting 3 (concluded) said local generator means to said means for receiving, for cor-relating said local random sequence of pulses against the random sequence of pulses contained in the received signal to provide a non-spread spectrum modulated carrier signal.
4. The spread spectrum system according to claim 3 and further comprising: means operatively connected to said local generator means for synchronizing said local random sequence of pulses with the random sequence of pulses contained in the re-ceived signal.
5. The spread spectrum system according to claim 1 where-in said matched filter is a surface acoustic wave device.
6. The spread spectrum system according to claim 4 and further comprising: means operatively connected to said local generator means for dithering the synchronizing of said local random sequence of pulses to the random sequence of pulses con-tained in the received signal.
7. A spread spectrum demodulator comprising: means for receiving a four-phase encoded spread spectrum signal; means for converting the received four-phase encoded spread spectrum signal into a two-phase encoded non-spread spectrum signal; matched filter means operatively connected to said means for converting, for filtering said two-phase encoded non-spread spectrum signal so as to filter all but desired signal components from said sig-nal; and carrier recovery means responsive to the filtered sig-nal from said matched filter for demodulating said signal to provide a decoded baseband signal.
8. The spread spectrum demodulator according to claim 7 wherein said matched filter is comprised of a surface acoustic wave device.
9. The spread spectrum demodulator according to claim 7 wherein said four-phase encoded spread spectrum signal is a phase shift keyed modulated carrier signal encoded with a random se-quence of pulses combined with an information data signal and wherein said means for converting comprises: means for generat-ing a local random sequence of pulses corresponding to the random sequence of pulses contained in the received signal; and correlat-ing means for correlating said local random sequence of pulses with the random sequence of pulses contained in the received sig-nal to provide said two-phase encoded non-spread spectrum signal.
10. The spread spectrum demodulator according to claim 9 and further comprising: means for synchronizing said local ran-dom sequence of pulses to the random sequence of pulses contain-ed in the received signal.
11. The spread spectrum demodulator according to claim 10 and further comprising: means for dithering the synchronization of said local random sequence of pulses.
12. A spread spectrum transmission system for processing a binary information signal comprising: means for generating a carrier signal; generating means for generating a pseudo-random sequence of pulses; encoding means for phase encoding said pulses;
mixing means for mixing the phase encoded pulses from said en-coding means with a binary information signal to provide modu-lating signals; phase modulating means for modulating said gen-erated carrier signal as a function of said modulating signals so as to provide a spread spectrum modulated signal; transmitter means for transmitting the modulated signal from said phase modu-lating means; receiver means for receiving the signal transmitted by said transmitter means; second generating means for generat-ing a local pseudo-random sequence of pulses; correlating means having as inputs the received signal from said receiver means and said local pseudo-random sequence of pulses for correlating the input signals so as to collapse the spread spectrum of said received signal; matched filter means responsive to the collapsed spread spectrum signal from said correlating means for filtering undesired signal components from said signal to provide an output signal corresponding to an intermediate signal; demodulation means operatively connected to the output of said matched filter means for de-modulating the intermediate signal to provide said binary information signal;
and timing means responsive to the signals from said matched filter and said demodulation means for providing a control signal to said second generating means to synchronize the local pseudo-random sequence of pulses to the pseudo-random sequence of pulses contained in said received signal.
mixing means for mixing the phase encoded pulses from said en-coding means with a binary information signal to provide modu-lating signals; phase modulating means for modulating said gen-erated carrier signal as a function of said modulating signals so as to provide a spread spectrum modulated signal; transmitter means for transmitting the modulated signal from said phase modu-lating means; receiver means for receiving the signal transmitted by said transmitter means; second generating means for generat-ing a local pseudo-random sequence of pulses; correlating means having as inputs the received signal from said receiver means and said local pseudo-random sequence of pulses for correlating the input signals so as to collapse the spread spectrum of said received signal; matched filter means responsive to the collapsed spread spectrum signal from said correlating means for filtering undesired signal components from said signal to provide an output signal corresponding to an intermediate signal; demodulation means operatively connected to the output of said matched filter means for de-modulating the intermediate signal to provide said binary information signal;
and timing means responsive to the signals from said matched filter and said demodulation means for providing a control signal to said second generating means to synchronize the local pseudo-random sequence of pulses to the pseudo-random sequence of pulses contained in said received signal.
13. The spread spectrum transmission system according to claim 12, wherein said matched filter is a surface acoustic wave device.
14. The spread spectrum transmission according to claim 12 and fur-ther comprising: means operatively connected to said second generating means for dithering the synchronizing of said local pseudo-random sequence of pulses to the pseudo-random sequence of pulses contained in said received signal.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/611,367 US4017798A (en) | 1975-09-08 | 1975-09-08 | Spread spectrum demodulator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1063677A true CA1063677A (en) | 1979-10-02 |
Family
ID=24448742
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA259,770A Expired CA1063677A (en) | 1975-09-08 | 1976-08-24 | Spread spectrum demodulator |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4017798A (en) |
| JP (1) | JPS5233461A (en) |
| CA (1) | CA1063677A (en) |
| DE (1) | DE2640325C3 (en) |
| FR (1) | FR2323271A1 (en) |
| GB (1) | GB1510745A (en) |
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-
1975
- 1975-09-08 US US05/611,367 patent/US4017798A/en not_active Expired - Lifetime
-
1976
- 1976-08-24 CA CA259,770A patent/CA1063677A/en not_active Expired
- 1976-09-02 GB GB36388/76A patent/GB1510745A/en not_active Expired
- 1976-09-06 JP JP51105879A patent/JPS5233461A/en active Pending
- 1976-09-07 FR FR7626850A patent/FR2323271A1/en active Granted
- 1976-09-08 DE DE2640325A patent/DE2640325C3/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE2640325A1 (en) | 1977-03-17 |
| JPS5233461A (en) | 1977-03-14 |
| GB1510745A (en) | 1978-05-17 |
| DE2640325C3 (en) | 1979-03-15 |
| FR2323271A1 (en) | 1977-04-01 |
| US4017798A (en) | 1977-04-12 |
| FR2323271B1 (en) | 1981-08-21 |
| DE2640325B2 (en) | 1978-07-06 |
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