CA1065055A - Charge coupled device systems - Google Patents
Charge coupled device systemsInfo
- Publication number
- CA1065055A CA1065055A CA244,007A CA244007A CA1065055A CA 1065055 A CA1065055 A CA 1065055A CA 244007 A CA244007 A CA 244007A CA 1065055 A CA1065055 A CA 1065055A
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- CA
- Canada
- Prior art keywords
- register
- charge
- stage
- coupled device
- column
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 16
- 238000005036 potential barrier Methods 0.000 claims description 14
- 238000006243 chemical reaction Methods 0.000 claims description 12
- 230000005855 radiation Effects 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 claims 1
- 238000012546 transfer Methods 0.000 abstract description 27
- 239000011159 matrix material Substances 0.000 abstract description 7
- 230000004888 barrier function Effects 0.000 description 7
- 230000005574 cross-species transmission Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 241000272470 Circus Species 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14825—Linear CCD imagers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
- G11C19/282—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
- G11C19/287—Organisation of a multiplicity of shift registers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/34—Digital stores in which the information is moved stepwise, e.g. shift registers using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C19/36—Digital stores in which the information is moved stepwise, e.g. shift registers using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using multistable semiconductor elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
- H01L27/1057—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components comprising charge coupled devices [CCD] or charge injection devices [CID]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/701—Line sensors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
Abstract
Abstract Analog signals initially are stored in a linear array such as a charge coupled device (CCD) register. There is provided, for each stage of the linear array, a different column of a CCD matrix, termed here a B register. During a transfer interval, the analog charge signals concurrently are permitted to flow into the columns. As the stages in the B register have much smaller charge storage capacity than the stages in the linear array, the charge signal fills and then overflows successive potential wells of each column until an equilibrium condition is reached. At equilibrium, the number of filled wells in a column will be proportional to the amplitude of the charge signal supplied to that column by the stage of the linear array coupled to the column. The matrix is read by concurrently sensing all of the signals present in one column, and then doing the same for each following column.
Description
RCA 68,582 1 This application deals generally with analog to digital conversion.
In a preferred form of the invention, analog signals initially are present in a first array. The respective stages of the array are coupled to columns of a second array--a charge coupled device (CCD) matrix, known as a B register. During a transfer interval, the analog signals concurrently are flowed into the columns and, as the stages in the CCD matrix have much smaller charge storage capacity than the stages in the first array, from 0 to n stages of any particular column may become filled depending upon the amplitude of the analog signal for that column. The matrix may be read by concurrently sensing all of the signals present in one column and then doing the same for the following columns.
In the drawing:
FIGURE 1 is a plan view of a portion of a system embodying the invention;
FIGURE 2 is a drawing of surface potential profiles to help explain the operation of the system of FIGURE l;
FIGURE 3 is a schematic showing of the charge present in the A and B registers during different periods of time;
FIGURE 4 is a graph to further help explain the operation of the system of FIGURE l;
FIGURE 5 is a block diagram of a memory embodying the invention; and FIGURE 6 is a block diagram of an imager system embodying the invention.
The system of FIGURE 1 includes a semiconductor .:
RCA 68,582 ~0~5055 1 substrate 10, an A register formed on one portion of the substrate, a CCD matrix of columns and rows, termed a B
register, formed on a second portion of the substrate, and a transfer gate 12 between the two registers. The A
register comprises an input means (not shown) which may comprise a region in the substrate of o~posite conductivity to the substrate which acts as a source of charge carriers.
The register also may include an input gate (not shown) to which an analog signal may be applied for transferring charge in serial fashion from the source electrode to the first storage electrode. (Alternatively, a form of A register could be employed which received input signals, in parallel).
The A register also includes a plurality of storage electrodes operated by three phase voltages 0Al~ 0A2 and 0A3- Two sets of such electrodes 14-1, 14-2, 14-3 and 16-1, 16-2 and 16-3 are illustrated. Each set of electro~es compr;ses ~ storage location. These electrodes are spaced from the suhstrate by a thin layer of insulation, such as one formed of silicon dioxide. The electrodes may be spaced very close to one another or may overlap one another at their edges. All of these elements make up a CCD register which in itself is well known.
The boundaries of the A register comprise channel stops 18 and 20. Channel stop 18 is continuous whereas channel stop 20 is present at the edges of the 0Al and 0A3 electrodes but is not present in the regions adjacent to ~ - -the 0A2 electrodes such as 14-2 and 16-2. As is well under-stood in the art, the channel stops may comprise regions of `-the substrate which are highly doped and which are of the same conductivity as the substrate. They confine charge , . , . ~ . . .
.
- : . . .; ' ~ ~ . .
.
.. . ..
I~CA 6X S~2 10650~S
l present in a register channel to the channel.
The B register has columns and rows of ~CD storage locations, and each row can be considered a digi~al register.
The s~ructure of the B register includes a plurality of channels, four of which are shown at 22, 24, 26 and 28, forming the rows of a matrix. The channe]s are separated from one another by regions maintained at surface potentials which form "spilloYer barriers~' discussed shortly. S~lch barriers may be obtained, for example, by placing diffused regions 30, 32 and 34 in the substrate. Each such region is of the same conductivity as the substTate but is not as highly doped as a channel stop region. Thus, the spillover potential barriers provided by regions such as 30, 32 and so on are not as high as the barrier provided by a channel stop.
15 The doping level is also such that the spillover barriers are --lower than the potential barriers along the length of the channels beneath the gate electrodes and which separate the potential wells along the channels from one another. These characteristics will be discussed at greater length later in connection with the operation of the system. The last of the registers is bounded on one edge by a channel stop 36.
The B register includes also a plurality of electrodes, two sets of which, 38-1, 38-2, 38-3 and 40-1, 40-2, 40-3, are illustrated. These electrodes align with corresponding electrodes of the A register and are operated by the three phase voltages 0Bl' 0B2 and 0B3. Charge stored beneath the phase two electrodes 14-2 and 16-2 of the A
register can be coupled to the phase two electrodes 38-2 and 40-2, respectively of the B register by applying an appro-priate voltage TE to the transfer gate electrode 12, as will RCA 68,582 l be discussed shortly.
In the discussion which follows of the operation of FIGURE 1, FIGURES 1-4 should all be referred to. It may be assumed to start with that charge signals representing analog information have been shifted into the A register and that the 0A voltages are such that the charge at each stage is stored only beneath the 0A2 electrodes 14-2 and 16-2. The remaining electrodes 14-1, 14-3, 16-1 and 16-3 are maintained at potentials such that potential barriers are present be-neath these electrodes. It may be observed that the electrodesof the A register are of substantial area - many times that of the area of a B register electrode over a particular channel.
In other words, an electrode such as 14-2 may have an area in the region of the electrode over the A channel which is lS lO times that of the area of electrode 38-2 over channel 22.
Put another way, if the channel of the A register has a width WA and the width of a channel of the B register is WB, then WA may be 10 times greater than WB, assuming electrodes 14-2 and 38-2 are of the same length. What this means, in effect, is that each stage of input register A has a much larger charge storage capacity then the corresponding stage of one channel of the B register, assuming the same voltage is applied to the electrodes of these stages. It should be mentioned, in passing, that the 10 to 1 ratio given is not critical, the number chosen being a matter of design. With a 10 to 1 ratio, the charge present at one stage of the A
register, when the well of that stage is full, is capable of filling the wells at a corresponding location in 10 channels of the B register (making the assumption that at least 10 different channels are present in the B register).
': ' ' ~' ' ,: : : . ,,' . , . . ,' . . .' : , . .
., ,: .. ' . ,. . : , ,:., . , ... ' , :
- . : . ,, . .: , . .
. . . .
RCA 68,582 -.
1 Returning to the operation, after the analog signals are stored in the A register, the surFace potential profile may be as shown at a in FIGIJRJ, 2. The potential well beneath the electrode 14-2, shown by way of example, is filled with an amount of charge proportional to an analog signal. The transfer electrode 12 is at a potential such that a barrier is present (shown at 42) in the transfer channel. The potential wells beneath electrode 38- 2 are all empty. The diffused regions 30, 32 and 34 cause relatively low potential barriers to be present between these potential wells. The channel stop 36 causes a relatively high potential barrier to be present at one edge of the B register. The phase 1 and phase 3 electrodes 38- 1, 40-1 and 38- 3, 40- 3 are at potentials to form potential barriers beneath these electrodes, which are higher ~han those provided by the regions 30, 32, 34.
A transfer pulse is now applied to the transfer gate electrode 12. The result is illustrated at _ in FIGURE 2.
In response to the pulse, the potential barrier 42 is removed and a conduction channel is substituted therefor. A
portion of the charge present beneath electrode 14-2 passes through-this conduction channel and partially fills the first, potential well 44. This well is the one present in channel ' 22 of FIGURE 1. This charge is prevented from spreading down channel 22 (the direction into the paper in FIGURE 2) by the potential barriers beneath the 0Bl and ~B3 electrodes of the B register.
Next the 0A2 potential is changed in a sense to reduce the depth of the potential well beneath electrode 14-2 while the TE pulse is still present. The result is shown at c in FIGURE 2. The first well 44 has overflowed and charge 6 ~ , .. ..
RCA 68,582 1 has passed over spillover barrier 45 ~o the second well 46.
Then the second well fills and overflows tlle harrier 47 to the tllird well 48. In the final cond-ition shown at c, all of the charge formerly present beneath electrode 14-2 has passed to regions of the substrate which include the trans-fer channel and the potential wells 44, 46 and 48. In the present example, potential well 44 is filled to thc top. The adjacent potential well 46 is filled to the top and the next potential well 48 is almost completely filled. The charge preferentially flows from channel-to-channel over the spill-over potential barriers provided by structures 30, 32, 34, rather than down a particular channel because the potential barriers beneath the 0Bl and 0B3 electrodes are higher than the spillover potential barriers.
The final step in the transfer process is shown at d at FIGURE 2. This is to return the transfer gate electrode 12 potential to its original value to again provide a potential barrier 42 as shown. This causes any charge remaining present beneath the transfer electrode to propagate into the potential wells beneath electrode 38- 2 . The result, illustrated in FIGURE 2 at d, is that potential well 48, which was only partially filled previously, now fills to the top and a slight amount of charge overflows to potential well 50. The electrode 14- 2 may now be returned to its original voltage level as illustrated at e in FIGURE 2.
Summarizing what is depicted in FIGURE 2, the charge initially present in a stage of the A register has caused a plurality of potential wells in the B register to become filled. The number of such wells which become filled will - -depend upon the amplitude of the charge signal in the A
.. . .. . . ., ~ - .~ . . .
RCA 68,5~2 ~0650S5 1 register stage. In the present example, three wells 44, 46 and 48 have become completely filled and a small amount of charge has passed into the well 50. The filled wells can be assumed to represent binary l. Any well filled less than half full can he assumed to represent h;nary 0. Accord;ngly, in the example given ~y way of illustration, the analog signal present in a particular stage of the A register has been translated to three l's.
After the transfer procedure described above, the 10 0B multiple phase voltages, which can be at the same or at a different frequency than the 0A voltages, transfer the digital or quantized information present in the B register to an output circuit. The transfer is in the channel direction as indicated in FIGURES l and 3. During this transfer process, the spillover barriers operate as channel stops to prevent the charge propagating down one channel from passing into an adjacent channel.
In the operation of the system of FIGURE l, the slowest transfer process is that from the A to the B register.
The reason is relatively long path length (the length of a phase 2 electrode in the A register, plus the length of a phase 2 electrode in the B register) over which the charge signal must propagate. This transfer time is much longer than the time required for the multiple phase voltages to move charge signals from one stage to the next down the channel. However, since the transfer of charge from the A
to B registers takes place in parallel, that is, the entire contents of the A register flows into the B register, and since the A register can have many many stages (lO0, 500 and more, all being reasonable) the analog to digital conversion .. . ~ ............................ . .
,- ,, " ' ~ .
R~A 68,582 1~)6505S
1 still takes place at reasonably high speed.
FIGURE 3 illustrates schematically the conversion of analog information in thc A register to quantized infor-mation in the B register. This information subsequently is propagated, column by column, to the output of the B register, by the 0B multiple phase voltages. There, each column of signals may be applied to a threshold circu;t 60. The latter may be set to produce an output signal representing a l when the charge is greater than a given value - say half a well, and to produce an output signal representing a 0 when the charge is smaller than this value. Thus, each multiple bit output signal produced is a digital or quantized equivalent of an analog signal present in a particular stage of the A
register.
The multiple bit signals produced by stage 60 may be applied to logic stages for translating the digital indication to a binary number or a binary coded decimal (BCD) number. Such binary or BCD number can be stored in, and later processed by, a digital computer. Alternatively, the individual signals in a group of such signals may be added to one another to substantially reproduce the analog signal from which the digital signal initially was derived.
FIGURE 4 is simply a graph to illustrate the outputs produced by threshold circuit 60 as a function of 25 time for the specific example illustrated in FIGURE 3. :
FIGURE 5 illustrates how the system of the present -invention may be employed as a memory. (The transfer gate 12, while not illustrated specifically, is assumed to be present.) The A and B registers are simiIar to those already illustrated and discussed. The output of the B
RCA 68,582 lQ~S055 1 register is applied to a refresh circuit 70 which regenerates the signals it receives and applies them back to the input circuit of the B register. (A threshold circuit is included in stage 70 for eliminating charge signa]s which occupy less than one half well.) Thus, once the initial transfer from the A to the B register is completed, the information in the B register may be stored ~circulated) for as long as desired. During readout, a summer 72 may be employed to add the individual signals in each group and to thereby repro-duce the analog signals initially present in the A register.Alternatively, logic circuits 74, shown in dashed line, may be employed to translate the digital signals to binary or BCD signals.
An important attribute of the memory of FIGURE 5 is that because of the digital nature of the signals, transfer losses have substantially no effect on the system operation.
Were the A register analog signal simply recirculated, there would be such losses. Each time a signal travelled around the loop from its initial location to the output terminal of 20 the A register back to the input terminal then back to its -~
initial location it would suffer some loss, dependent upon the number of charge transfers and the charge transfer efficiency. While such loss may be very small for a single recirculation, it becomes larger each additional recirculation and where hundreds or thousands of trips around the loop are involved, the analog signal soon may be destroyed. In the system of FIGURE 5, however, the refresh circuit decides, each time it receives a signal, whether a 1 or 0 is present, and produces a feedback signal at a predetermined level representing that binary digit. Thus, even if a 1 charge - .
.:
RCA 68,582 1 level deteriorates almost 50~ during one traversal of the loop, each time it reaches the refresh circuit it is returned to the lOO~ level.
If there are a large number of channels in the R
register, there will be a correspondingly large number of feedback leads needed in the system of FIGURE 5. In some circumstances, this may be undesirable. Such feedback leads may be dispensed with and a single lead 73, shown in phantom, substituted therefor in an alternative form of the system.
Now rather than feedback from the refresh circuit 70 to the B register, the output of the summer (an analog signal but quantized at one of n different levels, where n is the number of channels) is fed back to the A register. The operation, in other respects, is believed to be self-evident from the explanation already given. The price paid for the reduction in the number of feedback leads is that the recirculation -frequency will be limited by the transfer speed from the A
to the B register.
The arrangement of FIGURE 6 shows how radiation ~ -may be translated to digital signals. The array 80 preferably is a linear array such as a linear CCD imager, or a linear array of photodiodes, or a linear array of any other kind which has the ability to translate a radiation signal to a charge signal, and which either is self-resetting or which can be reset to a reference level after each transfer of charge signal through gate 12. One "line" of the scene being viewed may be projected onto the linear array to pro-duce a stored analog charge pattern corresponding to the received illumination. That charge pattern may be trans-lated into digital information stored in the B register in . ~
- . ~ .
, . .
1 the manner already discussed and that information shifted out of the B register via the threshold circuit to an output circuit. The output circuit may be any one of the types already discussed. The same process may be repeated for successive lines of the scene by producing relative movement between the linear array 80 and the scene, in a manner which in itself is known.
Resolution is substantially unaffected in the system of FIGURE 6, by transfer losses. Each analog charge level is translated immediately to a number of l's. The threshold circuit refreshes the signal so that the digital output is a very accurate representation of the analog signal.
While the invention has been illustrated in terms of a three phase system, the inventive teachings are equally applicable to 1, 2, 4 or higher phase CCD's. Also, either P channel (that is, N type substrate) or N channel (P type substrate) CCD's may be employed, provided appropriate operating voltages are employed. Further, the system can employ either "surface channel" or so called "buried channel" CCD's.
While in the embodiment of FIGURE 6 a linear radiation sensing array 80 is shown, other forms of arrays such as those having a number of columns and rows, or even spiral arrays may be employed instead. Where array 80 consists of a single row of elements, that row can be one row of a large array of sensing elements.
In a preferred form of the invention, analog signals initially are present in a first array. The respective stages of the array are coupled to columns of a second array--a charge coupled device (CCD) matrix, known as a B register. During a transfer interval, the analog signals concurrently are flowed into the columns and, as the stages in the CCD matrix have much smaller charge storage capacity than the stages in the first array, from 0 to n stages of any particular column may become filled depending upon the amplitude of the analog signal for that column. The matrix may be read by concurrently sensing all of the signals present in one column and then doing the same for the following columns.
In the drawing:
FIGURE 1 is a plan view of a portion of a system embodying the invention;
FIGURE 2 is a drawing of surface potential profiles to help explain the operation of the system of FIGURE l;
FIGURE 3 is a schematic showing of the charge present in the A and B registers during different periods of time;
FIGURE 4 is a graph to further help explain the operation of the system of FIGURE l;
FIGURE 5 is a block diagram of a memory embodying the invention; and FIGURE 6 is a block diagram of an imager system embodying the invention.
The system of FIGURE 1 includes a semiconductor .:
RCA 68,582 ~0~5055 1 substrate 10, an A register formed on one portion of the substrate, a CCD matrix of columns and rows, termed a B
register, formed on a second portion of the substrate, and a transfer gate 12 between the two registers. The A
register comprises an input means (not shown) which may comprise a region in the substrate of o~posite conductivity to the substrate which acts as a source of charge carriers.
The register also may include an input gate (not shown) to which an analog signal may be applied for transferring charge in serial fashion from the source electrode to the first storage electrode. (Alternatively, a form of A register could be employed which received input signals, in parallel).
The A register also includes a plurality of storage electrodes operated by three phase voltages 0Al~ 0A2 and 0A3- Two sets of such electrodes 14-1, 14-2, 14-3 and 16-1, 16-2 and 16-3 are illustrated. Each set of electro~es compr;ses ~ storage location. These electrodes are spaced from the suhstrate by a thin layer of insulation, such as one formed of silicon dioxide. The electrodes may be spaced very close to one another or may overlap one another at their edges. All of these elements make up a CCD register which in itself is well known.
The boundaries of the A register comprise channel stops 18 and 20. Channel stop 18 is continuous whereas channel stop 20 is present at the edges of the 0Al and 0A3 electrodes but is not present in the regions adjacent to ~ - -the 0A2 electrodes such as 14-2 and 16-2. As is well under-stood in the art, the channel stops may comprise regions of `-the substrate which are highly doped and which are of the same conductivity as the substrate. They confine charge , . , . ~ . . .
.
- : . . .; ' ~ ~ . .
.
.. . ..
I~CA 6X S~2 10650~S
l present in a register channel to the channel.
The B register has columns and rows of ~CD storage locations, and each row can be considered a digi~al register.
The s~ructure of the B register includes a plurality of channels, four of which are shown at 22, 24, 26 and 28, forming the rows of a matrix. The channe]s are separated from one another by regions maintained at surface potentials which form "spilloYer barriers~' discussed shortly. S~lch barriers may be obtained, for example, by placing diffused regions 30, 32 and 34 in the substrate. Each such region is of the same conductivity as the substTate but is not as highly doped as a channel stop region. Thus, the spillover potential barriers provided by regions such as 30, 32 and so on are not as high as the barrier provided by a channel stop.
15 The doping level is also such that the spillover barriers are --lower than the potential barriers along the length of the channels beneath the gate electrodes and which separate the potential wells along the channels from one another. These characteristics will be discussed at greater length later in connection with the operation of the system. The last of the registers is bounded on one edge by a channel stop 36.
The B register includes also a plurality of electrodes, two sets of which, 38-1, 38-2, 38-3 and 40-1, 40-2, 40-3, are illustrated. These electrodes align with corresponding electrodes of the A register and are operated by the three phase voltages 0Bl' 0B2 and 0B3. Charge stored beneath the phase two electrodes 14-2 and 16-2 of the A
register can be coupled to the phase two electrodes 38-2 and 40-2, respectively of the B register by applying an appro-priate voltage TE to the transfer gate electrode 12, as will RCA 68,582 l be discussed shortly.
In the discussion which follows of the operation of FIGURE 1, FIGURES 1-4 should all be referred to. It may be assumed to start with that charge signals representing analog information have been shifted into the A register and that the 0A voltages are such that the charge at each stage is stored only beneath the 0A2 electrodes 14-2 and 16-2. The remaining electrodes 14-1, 14-3, 16-1 and 16-3 are maintained at potentials such that potential barriers are present be-neath these electrodes. It may be observed that the electrodesof the A register are of substantial area - many times that of the area of a B register electrode over a particular channel.
In other words, an electrode such as 14-2 may have an area in the region of the electrode over the A channel which is lS lO times that of the area of electrode 38-2 over channel 22.
Put another way, if the channel of the A register has a width WA and the width of a channel of the B register is WB, then WA may be 10 times greater than WB, assuming electrodes 14-2 and 38-2 are of the same length. What this means, in effect, is that each stage of input register A has a much larger charge storage capacity then the corresponding stage of one channel of the B register, assuming the same voltage is applied to the electrodes of these stages. It should be mentioned, in passing, that the 10 to 1 ratio given is not critical, the number chosen being a matter of design. With a 10 to 1 ratio, the charge present at one stage of the A
register, when the well of that stage is full, is capable of filling the wells at a corresponding location in 10 channels of the B register (making the assumption that at least 10 different channels are present in the B register).
': ' ' ~' ' ,: : : . ,,' . , . . ,' . . .' : , . .
., ,: .. ' . ,. . : , ,:., . , ... ' , :
- . : . ,, . .: , . .
. . . .
RCA 68,582 -.
1 Returning to the operation, after the analog signals are stored in the A register, the surFace potential profile may be as shown at a in FIGIJRJ, 2. The potential well beneath the electrode 14-2, shown by way of example, is filled with an amount of charge proportional to an analog signal. The transfer electrode 12 is at a potential such that a barrier is present (shown at 42) in the transfer channel. The potential wells beneath electrode 38- 2 are all empty. The diffused regions 30, 32 and 34 cause relatively low potential barriers to be present between these potential wells. The channel stop 36 causes a relatively high potential barrier to be present at one edge of the B register. The phase 1 and phase 3 electrodes 38- 1, 40-1 and 38- 3, 40- 3 are at potentials to form potential barriers beneath these electrodes, which are higher ~han those provided by the regions 30, 32, 34.
A transfer pulse is now applied to the transfer gate electrode 12. The result is illustrated at _ in FIGURE 2.
In response to the pulse, the potential barrier 42 is removed and a conduction channel is substituted therefor. A
portion of the charge present beneath electrode 14-2 passes through-this conduction channel and partially fills the first, potential well 44. This well is the one present in channel ' 22 of FIGURE 1. This charge is prevented from spreading down channel 22 (the direction into the paper in FIGURE 2) by the potential barriers beneath the 0Bl and ~B3 electrodes of the B register.
Next the 0A2 potential is changed in a sense to reduce the depth of the potential well beneath electrode 14-2 while the TE pulse is still present. The result is shown at c in FIGURE 2. The first well 44 has overflowed and charge 6 ~ , .. ..
RCA 68,582 1 has passed over spillover barrier 45 ~o the second well 46.
Then the second well fills and overflows tlle harrier 47 to the tllird well 48. In the final cond-ition shown at c, all of the charge formerly present beneath electrode 14-2 has passed to regions of the substrate which include the trans-fer channel and the potential wells 44, 46 and 48. In the present example, potential well 44 is filled to thc top. The adjacent potential well 46 is filled to the top and the next potential well 48 is almost completely filled. The charge preferentially flows from channel-to-channel over the spill-over potential barriers provided by structures 30, 32, 34, rather than down a particular channel because the potential barriers beneath the 0Bl and 0B3 electrodes are higher than the spillover potential barriers.
The final step in the transfer process is shown at d at FIGURE 2. This is to return the transfer gate electrode 12 potential to its original value to again provide a potential barrier 42 as shown. This causes any charge remaining present beneath the transfer electrode to propagate into the potential wells beneath electrode 38- 2 . The result, illustrated in FIGURE 2 at d, is that potential well 48, which was only partially filled previously, now fills to the top and a slight amount of charge overflows to potential well 50. The electrode 14- 2 may now be returned to its original voltage level as illustrated at e in FIGURE 2.
Summarizing what is depicted in FIGURE 2, the charge initially present in a stage of the A register has caused a plurality of potential wells in the B register to become filled. The number of such wells which become filled will - -depend upon the amplitude of the charge signal in the A
.. . .. . . ., ~ - .~ . . .
RCA 68,5~2 ~0650S5 1 register stage. In the present example, three wells 44, 46 and 48 have become completely filled and a small amount of charge has passed into the well 50. The filled wells can be assumed to represent binary l. Any well filled less than half full can he assumed to represent h;nary 0. Accord;ngly, in the example given ~y way of illustration, the analog signal present in a particular stage of the A register has been translated to three l's.
After the transfer procedure described above, the 10 0B multiple phase voltages, which can be at the same or at a different frequency than the 0A voltages, transfer the digital or quantized information present in the B register to an output circuit. The transfer is in the channel direction as indicated in FIGURES l and 3. During this transfer process, the spillover barriers operate as channel stops to prevent the charge propagating down one channel from passing into an adjacent channel.
In the operation of the system of FIGURE l, the slowest transfer process is that from the A to the B register.
The reason is relatively long path length (the length of a phase 2 electrode in the A register, plus the length of a phase 2 electrode in the B register) over which the charge signal must propagate. This transfer time is much longer than the time required for the multiple phase voltages to move charge signals from one stage to the next down the channel. However, since the transfer of charge from the A
to B registers takes place in parallel, that is, the entire contents of the A register flows into the B register, and since the A register can have many many stages (lO0, 500 and more, all being reasonable) the analog to digital conversion .. . ~ ............................ . .
,- ,, " ' ~ .
R~A 68,582 1~)6505S
1 still takes place at reasonably high speed.
FIGURE 3 illustrates schematically the conversion of analog information in thc A register to quantized infor-mation in the B register. This information subsequently is propagated, column by column, to the output of the B register, by the 0B multiple phase voltages. There, each column of signals may be applied to a threshold circu;t 60. The latter may be set to produce an output signal representing a l when the charge is greater than a given value - say half a well, and to produce an output signal representing a 0 when the charge is smaller than this value. Thus, each multiple bit output signal produced is a digital or quantized equivalent of an analog signal present in a particular stage of the A
register.
The multiple bit signals produced by stage 60 may be applied to logic stages for translating the digital indication to a binary number or a binary coded decimal (BCD) number. Such binary or BCD number can be stored in, and later processed by, a digital computer. Alternatively, the individual signals in a group of such signals may be added to one another to substantially reproduce the analog signal from which the digital signal initially was derived.
FIGURE 4 is simply a graph to illustrate the outputs produced by threshold circuit 60 as a function of 25 time for the specific example illustrated in FIGURE 3. :
FIGURE 5 illustrates how the system of the present -invention may be employed as a memory. (The transfer gate 12, while not illustrated specifically, is assumed to be present.) The A and B registers are simiIar to those already illustrated and discussed. The output of the B
RCA 68,582 lQ~S055 1 register is applied to a refresh circuit 70 which regenerates the signals it receives and applies them back to the input circuit of the B register. (A threshold circuit is included in stage 70 for eliminating charge signa]s which occupy less than one half well.) Thus, once the initial transfer from the A to the B register is completed, the information in the B register may be stored ~circulated) for as long as desired. During readout, a summer 72 may be employed to add the individual signals in each group and to thereby repro-duce the analog signals initially present in the A register.Alternatively, logic circuits 74, shown in dashed line, may be employed to translate the digital signals to binary or BCD signals.
An important attribute of the memory of FIGURE 5 is that because of the digital nature of the signals, transfer losses have substantially no effect on the system operation.
Were the A register analog signal simply recirculated, there would be such losses. Each time a signal travelled around the loop from its initial location to the output terminal of 20 the A register back to the input terminal then back to its -~
initial location it would suffer some loss, dependent upon the number of charge transfers and the charge transfer efficiency. While such loss may be very small for a single recirculation, it becomes larger each additional recirculation and where hundreds or thousands of trips around the loop are involved, the analog signal soon may be destroyed. In the system of FIGURE 5, however, the refresh circuit decides, each time it receives a signal, whether a 1 or 0 is present, and produces a feedback signal at a predetermined level representing that binary digit. Thus, even if a 1 charge - .
.:
RCA 68,582 1 level deteriorates almost 50~ during one traversal of the loop, each time it reaches the refresh circuit it is returned to the lOO~ level.
If there are a large number of channels in the R
register, there will be a correspondingly large number of feedback leads needed in the system of FIGURE 5. In some circumstances, this may be undesirable. Such feedback leads may be dispensed with and a single lead 73, shown in phantom, substituted therefor in an alternative form of the system.
Now rather than feedback from the refresh circuit 70 to the B register, the output of the summer (an analog signal but quantized at one of n different levels, where n is the number of channels) is fed back to the A register. The operation, in other respects, is believed to be self-evident from the explanation already given. The price paid for the reduction in the number of feedback leads is that the recirculation -frequency will be limited by the transfer speed from the A
to the B register.
The arrangement of FIGURE 6 shows how radiation ~ -may be translated to digital signals. The array 80 preferably is a linear array such as a linear CCD imager, or a linear array of photodiodes, or a linear array of any other kind which has the ability to translate a radiation signal to a charge signal, and which either is self-resetting or which can be reset to a reference level after each transfer of charge signal through gate 12. One "line" of the scene being viewed may be projected onto the linear array to pro-duce a stored analog charge pattern corresponding to the received illumination. That charge pattern may be trans-lated into digital information stored in the B register in . ~
- . ~ .
, . .
1 the manner already discussed and that information shifted out of the B register via the threshold circuit to an output circuit. The output circuit may be any one of the types already discussed. The same process may be repeated for successive lines of the scene by producing relative movement between the linear array 80 and the scene, in a manner which in itself is known.
Resolution is substantially unaffected in the system of FIGURE 6, by transfer losses. Each analog charge level is translated immediately to a number of l's. The threshold circuit refreshes the signal so that the digital output is a very accurate representation of the analog signal.
While the invention has been illustrated in terms of a three phase system, the inventive teachings are equally applicable to 1, 2, 4 or higher phase CCD's. Also, either P channel (that is, N type substrate) or N channel (P type substrate) CCD's may be employed, provided appropriate operating voltages are employed. Further, the system can employ either "surface channel" or so called "buried channel" CCD's.
While in the embodiment of FIGURE 6 a linear radiation sensing array 80 is shown, other forms of arrays such as those having a number of columns and rows, or even spiral arrays may be employed instead. Where array 80 consists of a single row of elements, that row can be one row of a large array of sensing elements.
Claims (6)
1. A charge coupled device system comprising:
an input register having a plurality of stages each capable of storing a given amount of charge, each stage for storing an analog charge signal;
a plurality n of charge coupled device conversion registers each having a plurality of at least m stages and each stage having only a fraction of the storage capacity of a stage of said input register, where n and m are integers greater than 1;
means for flowing the charge signal in each j'th stage of said input register into from 0 to n of the j'th stages of said conversion registers, the number depending on the amplitude of the charge signal present in the j'th stage of the input register, where j is an integer equal to 1, 2---m, m being not greater than the total number of stages in the input register;
means for concurrently shifting the charge signals in said n conversion registers down said registers; and means for reading, in parallel, each group of charge signals reaching the output stage of said n conversion registers.
an input register having a plurality of stages each capable of storing a given amount of charge, each stage for storing an analog charge signal;
a plurality n of charge coupled device conversion registers each having a plurality of at least m stages and each stage having only a fraction of the storage capacity of a stage of said input register, where n and m are integers greater than 1;
means for flowing the charge signal in each j'th stage of said input register into from 0 to n of the j'th stages of said conversion registers, the number depending on the amplitude of the charge signal present in the j'th stage of the input register, where j is an integer equal to 1, 2---m, m being not greater than the total number of stages in the input register;
means for concurrently shifting the charge signals in said n conversion registers down said registers; and means for reading, in parallel, each group of charge signals reaching the output stage of said n conversion registers.
2. The charge coupled device system as set forth in Claim 1, wherein said conversion registers are integrated onto a common semiconductor substrate and each such register being separated from the next adjacent such register by means providing a potential barrier in the substrate which is sufficiently low to permit charge signal to pass from a stage in one register to a corresponding stage in the next register during the flowing of charge from said input register to said conversion registers, and which is sufficiently high to isolate the charge in one register from that in the next adjacent register, during the propagation of charge down said conversion registers.
3. The charge coupled device system as set forth in Claim 2 wherein said input register is a charge-coupled register.
4. The charge coupled device system as set forth in Claim 1 or 2 wherein said input register is a radiation sensing array.
5. The charge coupled device system as set forth in Claim 2, wherein said means providing a potential barrier comprises a diffusion in said substrate of the same conductivity as the substrate but more highly doped than the substrate.
6. The charge coupled device system as set forth in any of Claims 1, 2 or 3, wherein each conversion register includes an output stage at one end of the register and an input stage at the other end of the register, and further including n feedback connections, each connecting an output stage of a conversion register back to its input stage.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/547,129 US3958210A (en) | 1975-02-05 | 1975-02-05 | Charge coupled device systems |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1065055A true CA1065055A (en) | 1979-10-23 |
Family
ID=24183451
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA244,007A Expired CA1065055A (en) | 1975-02-05 | 1976-01-21 | Charge coupled device systems |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US3958210A (en) |
| JP (1) | JPS5442578B2 (en) |
| CA (1) | CA1065055A (en) |
| DE (1) | DE2604449C3 (en) |
| FR (1) | FR2300463A1 (en) |
| GB (1) | GB1529927A (en) |
| NL (1) | NL7601129A (en) |
Families Citing this family (34)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4910706A (en) * | 1972-09-11 | 1990-03-20 | Hyatt Gilbert P | Analog memory for storing digital information |
| US5615142A (en) * | 1970-12-28 | 1997-03-25 | Hyatt; Gilbert P. | Analog memory system storing and communicating frequency domain information |
| US5619445A (en) * | 1970-12-28 | 1997-04-08 | Hyatt; Gilbert P. | Analog memory system having a frequency domain transform processor |
| US5339275A (en) * | 1970-12-28 | 1994-08-16 | Hyatt Gilbert P | Analog memory system |
| US5566103A (en) * | 1970-12-28 | 1996-10-15 | Hyatt; Gilbert P. | Optical system having an analog image memory, an analog refresh circuit, and analog converters |
| NL7510311A (en) * | 1975-09-02 | 1977-03-04 | Philips Nv | LOAD TRANSFER DEVICE. |
| JPS5235536A (en) * | 1975-09-13 | 1977-03-18 | Toshiba Corp | Memory using charge cobination element |
| US4042835A (en) * | 1976-02-24 | 1977-08-16 | Grumman Aerospace Corporation | Charge coupled device |
| US4139910A (en) * | 1976-12-06 | 1979-02-13 | International Business Machines Corporation | Charge coupled device memory with method of doubled storage capacity and independent of process parameters and temperature |
| DE2704711C3 (en) * | 1977-02-04 | 1980-12-04 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | CCD memory chip |
| DE2704718C3 (en) * | 1977-02-04 | 1980-11-20 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | CCD memory chip |
| US4115766A (en) * | 1977-03-31 | 1978-09-19 | Bell Telephone Laboratories, Incorporated | Semiconductor apparatus for analog to digital conversion |
| US4136335A (en) * | 1977-04-18 | 1979-01-23 | Bell Telephone Laboratories, Incorporated | Semiconductor charge coupled device analog to digital converter |
| US4206446A (en) * | 1977-05-23 | 1980-06-03 | Rca Corporation | CCD A-to-D converter |
| IL55367A (en) * | 1977-08-19 | 1981-07-31 | Gen Electric | Charge transfer memory apparatus |
| US4130894A (en) * | 1977-11-21 | 1978-12-19 | International Business Machines Corporation | Loop organized serial-parallel-serial memory storage system |
| FR2428945A1 (en) * | 1978-06-13 | 1980-01-11 | Thomson Csf | TRANSITIONAL SIGNALING DEVICE |
| US4240068A (en) * | 1978-06-23 | 1980-12-16 | Xerox Corporation | CCD Analog to digital converter |
| CA1146278A (en) * | 1978-06-23 | 1983-05-10 | Roland J. Handy | Ccd analog to digital converter |
| US4272759A (en) * | 1978-06-23 | 1981-06-09 | Xerox Corporation | 16 Bit analog to digital converter |
| DE2831296C2 (en) * | 1978-07-17 | 1984-12-20 | Agfa-Gevaert Ag, 5090 Leverkusen | Apparatus for electronically scanning super eight films for display on a television set |
| US4246496A (en) * | 1978-07-17 | 1981-01-20 | International Business Machines Corporation | Voltage-to-charge transducer |
| US4206371A (en) * | 1978-10-27 | 1980-06-03 | Rca Corporation | CCD with differently doped substrate regions beneath a common electrode |
| US4241421A (en) * | 1979-07-26 | 1980-12-23 | General Electric Company | Solid state imaging apparatus |
| EP0087438B1 (en) * | 1981-09-07 | 1987-04-29 | SPALDING, David Ian | Signal sampling and conversion system |
| JPS58144287U (en) * | 1982-03-23 | 1983-09-28 | 株式会社精工舎 | Glass holding mechanism for watches, etc. |
| JPS5975773A (en) * | 1982-10-25 | 1984-04-28 | Toshiba Corp | Solid-state image pickup device |
| US4543558A (en) * | 1983-03-14 | 1985-09-24 | Miles Laboratories, Inc. | Method and apparatus for converting radiant energy levels to digital data |
| GB2178614A (en) * | 1985-07-26 | 1987-02-11 | Philips Electronic Associated | Producing a digital representation of the time-integral of an electric current |
| US4906997A (en) * | 1987-07-28 | 1990-03-06 | Seckora Michael C | CCD device adapted for changing signal formats |
| US5014059A (en) * | 1987-07-28 | 1991-05-07 | Tektronix, Inc. | Analog-to-digital converter system |
| US4967198A (en) * | 1988-06-13 | 1990-10-30 | Seckora Michael C | Serial-to-parallel analog CCD GaAs device |
| US5479170A (en) * | 1992-10-16 | 1995-12-26 | California Institute Of Technology | Method and apparatus for long-term multi-valued storage in dynamic analog memory |
| JP6264963B2 (en) * | 2014-03-13 | 2018-01-24 | コニカミノルタ株式会社 | Phased adder and ultrasonic probe |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3858232A (en) * | 1970-02-16 | 1974-12-31 | Bell Telephone Labor Inc | Information storage devices |
| US3771149A (en) * | 1971-12-30 | 1973-11-06 | Texas Instruments Inc | Charge coupled optical scanner |
| US3819958A (en) * | 1972-11-03 | 1974-06-25 | Texas Instruments Inc | Charge transfer device analog matched filter |
| US3903543A (en) * | 1974-01-16 | 1975-09-02 | Bell Telephone Labor Inc | Charge transfer device decoder and compander |
-
1975
- 1975-02-05 US US05/547,129 patent/US3958210A/en not_active Expired - Lifetime
-
1976
- 1976-01-21 CA CA244,007A patent/CA1065055A/en not_active Expired
- 1976-01-23 GB GB2716/76A patent/GB1529927A/en not_active Expired
- 1976-02-04 NL NL7601129A patent/NL7601129A/en not_active Application Discontinuation
- 1976-02-04 FR FR7603042A patent/FR2300463A1/en not_active Withdrawn
- 1976-02-05 DE DE2604449A patent/DE2604449C3/en not_active Expired
- 1976-02-05 JP JP1218676A patent/JPS5442578B2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE2604449A1 (en) | 1976-08-19 |
| JPS5442578B2 (en) | 1979-12-14 |
| GB1529927A (en) | 1978-10-25 |
| FR2300463A1 (en) | 1976-09-03 |
| NL7601129A (en) | 1976-08-09 |
| AU1027076A (en) | 1977-07-21 |
| JPS51103752A (en) | 1976-09-13 |
| US3958210A (en) | 1976-05-18 |
| DE2604449C3 (en) | 1980-09-18 |
| DE2604449B2 (en) | 1980-01-24 |
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| MKEX | Expiry |
Effective date: 19961023 |