CA1066779A - Spread spectrum demodulator - Google Patents
Spread spectrum demodulatorInfo
- Publication number
- CA1066779A CA1066779A CA259,160A CA259160A CA1066779A CA 1066779 A CA1066779 A CA 1066779A CA 259160 A CA259160 A CA 259160A CA 1066779 A CA1066779 A CA 1066779A
- Authority
- CA
- Canada
- Prior art keywords
- signal
- phase
- pseudo
- received signal
- spread spectrum
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/14—Relay systems
- H04B7/15—Active relay systems
- H04B7/204—Multiple access
- H04B7/216—Code division or spread-spectrum multiple access [CDMA, SSMA]
Abstract
Abstract of the Disclosure The present invention is directed to a demodulator for demodulating a wideband spread spectrum four-phase PSK
(phase shift keyed) modulated carrier signal wherein the phase modulation was in response to an encoded data signal and wherein the encoding of the data signal and spreading of the spectrum was accomplished by the mixing of the data sig-nal with a pseudo-random pulse sequence (PN-sequence).
The demodulator is comprised in part of a generator means for providing a pseudo-random pulse sequence correspond-ing to the sequence used to encode the data signal; and an encoding means for converting the provided PN-sequence into a four-phase PN sequence. A correlation means correlates the generated four-phase PN sequence against the received four-phase PSK modulated carrier signal to provide a two-phase collapsed spectrum signal. A switching means inter-posed between correlation means and the generator means switches two of the four phases of the four phase PN-se-quence signal applied to the correlation means until proper phasing is achieved.
(phase shift keyed) modulated carrier signal wherein the phase modulation was in response to an encoded data signal and wherein the encoding of the data signal and spreading of the spectrum was accomplished by the mixing of the data sig-nal with a pseudo-random pulse sequence (PN-sequence).
The demodulator is comprised in part of a generator means for providing a pseudo-random pulse sequence correspond-ing to the sequence used to encode the data signal; and an encoding means for converting the provided PN-sequence into a four-phase PN sequence. A correlation means correlates the generated four-phase PN sequence against the received four-phase PSK modulated carrier signal to provide a two-phase collapsed spectrum signal. A switching means inter-posed between correlation means and the generator means switches two of the four phases of the four phase PN-se-quence signal applied to the correlation means until proper phasing is achieved.
Description
Back~round of the Invention ; The present invention is directed to the field of demodulators and more particularly to a spread spectrum demodulator for demodulating a spread spectrum four-phase PSK (ph~se shift keyed) modulated carrier signal.
In a bi-phase PSK communication system the phase of a reference carrier ~ignal is shifted (encoded) in accordance with the coding of a data signal. As an exam-ple, if a binary "0" is to be transmitted the phase of the reference carrier signal would be unQhifted, or 0; and if a binary "1" were to be transmitted the phase of the refer-ence carrier signal would beshifted 180.
Once the carrier signal is phase modulated it may~
be transmitted to a receiver over a transmi~sion line or a radio link.
Aside from bi-pha~e PSK modulation, quadrature (four) phase modulation may also be used. In a quadrature phase communication system the information signal, which i8 generally a string of binary bits, is proportioned into baud intervals, that is, into groups of two binary bits.
The succession of phase changes occurring in successive baud intervals is then used to modulate the reference carr-ier signal in four phases.
For example, four digital symbols such a~ 00, 01 10 and 11 may be transmitted for quadrature phase modul~-tion of the carrier s~gnal. Each of the four different I phases of the carrier signal may be used to represent a `
,, :
~ 3 .s, different one of the four digital symbols. Th~t i8, the phase angle 0 can represent the digital symbol, 00; and the phase angles 90, 180, and 270, can repre~ent the digital symbols 01, 11 and 10, respectively.
In certain communication environments, it is necessary to provide a signal which cannot be interfered with, that iB, a signal which is secure and cannot be ~ammed, interrupted, or received by an unauthori~ed receiver.
The security afforded to a PSK signal is somewh~t limited in that a receiver, having its local reference carrier signal synchronized to the received PSK signal, will be able to demodulate the received PSK signal to ar- -rive at the data signal. In addition, once the frequency of the carrier signal or the frequency spectrum of the data signal is known, it is a relatively simple procedure for a ~ammer to intentionally disrupt communications. In order to minimize this particular weakness in digital communica-:~;
tions systems a scheme has been devised whereby the band-width of the transmitted signal ls spread over a larger bandwidth than that of the data signal. This is generally ~i accomplished by mixing the data signal with a pseudo-randomsequence of pulses having a bandwidth greater than the bsndwidth of the data. The mixed signal is then used to phase modulate a reference carrier signal. Transmission of this type of spread spectrum signal makes it exceedipgly dlfficult to determlne the data carrylng components of the ~.
- 4 - ;
?;~
transmitted slgnal and therefore, in turn, to achieve ef-fective ~amming. In order to receive a spread spectrum signal that is encoded in the above manner, it is nece-s~ary to know the particular sequence of the pseudo-random sequence of pulses that was used to spread the spectrum of the data sign~l. The present invention is directed towards such a ~ystem. Efficient decoding in the receiver requires an identical code generator for generating the pseudo-random sequence, which code generator mu~t be in precise time synchronization with the pseudo-random sequence of the spread spectrum signal.
A publication which provides an insight into the state of the art of spread spectrum signal processing i8 entitled "Surface Acoustic Wave Devices And Applications", by B. J. Hunsinger, published in the November 1973 issue of Ultragonics, page 25 to page 263. Another publication of interest is entitled "Optimal Binary Sequences For Spread Spectrum Multiplexing", by R. Gold published in the IEEE Transactions On Information Theory, October 1967, pages 619 to 621.
~` ~
~ 1 0 6 6 7 7 9 Summary of the Invention In the present invention a pseudo-random sequence of binary pulses is used to encode a data signal into four-phase signals. The encoded signals are then used to modu-late the phase of a carrier signal in four phases so as to spread the spectrum of the modulated signal to that of the pseudo-random sequence.
In a preferred embodiment of the pre~ent inven-tion there is provided a generator means for generating a local carrier signal corresponding to the spread spectrum signal portion of a received signal, correlator means for correlating the generated local carrier signal with the re-ceived signal so as to collapse the spread spectrum signal portion of the received signal, and reversing means inter-posed between the generator means and the correlator means - for changing the correlation relationship of components of ` the signal from the generated local carrier signal with the spread spectrum signal portion of the received signal.
More specifically, demodulation of 3 signal which is modulated utilizing the above technique is acco~plished by divid~ng the received signal along two signal paths, one of which shifts the phase of the received signal by 90. A
pair of mixers are positioned, one each, in each of the Signal psths. Means are provided for generating a local pseudo-random (PN) sequence of pulses, which sequence cor-responds to the sequence used to spread the spectru~ of the transmitted signal. Encoding means are provided for split-~`1 ting the pseudo-random sequence into quadrature related signalsO A switching means connects the quadrature related signals to respective inputs of the two mixers. A locking signal activates the switching means to periodically re-verse the connection~ of the quadrature related signals to ,. ~ . , . - ................ :
the two mixers for an unlocked condition and to maintain the connections in one position for a locked condition. The out-put signals from the two mixers are summed together in a summing circuit to provide the demodulator output signal which signal is a two-phase non-spread PSK modulated sig-nal. A lock detector provides the locking signal by . ~
.,: i , ;.......... ,~ . . ... , , ,~ .............. .
.. , . , .. ~..... .. .
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`'~ 10 6 6~r7~
detecting the degree of synchronizstion between the local i gener~ted PN sequence and the PN sequence contained in the ! received siRnal. A synchronizing control loop responds to the degree of synchronization 90 as to drive the local PN
sequence generator into ~ynchronization with the PN se-quence contained in the received signal.
The output ~ignal~ from the mixers are ~ignals corresponding to a four-phase PSK modulated signal of a narrow bandwidth in that each mixer removes one-half of the pseudo-rflndom modulation such that the spread bandwidth of the PN ~equence is totally removed from the received signal when the ~ignal is summed by the summing circuit. The summing circuit also, by comb~ning the signals from the mixers, converts the phase of the summed signals from four-phase to two-phase. Therefore, the output signal from the !` summing circuit i9 a two-phase collapsed spectrum PSK mod-ulàted signal, which signal may be further demodulated using well known demodulation techniques to detect the data signal.
From the foregoing, it can be seen that it is a primary ob~ect of the present invention to provide an lm-proved spread spectrum demodulator.
j It i8 still another ob~ect of the present ~nven-i~ tion to provide a demodulator for converting four-phase spread spectrum PSK signals into two-phase collapsed spec- ~-trum PSK signals.
¦~ It i8 another ob~ect of the present invention to ~,s~
.
`' 1066779 provide an improved demodulation system wherein spectrum ~, collapsing is facilitated by phase shifting a received ! spread spectrum PSK modulated signal as a function of a locally generated p9eudo-random sequence 8ignal.
These and other ob~ects of the present invention , will become more apparent when taken in con~unction with ; the following description and drawings in which like char-acters indicate like parts and which drawings form a part of the pre~ent invention.
Brief_Description of the Drawin~s Fig. 1 is a detailed block schematic diagram of a spread ~pectrum modulator;
-; Fig. 2 i~ a schematic diagram of a portion of a spread ~pectrum receiver utilizing the demodulator of the ` pre~ent invention;
Fig. 3 is a detailed block schem~tic diagram of . . .
-~ the demodulator of the present invention; and Figs. 4A and 4B are phase vectors useful in understanding the operation of the demodulator of Fig~. 2 -and 3.
.. . .
r .' ' Desc~ption of_the Preferred Embodiments l Referring to the modulator of Fig. l; an EXCLUSIVE-;! OR gate 11 receives at one of its input terminals a ~-seband (inform~tion) data signal having a repetition rate of RN.
The baseband data signal may, for example, be a string of binary data bits. The other input to the EXCLUSIVE-OR gate 11 is a pseudo-random pulse sequence PN having a data rate which is greater than the baseband data rate.
The baseband data signal is encoded (mixed) with the pseudo-random pulse sequence in the EXCLUSIVE-OR gate 11 and the encoded output signal from the EXCLUSIVE-OR gate is applied to the D input of the D-type flip-flops 13 and 14.
A D-type clocked flip-flop is defined ~s being the type of flip flop which provide~ output signals having two output ~tates, for example, a high state (1) and a low state (0);
and which is constructed to have at least a single data in-put terminal designated D; a clock input terminal designated C; and complemen~ary output terminals, designated Q and Q
The logic state of the signal present at the data input D
appears at the Q output after the occurrence of a particular clocking transition and remains at the Q output until the occurrence of the next like clocking ~ransition. In the preferred embodiment of the present invention, the trailing edge of a falling clock pulse i9 used as the particular clocking transition.
A PN clock signal having a rate that 1~ one-half the rate of the pseudo-random pulse sequence signal PN i8 _ 5 _ i, .
~ r~.~,.s~ ?~ rc ~ s ~v ~rrr7,~y~ tl~r~ , """ ",, applied to the C input of flip-flop 13 and to the input of an inverter 15. The PN clock ~ign~l is logically inverted by inverter 15 an~ applied to the C input of the fllp-flop 14. The signal present at the output of the EXCLUSIVE-OR
gate 11 is clocked to the Q terminals of the respective flip-flops in a staggered fashion; that iQ ~ every even bit of the mixed data and PN sequence signals i8 applied to the flip-flop 13 with every odd bit of the mixed data and PN
sequence signals being applied to the D input of flip-flop 14. The Q output of flip-flop 13 is connected to an input of a balanced mixer 17. The line connecting the two i8 labeled I'. The Q output from flip-flop 14 i9 connected to an input of a balanced mixer 18. The line connecting the two is labeled Q'. A carrier oscillator 19 generates a carrier signal of frequency, "fo", which signal i9 directed ~ to a ph~se shifting circuit 20. The phase shiftlng circuit 20 provides two output signals, one of which is shifted 90 in phase with respect to the other sign~l. The un-shifted carrier signal is directed to an input of the bal-anced mixer 17. The second output signal which is shifted 90 in phase i8 directed to an input of the balanced mixer 18. In operation, the output signal from the balanced mixer 17 is a signal which shifts in phase to either a 0 phase shift or a 180 phase shift in response to the level of the signal on the I' line. The output signal from the balanced mixer 18 i8 a signal which shifts in pha~e to either a 90 phase shift or a 270 pha~e shift in refipo~e - 10 ~
to the level of the signal on the Q' line. A ~umming cir-cuit 21 linearly combines the output ~ignals from the mixers 17 and 18 to provide a four-phase PSK modulated spread spectrum signal, which signal is modulated as a function of the mixed baseband data and the pseudo-random bit sequence signals. The summing circuit 21 may be a summing amplifier of the type di~closed in "Electronic Analog Computers", by Korn and Korn, McGraw Hill, 1952, page 14. The four-phace PSK modulated spread spectrum sig-nal is then transmitted to a receiver utilizing well known transmi~sion techniques.
Recovery of the narrow bandwidth two-phase data signal from the received four-phase PSK modulated spread spectrum signal requires a high degree of correlation be^
tween the exact replica of the wideband modulating signals and the received spread spectrum signal. In the preferred embodiment of this ~nvention the wideband modulating signal - is the pseudo-random sequence signal. Therefore, a locally 8enerated PN sequence signal must match and be synchronlzed to the PN sequence portion of the received signal i~ order to collapse the spectrum of the received signal.
~` Referring now to Fig. 2, a four-phfl~e PSK modu-lated received signal, which signal ha~ a spread spectrum is received by a receiver ~not shown) and i8 applied to the ' input terminal 29. The input terminal 29 i~ connected to the input of a demodulator 50. The demodulator 50 i~ com-prised of; a correlator 30, a switching circuit 31 ~nd a :
'; '' :, ~""~ S~ ~ r~ ~ P~ S ~
~(?~6779 two-phase to four-phase encoder 32. The output of the de-modulator 50 is taken from the output of the correlator 30.
The signal present at that output is a two-phase PSK modu-lated signal with a collapsed spectrum. The two-phase mod-ulated signal from the correlator 30 is receivéd by an IF
(intermediate frequency) strip 33. The IF strip 33 may be, for example, a matched filter, which filter operates upon the signal at its input to remove all but the desired sig-nal components. The filtered signal from the IF strip 33 is a two-phase PSK modulated signal having a collapsed spectrum which signal is fed to an envelope detector 34, and to a carrier recovery circuit and to associated data detection circuitry, which circuitry forms no part of the present invention but which circuitry is disclosed in fur-ther detail in U. S. Patent No. 4,017,798. The envelope detector 34 provides an output signal which is a function of the envelope of the signal at its input. The detected envelope signal is fed to a PN lock detector circuit 38 and to the input of a PN timing recovery loop circui~ 42. The PN lock detector circuit 38 provides a lock condition sig-nal, the level of which indicates the existence, or the non-existence, of a locked condition.
In this application the term "lock condition"
means a condition wherein the PN sequence generated in the receiver is matched in a par~icular phase relationship with the sequence of the PN signal contained in the received signal. The lock condition slgnal from the lock detector 7 circuit 38 is directed to an inverting amplifier 39 wherein the logic level of the signal is inverted. The inverted signal from the amplifier 39 i9 applied to the input of an OR gate 41. The OR gate 41 also receives, as an input, a train of pulses which train of pulses is generated by an oscillator 40. In the preferred embodiment of the inven-tion the oscillator 40 provides a pulse train having a repetition rate of lOOOHz. The logic level of the signal from the output of the OR gate is directed to a divide-by-two circuit 44 the output signal of which controls the state of the switch 31. Switch 31 has two states - one connects the lines marke ~ , and ~ , to the lines marked ; ~ and ~ respectively; the other state reverses the connections such that line ~ is connected to line ~ and line ~ is connected to line ~ .
The switch 31 will be switched to one state when - the logic level of the signal from gate 41 is, for example, high and to the other state when the logic level of the signal i8 low. The logic level of the signal from gate 41 is a function of the lock condition signal from the lock detector 38. When the level of the lock condition signal, from lock detector 38, is low indi~ating a locked con~
tion, the input signal to the OR gate from inverter 39 is high. The high signal at the input of the OR gate 41 causes the output signal from the OR gate to remain high.
The switch 31 will remain ln the one state 80 long as the .
Il ~ 0 6 6~79 1 lock condition signal from the lock detector 38 indicatei~
that a lock condition exists. When the lock condition 8ig-nsl from the lock detector 38 goes high, indicatlng a 10~8 of lock, the level of the signal at the output of the amp-lifier 39 goes low. The signal from oscillator 40 passes through the OR gate 41 and toggles the switch 31 from one state to the other. The divlde-by-two circuit changes state only when the signal on its input changes state, therefore when a high level i~ignal i8 received from OR gate 41, the divide-by-two circuit will hold the switch 31 in the position that it is in at the time the high level sig-nal i9 received, and will not change that position until the next change in level of the signal from the OR gate 41.
In partial summary then, although the squarewave pulse train from the oscillator 40 also appears on an input of the OR gate 41 it will be superimposed on to the constant high level signal from the inverting amplifier 39 ~uch that the output signal from the OR gate will remain at a hlgh state and will not switch to a low state until the PN lock :
.l 20 detector 38 indicateis a loss of lock.
` The lock condition signal from the lock detector 38 i8 also applied to a controlling input of a iswitch 37.
The PN timing recovery loop 42, in response to the envelope detected signal, provides a control ~ignal indicative of the degree of lock, which signal is connected by means of switch 37 to the input of a voltage controlled oscillator (VCO) 36. The VCO 36 provides a squarewave output signal, ,.
`~ 1066779 j the rate of which ls proportional to the signal received Jt its input. The squarewave signal from VCO 36 is applied as a clocklng signal to the input of a PN generator 35.
The PN generator 35 may be a shift regi~ter wherein certain stages of the shift register have their signals fed back to the input of the shift register 90 as to create a pseudo-random sequence of pulses which pulses are taken from the last stage of the shift register. The clocking signal from the VCO 36 is used to clock the pulses through the stages of the shift register. Therefore, if the clock pulses in-crease in rate, the PN sequence of pulses will increase in rate and conversely, if the clock pulses decrease in rate, the PN sequence of pulses will also decrease in rate. The pseudo-random sequence of pulses from the PN generator 35 are fed to the two-phase to four-phase encoder 32. The PN
sequence of pulses is at this point in the system binary in nature that is, the pulses have two states, a high ~tate, and a low state. Applying two phase pulses to a phase modulator will cause the phase modulator to shift between two phases, one phase corresponding to the high level and the other corresponding to the low level. Therefore, a blnary signal is considered to be a two-phase signal. The two-phase to four-phase encoder 32 generates at its output ¦ terminals labeled ~ and ~ two signals each of which are binary in nature but staggered in time from each other.
But, because each signal i~ a function of the ~ignal at its t input, when the signals ~ and ~ are u~ed to modulate /~
-~ 1 0 6 6~7~
' qusdrature carrier ~ign~ls~ each signal modulfltes the carr-j ¦ ier signal in two different phaseis to provide a four-phase modulated signal.
A dither circult 43 receives as it~ inputs a con-trol isiignal, and the signal present at the output of the VC0 36. The dithering circuit 43 functions to oscillate the pha~e of the signal from the VC0 36 before the 9ignal is applled to the two-pha~e to four-phase encoder 32. The control signal functions to control the rate of dither, which rate iis ad~u~ted to provide efficient system opera-tion. The signal pasised by switch 37 control~ the phase and frequency of the VC0 36. The VC0 36 is synchronized to the pseudo-random sequence of the received signal when the system is in a locked condition. When the system is in an unlocked condition switch 37 under the control of the sig-nal from the PN lock detector 38 switches to take its input ; from the tenminal labeled "search voltage". The search voltage is of such a magnitude that it will drive the VC0 36, which in turn will drive the PN generator 35, to cause the rate of the locally gener~ted PN sequence to sweep to a position with respect to the received PN sequence which po-~ition will provide a lock detection ~ignal at the output of the lock detector 38.
Referring now to Fig. 3 wherein a more detailed block diagram of the demodulator, or spectrum collapsing circuit, 50 is shown; the PN sequence signal from the PN
generator 35 is directed to the D inputs of the D-type ~ 7 7 9 flip-flops 45 and 46. The dithered signal from the dither circuit 43 is applied to the C input of flip-flop 45 and to the C input of fl~p-flop 46, after a logic inversion which takes place in the inverter 56. The Q output terminal of flip-flop 45 is connected to the ~ labeled line of switch 31, The Q output terminal of flip-flop 46 is connected to the ~ labeled linè of switch 310 Switch 31 is so construct-ed that a signal present on the lines ~ and ~ can be con-nected in one state to the lines labeled ~ and ~ respective-ly, and in the other state connected to the lines labeled `` ~ and ~ respectively. The state of the switch 31 is con-trolled by the switching signal from the OR gate 41 shown in Fig. 2, The line ~ from switch 31, is co~nected to an input of a mixer 52. The mixer 52 may be a balanced mixer.
: The line ~ , from switch 31, is connected to an input of a balanced mixer 54. The received four-phase PSK modulated spread spectrum signal is applied to terminal 49. Terminal 49 is connected to a phase splitting circuit 47. The phase splitting circuit 47 prov~des two output signals, one having a 0 phase shift and the other having a 90 phase shift.
The 0 phase shift signal is applied to an input of the balanced mixer`54 and the 90 phase shift signal is applied to an input of thebalanced mixer 52, In operation, the 90 phase shifted signal to the balanced mixer 54 will shift the phase of the signal re-ceived on the ~ labeled input to the balanced mixer by_ _ -,, :, . , ........... .. .,............ : .
. :- . . . . : , .
` 1066779 either 90 or 270 depending on the level of the signal from the phase splitter. The 0 phase shifted signal applied to an input of the phase mixer 54 will shift the phase of the signal present on the ~ labeled input by either 0 or 180 depending upon the level of the 0 phase shifted signal. The signals from the balanced mixers 52 and 54 are added together by a summing circuit 55. Each of the balanced mixers 52 and 54 remove one-half of the pseudo-random modulation sequence such that a combining of the two signals from the balanced mixer by the summer 55 removes totally the PN modulation sequence from the PSK
modulated signal. Removal of the PN sequence operates to effectively collapse the spectrum of the spread spectrum signal to its original bandwidth, while summing the two signals from the balanced mixers also removes the four-phase feature of the received signal such that the output signal from the summer 55 is a two-phase PSK modulated signal of narrow bandwidth.
In order to effectively accomplish the spectrum collapse of the received signal, it is necessary to proper-ly phase the locally generated PN sequence with respect to the received PN sequence such that cancellation takes place. This phasing is accomplished by rotating the phase map of the locally generated four-phase PN sequence slgnal about the 0 and 180 axis. Electronically this is accom-plished by the use of switch 31. Switch 31 in one pGsition connects the ~ and ~ lines and the ~ and ~ lines together. In the other position the switch connects the and ~ lines and the ~ and ~ lines together. In an unlocked condltion the switch 31 responds to the ~quare wave signal from the oscillator 40 to toggle back and forth 80 as to continually reverse the connection~ between the Q
outputs of the flip-flops 45 and 46 and the ~ and llnes connected to the balanced mixers 52 and 54.
Figs. 4A and 4B illustrate the principal of rota-ting the phase mflp of the spectrum collapsing circuit 50.
In Fig. 4A the 90 and 270 phase vectors correspond to the 01, and 10, digital symbols respectively. In Fig. 4B the 90 and 270 phase vectors correspond to the 10, and 01, digital Yymbols respectively. This reversal is brought a-bout by reversing the inputs to the respective double bal-anced mixers utilizing the switch 31.
Referring back momentarily to Fig. 2 in conjunc-tion with Fig. 3, the demodulator S0 is ~hown comprised of the correlator 30, the switch 31 and the two-phase to four-phase encoder 32. In Fig. 3 the correspondence in term~ of components are: the flip-flops 45 and 46 along with the inverter 56 form the two-pha~e to four-phase encoder 32, ~' the switch 31 corresponds to the switch block 31, and the correlator 30 corresponds to the balanced mixers 52 and 54 along with the phase shift circuit 47, and the summing cir-cuit 55.
While there has been shown what i8 con~idered to be the preferred embodiment of the invention, it will be _ ~.9 _ -~
` 1066~79 manifest that many changes and modification~ may be made therein without departing from the es~ential spirit of the invention. It is intended, therefore, in the annexed :` claims, to cover all such changes and modifications that may fall within the true scope of the invention.
In a bi-phase PSK communication system the phase of a reference carrier ~ignal is shifted (encoded) in accordance with the coding of a data signal. As an exam-ple, if a binary "0" is to be transmitted the phase of the reference carrier signal would be unQhifted, or 0; and if a binary "1" were to be transmitted the phase of the refer-ence carrier signal would beshifted 180.
Once the carrier signal is phase modulated it may~
be transmitted to a receiver over a transmi~sion line or a radio link.
Aside from bi-pha~e PSK modulation, quadrature (four) phase modulation may also be used. In a quadrature phase communication system the information signal, which i8 generally a string of binary bits, is proportioned into baud intervals, that is, into groups of two binary bits.
The succession of phase changes occurring in successive baud intervals is then used to modulate the reference carr-ier signal in four phases.
For example, four digital symbols such a~ 00, 01 10 and 11 may be transmitted for quadrature phase modul~-tion of the carrier s~gnal. Each of the four different I phases of the carrier signal may be used to represent a `
,, :
~ 3 .s, different one of the four digital symbols. Th~t i8, the phase angle 0 can represent the digital symbol, 00; and the phase angles 90, 180, and 270, can repre~ent the digital symbols 01, 11 and 10, respectively.
In certain communication environments, it is necessary to provide a signal which cannot be interfered with, that iB, a signal which is secure and cannot be ~ammed, interrupted, or received by an unauthori~ed receiver.
The security afforded to a PSK signal is somewh~t limited in that a receiver, having its local reference carrier signal synchronized to the received PSK signal, will be able to demodulate the received PSK signal to ar- -rive at the data signal. In addition, once the frequency of the carrier signal or the frequency spectrum of the data signal is known, it is a relatively simple procedure for a ~ammer to intentionally disrupt communications. In order to minimize this particular weakness in digital communica-:~;
tions systems a scheme has been devised whereby the band-width of the transmitted signal ls spread over a larger bandwidth than that of the data signal. This is generally ~i accomplished by mixing the data signal with a pseudo-randomsequence of pulses having a bandwidth greater than the bsndwidth of the data. The mixed signal is then used to phase modulate a reference carrier signal. Transmission of this type of spread spectrum signal makes it exceedipgly dlfficult to determlne the data carrylng components of the ~.
- 4 - ;
?;~
transmitted slgnal and therefore, in turn, to achieve ef-fective ~amming. In order to receive a spread spectrum signal that is encoded in the above manner, it is nece-s~ary to know the particular sequence of the pseudo-random sequence of pulses that was used to spread the spectrum of the data sign~l. The present invention is directed towards such a ~ystem. Efficient decoding in the receiver requires an identical code generator for generating the pseudo-random sequence, which code generator mu~t be in precise time synchronization with the pseudo-random sequence of the spread spectrum signal.
A publication which provides an insight into the state of the art of spread spectrum signal processing i8 entitled "Surface Acoustic Wave Devices And Applications", by B. J. Hunsinger, published in the November 1973 issue of Ultragonics, page 25 to page 263. Another publication of interest is entitled "Optimal Binary Sequences For Spread Spectrum Multiplexing", by R. Gold published in the IEEE Transactions On Information Theory, October 1967, pages 619 to 621.
~` ~
~ 1 0 6 6 7 7 9 Summary of the Invention In the present invention a pseudo-random sequence of binary pulses is used to encode a data signal into four-phase signals. The encoded signals are then used to modu-late the phase of a carrier signal in four phases so as to spread the spectrum of the modulated signal to that of the pseudo-random sequence.
In a preferred embodiment of the pre~ent inven-tion there is provided a generator means for generating a local carrier signal corresponding to the spread spectrum signal portion of a received signal, correlator means for correlating the generated local carrier signal with the re-ceived signal so as to collapse the spread spectrum signal portion of the received signal, and reversing means inter-posed between the generator means and the correlator means - for changing the correlation relationship of components of ` the signal from the generated local carrier signal with the spread spectrum signal portion of the received signal.
More specifically, demodulation of 3 signal which is modulated utilizing the above technique is acco~plished by divid~ng the received signal along two signal paths, one of which shifts the phase of the received signal by 90. A
pair of mixers are positioned, one each, in each of the Signal psths. Means are provided for generating a local pseudo-random (PN) sequence of pulses, which sequence cor-responds to the sequence used to spread the spectru~ of the transmitted signal. Encoding means are provided for split-~`1 ting the pseudo-random sequence into quadrature related signalsO A switching means connects the quadrature related signals to respective inputs of the two mixers. A locking signal activates the switching means to periodically re-verse the connection~ of the quadrature related signals to ,. ~ . , . - ................ :
the two mixers for an unlocked condition and to maintain the connections in one position for a locked condition. The out-put signals from the two mixers are summed together in a summing circuit to provide the demodulator output signal which signal is a two-phase non-spread PSK modulated sig-nal. A lock detector provides the locking signal by . ~
.,: i , ;.......... ,~ . . ... , , ,~ .............. .
.. , . , .. ~..... .. .
:f - `
`'~ 10 6 6~r7~
detecting the degree of synchronizstion between the local i gener~ted PN sequence and the PN sequence contained in the ! received siRnal. A synchronizing control loop responds to the degree of synchronization 90 as to drive the local PN
sequence generator into ~ynchronization with the PN se-quence contained in the received signal.
The output ~ignal~ from the mixers are ~ignals corresponding to a four-phase PSK modulated signal of a narrow bandwidth in that each mixer removes one-half of the pseudo-rflndom modulation such that the spread bandwidth of the PN ~equence is totally removed from the received signal when the ~ignal is summed by the summing circuit. The summing circuit also, by comb~ning the signals from the mixers, converts the phase of the summed signals from four-phase to two-phase. Therefore, the output signal from the !` summing circuit i9 a two-phase collapsed spectrum PSK mod-ulàted signal, which signal may be further demodulated using well known demodulation techniques to detect the data signal.
From the foregoing, it can be seen that it is a primary ob~ect of the present invention to provide an lm-proved spread spectrum demodulator.
j It i8 still another ob~ect of the present ~nven-i~ tion to provide a demodulator for converting four-phase spread spectrum PSK signals into two-phase collapsed spec- ~-trum PSK signals.
¦~ It i8 another ob~ect of the present invention to ~,s~
.
`' 1066779 provide an improved demodulation system wherein spectrum ~, collapsing is facilitated by phase shifting a received ! spread spectrum PSK modulated signal as a function of a locally generated p9eudo-random sequence 8ignal.
These and other ob~ects of the present invention , will become more apparent when taken in con~unction with ; the following description and drawings in which like char-acters indicate like parts and which drawings form a part of the pre~ent invention.
Brief_Description of the Drawin~s Fig. 1 is a detailed block schematic diagram of a spread ~pectrum modulator;
-; Fig. 2 i~ a schematic diagram of a portion of a spread ~pectrum receiver utilizing the demodulator of the ` pre~ent invention;
Fig. 3 is a detailed block schem~tic diagram of . . .
-~ the demodulator of the present invention; and Figs. 4A and 4B are phase vectors useful in understanding the operation of the demodulator of Fig~. 2 -and 3.
.. . .
r .' ' Desc~ption of_the Preferred Embodiments l Referring to the modulator of Fig. l; an EXCLUSIVE-;! OR gate 11 receives at one of its input terminals a ~-seband (inform~tion) data signal having a repetition rate of RN.
The baseband data signal may, for example, be a string of binary data bits. The other input to the EXCLUSIVE-OR gate 11 is a pseudo-random pulse sequence PN having a data rate which is greater than the baseband data rate.
The baseband data signal is encoded (mixed) with the pseudo-random pulse sequence in the EXCLUSIVE-OR gate 11 and the encoded output signal from the EXCLUSIVE-OR gate is applied to the D input of the D-type flip-flops 13 and 14.
A D-type clocked flip-flop is defined ~s being the type of flip flop which provide~ output signals having two output ~tates, for example, a high state (1) and a low state (0);
and which is constructed to have at least a single data in-put terminal designated D; a clock input terminal designated C; and complemen~ary output terminals, designated Q and Q
The logic state of the signal present at the data input D
appears at the Q output after the occurrence of a particular clocking transition and remains at the Q output until the occurrence of the next like clocking ~ransition. In the preferred embodiment of the present invention, the trailing edge of a falling clock pulse i9 used as the particular clocking transition.
A PN clock signal having a rate that 1~ one-half the rate of the pseudo-random pulse sequence signal PN i8 _ 5 _ i, .
~ r~.~,.s~ ?~ rc ~ s ~v ~rrr7,~y~ tl~r~ , """ ",, applied to the C input of flip-flop 13 and to the input of an inverter 15. The PN clock ~ign~l is logically inverted by inverter 15 an~ applied to the C input of the fllp-flop 14. The signal present at the output of the EXCLUSIVE-OR
gate 11 is clocked to the Q terminals of the respective flip-flops in a staggered fashion; that iQ ~ every even bit of the mixed data and PN sequence signals i8 applied to the flip-flop 13 with every odd bit of the mixed data and PN
sequence signals being applied to the D input of flip-flop 14. The Q output of flip-flop 13 is connected to an input of a balanced mixer 17. The line connecting the two i8 labeled I'. The Q output from flip-flop 14 i9 connected to an input of a balanced mixer 18. The line connecting the two is labeled Q'. A carrier oscillator 19 generates a carrier signal of frequency, "fo", which signal i9 directed ~ to a ph~se shifting circuit 20. The phase shiftlng circuit 20 provides two output signals, one of which is shifted 90 in phase with respect to the other sign~l. The un-shifted carrier signal is directed to an input of the bal-anced mixer 17. The second output signal which is shifted 90 in phase i8 directed to an input of the balanced mixer 18. In operation, the output signal from the balanced mixer 17 is a signal which shifts in phase to either a 0 phase shift or a 180 phase shift in response to the level of the signal on the I' line. The output signal from the balanced mixer 18 i8 a signal which shifts in pha~e to either a 90 phase shift or a 270 pha~e shift in refipo~e - 10 ~
to the level of the signal on the Q' line. A ~umming cir-cuit 21 linearly combines the output ~ignals from the mixers 17 and 18 to provide a four-phase PSK modulated spread spectrum signal, which signal is modulated as a function of the mixed baseband data and the pseudo-random bit sequence signals. The summing circuit 21 may be a summing amplifier of the type di~closed in "Electronic Analog Computers", by Korn and Korn, McGraw Hill, 1952, page 14. The four-phace PSK modulated spread spectrum sig-nal is then transmitted to a receiver utilizing well known transmi~sion techniques.
Recovery of the narrow bandwidth two-phase data signal from the received four-phase PSK modulated spread spectrum signal requires a high degree of correlation be^
tween the exact replica of the wideband modulating signals and the received spread spectrum signal. In the preferred embodiment of this ~nvention the wideband modulating signal - is the pseudo-random sequence signal. Therefore, a locally 8enerated PN sequence signal must match and be synchronlzed to the PN sequence portion of the received signal i~ order to collapse the spectrum of the received signal.
~` Referring now to Fig. 2, a four-phfl~e PSK modu-lated received signal, which signal ha~ a spread spectrum is received by a receiver ~not shown) and i8 applied to the ' input terminal 29. The input terminal 29 i~ connected to the input of a demodulator 50. The demodulator 50 i~ com-prised of; a correlator 30, a switching circuit 31 ~nd a :
'; '' :, ~""~ S~ ~ r~ ~ P~ S ~
~(?~6779 two-phase to four-phase encoder 32. The output of the de-modulator 50 is taken from the output of the correlator 30.
The signal present at that output is a two-phase PSK modu-lated signal with a collapsed spectrum. The two-phase mod-ulated signal from the correlator 30 is receivéd by an IF
(intermediate frequency) strip 33. The IF strip 33 may be, for example, a matched filter, which filter operates upon the signal at its input to remove all but the desired sig-nal components. The filtered signal from the IF strip 33 is a two-phase PSK modulated signal having a collapsed spectrum which signal is fed to an envelope detector 34, and to a carrier recovery circuit and to associated data detection circuitry, which circuitry forms no part of the present invention but which circuitry is disclosed in fur-ther detail in U. S. Patent No. 4,017,798. The envelope detector 34 provides an output signal which is a function of the envelope of the signal at its input. The detected envelope signal is fed to a PN lock detector circuit 38 and to the input of a PN timing recovery loop circui~ 42. The PN lock detector circuit 38 provides a lock condition sig-nal, the level of which indicates the existence, or the non-existence, of a locked condition.
In this application the term "lock condition"
means a condition wherein the PN sequence generated in the receiver is matched in a par~icular phase relationship with the sequence of the PN signal contained in the received signal. The lock condition slgnal from the lock detector 7 circuit 38 is directed to an inverting amplifier 39 wherein the logic level of the signal is inverted. The inverted signal from the amplifier 39 i9 applied to the input of an OR gate 41. The OR gate 41 also receives, as an input, a train of pulses which train of pulses is generated by an oscillator 40. In the preferred embodiment of the inven-tion the oscillator 40 provides a pulse train having a repetition rate of lOOOHz. The logic level of the signal from the output of the OR gate is directed to a divide-by-two circuit 44 the output signal of which controls the state of the switch 31. Switch 31 has two states - one connects the lines marke ~ , and ~ , to the lines marked ; ~ and ~ respectively; the other state reverses the connections such that line ~ is connected to line ~ and line ~ is connected to line ~ .
The switch 31 will be switched to one state when - the logic level of the signal from gate 41 is, for example, high and to the other state when the logic level of the signal i8 low. The logic level of the signal from gate 41 is a function of the lock condition signal from the lock detector 38. When the level of the lock condition signal, from lock detector 38, is low indi~ating a locked con~
tion, the input signal to the OR gate from inverter 39 is high. The high signal at the input of the OR gate 41 causes the output signal from the OR gate to remain high.
The switch 31 will remain ln the one state 80 long as the .
Il ~ 0 6 6~79 1 lock condition signal from the lock detector 38 indicatei~
that a lock condition exists. When the lock condition 8ig-nsl from the lock detector 38 goes high, indicatlng a 10~8 of lock, the level of the signal at the output of the amp-lifier 39 goes low. The signal from oscillator 40 passes through the OR gate 41 and toggles the switch 31 from one state to the other. The divlde-by-two circuit changes state only when the signal on its input changes state, therefore when a high level i~ignal i8 received from OR gate 41, the divide-by-two circuit will hold the switch 31 in the position that it is in at the time the high level sig-nal i9 received, and will not change that position until the next change in level of the signal from the OR gate 41.
In partial summary then, although the squarewave pulse train from the oscillator 40 also appears on an input of the OR gate 41 it will be superimposed on to the constant high level signal from the inverting amplifier 39 ~uch that the output signal from the OR gate will remain at a hlgh state and will not switch to a low state until the PN lock :
.l 20 detector 38 indicateis a loss of lock.
` The lock condition signal from the lock detector 38 i8 also applied to a controlling input of a iswitch 37.
The PN timing recovery loop 42, in response to the envelope detected signal, provides a control ~ignal indicative of the degree of lock, which signal is connected by means of switch 37 to the input of a voltage controlled oscillator (VCO) 36. The VCO 36 provides a squarewave output signal, ,.
`~ 1066779 j the rate of which ls proportional to the signal received Jt its input. The squarewave signal from VCO 36 is applied as a clocklng signal to the input of a PN generator 35.
The PN generator 35 may be a shift regi~ter wherein certain stages of the shift register have their signals fed back to the input of the shift register 90 as to create a pseudo-random sequence of pulses which pulses are taken from the last stage of the shift register. The clocking signal from the VCO 36 is used to clock the pulses through the stages of the shift register. Therefore, if the clock pulses in-crease in rate, the PN sequence of pulses will increase in rate and conversely, if the clock pulses decrease in rate, the PN sequence of pulses will also decrease in rate. The pseudo-random sequence of pulses from the PN generator 35 are fed to the two-phase to four-phase encoder 32. The PN
sequence of pulses is at this point in the system binary in nature that is, the pulses have two states, a high ~tate, and a low state. Applying two phase pulses to a phase modulator will cause the phase modulator to shift between two phases, one phase corresponding to the high level and the other corresponding to the low level. Therefore, a blnary signal is considered to be a two-phase signal. The two-phase to four-phase encoder 32 generates at its output ¦ terminals labeled ~ and ~ two signals each of which are binary in nature but staggered in time from each other.
But, because each signal i~ a function of the ~ignal at its t input, when the signals ~ and ~ are u~ed to modulate /~
-~ 1 0 6 6~7~
' qusdrature carrier ~ign~ls~ each signal modulfltes the carr-j ¦ ier signal in two different phaseis to provide a four-phase modulated signal.
A dither circult 43 receives as it~ inputs a con-trol isiignal, and the signal present at the output of the VC0 36. The dithering circuit 43 functions to oscillate the pha~e of the signal from the VC0 36 before the 9ignal is applled to the two-pha~e to four-phase encoder 32. The control signal functions to control the rate of dither, which rate iis ad~u~ted to provide efficient system opera-tion. The signal pasised by switch 37 control~ the phase and frequency of the VC0 36. The VC0 36 is synchronized to the pseudo-random sequence of the received signal when the system is in a locked condition. When the system is in an unlocked condition switch 37 under the control of the sig-nal from the PN lock detector 38 switches to take its input ; from the tenminal labeled "search voltage". The search voltage is of such a magnitude that it will drive the VC0 36, which in turn will drive the PN generator 35, to cause the rate of the locally gener~ted PN sequence to sweep to a position with respect to the received PN sequence which po-~ition will provide a lock detection ~ignal at the output of the lock detector 38.
Referring now to Fig. 3 wherein a more detailed block diagram of the demodulator, or spectrum collapsing circuit, 50 is shown; the PN sequence signal from the PN
generator 35 is directed to the D inputs of the D-type ~ 7 7 9 flip-flops 45 and 46. The dithered signal from the dither circuit 43 is applied to the C input of flip-flop 45 and to the C input of fl~p-flop 46, after a logic inversion which takes place in the inverter 56. The Q output terminal of flip-flop 45 is connected to the ~ labeled line of switch 31, The Q output terminal of flip-flop 46 is connected to the ~ labeled linè of switch 310 Switch 31 is so construct-ed that a signal present on the lines ~ and ~ can be con-nected in one state to the lines labeled ~ and ~ respective-ly, and in the other state connected to the lines labeled `` ~ and ~ respectively. The state of the switch 31 is con-trolled by the switching signal from the OR gate 41 shown in Fig. 2, The line ~ from switch 31, is co~nected to an input of a mixer 52. The mixer 52 may be a balanced mixer.
: The line ~ , from switch 31, is connected to an input of a balanced mixer 54. The received four-phase PSK modulated spread spectrum signal is applied to terminal 49. Terminal 49 is connected to a phase splitting circuit 47. The phase splitting circuit 47 prov~des two output signals, one having a 0 phase shift and the other having a 90 phase shift.
The 0 phase shift signal is applied to an input of the balanced mixer`54 and the 90 phase shift signal is applied to an input of thebalanced mixer 52, In operation, the 90 phase shifted signal to the balanced mixer 54 will shift the phase of the signal re-ceived on the ~ labeled input to the balanced mixer by_ _ -,, :, . , ........... .. .,............ : .
. :- . . . . : , .
` 1066779 either 90 or 270 depending on the level of the signal from the phase splitter. The 0 phase shifted signal applied to an input of the phase mixer 54 will shift the phase of the signal present on the ~ labeled input by either 0 or 180 depending upon the level of the 0 phase shifted signal. The signals from the balanced mixers 52 and 54 are added together by a summing circuit 55. Each of the balanced mixers 52 and 54 remove one-half of the pseudo-random modulation sequence such that a combining of the two signals from the balanced mixer by the summer 55 removes totally the PN modulation sequence from the PSK
modulated signal. Removal of the PN sequence operates to effectively collapse the spectrum of the spread spectrum signal to its original bandwidth, while summing the two signals from the balanced mixers also removes the four-phase feature of the received signal such that the output signal from the summer 55 is a two-phase PSK modulated signal of narrow bandwidth.
In order to effectively accomplish the spectrum collapse of the received signal, it is necessary to proper-ly phase the locally generated PN sequence with respect to the received PN sequence such that cancellation takes place. This phasing is accomplished by rotating the phase map of the locally generated four-phase PN sequence slgnal about the 0 and 180 axis. Electronically this is accom-plished by the use of switch 31. Switch 31 in one pGsition connects the ~ and ~ lines and the ~ and ~ lines together. In the other position the switch connects the and ~ lines and the ~ and ~ lines together. In an unlocked condltion the switch 31 responds to the ~quare wave signal from the oscillator 40 to toggle back and forth 80 as to continually reverse the connection~ between the Q
outputs of the flip-flops 45 and 46 and the ~ and llnes connected to the balanced mixers 52 and 54.
Figs. 4A and 4B illustrate the principal of rota-ting the phase mflp of the spectrum collapsing circuit 50.
In Fig. 4A the 90 and 270 phase vectors correspond to the 01, and 10, digital symbols respectively. In Fig. 4B the 90 and 270 phase vectors correspond to the 10, and 01, digital Yymbols respectively. This reversal is brought a-bout by reversing the inputs to the respective double bal-anced mixers utilizing the switch 31.
Referring back momentarily to Fig. 2 in conjunc-tion with Fig. 3, the demodulator S0 is ~hown comprised of the correlator 30, the switch 31 and the two-phase to four-phase encoder 32. In Fig. 3 the correspondence in term~ of components are: the flip-flops 45 and 46 along with the inverter 56 form the two-pha~e to four-phase encoder 32, ~' the switch 31 corresponds to the switch block 31, and the correlator 30 corresponds to the balanced mixers 52 and 54 along with the phase shift circuit 47, and the summing cir-cuit 55.
While there has been shown what i8 con~idered to be the preferred embodiment of the invention, it will be _ ~.9 _ -~
` 1066~79 manifest that many changes and modification~ may be made therein without departing from the es~ential spirit of the invention. It is intended, therefore, in the annexed :` claims, to cover all such changes and modifications that may fall within the true scope of the invention.
Claims (12)
1. A demodulator for collapsing the spectrum of a received signal, which signal is a spread spectrum phase shift keyed modu-lated carrier signal comprising: generator means for generating a local carrier signal corresponding to the spread spectrum sig-nal portion of said received signal; correlator means for cor-relating the generated local carrier signal with the received signal so as to collapse the spread spectrum signal portion of said received signal; and reversing means interposed between said generator means and said correlator means for changing the cor-relation relationship of components of the signal from said gen-erated local carrier signal with the spread spectrum signal por-tion of said received signal.
2. The demodulator according to claim 1 and further com-prising means responsive to the degree of correlation between the spread spectrum signal portion of said received signal and said generated local carrier signal for providing a control signal to said reversing means for switching said reversing means to a state which maximizes the degree of correlation.
3. The demodulator according to claim 1 and further com-prising synchronizing means responsive to the degree of corre-lation between the spread spectrum signal portion of said re-ceived signal and said generated local carrier signal for con-trolling the rate of said generated local carrier signal so as to synchronize said generated local carrier signal with the spread spectrum signal portion of said received signal.
4. The demodulator according to claim 1 wherein the spread spectrum of said received signal is generated by modulat-ing a carrier signal with a pseudo-random sequence signal, and 4 (concluded) wherein said generator means is a means for generating a local pseudo-random sequence signal corresponding to the pseudo-random sequence signal used to modulate the carrier signal of said re-ceived signal.
5. The demodulator according to claim 4 wherein the pseudo-random sequence signal used to modulate the carrier sig-nal of the received signal is four phase encoded and wherein said demodulator is further comprised of encoder means interposed between said reversing means and said generating means for encod-ing said local pseudo-random sequence signal in four phase.
6. A demodulator for collapsing the spectrum of a received signal, which signal is a four phase PSK modulated carrier signal having a spread spectrum component which component was generated by modulating said carrier signal with a pseudo-random sequence signal, said demodulator comprising: means for generating a local pseudo-random sequence signal corresponding to the pseudo-random sequence signal used for modulating said carrier signal;
encoder means receiving said local pseudo-random sequence signal for four phase encoding said signal; correlator means for cor-relating the signal from said encoder means with the received signal so as to collapse in-common signal components; and re-versing means interposed between said encoder means and said cor-relator means for changing the correlation of components of the signal from said encoder means with the received signal so as to effect cancellation of in-common signal components thereby col-lapsing the spectrum of said received signal.
encoder means receiving said local pseudo-random sequence signal for four phase encoding said signal; correlator means for cor-relating the signal from said encoder means with the received signal so as to collapse in-common signal components; and re-versing means interposed between said encoder means and said cor-relator means for changing the correlation of components of the signal from said encoder means with the received signal so as to effect cancellation of in-common signal components thereby col-lapsing the spectrum of said received signal.
7. The demodulator according to claim 6 and further com-prising means responsive to the degree of correlation between the signal from said encoder means and said received signal for providing a control signal to said reversing means for switching 7 (concluded) said reversing means to a state which maximizes the degree of correlation.
8. The demodulator according to claim 6 and further com-prising synchronizing means responsive to the degree of corre-lation between the signal from said encoder means and the re-ceived signal for controlling the rate of the local pseudo-random sequence signal, so as to synchronize the signal from said encod-er means with said received signal.
9. A demodulator comprising: phase splitting means re-sponsive to a received signal for dividing said received signal into two signals shifted in phase with respect to each other;
means for generating a local carrier signal corresponding to a signal component contained in the received signal; encoding means responsive to said local carrier signal for encoding said local carrier signal into two signals each corresponding to signal com-ponents contained in the received signal; correlating means for correlating each signal from said phase splitting means against the signals from said encoding means; and reversing means inter-posed between said encoding means and said correlating means for altering the phase correlation of signals from said encoding means to said correlating means so as to maintain a maximum cor-relation between the signals from said phase splitting means and the signals from said encoding means.
means for generating a local carrier signal corresponding to a signal component contained in the received signal; encoding means responsive to said local carrier signal for encoding said local carrier signal into two signals each corresponding to signal com-ponents contained in the received signal; correlating means for correlating each signal from said phase splitting means against the signals from said encoding means; and reversing means inter-posed between said encoding means and said correlating means for altering the phase correlation of signals from said encoding means to said correlating means so as to maintain a maximum cor-relation between the signals from said phase splitting means and the signals from said encoding means.
10. The demodulator according to claim 9 wherein said cor-relating means is comprised of: a pair of balanced mixers each adapted to compare one signal from said phase splitting means with one signal from said encoding means; and a summing means for summing the compared signal from said balanced mixers to provide a combined signal.
11. The demodulator according to claim 9 wherein said en-coding means divides said local carrier signal into two signals staggered in time one from the other.
12. The demodulator according to claim 9 and further com-prising dithering means for oscillating the phase of the signals from said encoding means as they are applied to said correlating means.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/611,366 US4039749A (en) | 1975-09-08 | 1975-09-08 | Spread spectrum demodulator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1066779A true CA1066779A (en) | 1979-11-20 |
Family
ID=24448738
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA259,160A Expired CA1066779A (en) | 1975-09-08 | 1976-08-16 | Spread spectrum demodulator |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4039749A (en) |
| JP (1) | JPS5233409A (en) |
| CA (1) | CA1066779A (en) |
| DE (1) | DE2640298C2 (en) |
| FR (1) | FR2323274A1 (en) |
| GB (1) | GB1510903A (en) |
Families Citing this family (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4091410A (en) * | 1976-11-08 | 1978-05-23 | Zenith Radio Corporation | Frequency and phase lock loop synchronous detecting system having a pair of phase lock conditions |
| US4149121A (en) * | 1977-06-23 | 1979-04-10 | Ncr Corporation | Four phase to two phase correlator |
| DE2742696C2 (en) * | 1977-09-22 | 1979-11-15 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Circuit for the synchronization of a pseudo-random generator arranged on the receiver for message transmission systems with pseudo-random phase shift modulation |
| US4215239A (en) * | 1977-12-05 | 1980-07-29 | E-Systems, Inc. | Apparatus for the acquisition of a carrier frequency and symbol timing lock |
| US4189677A (en) * | 1978-03-13 | 1980-02-19 | Purdue Research Foundation | Demodulator unit for spread spectrum apparatus utilized in a cellular mobile communication system |
| US4291409A (en) * | 1978-06-20 | 1981-09-22 | The Mitre Corporation | Spread spectrum communications method and apparatus |
| US4203070A (en) * | 1978-08-08 | 1980-05-13 | The Charles Stark Draper Laboratory, Inc. | Pseudo-random-number code detection and tracking system |
| US4279018A (en) * | 1979-03-06 | 1981-07-14 | Nasa | PN Lock indicator for dithered PN code tracking loop |
| US4221005A (en) * | 1979-05-21 | 1980-09-02 | Nasa | Pseudonoise code tracking loop |
| US4241312A (en) * | 1979-07-27 | 1980-12-23 | Barnes James R | Self-calibrating threshold detector |
| JPS56103557A (en) * | 1980-01-21 | 1981-08-18 | Matsushita Electric Ind Co Ltd | Receiving device |
| US4435821A (en) | 1981-03-24 | 1984-03-06 | Nippon Electric Co., Ltd. | Receiver in a frequency hopping communication system |
| DE3377886D1 (en) * | 1982-03-10 | 1988-10-06 | Emi Ltd | Improvements relating to communication over noisy lines |
| GB8621875D0 (en) * | 1986-09-11 | 1986-11-05 | Emi Plc Thorn | Signal receiver |
| US4888788A (en) * | 1986-11-20 | 1989-12-19 | Matsushita Electric Industrial Co., Ltd. | Transmitting and receiving systems |
| US4943975A (en) * | 1987-10-09 | 1990-07-24 | Clarion Co., Ltd. | Spread spectrum communication receiver |
| US5299148A (en) * | 1988-10-28 | 1994-03-29 | The Regents Of The University Of California | Self-coherence restoring signal extraction and estimation of signal direction of arrival |
| US5255210A (en) * | 1988-10-28 | 1993-10-19 | The Regents Of The University Of California | Self-coherence restoring signal extraction apparatus and method |
| US5144639A (en) * | 1989-09-08 | 1992-09-01 | Clarion Co., Ltd. | Spread-spectrum communication system |
| JP2500969Y2 (en) * | 1989-09-26 | 1996-06-12 | ミサワホーム株式会社 | Prefab housing unit |
| US5379456A (en) * | 1991-02-05 | 1995-01-03 | Whistler Corporation | Multiplying saw phase shift envelope detector |
| US5146227A (en) * | 1991-05-03 | 1992-09-08 | Whistler Corporation | Sweeping receiver |
| US5365550A (en) * | 1991-07-18 | 1994-11-15 | Pulse Electronics, Inc. | Initial synchronization and tracking circuits for spread spectrum receivers |
| US5309483A (en) * | 1991-09-16 | 1994-05-03 | Motorola, Inc. | Data recovery device |
| US5299236A (en) * | 1992-11-13 | 1994-03-29 | Toshiba America Information Systems, Inc. | System and method for obtaining and maintaining synchronization of a demodulated signal |
| CA2613096C (en) * | 2005-07-05 | 2012-08-21 | Greensols Australia Pty Ltd. | Preparation and use of cationic halides, sequestration of carbon dioxide |
| US11571261B2 (en) * | 2020-04-22 | 2023-02-07 | Medtronic Navigation, Inc. | System and method for navigation |
| US11857267B2 (en) | 2020-04-22 | 2024-01-02 | Medtronic Navigation, Inc. | System and method for navigation |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3350644A (en) * | 1965-05-20 | 1967-10-31 | Avco Corp | Slip corrector means and method for multistation networks |
| US3478268A (en) * | 1967-06-16 | 1969-11-11 | Sylvania Electric Prod | Suppression of strong interfering signals in a radio receiver |
| US3916313A (en) * | 1974-11-25 | 1975-10-28 | Us Navy | PSK-FSK spread spectrum modulation/demodulation |
-
1975
- 1975-09-08 US US05/611,366 patent/US4039749A/en not_active Expired - Lifetime
-
1976
- 1976-08-16 CA CA259,160A patent/CA1066779A/en not_active Expired
- 1976-09-02 GB GB36389/76A patent/GB1510903A/en not_active Expired
- 1976-09-06 JP JP51105880A patent/JPS5233409A/en active Pending
- 1976-09-07 FR FR7626849A patent/FR2323274A1/en active Granted
- 1976-09-08 DE DE2640298A patent/DE2640298C2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE2640298C2 (en) | 1982-09-09 |
| GB1510903A (en) | 1978-05-17 |
| DE2640298A1 (en) | 1977-03-17 |
| US4039749A (en) | 1977-08-02 |
| FR2323274A1 (en) | 1977-04-01 |
| FR2323274B1 (en) | 1981-04-30 |
| JPS5233409A (en) | 1977-03-14 |
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