CA1070022A - Digital demodulator - Google Patents
Digital demodulatorInfo
- Publication number
- CA1070022A CA1070022A CA259,763A CA259763A CA1070022A CA 1070022 A CA1070022 A CA 1070022A CA 259763 A CA259763 A CA 259763A CA 1070022 A CA1070022 A CA 1070022A
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- Canada
- Prior art keywords
- baud
- interval
- samples
- phase
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
- H04L27/233—Demodulator circuits; Receiver circuits using non-coherent demodulation
- H04L27/2331—Demodulator circuits; Receiver circuits using non-coherent demodulation wherein the received signal is demodulated using one or more delayed versions of itself
Abstract
DIGITAL DEMODULATOR
Abstract of the Disclosure A demodulator for differentially coherent phase-shift keyed data signals correlates samples taken in consecutive baud intervals. Depending on the results of at least two such correlations or lack thereof, counts are registered in unidirectional counters supplied with thresholds related to preassigned counts per baud interval.
Bistable circuits respond to the attainment, or failure of attainment, of the threshold-count levels during each baud interval, after which the counters are reset to a reference level. The states of the bistable circuits directly represent binary data without further logic operations in the four-phase case particularly.
Abstract of the Disclosure A demodulator for differentially coherent phase-shift keyed data signals correlates samples taken in consecutive baud intervals. Depending on the results of at least two such correlations or lack thereof, counts are registered in unidirectional counters supplied with thresholds related to preassigned counts per baud interval.
Bistable circuits respond to the attainment, or failure of attainment, of the threshold-count levels during each baud interval, after which the counters are reset to a reference level. The states of the bistable circuits directly represent binary data without further logic operations in the four-phase case particularly.
Description
S. Y. Tong 15 1 Field of the Invention
2 Thi.s invention relates to demodulators in da-ta.
3 transmissions systems, particularly to demodulators for
4 phase-shift~keyed data transmission systems.
5 Background of the Invention
6 Digital data transmission systems employing
7 differentially encoded phase-shift keying (PSK) are well .
8 known in t-he art. Present day PSK systems generally employ g hybrid arrangements of digital and analog circuit components. :
10 With the advent of relatively low-cost integrated circuit . ..... .. ... .
11 elements it has become possible to accomplish modulating 12 and demodulating functions in data transmission apparatus ..
13 with greater reliability and precision than with analog ele- :
14 ments known to the prior art.
15 In di~ferentially encoded PSK data transmission ~ .
16 systems~ as the name implies, data bits (taken one, two or 17 more at a time) are represented by discrete phase 18 differences measured between succeeding baud or symbol 19 intervals. Decoding is then accomplished broadly by storing 20 or delaying the absolute phases of received signals between 21 baud intervals and subtracti.ng the delayed pha.se from the .`
22 present phase. The comparison between succeeding discrete 23 phases can also be accomplished by correlating polarity ~, ~L~7~02'~
samples of the received signal with those of a replica of itself delayed by an amount comparable to a baud .interval, The latter correlation detection arrangement has been found to be highly adaptable to digital implementation. ~lowever, the siynal-processing logic arrangements heretofore proposed have been unduly complex and generally have involved pluralities of up-down counters, auxiliary shift registers and digitàl logic circuits. ~ :
It is accordingly an object of this invention to provide an improved digital demodulator for PSK data signals.
It is another object of this invention to simplify the signal processing required with digital demodulators for PSK data signals employing correlation detection.
Summary of the Invention In accordance with one aspect of the invention there is provided apparatus for demodulating a received data signaling wave encoding data elements by phase differences ~etween successive signaling in-tervals comprising: means for hard limiting said received wave to display polarity and zero crossings thereof only; shift register means having a plurality of stages for serially storing periodic samples of the output of said hard-limiting means extending over more than a signaling interval; means for comparing the instant sample of the received wave at the input of said shift register means with samples from the present and succeeding signalin~ interval stored therein, said comparing means generating complementary outputs corresponding to matches and mismatches respectively between compared samples;
counting means responsive to outputs of said comparing means representing m.smatches between pairs of ~ompared samples , 1al71)~;~2 and having preassigned threshold counts; bis-table circuit means responsive to the attainment or no-t of -threshold count levels by said counting means in each signaling interval, the output state of said bistable circuit means corresponding to decoded digital data; and means for resetting saicl counting means to a reference state at the beginning of each signaling interval.
In accordance with another aspect: of the invention there is provided a demodulator for differentiall~ phase encoded digi~al data comprising storage means for a plurality of samples of received digital data encoded on _ phases of a carrier wave of a given frequency, first and second exclusive~
OR means for correlating the input to said storage means .
with previous inputs separated by one baud interval plus and minus ~/n radians of said carrier wave to provide first and ~
second bivalued correlation signals, first and second re- ~.
settable counter means responsive to said first and second correlation signals respectively and having preassigned threshold output count levels, first and second bistahle circuit means, and means for gating the count-up state o said first and second counting means respectively to said ~irst and second bistable circuit means at baud intervals to indicate whe~her or not the preassigned thresholds of said counter means have been crossed and for thereafter resetting said counter means to a reference condition, the resultant states of said bistable means representing decoded digital data.
In accordance with this invention, a demodulator : for differentially coherent PSK data signals comprises an ..
amplitude limiter for squaring up received data signals, a shift register for serially storing periodic samples taken '..:
,~ .
:. ~
: . : , .
. ~ . - .
~170~;~Z
at a rate higher than the baud ra~e o~ the squared data signals, a pair of correlators for the instantly received signals and delayed replicas thereof, a unidirectional counter driven by each correlator and having at least one predetermined threshold-count level, and a bistable circuit responsive to each counter.
In a digital demodulator for an illustrative four-phase differentially encoded PSK data transmission system, wherein serial data are encoded in dibit-pairs on each o~
the discrete phase changes of 90_ electrical degrees, where _ = 0,1,2 and 3, i.e., zero degrees, +90 degrees, 180 degrees and 270 (-90) degrees, encoding dibits 00, 01, 11 and 10 respectively, a sampling rate is selected so that each half-cycle of the carrier wave is sampled at least Eour times and preferably several times that number to reduce quantizing error and thus to insure adequate noise performance. Correlations are made between the instant input sample and samples delayed by one baud interval plus and minus ~/4 radians or 45 electrical degrees. Thus correlations are made between the instant input and delayed samples relatively delayed by 90 degrees of the carrier wave. Exclusive-OR gates readily serve as correlators.
The illustrative embodiment contemplates data transmission within the telephone voiceband (approximately 300 to 3000 ~z) at a baud rate of 600 on a carrier wave at a frequency of 1200 Hz for an effective binary data rate of 1200 bits per second ~one dibit per baud interval). The counter thresholds are established at or somewhat above half the sampling count corresponding to a baud interval.
dibit coding scheme is selected such that a count above the counter threshold indicates that a "one" or mar~ing bit was ~ 4 ~
. ...,:
~L07~
`
transmitted and a count below the threshold within a baud interval indicates that a "zero" or spacing bit was transmitted. The s-tate of each counter, i.e., above or below threshold, is transferred to a bistable flip-10p at the end of each baud interval and each count:er is reset.
Finally, the state of one flip-flop is transerred to the other, whereby the two flip-flops act as parallel-to-serial converters. A baud-rate clock controls the transfers from counters to flip-flops and as well the resetting of the counters.
The principle of this invention can readily be extended to higher-level PSK systems. The establishment of additional counter thresholds and the provision of appropriate logic circuitry controlled by such additional thresholds then becomes straightforward.
Brief Description of the Drawing The objects and features of this invention will become more apparent from a consideration of the following detailed description and the drawing in which FIGo 1 is a block diagram of an embodiment for digital demodulation of a differentially encoded four-phase PSK data signal in accordance with this invention; and FIG~ 2 is vector diagram useful in explaining the principle of this invention.
Description of the Illustratlve Embodiment Turning first to FIG~ 2 O~ the drawing, one obs~rves a set of rectangular X- and Y-coordinates with a -~
polar diagram superimposed thereon. If a vector 6 representing the relative phase of a carrier wave is assumed to be centered at point 5, having rectangular coordinates (1~ 21)~ then the vector during the center portion of a given - 5 - ~
:
~)7~;2Z
signaling baud interval can rest a-t one of the ~our points, such as 7, centered in the four quadrants drawn about point 5. The four points are further identified by the discrete phase changes of zero, ~90 and 180 degrees represented thereby. The coordinates (21~ 12) of point 5 represent the normalized values of half the total count corresponding to a baud interval. Thus, if a sampling rate of 256 times per baud interval is chosen, thexe are 256 counts per baud interval and 12 corresponds to a count of 128. These coordinates then are the threshold counts for the correlation counters.
If the carrier waves for succeeding baud intervals are in phase and these waves are relatively delayed by one baud interval, there will be total correlation and a counter will register zero, assuming no noise in the system and conventional exclusive-OR operation with no correlator output on matching samples. If further these in-phase carrier waves are respectively advanced and retarded by 45 degrees, then it is apparent that correlation will be attained on three-fourths of the counts assigned to each baud interval and both correlation counters will fail to exceed the one-half count (128) threshold. The data decoded will accordingly be the dibit pair 00, as diagrammed in -quadrant III of FIG. 2.
I the carrier waves for succeeding baud intervals are in opposite phase and correlations are taken with 45 degree advancements and retardations, correlation will be attained for only one-fourth the assigned counts in both cases and both associated counters will exceed the threshold. Accordingly, the data decoded will be the dibit pair 11 (quadrant I of FIG. 2).
~ - 5a -~7~22 If the carrier waves in succeeding baud intervals differ in phase by plus or ~inus 90 degrees and correlations are taken with the prior wave advanced and retarded as before by 45 degrees, it can be shown that the respective correlations will occur during either one quarter or three-quarters of the baud interval. In the +90 degree phase-change case the X-correlation will be below the threshold count and the Y-correlation, above the threshold count. In the -90 degree phase-change case the X-correlation will be above the threshold count and the Y-correlation, below the threshold count. Thus the +90 degree and -90 degree correlations decode the dibit pairs 01 and 10, respectively, - 5b -S. Y. Tong 15 1 as sho~n in quadrants II and IV of ~IG. 2.
2 Under the plan ou-tlined above, the four dibit phase 3 codes can be recognized with only t~o up-counters in 4 contrast to the prior art, ~hlch required a reversible 5 averaging counter for each of the four dibit pairs.
6 It is apparent that this principle can be extended 7 to eight-phase (and even higher order cases where signal-8 to-noise ratios of the transmission medium permit) PSK
10 With the advent of relatively low-cost integrated circuit . ..... .. ... .
11 elements it has become possible to accomplish modulating 12 and demodulating functions in data transmission apparatus ..
13 with greater reliability and precision than with analog ele- :
14 ments known to the prior art.
15 In di~ferentially encoded PSK data transmission ~ .
16 systems~ as the name implies, data bits (taken one, two or 17 more at a time) are represented by discrete phase 18 differences measured between succeeding baud or symbol 19 intervals. Decoding is then accomplished broadly by storing 20 or delaying the absolute phases of received signals between 21 baud intervals and subtracti.ng the delayed pha.se from the .`
22 present phase. The comparison between succeeding discrete 23 phases can also be accomplished by correlating polarity ~, ~L~7~02'~
samples of the received signal with those of a replica of itself delayed by an amount comparable to a baud .interval, The latter correlation detection arrangement has been found to be highly adaptable to digital implementation. ~lowever, the siynal-processing logic arrangements heretofore proposed have been unduly complex and generally have involved pluralities of up-down counters, auxiliary shift registers and digitàl logic circuits. ~ :
It is accordingly an object of this invention to provide an improved digital demodulator for PSK data signals.
It is another object of this invention to simplify the signal processing required with digital demodulators for PSK data signals employing correlation detection.
Summary of the Invention In accordance with one aspect of the invention there is provided apparatus for demodulating a received data signaling wave encoding data elements by phase differences ~etween successive signaling in-tervals comprising: means for hard limiting said received wave to display polarity and zero crossings thereof only; shift register means having a plurality of stages for serially storing periodic samples of the output of said hard-limiting means extending over more than a signaling interval; means for comparing the instant sample of the received wave at the input of said shift register means with samples from the present and succeeding signalin~ interval stored therein, said comparing means generating complementary outputs corresponding to matches and mismatches respectively between compared samples;
counting means responsive to outputs of said comparing means representing m.smatches between pairs of ~ompared samples , 1al71)~;~2 and having preassigned threshold counts; bis-table circuit means responsive to the attainment or no-t of -threshold count levels by said counting means in each signaling interval, the output state of said bistable circuit means corresponding to decoded digital data; and means for resetting saicl counting means to a reference state at the beginning of each signaling interval.
In accordance with another aspect: of the invention there is provided a demodulator for differentiall~ phase encoded digi~al data comprising storage means for a plurality of samples of received digital data encoded on _ phases of a carrier wave of a given frequency, first and second exclusive~
OR means for correlating the input to said storage means .
with previous inputs separated by one baud interval plus and minus ~/n radians of said carrier wave to provide first and ~
second bivalued correlation signals, first and second re- ~.
settable counter means responsive to said first and second correlation signals respectively and having preassigned threshold output count levels, first and second bistahle circuit means, and means for gating the count-up state o said first and second counting means respectively to said ~irst and second bistable circuit means at baud intervals to indicate whe~her or not the preassigned thresholds of said counter means have been crossed and for thereafter resetting said counter means to a reference condition, the resultant states of said bistable means representing decoded digital data.
In accordance with this invention, a demodulator : for differentially coherent PSK data signals comprises an ..
amplitude limiter for squaring up received data signals, a shift register for serially storing periodic samples taken '..:
,~ .
:. ~
: . : , .
. ~ . - .
~170~;~Z
at a rate higher than the baud ra~e o~ the squared data signals, a pair of correlators for the instantly received signals and delayed replicas thereof, a unidirectional counter driven by each correlator and having at least one predetermined threshold-count level, and a bistable circuit responsive to each counter.
In a digital demodulator for an illustrative four-phase differentially encoded PSK data transmission system, wherein serial data are encoded in dibit-pairs on each o~
the discrete phase changes of 90_ electrical degrees, where _ = 0,1,2 and 3, i.e., zero degrees, +90 degrees, 180 degrees and 270 (-90) degrees, encoding dibits 00, 01, 11 and 10 respectively, a sampling rate is selected so that each half-cycle of the carrier wave is sampled at least Eour times and preferably several times that number to reduce quantizing error and thus to insure adequate noise performance. Correlations are made between the instant input sample and samples delayed by one baud interval plus and minus ~/4 radians or 45 electrical degrees. Thus correlations are made between the instant input and delayed samples relatively delayed by 90 degrees of the carrier wave. Exclusive-OR gates readily serve as correlators.
The illustrative embodiment contemplates data transmission within the telephone voiceband (approximately 300 to 3000 ~z) at a baud rate of 600 on a carrier wave at a frequency of 1200 Hz for an effective binary data rate of 1200 bits per second ~one dibit per baud interval). The counter thresholds are established at or somewhat above half the sampling count corresponding to a baud interval.
dibit coding scheme is selected such that a count above the counter threshold indicates that a "one" or mar~ing bit was ~ 4 ~
. ...,:
~L07~
`
transmitted and a count below the threshold within a baud interval indicates that a "zero" or spacing bit was transmitted. The s-tate of each counter, i.e., above or below threshold, is transferred to a bistable flip-10p at the end of each baud interval and each count:er is reset.
Finally, the state of one flip-flop is transerred to the other, whereby the two flip-flops act as parallel-to-serial converters. A baud-rate clock controls the transfers from counters to flip-flops and as well the resetting of the counters.
The principle of this invention can readily be extended to higher-level PSK systems. The establishment of additional counter thresholds and the provision of appropriate logic circuitry controlled by such additional thresholds then becomes straightforward.
Brief Description of the Drawing The objects and features of this invention will become more apparent from a consideration of the following detailed description and the drawing in which FIGo 1 is a block diagram of an embodiment for digital demodulation of a differentially encoded four-phase PSK data signal in accordance with this invention; and FIG~ 2 is vector diagram useful in explaining the principle of this invention.
Description of the Illustratlve Embodiment Turning first to FIG~ 2 O~ the drawing, one obs~rves a set of rectangular X- and Y-coordinates with a -~
polar diagram superimposed thereon. If a vector 6 representing the relative phase of a carrier wave is assumed to be centered at point 5, having rectangular coordinates (1~ 21)~ then the vector during the center portion of a given - 5 - ~
:
~)7~;2Z
signaling baud interval can rest a-t one of the ~our points, such as 7, centered in the four quadrants drawn about point 5. The four points are further identified by the discrete phase changes of zero, ~90 and 180 degrees represented thereby. The coordinates (21~ 12) of point 5 represent the normalized values of half the total count corresponding to a baud interval. Thus, if a sampling rate of 256 times per baud interval is chosen, thexe are 256 counts per baud interval and 12 corresponds to a count of 128. These coordinates then are the threshold counts for the correlation counters.
If the carrier waves for succeeding baud intervals are in phase and these waves are relatively delayed by one baud interval, there will be total correlation and a counter will register zero, assuming no noise in the system and conventional exclusive-OR operation with no correlator output on matching samples. If further these in-phase carrier waves are respectively advanced and retarded by 45 degrees, then it is apparent that correlation will be attained on three-fourths of the counts assigned to each baud interval and both correlation counters will fail to exceed the one-half count (128) threshold. The data decoded will accordingly be the dibit pair 00, as diagrammed in -quadrant III of FIG. 2.
I the carrier waves for succeeding baud intervals are in opposite phase and correlations are taken with 45 degree advancements and retardations, correlation will be attained for only one-fourth the assigned counts in both cases and both associated counters will exceed the threshold. Accordingly, the data decoded will be the dibit pair 11 (quadrant I of FIG. 2).
~ - 5a -~7~22 If the carrier waves in succeeding baud intervals differ in phase by plus or ~inus 90 degrees and correlations are taken with the prior wave advanced and retarded as before by 45 degrees, it can be shown that the respective correlations will occur during either one quarter or three-quarters of the baud interval. In the +90 degree phase-change case the X-correlation will be below the threshold count and the Y-correlation, above the threshold count. In the -90 degree phase-change case the X-correlation will be above the threshold count and the Y-correlation, below the threshold count. Thus the +90 degree and -90 degree correlations decode the dibit pairs 01 and 10, respectively, - 5b -S. Y. Tong 15 1 as sho~n in quadrants II and IV of ~IG. 2.
2 Under the plan ou-tlined above, the four dibit phase 3 codes can be recognized with only t~o up-counters in 4 contrast to the prior art, ~hlch required a reversible 5 averaging counter for each of the four dibit pairs.
6 It is apparent that this principle can be extended 7 to eight-phase (and even higher order cases where signal-8 to-noise ratios of the transmission medium permit) PSK
9 encoding (three bits per baud interval). In eight-phase PSX
10 $ystems eight allowable phase changes are assigned. Four of
11 these phases are identical to the four-phase case illustrated
12 in FIG. 2. The additional four phases are parallel to the
13 X- and Y- axes. Thus, the additional phase vectors extend
14 beyond the tips of the four-phase vectors and thus can ;
15 be distinguished by threshold counts established at
16 approximately one-eighth and seven-eighths the maximum
17 counts to determine the nature of a third bit in each baud
18 interval. A third flip-flop can be provided to monitor
19 the crossings of the added thresholds.
20 FIG. 1 is a block diagram of an illustrative four- ~ -
21 phase PSK demodulator employing the principles of this
22 invention. The demodulator comprises amplitude limiter 11,
23 mult~stage shift register 13, high-speed shift generator 14 2L~ which also provides the sampling function, exclusive-OR
25 gates 19 and 20, respectively, correlating the present 26 signal sample ~ith that delayed by one baud interval plus L~5 27 degrees of carrier phase and that delayed by one baud 28 interval less 45 degrees of carrier phase, resettable up-29 counting counters 21 and 22, AND-gates 23 and 2L~ flip-30 flops 25 and 26 and baud clock 27 ~ Oscillator 12 provides a 31 frequency source at an illustrative frequency of 61L~.4 kHz, _ 6 -. .
~7~
S. Y. Tong 15 1 which can be divided down to the shift rate of 153.6 kHz 2 (L~th subharmonic) and the baud rate of 60() Hz (102~th sub-3 harmonic).
4 The exact manner in which baud clock 27 is 5 synchronized is not pertinent to this invention. Suffice it 6 to say that conventional synchronization methOds are 7 available based on monitoring zero crossings in, or the 8 envelope of, the received signals.
g In FIG. 2 the received signal on inpu-t line 10 is a 10 constant frequency wave characterized by discrete phase 11 changes in successive baud intervals, except where ~ -12 consecutive 00 dibits are transmitted. This signal is 13 hard-limited so that only polarity and zero-crossing times 14 remain as observable parameters in limiter 1]~ which can 15 advantageously comprise an amplifier and positive and 16 negative clippers. The squared output from limiter 11 is 17 connected to multis(tage shift register 13 and junction 18 18 for exclusive-OR gates 19 and 20. Shift generator 14 is 19 preferably driven by oscillator 12, which can be phase-20 locked to incoming signal transitions. The illustrative 21 shifting frequency of 153.6 kHz derived by appropriate 22 frequency division from oscillator 12 is selected to provide 23 256 samples of the received signal wave during each baud
25 gates 19 and 20, respectively, correlating the present 26 signal sample ~ith that delayed by one baud interval plus L~5 27 degrees of carrier phase and that delayed by one baud 28 interval less 45 degrees of carrier phase, resettable up-29 counting counters 21 and 22, AND-gates 23 and 2L~ flip-30 flops 25 and 26 and baud clock 27 ~ Oscillator 12 provides a 31 frequency source at an illustrative frequency of 61L~.4 kHz, _ 6 -. .
~7~
S. Y. Tong 15 1 which can be divided down to the shift rate of 153.6 kHz 2 (L~th subharmonic) and the baud rate of 60() Hz (102~th sub-3 harmonic).
4 The exact manner in which baud clock 27 is 5 synchronized is not pertinent to this invention. Suffice it 6 to say that conventional synchronization methOds are 7 available based on monitoring zero crossings in, or the 8 envelope of, the received signals.
g In FIG. 2 the received signal on inpu-t line 10 is a 10 constant frequency wave characterized by discrete phase 11 changes in successive baud intervals, except where ~ -12 consecutive 00 dibits are transmitted. This signal is 13 hard-limited so that only polarity and zero-crossing times 14 remain as observable parameters in limiter 1]~ which can 15 advantageously comprise an amplifier and positive and 16 negative clippers. The squared output from limiter 11 is 17 connected to multis(tage shift register 13 and junction 18 18 for exclusive-OR gates 19 and 20. Shift generator 14 is 19 preferably driven by oscillator 12, which can be phase-20 locked to incoming signal transitions. The illustrative 21 shifting frequency of 153.6 kHz derived by appropriate 22 frequency division from oscillator 12 is selected to provide 23 256 samples of the received signal wave during each baud
24 interval. ~his is equivalent to taking 64 samples during
25 each half-cycle of the I200 Hz carrier wave, or sixteen
26 samples for each 45 degrees of carrier phase, provided no
27 frequency offset occurs.
28
29 ~7~6~22 Shift register 13 is a multistage shift regis-ter advantageously having 272 stages. At the shifting rate of 153.6 kHz, 256 samples from each baud interval are simultaneously available. Since 45 degrees of 1200 Hz carrier phase shift corresponds to sixteen samples, shift register 13 is extende~ to 272 stages so that the time difference between the input to stage 13A and the output of stage 13T corresponds to one baud interval plus ~/4 radians or 45 degrees of carrier phase. Stage 13M provides an output at the 240th sample, which corresponds in time to one baud interval less ~/4 radians measured from the input to stage 13A. In another view stages 13M and 13T are separated by 90 degrees of carrier phase from each other. Leads 16 and 17 are respectively connected to stages 13T and 13M.
The contents of the respective stages are shifted to the ;`
right one stage at a time under control of the 153.6 kHz pulses on shift lead 15 which has a parallel branch~ such as 15A and 15T shown, to each stage of shift register 13 for simultaneous shifting of all stages.
The received signal after limiting appears at junction 18 and is applied to one input of each of exclusive-OR gates 19 and 20. Exclusive-OR gates operate to produce complementary outputs, as is well known, in response ;
to whether their binar~ inputs are alike or different. For this description it is assumed that when both inputs are different, the output is high. Otherwise, the output is low. The remaining inputs of gates 19 and 20 are connected to respective leads 16 and 17. Accordingly, the output of gate 19 is high when the received signal sample at the input of shift register stage 13A is complementary to that at the output of 272nd stage 13T, i.e., there is a failure of IL~7~2Z
correlation between the present received signal sample and that received one baud interval and 45 degrees of carrier phase previously. Similarly, the outpu-t of gate 20 goes high when there is a failure of correlation between the present received signal sample and that received one baud interval less 45 degrees oE carrier phase previously. For instantaneous correlation the outputs of gates 19 and 20 remain low.
The outputs of exclusive-OR gates 19 and 20 are applied respectively to counters 21 and 22 as shown. Each time one of these outputs goes high another count is registered in the respective X and Y counters 21 and 22. At least one preassigned threshold count level is built into the counter so that when the appropriate level is reached the counter changes its output state. In the illustrative embodiment this threshold, in order to provide a margin against noise, is set at not less half the full count level, namely: 128. Crossing of the threshold is communicated to coincidence AND-gates 23 and 24, whose other inputs are controlled by an output of baud cloc~ 27 on lead 28. The activation of lead 28 also resets counters 21 and 22 to signal the beginning of another baud interval.
Baud clock 27 under the control of oscillator 12 by way of lead 31 provides two outputs at the 600-Hz baud interval. The outputs on leads 28 and 29 are interleaved so that the output on lead 28 marks the beginning of the baud interval and that on lead 29, the center of the baud interval.
The outputs of AND-gates 23 and 24 control the s~ates of bistable flip-flops 25 and 26. D-type -Elip-flops are illustrated. This type o~ flip-flop displays S. Y. Tong 15 1 At least an output Q which goes high responsive to ac-tiva-tion 2 of the set (S) input and is complemented into going :Low respon-3 sive to activation of the reset (~) input. The D flip-flop is 4 also provided with a clock (~) input and a data (D) input.
5 The output Q follows the state of the D input only when the 6 clock input is simultaneously applied. In the present embodi-7 ment the C and D inputs are used only on flip-flop 26. The S
8 inputs are directly controlled by the ou-tputs of AND-gates 23 9 and 24. The R inputs are controlled by outputs of AND~gates 10 23 and 2L~ after inversion in inverters 31 and 32. Thus, when 11 the output of AND-gate 23 goes high, flip-flop 25 is set and 12 output Q goes high. When the output of AND-gate 23 goes 13 low, that output is inverted in inverter 31 a,nd flip-flop 25 lL~ is reset so that output Q goes low.
Flip-flop 26 displays a high or low Q output in 16 response to the output of AND-gate 2L~ in the first half of 17 the baud interval. In the second half of the baud interval 18 the Q output is high or low in accordance with the output of 19 flip-flop 25 in coincidence with the clock pulse at input C
20 from lead 29. The Q output of flip-flop 25 is connected 21 directly to the D input of flip-flop 26. Thus, flip-flop 26 22 acts both to decode the count in Y-counter 22 and to act as 23 a parallel-to series converter for the count in X-counter 2L~ 23. Accordinglya the Q output of flip-flop 26 on 25 lead 30 is -the decoded serial binary data without fur-ther 26 logic processing.
27 ~hile this invention has been described by wa~ of a 28 particular embodiment employing a stated baud rate and 29 carrier fre~uency, it will be apparent to one skilled in the
The contents of the respective stages are shifted to the ;`
right one stage at a time under control of the 153.6 kHz pulses on shift lead 15 which has a parallel branch~ such as 15A and 15T shown, to each stage of shift register 13 for simultaneous shifting of all stages.
The received signal after limiting appears at junction 18 and is applied to one input of each of exclusive-OR gates 19 and 20. Exclusive-OR gates operate to produce complementary outputs, as is well known, in response ;
to whether their binar~ inputs are alike or different. For this description it is assumed that when both inputs are different, the output is high. Otherwise, the output is low. The remaining inputs of gates 19 and 20 are connected to respective leads 16 and 17. Accordingly, the output of gate 19 is high when the received signal sample at the input of shift register stage 13A is complementary to that at the output of 272nd stage 13T, i.e., there is a failure of IL~7~2Z
correlation between the present received signal sample and that received one baud interval and 45 degrees of carrier phase previously. Similarly, the outpu-t of gate 20 goes high when there is a failure of correlation between the present received signal sample and that received one baud interval less 45 degrees oE carrier phase previously. For instantaneous correlation the outputs of gates 19 and 20 remain low.
The outputs of exclusive-OR gates 19 and 20 are applied respectively to counters 21 and 22 as shown. Each time one of these outputs goes high another count is registered in the respective X and Y counters 21 and 22. At least one preassigned threshold count level is built into the counter so that when the appropriate level is reached the counter changes its output state. In the illustrative embodiment this threshold, in order to provide a margin against noise, is set at not less half the full count level, namely: 128. Crossing of the threshold is communicated to coincidence AND-gates 23 and 24, whose other inputs are controlled by an output of baud cloc~ 27 on lead 28. The activation of lead 28 also resets counters 21 and 22 to signal the beginning of another baud interval.
Baud clock 27 under the control of oscillator 12 by way of lead 31 provides two outputs at the 600-Hz baud interval. The outputs on leads 28 and 29 are interleaved so that the output on lead 28 marks the beginning of the baud interval and that on lead 29, the center of the baud interval.
The outputs of AND-gates 23 and 24 control the s~ates of bistable flip-flops 25 and 26. D-type -Elip-flops are illustrated. This type o~ flip-flop displays S. Y. Tong 15 1 At least an output Q which goes high responsive to ac-tiva-tion 2 of the set (S) input and is complemented into going :Low respon-3 sive to activation of the reset (~) input. The D flip-flop is 4 also provided with a clock (~) input and a data (D) input.
5 The output Q follows the state of the D input only when the 6 clock input is simultaneously applied. In the present embodi-7 ment the C and D inputs are used only on flip-flop 26. The S
8 inputs are directly controlled by the ou-tputs of AND-gates 23 9 and 24. The R inputs are controlled by outputs of AND~gates 10 23 and 2L~ after inversion in inverters 31 and 32. Thus, when 11 the output of AND-gate 23 goes high, flip-flop 25 is set and 12 output Q goes high. When the output of AND-gate 23 goes 13 low, that output is inverted in inverter 31 a,nd flip-flop 25 lL~ is reset so that output Q goes low.
Flip-flop 26 displays a high or low Q output in 16 response to the output of AND-gate 2L~ in the first half of 17 the baud interval. In the second half of the baud interval 18 the Q output is high or low in accordance with the output of 19 flip-flop 25 in coincidence with the clock pulse at input C
20 from lead 29. The Q output of flip-flop 25 is connected 21 directly to the D input of flip-flop 26. Thus, flip-flop 26 22 acts both to decode the count in Y-counter 22 and to act as 23 a parallel-to series converter for the count in X-counter 2L~ 23. Accordinglya the Q output of flip-flop 26 on 25 lead 30 is -the decoded serial binary data without fur-ther 26 logic processing.
27 ~hile this invention has been described by wa~ of a 28 particular embodiment employing a stated baud rate and 29 carrier fre~uency, it will be apparent to one skilled in the
30 art that its principle i.s susceptible of modification and ~C~7~
extension to other baud rates and carrier frequencies within the spirit and scope of the following claims.
. . , i`
; - .
' : ~:
,
extension to other baud rates and carrier frequencies within the spirit and scope of the following claims.
. . , i`
; - .
' : ~:
,
Claims (9)
1. Apparatus for demodulating a received data signaling wave encoding data elements by phase differences between successive signaling intervals comprising:
means for hard limiting said reveived wave to display polarity and zero crossings thereof only;
shift register means having a plurality of stages for serially storing periodic samples of the output of said hard-limiting means extending over more than a signaling interval;
means for comparing the instant sample of the received wave at the input of said shift register means with samples from the present and succeeding signaling interval stored therein, said comparing means generating complementary outputs corresponding to matches and mismatches respectively between compared samples;
counting means responsive to outputs of said comparing means representing mismatches between pairs of compared samples and having preassigned threshold counts;
bistable circuit means responsive to the attainment or not of threshold count levels by said counting means in each signaling interval, the output state of said bistable circuit means corresponding to decoded digital data; and means for resetting said counting means to a reference state at the beginning of each signaling interval.
means for hard limiting said reveived wave to display polarity and zero crossings thereof only;
shift register means having a plurality of stages for serially storing periodic samples of the output of said hard-limiting means extending over more than a signaling interval;
means for comparing the instant sample of the received wave at the input of said shift register means with samples from the present and succeeding signaling interval stored therein, said comparing means generating complementary outputs corresponding to matches and mismatches respectively between compared samples;
counting means responsive to outputs of said comparing means representing mismatches between pairs of compared samples and having preassigned threshold counts;
bistable circuit means responsive to the attainment or not of threshold count levels by said counting means in each signaling interval, the output state of said bistable circuit means corresponding to decoded digital data; and means for resetting said counting means to a reference state at the beginning of each signaling interval.
2. Apparatus in accordance with claim 1 in which the encoding carrier phase differences are 90m electrical degrees, m being equal to 0, 1, 2 and 3; and the phase separation between the input sample to said shift register means and the previous samples compared is one baud interval plus and minus .pi./4 radians of the received wave.
3. Apparatus in accordance with claim 1 in which said comparing means comprise exclusive-OR gates having a first output state when input signals are alike and a second complementary output state when input signals are mutually complementary.
4. Apparatus in accordance with claim l in which said counting means count in one direction only in response to one binary input state and are resettable to a reference condition in response to another binary input.
5. Apparatus in accordance with claim 1 in which the number of periodic samples taken for each signaling interval is n, and the threshold count level for each of said counting means is not less than n/2.
6. Apparatus in accordance with claim 1 in which the number of periodic samples taken for each signaling interval is 256 and the threshold count level for each of said counting means is not less than 128.
7. A demodulator for differentially phase encoded digital data comprising storage means for a plurality of samples of received digital data encoded on n phases of a carrier wave of a given frequency, first and second exclusive OR means for correlating the input to said storage means with previous inputs separated by one baud interval plus and minus .pi./n radians of said carrier wave to provide first and second bivalued correlation signals, first and second resettable counter means responsive to said first and second correlation signals respectively and having preassigned threshold output count levels, first and second bistable circuit means, and means for gating the count-up state of said first and second counting means respectively to said first and second bistable circuit means at baud intervals to indicate whether or not the preassigned thresholds of said counter means have been crossed and for thereafter resetting said counter means to a reference condition, the resultant states of said bistable means representing decoded digital data.
8. The demodulator defined in claim 7 in which digital data are encoded on four discrete phases of said carrier wave separated by 90 electrical degrees, said storage means is a multistage shift register storing samples separated by at least one baud interval plus and minus 45 electrical degrees, said first exclusive-OR gate compares a signal sample entering said storage means with another signal sample received one baud interval and 45 electrical degrees previously, and said second exclusive-OR gate compares a signal sample entering said storage means with another signal sample received one baud interval less 45 electrical degrees previously.
9. The demodulator defined in claim 7 in which each discrete carrier phase difference between succeeding baud intervals encodes two binary digits and the output states of said bistable circuit means corresponds to respective ones of said binary digits.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/626,659 US3997847A (en) | 1975-10-29 | 1975-10-29 | Digital demodulator for differentially encoded phase-shift-keyed data |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1070022A true CA1070022A (en) | 1980-01-15 |
Family
ID=24511291
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA259,763A Expired CA1070022A (en) | 1975-10-29 | 1976-08-24 | Digital demodulator |
Country Status (12)
| Country | Link |
|---|---|
| US (1) | US3997847A (en) |
| JP (1) | JPS5255363A (en) |
| AU (1) | AU506065B2 (en) |
| BE (1) | BE847647A (en) |
| CA (1) | CA1070022A (en) |
| DE (1) | DE2648977C3 (en) |
| ES (1) | ES452840A1 (en) |
| FR (1) | FR2330215A1 (en) |
| GB (1) | GB1512748A (en) |
| IT (1) | IT1073389B (en) |
| NL (1) | NL186360C (en) |
| SE (1) | SE410373B (en) |
Families Citing this family (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2811488A1 (en) * | 1978-03-16 | 1979-09-27 | Siemens Ag | INTEGRATED DEMODULATOR FOR CARRIERED DIGITAL SIGNALS |
| US4216463A (en) * | 1978-08-10 | 1980-08-05 | Motorola, Inc. | Programmable digital tone detector |
| US4190802A (en) * | 1978-08-17 | 1980-02-26 | Motorola, Inc. | Digital demodulator for phase shift keyed signals |
| US4457005A (en) * | 1981-12-07 | 1984-06-26 | Motorola, Inc. | Digital coherent PSK demodulator and detector |
| DE3246145A1 (en) * | 1982-12-14 | 1984-06-14 | Standard Elektrik Lorenz Ag, 7000 Stuttgart | TELEVISION TRANSMISSION SYSTEM WITH INTEGRATED TRANSMISSION OF ADDITIONAL INFORMATION, IN PARTICULAR SOUND SIGNALS |
| FR2571194B1 (en) * | 1984-09-28 | 1992-12-11 | Lignes Telegraph Telephon | DIFFERENTIAL DEMODULATOR OF MULTI-PHASE STATE ELECTRIC SIGNALS FOR DATA TRANSMISSION EQUIPMENT |
| US4575684A (en) * | 1985-02-22 | 1986-03-11 | Honeywell Inc. | Differential phase shift keying receiver |
| JPS6231238A (en) * | 1985-08-02 | 1987-02-10 | Canon Inc | Demodulation device |
| US4715047A (en) * | 1986-04-04 | 1987-12-22 | Harris Corporation | Digital differential phase shift keyed demodulator |
| US4750215A (en) * | 1986-06-24 | 1988-06-07 | Cincinnati Microwave, Inc. | Police radar signal detection circuitry for a police radar warning receiver |
| CA1260641A (en) * | 1986-10-22 | 1989-09-26 | Jan Heynen | (ds) transmitter |
| CA2019359C (en) * | 1989-06-21 | 1993-07-06 | Hiroyasu Muto | Detection of a particular signal sequence with no adverse influence of multipath transmission |
| US5122758A (en) * | 1989-12-18 | 1992-06-16 | Nec Corporation | Differential phase demodulator for psk-modulated signals |
| EP0467712B1 (en) * | 1990-07-20 | 1998-04-29 | Nec Corporation | Phase demodulator for psk-modulated signals |
| KR960014411B1 (en) * | 1991-12-13 | 1996-10-15 | 모토로라 인코포레이티드 | Apparatus and method for direct phase digitizing |
| IL107656A (en) * | 1993-11-18 | 1996-11-14 | Dsp Telecomm Ltd | Demodulator |
| US5920593A (en) * | 1993-11-29 | 1999-07-06 | Dsp Telecommunications Ltd. | Device for personal digital cellular telephones |
| US6084530A (en) * | 1996-12-30 | 2000-07-04 | Lucent Technologies Inc. | Modulated backscatter sensor system |
| US6046683A (en) * | 1996-12-31 | 2000-04-04 | Lucent Technologies Inc. | Modulated backscatter location system |
| US6130623A (en) * | 1996-12-31 | 2000-10-10 | Lucent Technologies Inc. | Encryption for modulated backscatter systems |
| US6456668B1 (en) * | 1996-12-31 | 2002-09-24 | Lucent Technologies Inc. | QPSK modulated backscatter system |
| US6184841B1 (en) | 1996-12-31 | 2001-02-06 | Lucent Technologies Inc. | Antenna array in an RFID system |
| FR2759224B1 (en) * | 1997-02-06 | 1999-04-30 | Info Telecom | METHODS FOR ACOUSTIC TRANSMISSION AND DECODING OF A DIGITAL MESSAGE AND CORRESPONDING DEVICES |
| JP3300808B2 (en) * | 1997-03-26 | 2002-07-08 | 株式会社鷹山 | π / n shift PSK demodulator |
| US6369710B1 (en) | 2000-03-27 | 2002-04-09 | Lucent Technologies Inc. | Wireless security system |
| US20020195388A1 (en) * | 2001-05-22 | 2002-12-26 | Sierens Stephen E. | Advanced leaf disc filter segment |
| US8120465B2 (en) | 2006-02-01 | 2012-02-21 | Vitaly Drucker | RFID tag, interrogator and system with improved symbol encoding and decoding |
| US8072313B2 (en) | 2006-02-01 | 2011-12-06 | Vitaly Drucker | RFID interrogator with improved symbol decoding and systems based thereon |
| US8509361B2 (en) * | 2010-02-04 | 2013-08-13 | Issc Technologies Corp. | Simplified acquisition apparatus and method for a Bluetooth receiver |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3729684A (en) * | 1971-07-01 | 1973-04-24 | Sanders Associates Inc | Data demodulator employing multiple correlations and filters |
| US3938052A (en) * | 1974-05-09 | 1976-02-10 | Teletype Corporation | Digital demodulator for phase-modulated waveforms |
-
1975
- 1975-10-29 US US05/626,659 patent/US3997847A/en not_active Expired - Lifetime
-
1976
- 1976-08-24 CA CA259,763A patent/CA1070022A/en not_active Expired
- 1976-10-22 SE SE7611785A patent/SE410373B/en not_active IP Right Cessation
- 1976-10-25 FR FR7632073A patent/FR2330215A1/en active Granted
- 1976-10-26 AU AU19003/76A patent/AU506065B2/en not_active Expired
- 1976-10-26 BE BE171798A patent/BE847647A/en not_active IP Right Cessation
- 1976-10-27 NL NLAANVRAGE7611901,A patent/NL186360C/en not_active IP Right Cessation
- 1976-10-28 GB GB44858/76A patent/GB1512748A/en not_active Expired
- 1976-10-28 IT IT28817/76A patent/IT1073389B/en active
- 1976-10-28 DE DE2648977A patent/DE2648977C3/en not_active Expired
- 1976-10-29 ES ES452840A patent/ES452840A1/en not_active Expired
- 1976-10-29 JP JP51129555A patent/JPS5255363A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| FR2330215B1 (en) | 1981-10-23 |
| DE2648977B2 (en) | 1979-03-22 |
| IT1073389B (en) | 1985-04-17 |
| FR2330215A1 (en) | 1977-05-27 |
| AU1900376A (en) | 1978-05-04 |
| US3997847A (en) | 1976-12-14 |
| BE847647A (en) | 1977-02-14 |
| JPS5255363A (en) | 1977-05-06 |
| NL186360C (en) | 1990-11-01 |
| SE410373B (en) | 1979-10-08 |
| DE2648977C3 (en) | 1979-11-15 |
| ES452840A1 (en) | 1977-10-16 |
| GB1512748A (en) | 1978-06-01 |
| NL7611901A (en) | 1977-05-03 |
| AU506065B2 (en) | 1979-12-13 |
| DE2648977A1 (en) | 1977-05-12 |
| SE7611785L (en) | 1977-04-30 |
| NL186360B (en) | 1990-06-01 |
| JPS568537B2 (en) | 1981-02-24 |
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