CA1089996A - Safety output control for a data processing system emitting binary signals - Google Patents
Safety output control for a data processing system emitting binary signalsInfo
- Publication number
- CA1089996A CA1089996A CA290,523A CA290523A CA1089996A CA 1089996 A CA1089996 A CA 1089996A CA 290523 A CA290523 A CA 290523A CA 1089996 A CA1089996 A CA 1089996A
- Authority
- CA
- Canada
- Prior art keywords
- output
- triggering
- signals
- current supply
- exclusive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000012544 monitoring process Methods 0.000 claims abstract description 14
- 238000009434 installation Methods 0.000 claims abstract description 11
- 230000003068 static effect Effects 0.000 claims abstract description 7
- 230000001360 synchronised effect Effects 0.000 claims abstract description 4
- 238000004804 winding Methods 0.000 claims abstract description 4
- 230000008878 coupling Effects 0.000 claims abstract description 3
- 238000010168 coupling process Methods 0.000 claims abstract description 3
- 238000005859 coupling reaction Methods 0.000 claims abstract description 3
- 229910052729 chemical element Inorganic materials 0.000 abstract 1
- 238000000034 method Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 208000003251 Pruritus Diseases 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000007803 itching Effects 0.000 description 2
- 230000011664 signaling Effects 0.000 description 2
- 241000582342 Carria Species 0.000 description 1
- 101150087426 Gnal gene Proteins 0.000 description 1
- 101000657326 Homo sapiens Protein TANC2 Proteins 0.000 description 1
- 108091034117 Oligonucleotide Proteins 0.000 description 1
- 102100034784 Protein TANC2 Human genes 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 101150115956 slc25a26 gene Proteins 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1629—Error detection by comparing the output of redundant processing systems
- G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B9/00—Safety arrangements
- G05B9/02—Safety arrangements electric
- G05B9/03—Safety arrangements electric with multiple-channel loop, i.e. redundant control systems
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00392—Modifications for increasing the reliability for protection by circuit redundancy
Abstract
ABSTRACT OF THE DISCLOSURE
A safety output unit for a data processing installation which in use supplies binary signals, the safety output unit being for supplying an output amplifier comprising an output transformer having a secondary winding which in use supplies a load with fail-safe signals through a rectifier arrangement.
The unit comprises inputs for coupling to a pair of data lines which in use carry like binary signals from two micro-computers which are synchronously controlled by a common timing current supply. Two first triggering elements are coupled to receive data via respective ones of the inputs and have outputs connected to reset inputs of two respective second triggering elements of the safety output unit. The two second triggering elements have timing inputs available to receive synchronous timing pulses from the timing current supply and the two first triggering elements comprise reset inputs available for connection to the timing current supply to receive therefrom a normal setting signal. There is connected to a negated output of one second triggering ele-ment and to an output of the other second triggering element an exclusive-OR
monitoring element which can be read in dependence upon test pulses from the timing current supply and which is arranged to output the test pulses from the the case of static exclusive-OR signals and in the case of dynamic exclusive-OR signals for maintaining the timing current supply, at least one of the two second triggering elements being available for connection to an output amplifier which is to be supplied by the safety output unit.
A safety output unit for a data processing installation which in use supplies binary signals, the safety output unit being for supplying an output amplifier comprising an output transformer having a secondary winding which in use supplies a load with fail-safe signals through a rectifier arrangement.
The unit comprises inputs for coupling to a pair of data lines which in use carry like binary signals from two micro-computers which are synchronously controlled by a common timing current supply. Two first triggering elements are coupled to receive data via respective ones of the inputs and have outputs connected to reset inputs of two respective second triggering elements of the safety output unit. The two second triggering elements have timing inputs available to receive synchronous timing pulses from the timing current supply and the two first triggering elements comprise reset inputs available for connection to the timing current supply to receive therefrom a normal setting signal. There is connected to a negated output of one second triggering ele-ment and to an output of the other second triggering element an exclusive-OR
monitoring element which can be read in dependence upon test pulses from the timing current supply and which is arranged to output the test pulses from the the case of static exclusive-OR signals and in the case of dynamic exclusive-OR signals for maintaining the timing current supply, at least one of the two second triggering elements being available for connection to an output amplifier which is to be supplied by the safety output unit.
Description
99~
The invention relates to a sa~ety output unit ~or ~ data processing installation which in use supplies binary signals~ the safety output unit being for supplying an output amplifier comprising an output trans~ormer having a secondary winding which in use supplies a load with ~ail-safe signals through a rectifier arrangement.
In many t~chnical fields, electronic devices are being increasingly employed to control automated procedures. These include devices which have meanwhile become commonly commercially obtainable~ such as process computers and micro-computers. In the field of railway signalling, special s~itching 0 systems are employed with special logic circUitS which are built up from pas~-and active component parts, upon the normal working of which the safety o~ railw.~y traffic ultimately depends. However, since it must be expected that lome d~fects will arise in the component parts~ the logic circuits are ~encrally so constructed that faults in component parts can at the worst re~
sl~t in a hindrance to the operation of the signalling system~ but not in any dangerous hazard. Consequently, modenn(~ata processing installations whose units are not constructed to meet the aforesaid safety requirements cannot raadLly ba ~mployed in teclm:Lcal fields involving responsibility for safety~
auch as in railw~y systems. This applies equall~y t~herever processes must, ~0 in the event oE a Eault in the controlling devices~ be brought into a condi-kion which constitUtes no ha~ard to persons and maahines.
~ his principle can be Eurther illustrated by a mlmbcr of examples.
~on~rols Ln nuclear medicin~ may be so designed that in the event oE a defect~
for e~m~e, the irrndiation :is interrupted.
~ n control systems of passenger vehicles a reliable radar-controlled distance warning system or a reliable control means for slcid-Eree braking may be so constructed that any defect arising is brought to the driver's attention ;~
before the fault causes a malfunction ~hich restricts the travel safety.
In addition, the aforesaid safety principles should be employed in -1- ~, .
the ease of traffie-light eontrols, large-seale ehemieal proeesses, rolling mill contr~ls, power plant control~ and naclear reactor monitoring.
For the output of binary signals from an eleetronie switehing sys~
tem ~der eonditions of safety, there are gen rally employed alternating-volt-age amplifiers which deliv~r their energy for the control of any desired loads, for ~ nple relays~ through a transformer and a reetifier arrangement fed -thera~yO Sueh eireuit arrangements have the advantage that any defeets~ more particularly a short-circuit in the switching path of amplifier transistors, always result in a reduetion of the output voltage~ but never in an output volta~e whieh would eause an untimely aetivation of the relay to be eontrolled, `
which would lead to an ineorreet signal or to an undesired process control.
The de~arlbea output arrangemonts are employed in aeeordanee ~ith the fail-safe prineiplq in sueh mannor that their output voltage having zero value is alloe-~a~ td ~ha sa~o and operation-inhibiting information.
An output unit Por a logic system in which electrical loads in an ax~ernal installation are eontrolled by eontaetors by way of various linlcs batwaan the external installation and the switehing system is deseribed in aar~n Of~anla~ng~schrift 2 113 546. In this case, it is tacitly assumed th~ th~ nals n~ pll-t by -the logie system are not erroneous and that it is ~araly a matter of outputting these signals in aceordanee wib~ the aforemen-ti~nad ~a-~e-ty prineiples by creating an electric isolation between the input ~nd ~utp~lrallits~ In th:ls way~ only the eritieal ease ~f:orror is clealt with ln whicll one o~ ~he raetifier elements has a short-circuit.
Howe~ar~ the descr:`Lbed olltput un:;t eannot be directly employed in QU~9 1~ whlGh clavleo9 eontrolling a proeess, for examplejmiero-eomputors~
ara duplicated for reasons of safety, because these devices are not eonstueted in aeeordanee with the known fail-safe principle and can henee output faulty signals.
A safety arrangement for carrying out logic operations with fail-safe
The invention relates to a sa~ety output unit ~or ~ data processing installation which in use supplies binary signals~ the safety output unit being for supplying an output amplifier comprising an output trans~ormer having a secondary winding which in use supplies a load with ~ail-safe signals through a rectifier arrangement.
In many t~chnical fields, electronic devices are being increasingly employed to control automated procedures. These include devices which have meanwhile become commonly commercially obtainable~ such as process computers and micro-computers. In the field of railway signalling, special s~itching 0 systems are employed with special logic circUitS which are built up from pas~-and active component parts, upon the normal working of which the safety o~ railw.~y traffic ultimately depends. However, since it must be expected that lome d~fects will arise in the component parts~ the logic circuits are ~encrally so constructed that faults in component parts can at the worst re~
sl~t in a hindrance to the operation of the signalling system~ but not in any dangerous hazard. Consequently, modenn(~ata processing installations whose units are not constructed to meet the aforesaid safety requirements cannot raadLly ba ~mployed in teclm:Lcal fields involving responsibility for safety~
auch as in railw~y systems. This applies equall~y t~herever processes must, ~0 in the event oE a Eault in the controlling devices~ be brought into a condi-kion which constitUtes no ha~ard to persons and maahines.
~ his principle can be Eurther illustrated by a mlmbcr of examples.
~on~rols Ln nuclear medicin~ may be so designed that in the event oE a defect~
for e~m~e, the irrndiation :is interrupted.
~ n control systems of passenger vehicles a reliable radar-controlled distance warning system or a reliable control means for slcid-Eree braking may be so constructed that any defect arising is brought to the driver's attention ;~
before the fault causes a malfunction ~hich restricts the travel safety.
In addition, the aforesaid safety principles should be employed in -1- ~, .
the ease of traffie-light eontrols, large-seale ehemieal proeesses, rolling mill contr~ls, power plant control~ and naclear reactor monitoring.
For the output of binary signals from an eleetronie switehing sys~
tem ~der eonditions of safety, there are gen rally employed alternating-volt-age amplifiers which deliv~r their energy for the control of any desired loads, for ~ nple relays~ through a transformer and a reetifier arrangement fed -thera~yO Sueh eireuit arrangements have the advantage that any defeets~ more particularly a short-circuit in the switching path of amplifier transistors, always result in a reduetion of the output voltage~ but never in an output volta~e whieh would eause an untimely aetivation of the relay to be eontrolled, `
which would lead to an ineorreet signal or to an undesired process control.
The de~arlbea output arrangemonts are employed in aeeordanee ~ith the fail-safe prineiplq in sueh mannor that their output voltage having zero value is alloe-~a~ td ~ha sa~o and operation-inhibiting information.
An output unit Por a logic system in which electrical loads in an ax~ernal installation are eontrolled by eontaetors by way of various linlcs batwaan the external installation and the switehing system is deseribed in aar~n Of~anla~ng~schrift 2 113 546. In this case, it is tacitly assumed th~ th~ nals n~ pll-t by -the logie system are not erroneous and that it is ~araly a matter of outputting these signals in aceordanee wib~ the aforemen-ti~nad ~a-~e-ty prineiples by creating an electric isolation between the input ~nd ~utp~lrallits~ In th:ls way~ only the eritieal ease ~f:orror is clealt with ln whicll one o~ ~he raetifier elements has a short-circuit.
Howe~ar~ the descr:`Lbed olltput un:;t eannot be directly employed in QU~9 1~ whlGh clavleo9 eontrolling a proeess, for examplejmiero-eomputors~
ara duplicated for reasons of safety, because these devices are not eonstueted in aeeordanee with the known fail-safe principle and can henee output faulty signals.
A safety arrangement for carrying out logic operations with fail-safe
-2-9~
action is disclosed, for example~ in German Auslegesch~f~ 1 537 379. Withthe aid of this safety arrangement, employing special integrated switching circuits, essential parts of the installation are constructed in two-channel form~ like data lines carrying, in normal operation, exclusive-OR signals in the form of square-wave voltages, the phase position of which determines the momentary logic value o or l. An exclusive-OR monitoring member is associated with each circuit building block perEorming a storage or logic function.
A timing current supply system (German Patentschrift 2 135 683) for a switching system constructed in such two-channel form is so designed .
~lat, when the exclusive-OR condition is dist~rbed at one of the m~ny switch-ing membars performing storage and/or logic functions, the timing current Aupply -l~ Cllt oEE ~or tho .Eurther operat:ion. In :Eault-:Eree operation, the tim:ing s:i~na1 ~cnerator forms, together with the switching system, a kind oE
solf_holdin~ circuit, and a starting action is th~e~re required for the commencoment of operation~ The circuit building bloclcs which per-Eorm storage and logic operations in such installations need not be constructed in accord-ande with the Eail-safe principle, but a disadvantage thered`Eis that special bl~ilding bloclcs are required whLch occupy a relatively large amount oE space in ex~enslv~ switching systems as compared with micro-computers.
~ ccord.Ln~ to the present in~ention there is provided a sa:Eety OUtpllt uni~ ~or a data procc~.Lng installation which :Ln use supplLes bin~ry s:i.gnal~
~h~ ~At`et;y OlltpUt un;Lt bo:Lng Por supply:Lng an oltpUt ampli.Eicr compr:Lsing an ou-tpu~ ~ran~formor llavLng a secondary w:inding which in use supplies a load wlth :~:ll-aa~e ~:L~nals through a rect;lf;er arrangement, wherein the safety OlltpU~ uni~ comprlses inputs for coupling to a pair of data lines which in u3e carry like binary signals from two micro-computers which are synchronously controlled by a common timing current supply7 two first triggering elements coupled to receive data via respective ones of said inputs and having outputs connected to reset inputs of two respective second triggering elements of the ~1~)8~
safety output unit, the two second triggering elements having timing inputs available to recei~e synchronous timing pulses from said timing current supply and the two first triggering elements comprising reset inputs available for connection to said timing current supply t~ receiva therefrom a normal set-ting signal, there being connected to a negated output of one second trigger-ing element and to an output of the other second triggering element an exclus- `~` `
ive-OR monitoring element which can be read in dependence upon test pulses from said timing current supply and which is arranged to output the test pulses both in the case of static exclusive-OR signals and in the case of dynamic exclusive-OR signals Eor maintaining the timing current supply, a~ least one of the two second triggering elements being available for connection to an outpl~amplifier ~hich is to be supplied by the safety output unit~ ;~
With the aid of the above safety output unit, there may be obtained in an advantageous manner a pair-wise association of two data lines carrying like binary signals, it being provided in a simple ma~ner thatJ in the case oE
a fault, in the event of variation of one of two binary signals which are oP
like kind during normal operation~ the further outputting is interruptedO
~ha ao~t involvod Eor each output channel may be low. In addition, the safety ou-tput unlt only reql~ires normal commercially obtainable passive and active ~n component parts.
In one embodiment of such a saEety oukput unit~ crrors may be reveal-ad ln a sllort timo which i9 independant of the data t`low.
preferred embodimen-t~ when in use~ mc~y Eurther shorten the time ~alcan to reveal crrors in the output of binary signals having the logic value 1~ if the micro-computers can provide brief signal change-overs per programme at re~llar intervals, so that the logic value O is output for a period of a few microseconds. Such short signal change-overs pro~ided for test purposes do not cau~edisconnection of the loads owing ~o the delay properties of the latter. Thus, relays do not fall off, and the signal pattern is not changed.
4~
:. . .:. , , : - ; ..
action is disclosed, for example~ in German Auslegesch~f~ 1 537 379. Withthe aid of this safety arrangement, employing special integrated switching circuits, essential parts of the installation are constructed in two-channel form~ like data lines carrying, in normal operation, exclusive-OR signals in the form of square-wave voltages, the phase position of which determines the momentary logic value o or l. An exclusive-OR monitoring member is associated with each circuit building block perEorming a storage or logic function.
A timing current supply system (German Patentschrift 2 135 683) for a switching system constructed in such two-channel form is so designed .
~lat, when the exclusive-OR condition is dist~rbed at one of the m~ny switch-ing membars performing storage and/or logic functions, the timing current Aupply -l~ Cllt oEE ~or tho .Eurther operat:ion. In :Eault-:Eree operation, the tim:ing s:i~na1 ~cnerator forms, together with the switching system, a kind oE
solf_holdin~ circuit, and a starting action is th~e~re required for the commencoment of operation~ The circuit building bloclcs which per-Eorm storage and logic operations in such installations need not be constructed in accord-ande with the Eail-safe principle, but a disadvantage thered`Eis that special bl~ilding bloclcs are required whLch occupy a relatively large amount oE space in ex~enslv~ switching systems as compared with micro-computers.
~ ccord.Ln~ to the present in~ention there is provided a sa:Eety OUtpllt uni~ ~or a data procc~.Lng installation which :Ln use supplLes bin~ry s:i.gnal~
~h~ ~At`et;y OlltpUt un;Lt bo:Lng Por supply:Lng an oltpUt ampli.Eicr compr:Lsing an ou-tpu~ ~ran~formor llavLng a secondary w:inding which in use supplies a load wlth :~:ll-aa~e ~:L~nals through a rect;lf;er arrangement, wherein the safety OlltpU~ uni~ comprlses inputs for coupling to a pair of data lines which in u3e carry like binary signals from two micro-computers which are synchronously controlled by a common timing current supply7 two first triggering elements coupled to receive data via respective ones of said inputs and having outputs connected to reset inputs of two respective second triggering elements of the ~1~)8~
safety output unit, the two second triggering elements having timing inputs available to recei~e synchronous timing pulses from said timing current supply and the two first triggering elements comprising reset inputs available for connection to said timing current supply t~ receiva therefrom a normal set-ting signal, there being connected to a negated output of one second trigger-ing element and to an output of the other second triggering element an exclus- `~` `
ive-OR monitoring element which can be read in dependence upon test pulses from said timing current supply and which is arranged to output the test pulses both in the case of static exclusive-OR signals and in the case of dynamic exclusive-OR signals Eor maintaining the timing current supply, a~ least one of the two second triggering elements being available for connection to an outpl~amplifier ~hich is to be supplied by the safety output unit~ ;~
With the aid of the above safety output unit, there may be obtained in an advantageous manner a pair-wise association of two data lines carrying like binary signals, it being provided in a simple ma~ner thatJ in the case oE
a fault, in the event of variation of one of two binary signals which are oP
like kind during normal operation~ the further outputting is interruptedO
~ha ao~t involvod Eor each output channel may be low. In addition, the safety ou-tput unlt only reql~ires normal commercially obtainable passive and active ~n component parts.
In one embodiment of such a saEety oukput unit~ crrors may be reveal-ad ln a sllort timo which i9 independant of the data t`low.
preferred embodimen-t~ when in use~ mc~y Eurther shorten the time ~alcan to reveal crrors in the output of binary signals having the logic value 1~ if the micro-computers can provide brief signal change-overs per programme at re~llar intervals, so that the logic value O is output for a period of a few microseconds. Such short signal change-overs pro~ided for test purposes do not cau~edisconnection of the loads owing ~o the delay properties of the latter. Thus, relays do not fall off, and the signal pattern is not changed.
4~
:. . .:. , , : - ; ..
3~
If s~itching becomes impossible owing to a defect in one of the triggering elements, this results in a dist~rbance in the exclusive-OR condition~ where-by a safety tripping is automatically brought about.
For a better understanding of the inven-tion and to show how it may be put into effect reference will now be made, by way of example, to the single fi~re of the accompanying drawing, which shows a data processing installation includ-ing a safety output Imit according to the invention.
The installation, which is illus~rated substantially as a block circuit diagrc~m, comprises two micro-computers MRl and MR2 which process tuo ~;
1~ it~ems of information synchronously for reasons of sc~fety. ~espective input linoa have becn omitted from the drawing for the sake of clarity. In the il-' hlstratad emboclimont, Lt i~ immaterial what devices are~ ultimately controlled ~y tha output signals of the two micro-computers, it merely being essential thAt fail-safe ~ignals are ultinately available from the micro-computers, .ilthough they are not constructed on a Eail-safe basis.
Synchronous control of the two micro-computers MRl and MR2 takes placa by means of a timing current suppl~ TG through lines Ll and L20 In ordar that the draw:ing may be made as clear as possible, there is associated wi~h a~Gh Or th~ two micro-comp~lters MRl and MR2 only a single data line DLl and nL2 respuatively~ -through which binary signals are output either with the la~c v~lua ~ or wi-th the logic value la The pair of data lines nLl and ~L2 th~ lways carry durlng normal operAtion binary signals having the samc :logic val~l~ nnd cQrres~ondln~ to one and the same item oE information.
Tha b-lnary sign~ls outpu~ by way of the data lines DLl and DL2 lndirackly control a push-pull amplifier consisting of two amplifiers Vl and V2 and an output transformer U, to which there i9 connected a rectifier arrang- ~`
~mant GLl,.sGL~ succeeded by a capacitor Cl. There may be connected to two OUtpllt lines L3 and L4~ for example~ a rela~ which is activated when there are identic~il binary signals having the logic value 1 along the data lines DLl and ' ~0~39~
. ~.. `
DL2.
There is provided as an output building block for the micro-computer MRl, in respect of the data line DLl~ a D~triggering element Kl (to be explain-ed l~ter). Similarly~ there is connected to the data line DL2 a D-trigger-ing element KlOo The data lines DLl and DL2 are connected to the respective D_inputs oE the D-triggering elements Kl and K10. The timing pulse inputs C
of the D_triggering elemenfs Kl c~nd K10 are connected by way of control signals SGl and SG2 to the micro-computers MRl and MR2 respectively. It is incidental-ly to be noted that the lines DLl and SGl, and DL2 and SG2 are connected to the respective bus lines of the associated micro-computer. The respective reset inputs R of the D~triggering element Kl and K10 are connected by way o~ lines L5 and L6 to the timing current supply TG, whereby normal setting signals GLl nnd GL2 having the logic value 0 can be applied at a given time for the reset-t-lng oE the respective D-triggering elements Kl and K10. Generally spealcing, a flip-flop is a bistable triggering stage with two stable state~, one state of which is designated by 1 and the other by 0~ The signal that is at an output Q shows respectively which of the two states the flip-Elop is in at a particular instant. The flip-Elop can therefore be caused to alter its state vln one or several inputs. With a D-Elip-Elop or D-triggering element, thcrc a i9 provided ~an input designated by D whose ~alue during a switching step is taken ovar into the fl~p-Elop and is stored there until the next switch;ng a-tap. With the las-t ~entioned swLtching step the Elip_Elop is adlusted again nGcordin~ to thc 9ignal 1 or 0 present at -the DLinput. The switching step oE
tha ~lip-~lop that is mentioned is carr:ied out by a pulse which is supplied to the pulse input C periodically independent of the signals at the D~input to be processed. The characteristiG equation of a D-triggering element reads:
Q = D 0 T.
The outputs Q of the D-triggering elements Kl and K10 are connected to the reset inputs R of respective second D-triggering elements K2 and K200 -6_ , In this way, it is ensured that when the D-triggering element Kl or K10 is reset the respective succeeding D-triggering element K2 or K20 also remains in the reset condition by way of the respective reset input R~ The negated out-puts Q of the two D-triggering elements 1~2 and K20 then carry a signal having the logic value 1. Of the two D-triggering elements K2 and K20 the negated output Q is connected to the D-input in each instance. For a signal edge con--~rol~ tho t.iming input C of the D~triggering element K2 is connected to the timing current supply T~ through a timing signal line TLGl, and that of the D_ triggering element K20 is connected to the same timing current supply through a timing signal line TLG2. In this way, the two DLtriggering elements K2 and ~20 are continuously activated in synchronism during normal operation.
Xn add:ition, the c~mplifier Vl is connected on its input side to the n~tad mltpu-t ~of the D-triggering element K20 On the other hand~ the amp-ll~ler V2 is connected to the output Q o:E the D triggering element K20. Con-sequently during normal operation, provided that a binary signal having the logic value O i9 output through the data lines DLl and DL2, static exclusive-OR signals are applied to the two inputs of the two amplifiers Vl and V2. At the output of each binary signal having the logic value 1 through the afore-~ld dA~a line9~ dyn~mic e~clu9ive-OR 9ignals are applied to the amplifier ~0 inyuts :ln the -~or~ of two square-wave voltages 180 apart in phase~ which can ~o procassed by -th~ push-pull ~nplifier to form an output signal along ~he lin~s 1~ and ~4~
An exGlu~:Lve-OR moni-toring element AD which is connected in the same w~y as ~ha nmpl:Lfiors Vl and V2 ~o the outputs of the two D-triggering elements K2 ~nd K~ so con9-trlcted that it can serve to indicate either stat:ic ~olusive-OR signals or dynamic exclusive-OR signals (unidirectional voltage square-wave voltage)O In principle, the exclusive-OR monitoring element AD
consists of a switching transistor TR whose switching path is connected in series with a working resistor R to the direct-current branch of a bridge . ., : . . : : . . : , ... . ~, . . ...
~Lt~ 9~
rectifier arrangement comprising rectifiers Dl, D2, D3, and D40 In the case~f this exclusive-OR monitoring member AD, the switching transistor TR only receives a supply voltage whenei~er the two D-triggering elements E2 and K20 are statically in the same condition without disturbance, or operate dynami-cally and exhibit like changes of condi~ion. Test pulses TS pass from the timing current supply TG through the line L7 connected to the base electrode of thc switching transistor TR for reading the exclusive-OR monitoring element QD~ Only when the exclusive-OR condition is present are the applied test pulses TS fed back through the line L8 to the timing current supply TG, which 1~ outputs control sigllals through the lines Ll, ~2, TLGl, TLG2~ L5 and L6 by r~ason nf this faot~ until the instànt of the next test pulse TS.
SinGe~ in genercil~ not only one data line extends from each of the ml~ro-eomputers ~IRl and MR2 as illustrated in the drawing, but a plurality of d~ta lin~s, it will be obvious that~ in practice, a corresponding number of ~xclusive-OR ~onitoring elements are present. In this case~ the line L8 is n~t connected to the timing current supp:ly TG~ but extends to a further ex-sive-QR monltoring element. Consequently, the exclusive-OR monitoring al~en~s for~ a ser:ies arrangement in wh~ich the exclusive-OR monitoring ele-~nt sitllAtad last :Ln thc series i9 finally connected to the timing current supply T~.
In the ca~e of the zero setting signals ~Ll and GL2 eaah having the lo~i~ valua ~ throunh the l:Lne L5 and L6 respectively, -the D-triggering eLements Kl ~nd ~10 ~re ~aturned into coincidcnt ini-tial switching pos:ition which is es~antial fnr ~he ~tArtin~ o~ the s~f~ty output unit. In the said initial swi~al~n~ p~sition, -the -two D-triggering elements Kl and K10 apply a signal haYing the logic value O through the respective ~output to the respective reset input R of the succeeding DLtriggering elements K2 and K20 resp~ively, so that the two D~triggering elements K2 and K20 are in the reset switching con~ition and remain therein. The output Q of the D~triggering element K2 _8-.~. ' `
9~
then has the logic value l and the output Q of the D-triggering element K20 has thr logic value o. The exclusive-OR monitoring element AD consequently receives exclusive-OR static signals and is therefore conductive for the applied test pulse TS through the line L7. Si~nce the two amplifiers Vl and V2 still recieve no dynamic control signals, the voltage at the output lines L3 and L~
remains at ~ero as before.
After the first test pulse TS applied to the exclusi~e-OR monitoring element AD has returned into the timing current supply TG, the "on" phase is terminated with the cessation of the normal setting signals GLl and GL20 When signals having the logic value O are output by the micro-computers MRl and ~2 through their data lines DLl and DL2~ no change occurs in the switching condition of tha ~triggering elements 1~l and K2, and KlO and K20 respectively.
On the other hand, when the data lines DLl and DL2 carry binary ~ign~ls having the logic value l~ this value is taken up by the associated D~triggering elements Kl and K2 respectively. The respective Q-output o~ the D-trig~ering elements Kl, KlO then output the logic vilue l, whereby the associated D~triggering element K2~ K20 is cleared. This has the result that the logic value l present at the respective output ~ of the triggering elements K~ and 1520 nt this instant is t~cen up with timing control by the D~input.
2n ~hcr~after~ the respective ~-output of the D-triggering elements K2 and 1S20 carrias the logic value 0. ~hen the next timing pulse is passed through ~he tim:ln~ line TLGl~ TLG2, the D-input o~ the D-triggering element IS2, K20 takes up the logic value 0 del:ivered by the associated ~-output. It will be seen ~ha~ lth normal timing current supply, the two D-triggering elements IS2 and Is~n always switoh to and fro with t~ming control between the two possible switching conditions. In this way, the amplifiers Vl and V2 receive dynamic e~Yclusive-OR signals, i.e. square-wave voltages, which are necessary for the operation of the push-pull amplifier. Consequently, the voltage necessary for activating a relay (not shown) is present at the output lines L3, L~ in _9_ , . - ..
-9~6 accordance with the binary logic signal 1 of the data lines DLl and DL2.
As soon as the binary signal having the logic value O appearsalong the two data lines DLl and DL2 instead of the binary signal having the logic value 1, the two D-triggering elements K2 and K20 are reset with the aid of the associated D-triggering elements Kl and K10 respectivelyg and remain in this static switching position. The push-pull amplifier Vl~ V2 is then inac-tive~ so that the voltage along the lines L3 and L4 disappears. Owing to the static exclusive-OR signals which are still present at the exclusive-OR
~onitorIng element AD, the latter is still conductive for the test pulses TS~
30 ~hat the timing current gupply TG continues to output signals.
The doscribed embodi~ent of the invention may be varied in various ways.
Instead of the D triggering elements Kl, K2, K10 and K20~ other types of tri~ering element may be employed which perform the same function.
The norm~l setting signal GLl~ GL2 may be applied also to the resped-iiva sqkting input S of the triggering elements Kl, K10 in the form of a binary al~n~l having ~he logic v~luc 1. In this case, the connections to the ra~t tnpllt~ R nf ~he triggering elements Kl and K10 are omitted~ and the ou~pll~ Q is l~sad in~-~ead of -the respective output Q.
`'~ Al~o~ th~ embodtment m.~y ~e advan-tageously operated wLth only one ~pli~ r Vl or V2. In -thLs oaso, the primary ~inding U~ U2 of thc ou-tput tran~f~rmer U l~ ~mi~t~d.
In ~n~h~r ~orm oE construotion~ the ampliEiers Vl and V2 are not ~`
~a~h ~lactrically connected to a triggering element K2, K20, but are connected only to one triggering element K2 or K20 through a transformer.
: ~;
If s~itching becomes impossible owing to a defect in one of the triggering elements, this results in a dist~rbance in the exclusive-OR condition~ where-by a safety tripping is automatically brought about.
For a better understanding of the inven-tion and to show how it may be put into effect reference will now be made, by way of example, to the single fi~re of the accompanying drawing, which shows a data processing installation includ-ing a safety output Imit according to the invention.
The installation, which is illus~rated substantially as a block circuit diagrc~m, comprises two micro-computers MRl and MR2 which process tuo ~;
1~ it~ems of information synchronously for reasons of sc~fety. ~espective input linoa have becn omitted from the drawing for the sake of clarity. In the il-' hlstratad emboclimont, Lt i~ immaterial what devices are~ ultimately controlled ~y tha output signals of the two micro-computers, it merely being essential thAt fail-safe ~ignals are ultinately available from the micro-computers, .ilthough they are not constructed on a Eail-safe basis.
Synchronous control of the two micro-computers MRl and MR2 takes placa by means of a timing current suppl~ TG through lines Ll and L20 In ordar that the draw:ing may be made as clear as possible, there is associated wi~h a~Gh Or th~ two micro-comp~lters MRl and MR2 only a single data line DLl and nL2 respuatively~ -through which binary signals are output either with the la~c v~lua ~ or wi-th the logic value la The pair of data lines nLl and ~L2 th~ lways carry durlng normal operAtion binary signals having the samc :logic val~l~ nnd cQrres~ondln~ to one and the same item oE information.
Tha b-lnary sign~ls outpu~ by way of the data lines DLl and DL2 lndirackly control a push-pull amplifier consisting of two amplifiers Vl and V2 and an output transformer U, to which there i9 connected a rectifier arrang- ~`
~mant GLl,.sGL~ succeeded by a capacitor Cl. There may be connected to two OUtpllt lines L3 and L4~ for example~ a rela~ which is activated when there are identic~il binary signals having the logic value 1 along the data lines DLl and ' ~0~39~
. ~.. `
DL2.
There is provided as an output building block for the micro-computer MRl, in respect of the data line DLl~ a D~triggering element Kl (to be explain-ed l~ter). Similarly~ there is connected to the data line DL2 a D-trigger-ing element KlOo The data lines DLl and DL2 are connected to the respective D_inputs oE the D-triggering elements Kl and K10. The timing pulse inputs C
of the D_triggering elemenfs Kl c~nd K10 are connected by way of control signals SGl and SG2 to the micro-computers MRl and MR2 respectively. It is incidental-ly to be noted that the lines DLl and SGl, and DL2 and SG2 are connected to the respective bus lines of the associated micro-computer. The respective reset inputs R of the D~triggering element Kl and K10 are connected by way o~ lines L5 and L6 to the timing current supply TG, whereby normal setting signals GLl nnd GL2 having the logic value 0 can be applied at a given time for the reset-t-lng oE the respective D-triggering elements Kl and K10. Generally spealcing, a flip-flop is a bistable triggering stage with two stable state~, one state of which is designated by 1 and the other by 0~ The signal that is at an output Q shows respectively which of the two states the flip-Elop is in at a particular instant. The flip-Elop can therefore be caused to alter its state vln one or several inputs. With a D-Elip-Elop or D-triggering element, thcrc a i9 provided ~an input designated by D whose ~alue during a switching step is taken ovar into the fl~p-Elop and is stored there until the next switch;ng a-tap. With the las-t ~entioned swLtching step the Elip_Elop is adlusted again nGcordin~ to thc 9ignal 1 or 0 present at -the DLinput. The switching step oE
tha ~lip-~lop that is mentioned is carr:ied out by a pulse which is supplied to the pulse input C periodically independent of the signals at the D~input to be processed. The characteristiG equation of a D-triggering element reads:
Q = D 0 T.
The outputs Q of the D-triggering elements Kl and K10 are connected to the reset inputs R of respective second D-triggering elements K2 and K200 -6_ , In this way, it is ensured that when the D-triggering element Kl or K10 is reset the respective succeeding D-triggering element K2 or K20 also remains in the reset condition by way of the respective reset input R~ The negated out-puts Q of the two D-triggering elements 1~2 and K20 then carry a signal having the logic value 1. Of the two D-triggering elements K2 and K20 the negated output Q is connected to the D-input in each instance. For a signal edge con--~rol~ tho t.iming input C of the D~triggering element K2 is connected to the timing current supply T~ through a timing signal line TLGl, and that of the D_ triggering element K20 is connected to the same timing current supply through a timing signal line TLG2. In this way, the two DLtriggering elements K2 and ~20 are continuously activated in synchronism during normal operation.
Xn add:ition, the c~mplifier Vl is connected on its input side to the n~tad mltpu-t ~of the D-triggering element K20 On the other hand~ the amp-ll~ler V2 is connected to the output Q o:E the D triggering element K20. Con-sequently during normal operation, provided that a binary signal having the logic value O i9 output through the data lines DLl and DL2, static exclusive-OR signals are applied to the two inputs of the two amplifiers Vl and V2. At the output of each binary signal having the logic value 1 through the afore-~ld dA~a line9~ dyn~mic e~clu9ive-OR 9ignals are applied to the amplifier ~0 inyuts :ln the -~or~ of two square-wave voltages 180 apart in phase~ which can ~o procassed by -th~ push-pull ~nplifier to form an output signal along ~he lin~s 1~ and ~4~
An exGlu~:Lve-OR moni-toring element AD which is connected in the same w~y as ~ha nmpl:Lfiors Vl and V2 ~o the outputs of the two D-triggering elements K2 ~nd K~ so con9-trlcted that it can serve to indicate either stat:ic ~olusive-OR signals or dynamic exclusive-OR signals (unidirectional voltage square-wave voltage)O In principle, the exclusive-OR monitoring element AD
consists of a switching transistor TR whose switching path is connected in series with a working resistor R to the direct-current branch of a bridge . ., : . . : : . . : , ... . ~, . . ...
~Lt~ 9~
rectifier arrangement comprising rectifiers Dl, D2, D3, and D40 In the case~f this exclusive-OR monitoring member AD, the switching transistor TR only receives a supply voltage whenei~er the two D-triggering elements E2 and K20 are statically in the same condition without disturbance, or operate dynami-cally and exhibit like changes of condi~ion. Test pulses TS pass from the timing current supply TG through the line L7 connected to the base electrode of thc switching transistor TR for reading the exclusive-OR monitoring element QD~ Only when the exclusive-OR condition is present are the applied test pulses TS fed back through the line L8 to the timing current supply TG, which 1~ outputs control sigllals through the lines Ll, ~2, TLGl, TLG2~ L5 and L6 by r~ason nf this faot~ until the instànt of the next test pulse TS.
SinGe~ in genercil~ not only one data line extends from each of the ml~ro-eomputers ~IRl and MR2 as illustrated in the drawing, but a plurality of d~ta lin~s, it will be obvious that~ in practice, a corresponding number of ~xclusive-OR ~onitoring elements are present. In this case~ the line L8 is n~t connected to the timing current supp:ly TG~ but extends to a further ex-sive-QR monltoring element. Consequently, the exclusive-OR monitoring al~en~s for~ a ser:ies arrangement in wh~ich the exclusive-OR monitoring ele-~nt sitllAtad last :Ln thc series i9 finally connected to the timing current supply T~.
In the ca~e of the zero setting signals ~Ll and GL2 eaah having the lo~i~ valua ~ throunh the l:Lne L5 and L6 respectively, -the D-triggering eLements Kl ~nd ~10 ~re ~aturned into coincidcnt ini-tial switching pos:ition which is es~antial fnr ~he ~tArtin~ o~ the s~f~ty output unit. In the said initial swi~al~n~ p~sition, -the -two D-triggering elements Kl and K10 apply a signal haYing the logic value O through the respective ~output to the respective reset input R of the succeeding DLtriggering elements K2 and K20 resp~ively, so that the two D~triggering elements K2 and K20 are in the reset switching con~ition and remain therein. The output Q of the D~triggering element K2 _8-.~. ' `
9~
then has the logic value l and the output Q of the D-triggering element K20 has thr logic value o. The exclusive-OR monitoring element AD consequently receives exclusive-OR static signals and is therefore conductive for the applied test pulse TS through the line L7. Si~nce the two amplifiers Vl and V2 still recieve no dynamic control signals, the voltage at the output lines L3 and L~
remains at ~ero as before.
After the first test pulse TS applied to the exclusi~e-OR monitoring element AD has returned into the timing current supply TG, the "on" phase is terminated with the cessation of the normal setting signals GLl and GL20 When signals having the logic value O are output by the micro-computers MRl and ~2 through their data lines DLl and DL2~ no change occurs in the switching condition of tha ~triggering elements 1~l and K2, and KlO and K20 respectively.
On the other hand, when the data lines DLl and DL2 carry binary ~ign~ls having the logic value l~ this value is taken up by the associated D~triggering elements Kl and K2 respectively. The respective Q-output o~ the D-trig~ering elements Kl, KlO then output the logic vilue l, whereby the associated D~triggering element K2~ K20 is cleared. This has the result that the logic value l present at the respective output ~ of the triggering elements K~ and 1520 nt this instant is t~cen up with timing control by the D~input.
2n ~hcr~after~ the respective ~-output of the D-triggering elements K2 and 1S20 carrias the logic value 0. ~hen the next timing pulse is passed through ~he tim:ln~ line TLGl~ TLG2, the D-input o~ the D-triggering element IS2, K20 takes up the logic value 0 del:ivered by the associated ~-output. It will be seen ~ha~ lth normal timing current supply, the two D-triggering elements IS2 and Is~n always switoh to and fro with t~ming control between the two possible switching conditions. In this way, the amplifiers Vl and V2 receive dynamic e~Yclusive-OR signals, i.e. square-wave voltages, which are necessary for the operation of the push-pull amplifier. Consequently, the voltage necessary for activating a relay (not shown) is present at the output lines L3, L~ in _9_ , . - ..
-9~6 accordance with the binary logic signal 1 of the data lines DLl and DL2.
As soon as the binary signal having the logic value O appearsalong the two data lines DLl and DL2 instead of the binary signal having the logic value 1, the two D-triggering elements K2 and K20 are reset with the aid of the associated D-triggering elements Kl and K10 respectivelyg and remain in this static switching position. The push-pull amplifier Vl~ V2 is then inac-tive~ so that the voltage along the lines L3 and L4 disappears. Owing to the static exclusive-OR signals which are still present at the exclusive-OR
~onitorIng element AD, the latter is still conductive for the test pulses TS~
30 ~hat the timing current gupply TG continues to output signals.
The doscribed embodi~ent of the invention may be varied in various ways.
Instead of the D triggering elements Kl, K2, K10 and K20~ other types of tri~ering element may be employed which perform the same function.
The norm~l setting signal GLl~ GL2 may be applied also to the resped-iiva sqkting input S of the triggering elements Kl, K10 in the form of a binary al~n~l having ~he logic v~luc 1. In this case, the connections to the ra~t tnpllt~ R nf ~he triggering elements Kl and K10 are omitted~ and the ou~pll~ Q is l~sad in~-~ead of -the respective output Q.
`'~ Al~o~ th~ embodtment m.~y ~e advan-tageously operated wLth only one ~pli~ r Vl or V2. In -thLs oaso, the primary ~inding U~ U2 of thc ou-tput tran~f~rmer U l~ ~mi~t~d.
In ~n~h~r ~orm oE construotion~ the ampliEiers Vl and V2 are not ~`
~a~h ~lactrically connected to a triggering element K2, K20, but are connected only to one triggering element K2 or K20 through a transformer.
: ~;
Claims (4)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A safety output unit for a data processing installation which in use supplies binary signals, the safety output unit being for supplying an output amplifier comprising an output transformer having a secondary winding which in use supplies a load with fail-safe signals through a rectifier arran-gement, wherein the safety output unit comprises inputs for coupling to a pair of data lines which in use carry like binary signals from two micro-com-puters which are synchronously controlled by a common timing current supply, two first triggering elements coupled to receive data via respective ones of said inputs and having outputs connected to reset inputs of two respective second triggering elements of the safety output unit, the two second trigger-ing elements having timing inputs available to receive synchronous timing pulses from said timing current supply and the two first triggering elements comprising reset inputs available for connection to said timing current sup-ply to receive therefrom a normal setting signal, there being connected to a negated output of one second triggering element and to an output of the other second triggering element an exclusive-OR monitoring element which can be read in dependence upon test pulses from said timing current supply and which is arranged to output the test pulses both in the case of static exclusive-OR
signals and in the case of dynamic exclusive-OR signals for maintaining the timing current supply, at least one of the two second triggering elements being available for connection to an output amplifier which is to be supplied by the safety output unit.
signals and in the case of dynamic exclusive-OR signals for maintaining the timing current supply, at least one of the two second triggering elements being available for connection to an output amplifier which is to be supplied by the safety output unit.
2. A safety output unit according to claim 1, wherein the output amp-lifier is a push-pull amplifier and the output transformer has a primary winding connected to said negated output of the one second triggering element via a first amplifier and to said output of the other second triggering element via a second amplifier.
3. A safety output unit according to claim 2, wherein the first and second triggering elements are D-triggering elements and each second D-trig-gering element has a feedback path from its negated output to its D-input.
4. A safety output unit according to claim 1, 2 or 3, wherein the exclusive-OR monitoring element comprises an electronic switching amplifier and a rectifier arrangement via which the current supply for the electronic switching amplifier is to take place from the signals to be monitored for the exclusive-OR condition.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DEP2651314.4 | 1976-11-10 | ||
| DE2651314A DE2651314C2 (en) | 1976-11-10 | 1976-11-10 | Safety output circuit for a data processing system that emits binary signals |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1089996A true CA1089996A (en) | 1980-11-18 |
Family
ID=5992847
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA290,523A Expired CA1089996A (en) | 1976-11-10 | 1977-11-09 | Safety output control for a data processing system emitting binary signals |
Country Status (18)
| Country | Link |
|---|---|
| US (1) | US4149069A (en) |
| JP (1) | JPS5361244A (en) |
| AR (1) | AR213014A1 (en) |
| AT (1) | AT356708B (en) |
| BE (1) | BE860639A (en) |
| CA (1) | CA1089996A (en) |
| CH (1) | CH618029A5 (en) |
| DE (1) | DE2651314C2 (en) |
| DK (1) | DK142474C (en) |
| FI (1) | FI62602C (en) |
| FR (1) | FR2371016A1 (en) |
| GB (1) | GB1565307A (en) |
| IN (1) | IN148688B (en) |
| LU (1) | LU78470A1 (en) |
| NL (1) | NL7712402A (en) |
| SE (1) | SE423287B (en) |
| YU (1) | YU39156B (en) |
| ZA (1) | ZA776433B (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3003291C2 (en) * | 1980-01-30 | 1983-02-24 | Siemens AG, 1000 Berlin und 8000 München | Two-channel data processing arrangement for railway safety purposes |
| US4338650A (en) * | 1980-11-10 | 1982-07-06 | Otis Elevator Company | Fail-safe relay driving |
| DE3114230C2 (en) * | 1981-04-08 | 1983-02-03 | Siemens AG, 1000 Berlin und 8000 München | Circuit arrangement for the safe operation of a two-channel switchgear |
| DE3137450C2 (en) * | 1981-09-21 | 1984-03-22 | Siemens AG, 1000 Berlin und 8000 München | Safety output circuit for a data processing system |
| FR2513409A1 (en) * | 1981-09-22 | 1983-03-25 | Alsthom Cgee | METHOD FOR SYNCHRONIZING TWO MICROPROCESSORS |
| DE3209718A1 (en) * | 1982-03-17 | 1983-09-29 | M.A.N. Maschinenfabrik Augsburg-Nürnberg AG, 8000 München | Functionally reliable control device |
| FR2539887B1 (en) * | 1983-01-20 | 1985-07-26 | Tech Europ Commutation | PROCESS FOR ENSURING THE SECURITY OF THE OPERATION OF A PROGRAMMABLE AUTOMATON AND AUTOMATON FOR THE IMPLEMENTATION OF THE PROCESS |
| FR2540685A1 (en) * | 1983-02-03 | 1984-08-10 | Jeumont Schneider | INTERFACE FOR CONNECTING A COMPUTER SYSTEM TO AN ACTUATOR DEVICE |
| GB2228114B (en) * | 1989-02-13 | 1993-02-10 | Westinghouse Brake & Signal | A system comprising a processor |
| JP2674392B2 (en) * | 1991-11-01 | 1997-11-12 | 三菱電機株式会社 | Hydraulic elevator installation method |
| FR2773409A1 (en) * | 1998-01-07 | 1999-07-09 | Honeywell | POSITIVE SECURITY CONTROL DEVICE |
| AU2015296645A1 (en) | 2014-07-28 | 2017-02-16 | Econolite Group, Inc. | Self-configuring traffic signal controller |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3517174A (en) * | 1965-11-16 | 1970-06-23 | Ericsson Telefon Ab L M | Method of localizing a fault in a system including at least two parallelly working computers |
| US3452159A (en) * | 1965-12-29 | 1969-06-24 | Automatic Elect Lab | Call-for-service circuits of communication switching marker |
| DE1588431A1 (en) * | 1967-04-04 | 1970-05-21 | Waltungs Gmbh | Circuit arrangement for monitoring the switching state? Ens two switching paths |
| DE1537379C3 (en) * | 1967-09-22 | 1980-07-03 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Safety circuit for performing logical links for binary switching variables and their complementary switching variables |
| US3560942A (en) * | 1968-07-15 | 1971-02-02 | Ibm | Clock for overlapped memories with error correction |
| DE2034869A1 (en) * | 1970-07-09 | 1972-01-20 | Licentia Gmbh | Fail-safe control system for the transmission of digital information |
| US3810119A (en) * | 1971-05-04 | 1974-05-07 | Us Navy | Processor synchronization scheme |
| DE2133457C3 (en) * | 1971-07-06 | 1979-12-20 | Brown, Boveri & Cie Ag, 6800 Mannheim | Arrangement for monitoring two signal channels processing binary signals |
| US3978327A (en) * | 1972-03-13 | 1976-08-31 | Siemens Aktiengesellschaft | Program-controlled data processor having two simultaneously operating identical system units |
| DE2219546A1 (en) * | 1972-04-21 | 1973-10-31 | Heidelberger Druckmasch Ag | QUICK CLAMPING DEVICE ON ROTARY CYLINDERS OF PRINTING MACHINES |
| FR2182259A5 (en) * | 1972-04-24 | 1973-12-07 | Cii | |
| DE2247276C3 (en) * | 1972-09-27 | 1981-06-11 | Siemens AG, 1000 Berlin und 8000 München | Antivalence control device for a two-channel switchgear |
| IT1014277B (en) * | 1974-06-03 | 1977-04-20 | Cselt Centro Studi Lab Telecom | CONTROL SYSTEM OF PROCESS COMPUTERS OPERATING IN PARALLEL |
-
1976
- 1976-11-10 DE DE2651314A patent/DE2651314C2/en not_active Expired
-
1977
- 1977-06-23 AT AT444177A patent/AT356708B/en not_active IP Right Cessation
- 1977-06-29 CH CH796977A patent/CH618029A5/de not_active IP Right Cessation
- 1977-08-04 FR FR7724028A patent/FR2371016A1/en active Granted
- 1977-08-30 AR AR269004A patent/AR213014A1/en active
- 1977-09-19 US US05/834,155 patent/US4149069A/en not_active Expired - Lifetime
- 1977-09-28 GB GB40404/77A patent/GB1565307A/en not_active Expired
- 1977-10-04 DK DK439177A patent/DK142474C/en not_active IP Right Cessation
- 1977-10-28 ZA ZA00776433A patent/ZA776433B/en unknown
- 1977-10-28 IN IN1550/CAL/77A patent/IN148688B/en unknown
- 1977-10-31 SE SE7712267A patent/SE423287B/en not_active IP Right Cessation
- 1977-11-07 YU YU02661/77A patent/YU39156B/en unknown
- 1977-11-08 FI FI773343A patent/FI62602C/en not_active IP Right Cessation
- 1977-11-08 LU LU78470A patent/LU78470A1/xx unknown
- 1977-11-09 BE BE182474A patent/BE860639A/en not_active IP Right Cessation
- 1977-11-09 CA CA290,523A patent/CA1089996A/en not_active Expired
- 1977-11-10 NL NL7712402A patent/NL7712402A/en not_active Application Discontinuation
- 1977-11-10 JP JP13521877A patent/JPS5361244A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| SE7712267L (en) | 1978-05-11 |
| DK439177A (en) | 1978-05-11 |
| FI62602B (en) | 1982-09-30 |
| IN148688B (en) | 1981-05-09 |
| CH618029A5 (en) | 1980-06-30 |
| YU266177A (en) | 1982-02-28 |
| LU78470A1 (en) | 1978-07-14 |
| AT356708B (en) | 1980-05-27 |
| JPS5722494B2 (en) | 1982-05-13 |
| AR213014A1 (en) | 1978-11-30 |
| DE2651314B1 (en) | 1977-12-08 |
| FR2371016A1 (en) | 1978-06-09 |
| NL7712402A (en) | 1978-05-12 |
| FI773343A (en) | 1978-05-11 |
| SE423287B (en) | 1982-04-26 |
| ATA444177A (en) | 1979-10-15 |
| FI62602C (en) | 1983-01-10 |
| DE2651314C2 (en) | 1982-03-25 |
| BE860639A (en) | 1978-05-09 |
| DK142474C (en) | 1981-03-23 |
| GB1565307A (en) | 1980-04-16 |
| FR2371016B1 (en) | 1981-05-22 |
| DK142474B (en) | 1980-11-03 |
| JPS5361244A (en) | 1978-06-01 |
| ZA776433B (en) | 1978-08-30 |
| US4149069A (en) | 1979-04-10 |
| YU39156B (en) | 1984-06-30 |
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