CA1112356A - Multiple bit deskew buffer - Google Patents
Multiple bit deskew bufferInfo
- Publication number
- CA1112356A CA1112356A CA300,426A CA300426A CA1112356A CA 1112356 A CA1112356 A CA 1112356A CA 300426 A CA300426 A CA 300426A CA 1112356 A CA1112356 A CA 1112356A
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- Prior art keywords
- data
- error
- output
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- byte
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/20—Signal processing not specific to the method of recording or reproducing; Circuits therefor for correction of skew for multitrack recording
Abstract
MULTIPLE BIT DESKEW BUFFER
ABSTRACT
A multiple bit deskew buffer while providing skew correction for multi-track data read on mass storage devices is disclosed.
All data transfers are synchronized to one basic clock eliminating the multiple clocking systems utilized in the prior art. The invention is arranged such that it could be easily modified so as to vary the number of bytes of data held in the byte buffer by either hardware, firmware, or software means.
ABSTRACT
A multiple bit deskew buffer while providing skew correction for multi-track data read on mass storage devices is disclosed.
All data transfers are synchronized to one basic clock eliminating the multiple clocking systems utilized in the prior art. The invention is arranged such that it could be easily modified so as to vary the number of bytes of data held in the byte buffer by either hardware, firmware, or software means.
Description
CROSS P~FERENCRS TO REI,ATED APPLICATION.S
1. Apparatus Eor Digltal Data Recovery fronl Mass Storage Devices by Edward R. Besenfelder, Steve Cantrell, Charles Cobeen, bearing S.N. 807,711, Elled ~une 17, 1977, now issued as United States Patent No. 4,109,236 and assigned to the same 05 assignee as the instant invention.
1. Apparatus Eor Digltal Data Recovery fronl Mass Storage Devices by Edward R. Besenfelder, Steve Cantrell, Charles Cobeen, bearing S.N. 807,711, Elled ~une 17, 1977, now issued as United States Patent No. 4,109,236 and assigned to the same 05 assignee as the instant invention.
2. Deskewing Buffer Arrangement Which Includes Means For Detecting and Correcting Channel Errors invented by David D. Devoy, et al, bearing S.N. 321,094, filed January 4, 1973, now issued as U.S. Patent No. 3,792,436, and assigned to the same assignee 1~` as the instant invention.
3. Apparatus for Deskewin~ ~ata Signals in a MuIti-Track Recording System invented by Marion L. Town bearing S.N. 326,707, filed January 26, 1973, now issued as U.S. Patent No. 3,789,400 and assigned to the same assignee as the instant invention.
~5 4. Inter-Channel Time Displacement Corr~c~ion ~ethod and Apparatus in~ented by Jan S. Hed n bearing S~N. 15~,420, Elled June 18, 1971 and now issued~as U~.~S. Patent No. 3,708,783 The~apparatus described~in U.S. Patent No. i,789,400, while ~20 performlng a simila~ fullction to that described in the instant nvention, it is to be distlnqulshed in~ that the "Apparatus :~or Deskewing Data~Signals in a Multi-Traok Recordinq System" requires~
a~separate~control oscillator for each data track as~ well~as being oonslderably~more~complex and~requiring~more parts than the instant 25~ inventlon.~ Anothe~r ~advantage that the lnst;ant invention has over the~Town's lnventlon~is that~ln utiliziny the Town's system each bit~must~be~clocked throu~h dS ~many~separate bu~fe~ing stages as -2 5~0~7~7 :~ :
: ~ :
are includecl :in the system before that hit:.i.s avai.1.able to be ou-tputted in a deskewed byte. The i.nstarlt i.nve~nti.orl provic1es :Fo:r a first in/~l.rst out data positioninq arranyement, where:i.n t-.he first data bit i.5 not required to be shifted t.hrough each oF the 05 mult.iple bit stages prior to beincr ab~e to be ou-tputted to the byte process.ing device.
~ he "Deskewing Buffer Arrangement wh.ich Includes Means for Detecting and Correcting Channel Errors" of U~S. Patent ~o.
3,792,436 is also more complex and re~uires moxe parts than the instant invention. In addition, a separate pseudo clock is required .for each of the nine channels, whereas the instant invention runs all nine channels synchronously to one reference cIock. As with the Town's patent., this invention is a tr,ickle through device, wherein each bit must he clocked through all ~uffering sections befoxe .it is capable of heing outputted to -the data utilization deviceu The Interchannel Time Displacement Correction ~ethod and Apparatus described in U.S. Patent No. 3,708,783 is a complex, pa.rts-consuming device that requires ~he lnsertion of a sync word in each track or each bit read in order for the data to be synchronized and deskewed at the output.
The Apparatus for Di~i~al Data Recovery From Mass Stora~e Devices, U.S. Patent No. 4,lO9,23~ is cited as a reference to show how the lnput signa.ls transmitted to th~ multiple bit deskew buffer are generated.
r l~v~
Thls invention rela~es generally to electronlcs clrcuitry used to retrieve and process dlgital data ~rom mass s~o.ra~e devices.
More specificallyf the multiple bit deskew buffer pxovides a meclns for deskew.ing data from magnetic mass storaqe devices ~hat 3- 5~02707 ~ ~sr 2~' ~
~ 3~
substantially cuts clo~n on error rate caused by deskew oE the ~agnetic medium being read and also provides a versatile, programmable means oE
varying the size o the deskew buf~er itself. It is to be noted that the instant invention does not require the use of any analog circuitry.
B~CKGRW K O~ ~llE INVENTION
Prior art apparatus used to deskew digital data read from mass storage devices utilized hybrid analog~digital circuitry to implement the circuitry necessary to generate the proper timin~ and control signals for deskewing multi-track data. secause of this utilization o hybrid aevices, the prior art apparatus was not as adaptable to automatic test-ing procedures and, consequently, required greater amounts of labor with greater skills to test the equipment than that re~uired by an all digital approach. Prior art devices also required a separate clocking mechanism for each of the data tracks resulting in the need for more circuitry than that necessary for the instant invention as well as requiring that each bit be shifted through all stages of the deskew buffer.
SUMM~RY OF THE INVENTION
.
In accordance with the present invention, there is provided in a data processing system that reads data ~rom peripheral devices which utilizes a plurality of apparatus for reading digital data from mass storage deYices and a pluralit~ of data and error detectors, a multiple bit deskew buffer comprising: a plurality of bit tracking and storing sections, each of said sections comprising: a position counter responsive to a one of said plurality of data and error detectoxs for determining the number of bits stored in the section; a position decoder/overload detector responsive to the outputs of the position counter for providing individual error signals and a digital count of the number of bits stored in the secLion; a control shift xegister responsive to the position decoder~
overload detector and the data an error detector for providing a bit 3Q ready output signal indicating that a bit of data from that section is now ready to be read; a data shift ra~ister responsive to the position dècoder/overload detector and the data an error detector for providing a
~5 4. Inter-Channel Time Displacement Corr~c~ion ~ethod and Apparatus in~ented by Jan S. Hed n bearing S~N. 15~,420, Elled June 18, 1971 and now issued~as U~.~S. Patent No. 3,708,783 The~apparatus described~in U.S. Patent No. i,789,400, while ~20 performlng a simila~ fullction to that described in the instant nvention, it is to be distlnqulshed in~ that the "Apparatus :~or Deskewing Data~Signals in a Multi-Traok Recordinq System" requires~
a~separate~control oscillator for each data track as~ well~as being oonslderably~more~complex and~requiring~more parts than the instant 25~ inventlon.~ Anothe~r ~advantage that the lnst;ant invention has over the~Town's lnventlon~is that~ln utiliziny the Town's system each bit~must~be~clocked throu~h dS ~many~separate bu~fe~ing stages as -2 5~0~7~7 :~ :
: ~ :
are includecl :in the system before that hit:.i.s avai.1.able to be ou-tputted in a deskewed byte. The i.nstarlt i.nve~nti.orl provic1es :Fo:r a first in/~l.rst out data positioninq arranyement, where:i.n t-.he first data bit i.5 not required to be shifted t.hrough each oF the 05 mult.iple bit stages prior to beincr ab~e to be ou-tputted to the byte process.ing device.
~ he "Deskewing Buffer Arrangement wh.ich Includes Means for Detecting and Correcting Channel Errors" of U~S. Patent ~o.
3,792,436 is also more complex and re~uires moxe parts than the instant invention. In addition, a separate pseudo clock is required .for each of the nine channels, whereas the instant invention runs all nine channels synchronously to one reference cIock. As with the Town's patent., this invention is a tr,ickle through device, wherein each bit must he clocked through all ~uffering sections befoxe .it is capable of heing outputted to -the data utilization deviceu The Interchannel Time Displacement Correction ~ethod and Apparatus described in U.S. Patent No. 3,708,783 is a complex, pa.rts-consuming device that requires ~he lnsertion of a sync word in each track or each bit read in order for the data to be synchronized and deskewed at the output.
The Apparatus for Di~i~al Data Recovery From Mass Stora~e Devices, U.S. Patent No. 4,lO9,23~ is cited as a reference to show how the lnput signa.ls transmitted to th~ multiple bit deskew buffer are generated.
r l~v~
Thls invention rela~es generally to electronlcs clrcuitry used to retrieve and process dlgital data ~rom mass s~o.ra~e devices.
More specificallyf the multiple bit deskew buffer pxovides a meclns for deskew.ing data from magnetic mass storaqe devices ~hat 3- 5~02707 ~ ~sr 2~' ~
~ 3~
substantially cuts clo~n on error rate caused by deskew oE the ~agnetic medium being read and also provides a versatile, programmable means oE
varying the size o the deskew buf~er itself. It is to be noted that the instant invention does not require the use of any analog circuitry.
B~CKGRW K O~ ~llE INVENTION
Prior art apparatus used to deskew digital data read from mass storage devices utilized hybrid analog~digital circuitry to implement the circuitry necessary to generate the proper timin~ and control signals for deskewing multi-track data. secause of this utilization o hybrid aevices, the prior art apparatus was not as adaptable to automatic test-ing procedures and, consequently, required greater amounts of labor with greater skills to test the equipment than that re~uired by an all digital approach. Prior art devices also required a separate clocking mechanism for each of the data tracks resulting in the need for more circuitry than that necessary for the instant invention as well as requiring that each bit be shifted through all stages of the deskew buffer.
SUMM~RY OF THE INVENTION
.
In accordance with the present invention, there is provided in a data processing system that reads data ~rom peripheral devices which utilizes a plurality of apparatus for reading digital data from mass storage deYices and a pluralit~ of data and error detectors, a multiple bit deskew buffer comprising: a plurality of bit tracking and storing sections, each of said sections comprising: a position counter responsive to a one of said plurality of data and error detectoxs for determining the number of bits stored in the section; a position decoder/overload detector responsive to the outputs of the position counter for providing individual error signals and a digital count of the number of bits stored in the secLion; a control shift xegister responsive to the position decoder~
overload detector and the data an error detector for providing a bit 3Q ready output signal indicating that a bit of data from that section is now ready to be read; a data shift ra~ister responsive to the position dècoder/overload detector and the data an error detector for providing a
4 -data output corresponding to the bit ready ou-t.put signal o-f -the control shift register; the data shi~t register also providing means for storing a plurality of data bitsi an error register responsive -to -the clata an error detector and the posi-tion decoder./overload detector for providing a track erxor signal when an error is detected, said track error signal Eorcing the bit ready output signal to indicate that a bit is ready to be read and forcing the data shift register data output to indicate tha-t a lo~ic "0" data bit is ready to be read; a byte ready detector responsive to the bit ready output signal of each of said control shift registers and to the strobe output signal of each of the data and error detectors for . , . ~ . .
providing an output signal indicating that one byte of data is properly aligned and ready to be transmitted, and a byte buffer responsive to the output of the byte ready detector and the data output o~ each of said data shift registers for providing one byte of deskewea data as an output.
In accordance with the present invention, there is also provided a multiple bit deskew buffer for use in a device for reading multl-track ~ :
data from mass storage devices utilizing a data an error detector in each data track comprising: a plurality of data positioning means Eor providing a bit ready signal and a data signal, each of said plurality of posi-tioning 20 means co~prising; counter means responsive to a corresponaing one of the -data an error detectors for providing an output signal indicative of the num~er of bits of data that has been read but not yet transferred from the positioning means; decoding means connected to the counter means for providing a unique output for each state of said counter means and a .
plura].ity of error signals; data storage means responsive to the data an error detector and the counter means for storing bits of data that have been read but not yet -transferred from the position means; control means responsive to the decoder means for providing an output signal corresponding to a one of the bits of data stored ln the data storage means; error recognition means connected to the corresponding data an error detector and the decoder means for providing an error signal that will force the output of the data storage means and the control means to a predetermined ~ ~, - 4a -.:
state; byte detection means responsive to the outpu-t of each oE said control means for providing an output signal indicating that each bit of the data byte is now aeskewed and ready to be transferred; and byte buffer means connected to the output of each of said data s-torage means for pro-viding a multiple deskewed byte output.
The multiple bit deskew buffer of the inst:ant invention is designed to be utilized downstream from the digital data recovery apparatus with a data and error detector interface between the two. A position counter, position decoder/overload detector, control shift register, data shift register, error register, byte ready detector, and a byte bu*fer comprise the various components utilized to implement the deskewing oper-ation. E~cept for the byte buEfer detector and byte buffer, of which only one per system is requiredl the other portions of the multiple bit deskew buffer must - 4b -. . .
be reproduced for each track of data being read. In the case o~
a nine track data system, in which case one of the tracks of data represants a parity bit,.~ine sepaxate circuits would be required.
In operation the multiple bit deskew buffer keeps track of each 05 data bit read by the corresponding data recovery device by use of a bit position counter which is decoded by the position decoder/
overload detector and used by the control shift register and data shift register. The control shift regi~ter provides a bit ready signal when valid data is ready to be transferred to the byte bu~fer, while the data shift register maintains the relative positions of the bit ready signals and storage of the actual data bit itself. By selectivel~ incrementing and decrementing the position counter as well as appropriate shi~ting of the shift . .
registers, multiple data bits may be maintainea in a manner for later aligNment with the correspondlng data tracks at the byte buffer, At the same time the position count r and po~ition decoder/
: overload detector provides output ~ignals that indicate either that : an attempt is being made to stora more bits of data than what the shift registers are capable o~ stori~g and, thereby in roducing a track error into the computatlon, as well as a write mode overload signal that is used when writing into the mass storage device, which i~ also read at the same kime, in order to ensure that any deskew that later occurs on a subsequent read is not caused by ~ initial skewing in the write operation.
: ~ 25 By ~NDing all the bit read~ signals to provide a signal indicating that all data bits o~ the record are ready to be rea~
and also ~ ANDing the strobe signal for each of the data tracks : to provide an output signal ensuring that ~o data in any track i~
, ~ - in a transitionary mode~ output signals are provided to the byte ; 30 buffer for ~ubsequant transmission to the interface ~ha~ is to : 5.~02707 2~
read the now deskew~d byke of data. The output signals indicate to the inter~ace that the b~te buff~r may now be read~ Upon acceptance of the data by the lnterface an acknowledge si~nal is transmitted to the deskew buffer resettiAg the byte buffer and 05 preparing the circuitry for the next deskewed byte transfer.
It is therefore an object of this invention to provide an all digital multiple bit desk~3w buffer apparatus for deskewing multi-track data bit fro~ mass storage devices.
It is a further object of this invention to provide a deskew buffer apparatus utilizing a sin~le master clock with all data manipulations and transfers synchronized to that single master clock.
It is a still further obiect of this invention to provide apparatus easily adaptable to expansion as well as ~irmware or software control.
BRIEF DESC~IPTION OF THE DRAWINGS
_ ~ _ _ _ Figure 1 is a ~lock diagram of the instant invention.
~igure 2 is a sch~matic diagram of the position counter~
; position decvder/overload detector, data shift register, and ~ontrol shift register.
Figure 3 i~ a schematic diagram of the byte ready detector.
~iyure 4 is a schematic diagram of ~he byte buffer as ~associated control circuitry.
Figure 5 is a flow diagram of the instant invention.
~ Figure~6A, 6B, and 6C are timing diagrams illustrating timing signa1s generated by an utilized in the multiple bit deskew bufe~.
DET~ILE~ ~SCRIP~ION O~ T~E P~EFERRED EMBODI~ENT ~
The data and error detector depicted in Figure 1 is more fully explained in U.S. Patent No. 3,83X,584 entitled "Apparatus for Detecting Daka Bits and Error Bit~ in Phase~Coded Data"~ In addition, although not in the flow diagrarn, a master clock and data clock generated by the ~pparatus for Digital Data Recovery fr~m Mass St~rage Devices, S~No 807~711~ filed June. 17, 1977 05 is also utiliæed in the instant invention. As indicated in Figure 1, a data and error detector, control shit regi.ster, position counter, data shift register, position decoder~overload detector, and error register is required fox each track of data to ~e read from the stora~0 device. In contrast the byte ready detector and tha byte buffer are utilized only once in each system, their function being to operate on the signals provided from the control shift register and data shift register of each track of data. Although shown in Figure 1, the e.rror register is not described in the drawings insofar as it may be implemented in a straight forward manner with the use of a simple J-K flip-flop.
The purpo~e of the register i$ to latch any error that occurs either because an error has been detected upstre~m in the data an error detector or if the overload detector indicate~ that when the mass storage device is being writ~en into ~a~d read from at the same time) a deskew of more than ~ne bit~occurs.
For the general case, when nine track data is being read, one track being used as a parity track,~a single error in the data : byte will not cau~e an incorrectible o~dition, Thereore, whenever a track error i~ encountere~, the bit X ready and the bit X data ~5 lines are enahled ~or future correction by the error detecting and correcting circuitry downstream fro~ the deskew :buffer. In ~ the ~vent two or moxe tracks develop a track error, the entire : record is voided and must be rer~ad or passad over.
~ Figure 2 depicts the position counter 200 the position decoder/overload detector 210, ~he control shi.ft reg.ister 220, and the data shift register 250. Position co~mter 200 i.s a four load inputs represent the binary number 1].00. The load inputs are so fixed in order that when the counter load signal P.E.
Detect. (postamble end detect) is a logical "0" utiliæing the positive logic notation, the counter outputs will also be a 05 binary 1100, there~y ensuring that no data can be transmitted through the control or data shift regis~exs. When the P.E. Detect.
signal is a logic "0" level, it represent~ that the data record being read no longer contains useful data and ther~fore any ~ur~her data transmi sion would be erroneous. The initialize signal is connected to the clear inputs of the counter and registers to initialize these circuits prior to the ~eginning of `
the data block. It is active in the logic "1" stage. ~A strobe X signal generated b~ the data and error detector occurs simul~aneously with the data X pulse and represent~ that valid data 15~ is on the data X line. The strobe X signal is used to increment the poæition counter as well as load the outputs o~ the position decoder/overload datector into the con~rol shift register. It is important to note that both the control shift register and data shlft r gisters are loadable with an active high signal at the ;20 ~load input an~ also that only~logic "l's" can be loaded into the shift registers, i.e.~, if the~logic "1" has been pre~iously loadqd to a register stage, or has been shi~ted to that stage, a . :
lQad~signal with a ~l0~ level lnput will not change the register outputs~signa~;corresponding to the register input for that stage.
~The~byte~read aignal generated in Figure 3 is used t~ decrem2nt the~position ~ounter and cloc~ both the control shit register and data shift regi~ter. The clock input is overridde~ by an ; active hLgh signal at the load input. When either of the sh;if t registers i~ clo~ked, the data at output "a" is transferred ~o "b"/
:: :
~ ~ -8- 5202707 ;3~
from "b" to "c", etc., at the sæme time the serial input being kied to ground inputs a logical level "0" at the "a`' output. A high level signal at the track error input forces the bit X ready output to be a logic "1" and th~ bit X data to a logic "0" state.
os In this manner a track with a track errox will always be ready to be read with a logic "0" data bit always being an input into the byte buffer. As mentioned previously, so long as only one track is in error, the error correction and detection circuitxy down tream will adjust this particular tracks data to the correct logic level. The data X input is used to enable the load function of the data shift register, since th~ strobe X signal is coincident with the data X signal when both are logic "I's", and the position counter is not clocked until the falli~g edge of : the strobe X, pulse the data X pulse enab1es the aurrent count in the position decoder/overload detector to be loaded into the data shift register pxior to clocking of the positio~ counter. An example of how this would work would be as follows: after the initialization pulse has cleared the position counter and the shift registers, th~ "0" output of the position decoder is a ~; 20 logic "1" and is conne¢ted to the "e'! inputs of both -he contr~l ~hift register and the data shit register. If tha fir~t data ~ bit Ls a logic l'l", a logic "1" is loaded into the 'le" position of : both of the shift registers and on the falling edge of the strobe X pu1se the position counte~ is clocked to the binary 0001 state which in tuxn cause~ the "1ll output of the position/decoder into the logic "1" state. When a logic ":1" input having been loaded in the "e" position of both re~isters, the bit X ready output is a logical "1" as is the bit X da~a output. These æignalE, being ~: input~ to the byke ready detector and byte buffer respectively.
l~ second logic "~ 1l data input is received pri.or to traln~fer of _9_ 52~2707 the data from the byte buffer, a logic "1" is then loaded into po~ition "d" o both the registers. At this time there is therefore a logic "1'l output of both the "d" and "e" outputs of both of the ragisters and the position/decoder has a logic "1"
05 output "a" po~ition. If at thi~ time, the first byte o~ data is ready to be transferred and is, in fact, transferred, the byte read signal will clock the down clock input of the position counter and the positionJdecoder output will become a logic level "1" at the "1" output and a logic "0" at the "2" output, at the same time the two registers are shifted such that the logic level "1"
at the "d" output is transferred to the "e" output and the data that previously existed at the "e" output is lost, that data byte as~ocia*ed with~that bit havin~ already been read. If the next data bit is a "0", a logic "1" i~ loaded into the "d" input of the control shift register but not the data shift registert since a logic "0" data bit does not activate the load function of the register. In this instance th~ "d" and "e" outputs of:the control : shift regi~ter are both logic "l's" indicatiny that two data bits have been stored, while the "d" and "e" outputs of the data shift regi~ter are a "0" and "1" respectively, indicating the data ~ correspondi~g to the control shift r~gister ~tages.
:` ~ In this manner up to five bits of data can be tracked by the control shift register, while the corresponding data bits are ~tored i~ the data shift register.
.
2S Figure 3 of the schematic diagra~ vf the byte ready detector.
As ment1oned supra,~ only one byte ready detector per system is ~`~ required, th~ necessary signals from each of ~he mu:i~.iple tracks being used a5 inputs t~ the detector. Operation of the byte ready dete tor is as followsii The initia~ize pulse clears the Q output's of flip-flops 310 : `
and 3S0 to the logic "0" ~tate. Subsequ~ently, as the diferent bit X ready signals rom each of the dat~ tracks become a logic "1" signal, i.e., indicating that the bit in that track is ready to be read, the output of AND g,ate 300 will go to a 05 logic "1" state and, upon occurrence of the next reerence clock, the Q output of flip-flop 310 will go to the logic "1" statef thereby enabling the output of AND gate 360. The outpu~ o~ AND
gate 360 when the go to a logical l'l" state, since upon receipt of th~ initi~lize pulse the ~ output of flip-flop 350 became a logic "1". Until such time as the output of AND gate 340 goes to a logic "1" state, none of the flip-flop output~ or AND/NAND
output~ of the byte ready detector will change. However, with the byte ready bufer ready signal now being~a ~ . the interface will read the byte bu~fer and cau~e a reset ~ignal, more fully ~ described in the de~cript'on o~ Figuxe 4, to set flip-flop 350 and enable the output of ~ND gate ~40 when such ~ime as thexe is no a~tive level signal in any of the strobe X lines. When the output of ~ND gate 340 becomes a logic "1" level, the byte read signal, the output of N~ND gate 320 creates a negative : 20 golng pulse upon the next refere~ce clock. This byte read signal is~ used to cloak the contxol and data shift regi~ters as well as ~; decrement the position counter. At ~he ~ame time the byte xead :
signal is generated, the Q output of ~lip-flop 310 wilI togyle from a logio~"l" to a logic "0" level. Thls result is caused by ~he logical "1" output o~ AND gate 340 which i5 tied to the K input of flip-flop 310, with khe bit ready signal at the J
put a logic level "1" a reference cloc~ will:togg:le the flip-:
flop. ~aving toggled ~lip-flop 310 the Q output goes from a logic "1" to a logic "0", forcing the output of AND gate 34:0 to .
~ 520~707 3~
a logic "0", the next logic "1l' bit ready signal from AMD gate 305 will cause the byte ready signal to go to a logic "1" le~el when the ~lip-flop i~ strobed by the r~ference clock. This se~uence is repeated as n-cessary during the entire data record.
05 Figure 4 i~ a schematic diagram of the byte buffer itself, along with its associated ~ontrol circuitry. The byte buffer like the re t of the multiple bit deskew buffer circuitry is set to the proper initialize conditions by the initialize pulse which res.ts the multiple bit parallel in~parallel out register 400 as well as clears flip-~lops 420 and 440O Subse~u~nt to the initialize pulse byte buffer ready signal descri~ed in the detailed description oE Figure 3 will enable one~half of ga~e 410 when in the logic "1l' state indicating that the byte buffex has valid data at all data input~. At the same time the byte buffer full output of register 400 is a logic "0", having been reset ~by the initialize pulse. This ~"0" signal) in connection with a high level byte buf~er r-ady signal enables gate 410 and pre~ents a logic ~ level signal a~ the J input to flip-flop 420, which on the falling edge of ~he next mastex clock will toggle the Q output for the logic "0" to logic "1" stat~. The ma~ter clQck a9 described i~n the apparatus for digital data recovery from mass storage devices is a multiple of the - r~ference clock described 1~ Figure 3. With the Q output o~
flip-flop 420 a logic l'l" MAND gate 430 wiIl now pass the next . ~ 25 ma er clock pulse which in turn will trans~er the data and the byte buffer read~ inputs from the input side.of reg:ister 400 to the: output side, and at the same time disable the output of gate 410 which in turn causes the Q output of flip-flop 420 to the logic '~0" state on the next master clock pulse. rrhe acknowledge -12- 'i202707 signal i~ transmitted fr~m the receiving d~3vice , i . e O, th~
interf ace f to the byte buf er as soon as the byte presen ted has been read. A high leval acknowl~dge signal allows the next master clock pulse to clock the ~ c~utput o:E flip-flop 440 from 05 a logic "1" to a logic "O" ~tate and reset flip-flop 350 of Figure 3 as mentioned previously. At the same time the ~ output of flip-flop 440 goe to the logic "O" state the Q output goes to the logic 1'1" state enabling NAND g~te 450 to pass the next master clock pulse through gate 460 resetting the parallel in/
parallel out register 400 and enabling the apparatus to be ready to begin the next sequence.
Figure 5 is a flow diagram of t~e decision maki~g and actions ta~en by the multiple bit deskew buffer.
The timing diagrams of Figures 6A, 6B, and 6C are illu~trative o~ the signal utilized by and generated in multiple bit deskew bufferO For purpoa~s of illustration it should be noted that the abbreviation P.C. ~tands ~or a position counter output, C.5.R~
repre~en~ the control shift register, and D~S.R. is an abbreviation for data shift register.
While th~ principles of the instant invention have now been made clear in an illustrative embodiment, there will be many modifications as to the structl-re~ arrangement, proportion, elaments, materials and components that are obvious to those skilled in the art without departing from those principles.. The 25 appended c:Laims are therefore inte~ded to cover and embrace any such modification within ~he limits of the true scope and spir.it of the inverl~ion.
- -13- 52~2707
providing an output signal indicating that one byte of data is properly aligned and ready to be transmitted, and a byte buffer responsive to the output of the byte ready detector and the data output o~ each of said data shift registers for providing one byte of deskewea data as an output.
In accordance with the present invention, there is also provided a multiple bit deskew buffer for use in a device for reading multl-track ~ :
data from mass storage devices utilizing a data an error detector in each data track comprising: a plurality of data positioning means Eor providing a bit ready signal and a data signal, each of said plurality of posi-tioning 20 means co~prising; counter means responsive to a corresponaing one of the -data an error detectors for providing an output signal indicative of the num~er of bits of data that has been read but not yet transferred from the positioning means; decoding means connected to the counter means for providing a unique output for each state of said counter means and a .
plura].ity of error signals; data storage means responsive to the data an error detector and the counter means for storing bits of data that have been read but not yet -transferred from the position means; control means responsive to the decoder means for providing an output signal corresponding to a one of the bits of data stored ln the data storage means; error recognition means connected to the corresponding data an error detector and the decoder means for providing an error signal that will force the output of the data storage means and the control means to a predetermined ~ ~, - 4a -.:
state; byte detection means responsive to the outpu-t of each oE said control means for providing an output signal indicating that each bit of the data byte is now aeskewed and ready to be transferred; and byte buffer means connected to the output of each of said data s-torage means for pro-viding a multiple deskewed byte output.
The multiple bit deskew buffer of the inst:ant invention is designed to be utilized downstream from the digital data recovery apparatus with a data and error detector interface between the two. A position counter, position decoder/overload detector, control shift register, data shift register, error register, byte ready detector, and a byte bu*fer comprise the various components utilized to implement the deskewing oper-ation. E~cept for the byte buEfer detector and byte buffer, of which only one per system is requiredl the other portions of the multiple bit deskew buffer must - 4b -. . .
be reproduced for each track of data being read. In the case o~
a nine track data system, in which case one of the tracks of data represants a parity bit,.~ine sepaxate circuits would be required.
In operation the multiple bit deskew buffer keeps track of each 05 data bit read by the corresponding data recovery device by use of a bit position counter which is decoded by the position decoder/
overload detector and used by the control shift register and data shift register. The control shift regi~ter provides a bit ready signal when valid data is ready to be transferred to the byte bu~fer, while the data shift register maintains the relative positions of the bit ready signals and storage of the actual data bit itself. By selectivel~ incrementing and decrementing the position counter as well as appropriate shi~ting of the shift . .
registers, multiple data bits may be maintainea in a manner for later aligNment with the correspondlng data tracks at the byte buffer, At the same time the position count r and po~ition decoder/
: overload detector provides output ~ignals that indicate either that : an attempt is being made to stora more bits of data than what the shift registers are capable o~ stori~g and, thereby in roducing a track error into the computatlon, as well as a write mode overload signal that is used when writing into the mass storage device, which i~ also read at the same kime, in order to ensure that any deskew that later occurs on a subsequent read is not caused by ~ initial skewing in the write operation.
: ~ 25 By ~NDing all the bit read~ signals to provide a signal indicating that all data bits o~ the record are ready to be rea~
and also ~ ANDing the strobe signal for each of the data tracks : to provide an output signal ensuring that ~o data in any track i~
, ~ - in a transitionary mode~ output signals are provided to the byte ; 30 buffer for ~ubsequant transmission to the interface ~ha~ is to : 5.~02707 2~
read the now deskew~d byke of data. The output signals indicate to the inter~ace that the b~te buff~r may now be read~ Upon acceptance of the data by the lnterface an acknowledge si~nal is transmitted to the deskew buffer resettiAg the byte buffer and 05 preparing the circuitry for the next deskewed byte transfer.
It is therefore an object of this invention to provide an all digital multiple bit desk~3w buffer apparatus for deskewing multi-track data bit fro~ mass storage devices.
It is a further object of this invention to provide a deskew buffer apparatus utilizing a sin~le master clock with all data manipulations and transfers synchronized to that single master clock.
It is a still further obiect of this invention to provide apparatus easily adaptable to expansion as well as ~irmware or software control.
BRIEF DESC~IPTION OF THE DRAWINGS
_ ~ _ _ _ Figure 1 is a ~lock diagram of the instant invention.
~igure 2 is a sch~matic diagram of the position counter~
; position decvder/overload detector, data shift register, and ~ontrol shift register.
Figure 3 i~ a schematic diagram of the byte ready detector.
~iyure 4 is a schematic diagram of ~he byte buffer as ~associated control circuitry.
Figure 5 is a flow diagram of the instant invention.
~ Figure~6A, 6B, and 6C are timing diagrams illustrating timing signa1s generated by an utilized in the multiple bit deskew bufe~.
DET~ILE~ ~SCRIP~ION O~ T~E P~EFERRED EMBODI~ENT ~
The data and error detector depicted in Figure 1 is more fully explained in U.S. Patent No. 3,83X,584 entitled "Apparatus for Detecting Daka Bits and Error Bit~ in Phase~Coded Data"~ In addition, although not in the flow diagrarn, a master clock and data clock generated by the ~pparatus for Digital Data Recovery fr~m Mass St~rage Devices, S~No 807~711~ filed June. 17, 1977 05 is also utiliæed in the instant invention. As indicated in Figure 1, a data and error detector, control shit regi.ster, position counter, data shift register, position decoder~overload detector, and error register is required fox each track of data to ~e read from the stora~0 device. In contrast the byte ready detector and tha byte buffer are utilized only once in each system, their function being to operate on the signals provided from the control shift register and data shift register of each track of data. Although shown in Figure 1, the e.rror register is not described in the drawings insofar as it may be implemented in a straight forward manner with the use of a simple J-K flip-flop.
The purpo~e of the register i$ to latch any error that occurs either because an error has been detected upstre~m in the data an error detector or if the overload detector indicate~ that when the mass storage device is being writ~en into ~a~d read from at the same time) a deskew of more than ~ne bit~occurs.
For the general case, when nine track data is being read, one track being used as a parity track,~a single error in the data : byte will not cau~e an incorrectible o~dition, Thereore, whenever a track error i~ encountere~, the bit X ready and the bit X data ~5 lines are enahled ~or future correction by the error detecting and correcting circuitry downstream fro~ the deskew :buffer. In ~ the ~vent two or moxe tracks develop a track error, the entire : record is voided and must be rer~ad or passad over.
~ Figure 2 depicts the position counter 200 the position decoder/overload detector 210, ~he control shi.ft reg.ister 220, and the data shift register 250. Position co~mter 200 i.s a four load inputs represent the binary number 1].00. The load inputs are so fixed in order that when the counter load signal P.E.
Detect. (postamble end detect) is a logical "0" utiliæing the positive logic notation, the counter outputs will also be a 05 binary 1100, there~y ensuring that no data can be transmitted through the control or data shift regis~exs. When the P.E. Detect.
signal is a logic "0" level, it represent~ that the data record being read no longer contains useful data and ther~fore any ~ur~her data transmi sion would be erroneous. The initialize signal is connected to the clear inputs of the counter and registers to initialize these circuits prior to the ~eginning of `
the data block. It is active in the logic "1" stage. ~A strobe X signal generated b~ the data and error detector occurs simul~aneously with the data X pulse and represent~ that valid data 15~ is on the data X line. The strobe X signal is used to increment the poæition counter as well as load the outputs o~ the position decoder/overload datector into the con~rol shift register. It is important to note that both the control shift register and data shlft r gisters are loadable with an active high signal at the ;20 ~load input an~ also that only~logic "l's" can be loaded into the shift registers, i.e.~, if the~logic "1" has been pre~iously loadqd to a register stage, or has been shi~ted to that stage, a . :
lQad~signal with a ~l0~ level lnput will not change the register outputs~signa~;corresponding to the register input for that stage.
~The~byte~read aignal generated in Figure 3 is used t~ decrem2nt the~position ~ounter and cloc~ both the control shit register and data shift regi~ter. The clock input is overridde~ by an ; active hLgh signal at the load input. When either of the sh;if t registers i~ clo~ked, the data at output "a" is transferred ~o "b"/
:: :
~ ~ -8- 5202707 ;3~
from "b" to "c", etc., at the sæme time the serial input being kied to ground inputs a logical level "0" at the "a`' output. A high level signal at the track error input forces the bit X ready output to be a logic "1" and th~ bit X data to a logic "0" state.
os In this manner a track with a track errox will always be ready to be read with a logic "0" data bit always being an input into the byte buffer. As mentioned previously, so long as only one track is in error, the error correction and detection circuitxy down tream will adjust this particular tracks data to the correct logic level. The data X input is used to enable the load function of the data shift register, since th~ strobe X signal is coincident with the data X signal when both are logic "I's", and the position counter is not clocked until the falli~g edge of : the strobe X, pulse the data X pulse enab1es the aurrent count in the position decoder/overload detector to be loaded into the data shift register pxior to clocking of the positio~ counter. An example of how this would work would be as follows: after the initialization pulse has cleared the position counter and the shift registers, th~ "0" output of the position decoder is a ~; 20 logic "1" and is conne¢ted to the "e'! inputs of both -he contr~l ~hift register and the data shit register. If tha fir~t data ~ bit Ls a logic l'l", a logic "1" is loaded into the 'le" position of : both of the shift registers and on the falling edge of the strobe X pu1se the position counte~ is clocked to the binary 0001 state which in tuxn cause~ the "1ll output of the position/decoder into the logic "1" state. When a logic ":1" input having been loaded in the "e" position of both re~isters, the bit X ready output is a logical "1" as is the bit X da~a output. These æignalE, being ~: input~ to the byke ready detector and byte buffer respectively.
l~ second logic "~ 1l data input is received pri.or to traln~fer of _9_ 52~2707 the data from the byte buffer, a logic "1" is then loaded into po~ition "d" o both the registers. At this time there is therefore a logic "1'l output of both the "d" and "e" outputs of both of the ragisters and the position/decoder has a logic "1"
05 output "a" po~ition. If at thi~ time, the first byte o~ data is ready to be transferred and is, in fact, transferred, the byte read signal will clock the down clock input of the position counter and the positionJdecoder output will become a logic level "1" at the "1" output and a logic "0" at the "2" output, at the same time the two registers are shifted such that the logic level "1"
at the "d" output is transferred to the "e" output and the data that previously existed at the "e" output is lost, that data byte as~ocia*ed with~that bit havin~ already been read. If the next data bit is a "0", a logic "1" i~ loaded into the "d" input of the control shift register but not the data shift registert since a logic "0" data bit does not activate the load function of the register. In this instance th~ "d" and "e" outputs of:the control : shift regi~ter are both logic "l's" indicatiny that two data bits have been stored, while the "d" and "e" outputs of the data shift regi~ter are a "0" and "1" respectively, indicating the data ~ correspondi~g to the control shift r~gister ~tages.
:` ~ In this manner up to five bits of data can be tracked by the control shift register, while the corresponding data bits are ~tored i~ the data shift register.
.
2S Figure 3 of the schematic diagra~ vf the byte ready detector.
As ment1oned supra,~ only one byte ready detector per system is ~`~ required, th~ necessary signals from each of ~he mu:i~.iple tracks being used a5 inputs t~ the detector. Operation of the byte ready dete tor is as followsii The initia~ize pulse clears the Q output's of flip-flops 310 : `
and 3S0 to the logic "0" ~tate. Subsequ~ently, as the diferent bit X ready signals rom each of the dat~ tracks become a logic "1" signal, i.e., indicating that the bit in that track is ready to be read, the output of AND g,ate 300 will go to a 05 logic "1" state and, upon occurrence of the next reerence clock, the Q output of flip-flop 310 will go to the logic "1" statef thereby enabling the output of AND gate 360. The outpu~ o~ AND
gate 360 when the go to a logical l'l" state, since upon receipt of th~ initi~lize pulse the ~ output of flip-flop 350 became a logic "1". Until such time as the output of AND gate 340 goes to a logic "1" state, none of the flip-flop output~ or AND/NAND
output~ of the byte ready detector will change. However, with the byte ready bufer ready signal now being~a ~ . the interface will read the byte bu~fer and cau~e a reset ~ignal, more fully ~ described in the de~cript'on o~ Figuxe 4, to set flip-flop 350 and enable the output of ~ND gate ~40 when such ~ime as thexe is no a~tive level signal in any of the strobe X lines. When the output of ~ND gate 340 becomes a logic "1" level, the byte read signal, the output of N~ND gate 320 creates a negative : 20 golng pulse upon the next refere~ce clock. This byte read signal is~ used to cloak the contxol and data shift regi~ters as well as ~; decrement the position counter. At ~he ~ame time the byte xead :
signal is generated, the Q output of ~lip-flop 310 wilI togyle from a logio~"l" to a logic "0" level. Thls result is caused by ~he logical "1" output o~ AND gate 340 which i5 tied to the K input of flip-flop 310, with khe bit ready signal at the J
put a logic level "1" a reference cloc~ will:togg:le the flip-:
flop. ~aving toggled ~lip-flop 310 the Q output goes from a logic "1" to a logic "0", forcing the output of AND gate 34:0 to .
~ 520~707 3~
a logic "0", the next logic "1l' bit ready signal from AMD gate 305 will cause the byte ready signal to go to a logic "1" le~el when the ~lip-flop i~ strobed by the r~ference clock. This se~uence is repeated as n-cessary during the entire data record.
05 Figure 4 i~ a schematic diagram of the byte buffer itself, along with its associated ~ontrol circuitry. The byte buffer like the re t of the multiple bit deskew buffer circuitry is set to the proper initialize conditions by the initialize pulse which res.ts the multiple bit parallel in~parallel out register 400 as well as clears flip-~lops 420 and 440O Subse~u~nt to the initialize pulse byte buffer ready signal descri~ed in the detailed description oE Figure 3 will enable one~half of ga~e 410 when in the logic "1l' state indicating that the byte buffex has valid data at all data input~. At the same time the byte buffer full output of register 400 is a logic "0", having been reset ~by the initialize pulse. This ~"0" signal) in connection with a high level byte buf~er r-ady signal enables gate 410 and pre~ents a logic ~ level signal a~ the J input to flip-flop 420, which on the falling edge of ~he next mastex clock will toggle the Q output for the logic "0" to logic "1" stat~. The ma~ter clQck a9 described i~n the apparatus for digital data recovery from mass storage devices is a multiple of the - r~ference clock described 1~ Figure 3. With the Q output o~
flip-flop 420 a logic l'l" MAND gate 430 wiIl now pass the next . ~ 25 ma er clock pulse which in turn will trans~er the data and the byte buffer read~ inputs from the input side.of reg:ister 400 to the: output side, and at the same time disable the output of gate 410 which in turn causes the Q output of flip-flop 420 to the logic '~0" state on the next master clock pulse. rrhe acknowledge -12- 'i202707 signal i~ transmitted fr~m the receiving d~3vice , i . e O, th~
interf ace f to the byte buf er as soon as the byte presen ted has been read. A high leval acknowl~dge signal allows the next master clock pulse to clock the ~ c~utput o:E flip-flop 440 from 05 a logic "1" to a logic "O" ~tate and reset flip-flop 350 of Figure 3 as mentioned previously. At the same time the ~ output of flip-flop 440 goe to the logic "O" state the Q output goes to the logic 1'1" state enabling NAND g~te 450 to pass the next master clock pulse through gate 460 resetting the parallel in/
parallel out register 400 and enabling the apparatus to be ready to begin the next sequence.
Figure 5 is a flow diagram of t~e decision maki~g and actions ta~en by the multiple bit deskew buffer.
The timing diagrams of Figures 6A, 6B, and 6C are illu~trative o~ the signal utilized by and generated in multiple bit deskew bufferO For purpoa~s of illustration it should be noted that the abbreviation P.C. ~tands ~or a position counter output, C.5.R~
repre~en~ the control shift register, and D~S.R. is an abbreviation for data shift register.
While th~ principles of the instant invention have now been made clear in an illustrative embodiment, there will be many modifications as to the structl-re~ arrangement, proportion, elaments, materials and components that are obvious to those skilled in the art without departing from those principles.. The 25 appended c:Laims are therefore inte~ded to cover and embrace any such modification within ~he limits of the true scope and spir.it of the inverl~ion.
- -13- 52~2707
Claims (8)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. In a data processing system that reads data from peripheral devices which utilizes a plurality of apparatus for reading digital data from mass storage devices and a plurality of data and error detectors, a multiple bit deskew buffer comprising:
a plurality of bit tracking and storing sections, each of said sections comprising:
a position counter responsive to a one of said plurality of data and error detectors for determining the number of bits stored in the section;
a position decoder/overload detector responsive to the outputs of the position counter for providing individual error signals and a digital count of the number of bits stored in the section;
a control shift register responsive to the position decoder/
overload detector and the data an error detector for providing a bit ready output signal indicating that a bit of data from that section is now ready to be read;
a data shift register responsive to the position decoder/
overload detector and the data an error detector for providing a data output corresponding to the bit ready output signal of the control shift register; the data shift register also providing means for storing a plurality of data bits;
an error register responsive to the data an error detector and the position decoder/overload detector for providing a track error signal when an error is detected, said track error signal forcing the bit ready output signal to indicate that a bit is ready to be read and forcing the data shift register data output to indicate that a logic "O" data bit is ready to be read;
a byte ready detector responsive to the bit ready output signal of each of said control shift registers and to the strobe output signal of each of the data and error detectors for providing an output signal indicating that one byte of data is properly aligned and ready to be transmitted, and a byte buffer responsive to the output of the byte ready detector and the data output of each of said data shift registers for providing one byte of deskewed data as an output.
a plurality of bit tracking and storing sections, each of said sections comprising:
a position counter responsive to a one of said plurality of data and error detectors for determining the number of bits stored in the section;
a position decoder/overload detector responsive to the outputs of the position counter for providing individual error signals and a digital count of the number of bits stored in the section;
a control shift register responsive to the position decoder/
overload detector and the data an error detector for providing a bit ready output signal indicating that a bit of data from that section is now ready to be read;
a data shift register responsive to the position decoder/
overload detector and the data an error detector for providing a data output corresponding to the bit ready output signal of the control shift register; the data shift register also providing means for storing a plurality of data bits;
an error register responsive to the data an error detector and the position decoder/overload detector for providing a track error signal when an error is detected, said track error signal forcing the bit ready output signal to indicate that a bit is ready to be read and forcing the data shift register data output to indicate that a logic "O" data bit is ready to be read;
a byte ready detector responsive to the bit ready output signal of each of said control shift registers and to the strobe output signal of each of the data and error detectors for providing an output signal indicating that one byte of data is properly aligned and ready to be transmitted, and a byte buffer responsive to the output of the byte ready detector and the data output of each of said data shift registers for providing one byte of deskewed data as an output.
2. A multiple bit deskew buffer as recited in claim 1, wherein said position counter further comprise a multiple bit, up/down, binary counter with load and clear capabilities.
3. A multiple bit deskew buffer as recited in claim 1, wherein said position decoder/overload detector further comprises a binary to decimal decoder, the decimal 2 output being an error output when the system is operating in the write mode and the decimal 6 output being an error indicator when operating in the read mode.
4. A multiple bit deskew buffer as recited in claim 1, wherein said control shift register and said data shift register comprise a multiple bit, parallel in/parallel out, serial clocked shift register with load and clear capabilities;
the load function so configured as to allow the loading only of logical "1" inputs.
the load function so configured as to allow the loading only of logical "1" inputs.
5. The multiple deskew buffer as recited in claim 1, wherein said error register further comprises means for detecting an error signal from either the data an error detector or the control shift register and providing a track error signal output when an error input signal occurs.
6. A multiple deskew buffer as recited in claim 1, wherein the byte ready detector further comprises;
a first multiple bit AND gate each of whose input is connected to a one of said plurality of control shift register bit ready output signals for providing a signal indicating that all bit tracking and storage sections are ready to transfer one bit of data to the byte buffer;
a second multiple input AND gate each of said inputs connected to a one of said plurality of data and error detector strobe output signals for providing a signal indicating that none of the bit tracking and storage sections is in the process of accepting a bit of data from the data an error detector; and control means responsive to the outputs of the first and second AND gates for providing a byte read signal and a byte buffer ready signal.
a first multiple bit AND gate each of whose input is connected to a one of said plurality of control shift register bit ready output signals for providing a signal indicating that all bit tracking and storage sections are ready to transfer one bit of data to the byte buffer;
a second multiple input AND gate each of said inputs connected to a one of said plurality of data and error detector strobe output signals for providing a signal indicating that none of the bit tracking and storage sections is in the process of accepting a bit of data from the data an error detector; and control means responsive to the outputs of the first and second AND gates for providing a byte read signal and a byte buffer ready signal.
7. The multiple bit deskew buffer as recited in claim 1, wherein the byte buffer further comprises:
a multiple bit parallel in/parallel out resettable register, said register connected to the data shift register data output signal of each of said sections and the byte buffer ready output of the byte ready detector for latching a deskewed byte of data for transfer; and control means for providing a reset signal to the byte ready detector after the deskewed byte of data has been read from the register.
a multiple bit parallel in/parallel out resettable register, said register connected to the data shift register data output signal of each of said sections and the byte buffer ready output of the byte ready detector for latching a deskewed byte of data for transfer; and control means for providing a reset signal to the byte ready detector after the deskewed byte of data has been read from the register.
8. A multiple bit deskew buffer for use in a device for reading multi-track data from mass storage devices utilizing a data an error detector in each data track comprising:
a plurality of data positioning means for providing a bit ready signal and a data signal, each of said plurality of positioning means comprising;
counter means responsive to a corresponding one of the data an error detectors for providing an output signal indicative of the number of bits of data that has been read but not yet transferred from the positioning means;
decoding means connected to the counter means for providing a unique output for each state of said counter means and a plurality of error signals;
data storage means responsive to the data an error detector and the counter means for storing bits of data that have been read but not yet transferred from the position means;
control means responsive to the decoder means for providing an output signal corresponding to a one of the bits of data stored in the data storage means;
error recognition means connected to the corresponding data an error detector and the decoder means for providing an error signal that will force the output of the data storage means and the control means to a predetermined state;
byte detection means responsive to the output of each of said control means for providing an output signal indicating that each bit of the data byte is now deskewed and ready to be transferred; and byte buffer means connected to the output of each of said data storage means for providing a multiple deskewed byte output.
a plurality of data positioning means for providing a bit ready signal and a data signal, each of said plurality of positioning means comprising;
counter means responsive to a corresponding one of the data an error detectors for providing an output signal indicative of the number of bits of data that has been read but not yet transferred from the positioning means;
decoding means connected to the counter means for providing a unique output for each state of said counter means and a plurality of error signals;
data storage means responsive to the data an error detector and the counter means for storing bits of data that have been read but not yet transferred from the position means;
control means responsive to the decoder means for providing an output signal corresponding to a one of the bits of data stored in the data storage means;
error recognition means connected to the corresponding data an error detector and the decoder means for providing an error signal that will force the output of the data storage means and the control means to a predetermined state;
byte detection means responsive to the output of each of said control means for providing an output signal indicating that each bit of the data byte is now deskewed and ready to be transferred; and byte buffer means connected to the output of each of said data storage means for providing a multiple deskewed byte output.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/822,476 US4115759A (en) | 1977-08-08 | 1977-08-08 | Multiple bit deskew buffer |
| US822,476 | 1977-08-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1112356A true CA1112356A (en) | 1981-11-10 |
Family
ID=25236142
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA300,426A Expired CA1112356A (en) | 1977-08-08 | 1978-04-04 | Multiple bit deskew buffer |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4115759A (en) |
| JP (1) | JPS5428608A (en) |
| AU (1) | AU521906B2 (en) |
| CA (1) | CA1112356A (en) |
| DE (1) | DE2834094A1 (en) |
| FR (1) | FR2400242A1 (en) |
| GB (1) | GB2002555B (en) |
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| CN1172459C (en) * | 1998-09-30 | 2004-10-20 | 夸尔柯姆股份有限公司 | Apparatus and method for sending common information on common data channels |
| US7430171B2 (en) | 1998-11-19 | 2008-09-30 | Broadcom Corporation | Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost |
| US6775302B1 (en) | 1998-12-14 | 2004-08-10 | Agere Systems Inc. | Communications system with symmetrical interfaces and associated methods |
| US6675327B1 (en) | 1998-12-14 | 2004-01-06 | Agere Systems Inc. | Communications system including lower rate parallel electronics with skew compensation and associated methods |
| US6909727B1 (en) | 1998-12-14 | 2005-06-21 | Agere Systems Inc. | Communications system and associated methods with out-of-band control |
| US6678842B1 (en) | 1998-12-14 | 2004-01-13 | Agere Systems Inc. | Communications system and associated deskewing methods |
| US6536025B2 (en) | 2001-05-14 | 2003-03-18 | Intel Corporation | Receiver deskewing of multiple source synchronous bits from a parallel bus |
| TWI242205B (en) * | 2003-07-18 | 2005-10-21 | Via Tech Inc | Method and circuit for generating the tracking error signal using differential phase detection |
| US8365023B2 (en) | 2011-04-29 | 2013-01-29 | International Business Machines Corporation | Runtime dynamic performance skew elimination |
| CN114564441B (en) * | 2022-04-24 | 2022-07-05 | 飞腾信息技术有限公司 | System on chip, data processing method and computer equipment |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE25572E (en) * | 1958-06-30 | 1964-05-12 | Fired silica refractories | |
| US3708783A (en) * | 1971-06-18 | 1973-01-02 | Ampex | Interchannel time displacement correction method and apparatus |
| US3800280A (en) * | 1972-11-06 | 1974-03-26 | Gte Automatic Electric Lab Inc | Time skew measurement circuit for mag tape transports |
| US3790954A (en) * | 1972-12-26 | 1974-02-05 | Ibm | Skew controlled readback systems |
| US3792436A (en) * | 1973-01-04 | 1974-02-12 | Honeywell Inf Systems | Deskewing buffer arrangement which includes means for detecting and correcting channel errors |
| US3789400A (en) * | 1973-01-26 | 1974-01-29 | Honeywell Inf Systems | Apparatus for deskewing data signals in a multi-track recording system |
| US3832684A (en) * | 1973-10-31 | 1974-08-27 | Honeywell Inf Systems | Apparatus for detecting data bits and error bits in phase encoded data |
| US3863228A (en) * | 1973-12-13 | 1975-01-28 | Honeywell Inf Systems | Apparatus for detecting and elminating a transfer of noise records to a data processing apparatus |
| US3882459A (en) * | 1974-05-02 | 1975-05-06 | Honeywell Inf Systems | Deadtracking system |
| FR2313709A1 (en) * | 1974-12-31 | 1976-12-31 | Ibm | Misalignment correction systems for data processors - has intermediate circuits which are controlled by single counter unit |
| US4109236A (en) * | 1977-06-17 | 1978-08-22 | Honeywell Information Systems Inc. | Apparatus for digital data recovery from mass storage devices |
-
1977
- 1977-08-08 US US05/822,476 patent/US4115759A/en not_active Expired - Lifetime
-
1978
- 1978-04-04 CA CA300,426A patent/CA1112356A/en not_active Expired
- 1978-04-24 JP JP4862978A patent/JPS5428608A/en active Granted
- 1978-07-26 AU AU38372/78A patent/AU521906B2/en not_active Ceased
- 1978-08-03 DE DE19782834094 patent/DE2834094A1/en active Granted
- 1978-08-04 FR FR7823188A patent/FR2400242A1/en active Granted
- 1978-08-08 GB GB7832607A patent/GB2002555B/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6334548B2 (en) | 1988-07-11 |
| DE2834094A1 (en) | 1979-03-01 |
| US4115759A (en) | 1978-09-19 |
| FR2400242B1 (en) | 1983-06-03 |
| JPS5428608A (en) | 1979-03-03 |
| DE2834094C2 (en) | 1989-10-12 |
| FR2400242A1 (en) | 1979-03-09 |
| AU521906B2 (en) | 1982-05-06 |
| GB2002555B (en) | 1982-03-24 |
| AU3837278A (en) | 1980-01-31 |
| GB2002555A (en) | 1979-02-21 |
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Legal Events
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| MKEX | Expiry |