CA1132235A - Selectively controlled digital pad - Google Patents
Selectively controlled digital padInfo
- Publication number
- CA1132235A CA1132235A CA331,421A CA331421A CA1132235A CA 1132235 A CA1132235 A CA 1132235A CA 331421 A CA331421 A CA 331421A CA 1132235 A CA1132235 A CA 1132235A
- Authority
- CA
- Canada
- Prior art keywords
- memory
- data
- digital
- control means
- send
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000015654 memory Effects 0.000 claims abstract description 211
- 230000005540 biological transmission Effects 0.000 claims abstract description 27
- 238000003780 insertion Methods 0.000 claims abstract description 24
- 230000037431 insertion Effects 0.000 claims abstract description 24
- 238000012546 transfer Methods 0.000 claims description 22
- 230000006872 improvement Effects 0.000 claims description 3
- 230000003252 repetitive effect Effects 0.000 claims description 3
- 238000013500 data storage Methods 0.000 claims 6
- 239000011159 matrix material Substances 0.000 abstract description 37
- 238000010586 diagram Methods 0.000 description 13
- 101100521334 Mus musculus Prom1 gene Proteins 0.000 description 10
- 230000004044 response Effects 0.000 description 10
- 238000012545 processing Methods 0.000 description 8
- 230000007704 transition Effects 0.000 description 6
- 230000006870 function Effects 0.000 description 5
- 101100402629 Amanita bisporigera MSD7 gene Proteins 0.000 description 3
- 101150007063 MSD5 gene Proteins 0.000 description 2
- 230000008929 regeneration Effects 0.000 description 2
- 238000011069 regeneration method Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 101100402628 Amanita bisporigera MSD6 gene Proteins 0.000 description 1
- 101100223804 Arabidopsis thaliana At5g56368 gene Proteins 0.000 description 1
- 101100223805 Arabidopsis thaliana At5g56369 gene Proteins 0.000 description 1
- 101100115215 Caenorhabditis elegans cul-2 gene Proteins 0.000 description 1
- 101000857682 Homo sapiens Runt-related transcription factor 2 Proteins 0.000 description 1
- 102100025368 Runt-related transcription factor 2 Human genes 0.000 description 1
- 230000002301 combined effect Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000009432 framing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012552 review Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
Abstract
ABSTRACT OF THE DISCLOSURE
In a digital data transmission system including one or more matrix switches in which data in digital form is stored in a send memory during one selected time slot of a recurring time frame, transferred to a receive memory and sent out from the receive memory during another time slot of the recurring time frame to establish desired data paths through the switch between selected inputs and outputs, means is provided in the form of a programmable read only memory to control the insertion loss of each data path in a selective manner.
In a digital data transmission system including one or more matrix switches in which data in digital form is stored in a send memory during one selected time slot of a recurring time frame, transferred to a receive memory and sent out from the receive memory during another time slot of the recurring time frame to establish desired data paths through the switch between selected inputs and outputs, means is provided in the form of a programmable read only memory to control the insertion loss of each data path in a selective manner.
Description
~L~3Z~3S
In our prior Application No. 316,948 filed November 27, 1978, there is disclosed a digital private branch exchange, in which a pulse code modulation circuit connected to a sending telephone station samples each of a number of input analog ter-5 minations, which may be derived from line circuits, centraloffice trunk circuits, tie trunk circuits, etc. The samples are converted to eight bit pulse code modulation words and the words are multiplexed to provide a serial digital output in a modified D3 channel bank format. h'ach of the samples results 10 in a "frame" of data consisting of one eight bit PCM word for each of the input analog signals and an additional bit used for frame synchronization at the receiving end. The data is sup-plied to a data conditioner, which converts the eight bit seri-al data of D3 format to an eight bit parallel PCM word, and 15 supplies this data to a data switch arrangement.
A typical data switch arrangement as used in digital switching systems includes a plurality of matrix switches along with an expander-concentrator to interconnect the matrix swit-ches for time slot interchange. Data is transferred through 20 the matrix switches and the expander-concentrator by time slot interchange in time slots of a repetitive time frame assigned and controlled by a central processing unit. Each matrix swit-ch generally includes a send data memory and a receive data memory, and the system clock controls the operation of these 25 memories in such a way that data from the data conditioner is applied to and stored in the send memory at the same time that data stored previously in the receive memory is gated out to the data conditioner. During the second half of the clock cyc-le, the data which has been stored in the send memory undergoes 30 time slot interchange by transferring it from the send memory into the receive memory. Thus, data from a send telephone sta-tion will be shifted into the send memory of a first matrix switch during the first half of the clock cycle. During the second half of the clock cycle, the data which as been stored 35 in the send memory of the first matrix switch will be trans-ferred through the expander-concentrator to the receive memory of a second matrix switch, and during the first half of the following clock cycle this data stored in the receive memory ~ .
. . ~ ~
, ,. . , . . :
~32~3t-j of the second matrix switch will be shifted out. The eight bit parallel PCM word received from the second matrix switch will be converted to serial format and outputted to the pulse code modulation circuit which will convert the eight bit PCM
5 word to voice frequency and apply it to the receive telephone station.
Telephone commtmication systems, such as disclosed in the above-mentioned application No. 316,948, for example, are generally designed to provide a nominal insertion 106s for all 10 transmission paths through the system, which provides the pro-per level for most types of connections. However, certain types of calls require an additional insertion loss for proper attenuation, so that, for such calls the nominal insertion loss provided by the system is insufficient. For example, 15 line-to-line connections may require a greater insertion loss than line-to-tie trunk connections and an even greater inser-tion loss than line-to-central office trunk connections.
It is therefore an object of the pxesent invention to provide a selectively controlled digital pad for providing 20 variable insertion loss in a digital transmission system.
The present invention is therefore directed to the improvement in a digital transmission system including a send memory, a receive memory, transfer means connecting said 25 send memory to said receive memory and memory control means for selectively effecting transfer of digital data stored in addressable memory locations of said send memory into selected memory locations of said receive memory to establish selective data paths through said transfer means between inputs of said 30 send memory and outputs of said receive memory, said improve-ment comprising impedance control means connected in said data paths for controlling the insertion loss of said data paths by selectively adjusting the level of said digital data, said impedance control means including programmable memory means for 35 storing a range of adjusted digital values corresponding to a range of levels of digital data carried by said data paths, and means for applying the digital data to said programmable ~ .
:
~132~35 memory means as addresses for the stored adjusted digital values.
Features and advantages of the present invention will become more apparent from a detailed description of an exem-5 plary embodiment thereof, when taken in conjunction with theaccompanying dxawings, in which:
~3~35 Figure 1 is a schematic block diagram of a digital trans-mission network to which the present invention may be applied, Figure 2 is a schernatic block diagram of the matrix switch;
Figure 3 is a waveform diagram illustrating system clock signals;
Figures 4 and 5 are schematic circuit diagrams of the clock and memory control circuit;
Figure 6 is a wave timing diagram relating to the circuit of 10 Figures 4 and 5;
Figures 7 and 8 are schematic circuit diagrams of the store memory;
Figure 9 is a schematic circuit diagram of the pad store ~rming part of the present invention;
Figure 10 is a schematic circuit diagram of the store con-trol ~ogic circuit;
Figures 11 and 12 are schematic circuit diagrams of the control data output circuit;
Figure 13 is a schematic circwit diagrarn of the send data 20 memory;
Figure 14 is a schematic circuit diagram of the circuit pro-viding the digital pads in accordance with the present invention; and Figures 15 and 16 are schematic circuit diagrams of the - ~ receive data memory.
3.~.3~3~
Figure 1 illustrates a typical example of a digital trans~
mission network, of the type disclosed in the above-mentioned ~.-,q~
patent application Serial No. ~1, to which the present invention may be applied. Such a system provides 6iX matrix switches MS0 - MS5 in the common control 1, with each matrix switch being capable of handling data derived from four port groups or three port groups and a miscellaneous cell and another lead from a digital conference circuit. Two pulse code modulation circuits in each port-group provide a ]ine on the port group highway to the digital transmission network. Thus, each of the data condi-tioners D~0 - DC5 has eight incoming lines each carrying serial data associated with twenty-four ports, and converts the serial data to eight bit parallel words and transfers the eight bit parallel words to the asso-ciated matrix switch MS0 - MS5.
~ime slot interchange in the system is effected by the central processing unit 2 through the interrupt encoder 3 and the controller 4, the latter directly controlling the respective matrix switches MS0 - MSS
in accordance with instructions received from the central processing unit 2.
Each matrix switch operates on an essentially standard time-division mu~tiplex concept for time slot interchange. A set of eight memories are used on the send side to receive the eight bit words from the data condi-tioner and a set of eight memories are used on the receive side to store the data required for output to the data conditioner. The m emories are time shared with the first half of the clock cycle being used for input/
- output to the line side interface (data conditioner) and the second half of -- 25 the clock cycle for time slot interchange.
Since there are 192 unique inputs applied to the matrix, only 192 memory locations are utilized for input/output data. However, due to the frame data bit incorporated in the serial data stream, there are in reality 193 time slots available for time slot interchange. I:~uring 3Q the first half of the clock c;ycle, memory addressing is under control of a sequential counter which steps through the 192 memory addresses.
Data for the equivalent line address is clocked into the send memory and from the receive memory at this time. During the second half of the clock cycle, memory addressing is under control of the call store memories which transfer data from the send memory to the receive memory . , .
~3~35 in accordance with the preprogrammed data received from the central processing unit 2 via the controller 4 and stored in the store memories.
The expander-concentrator 20 enables time slot interchan~e between any of six matrix send memories to any one of the six matrix receive memories.
The call store memories in each matrix switch are pro-grammed by the controller 4 which in turn receives its direction from the central processing unit 2. The call store memory consists of twenty-three individual memories. Eight memories store the send port number with a ninth memory used to designate whether the time slot is active or 10 inactive, i. e., reserve. Eight memories store the receive port number with a ninth memory being used to designate the active-inactive status.
Five memories are then provided to store the cross-office highway number through the expander-concentrator 20.
The controller 4, under control of the central processing 15 unit 2, has the capability to write data into any given time slot in the call store memories, read data previously stored in any given time slot, or search the receive store memory to determine the time slot a given receive port number has been stored in. The send active-inactive and receive active-inactive memories provide the ability to ~tore call data in 20 the matrix and reserve time slots while data transfer is inhibited. The expander-concentrator 20 is a space-divided network which permits up to six matrices to ~e interconnected, and consists basically of combinational logic which steers the data by the cross office highway address informa-tion supplied from the matrix cross office memory stores.
:5?igure 2 is a general block diagram of the matrix switch, the principal components of which are the send data memor~ 10, the receive data memory 11, and the store memory 14. The matrix switch is a time division multiplex switch which interchanges eight bit parallel time slots from the input to the output, the matrix having a single eight-bit 30 wide cross office highway output and a dual eight bit wide cross office highway input. Interconnection of a plurality of matrices can be accom-plished by use of the space-divided expander/concentrator 20.
The operating speed of the matrix switch is 1~ 544 M~Iz, the combined effect of the 8, 000 sample per second rate and 193rd framing bit withthe D3 format resulting in 192 input-output time slots and 1~3 switching time slots, which are generated within the clock and memory 5 control 12 along with other control signals necessary to the functioning of the matrix switch. Functionally, the matrix switch performs continuous synchronous time slot interchange between the send data memory 10 and the receive data memory 11 through the expander/concentrator 20 under control of the address data contained in the store memory 14. The matrix is 10 transparent with respect to time slot data, the data out being equivalent to the data in with no restrictions on time slot contents or format.
The store control logic 13 is responsive to the clock and control signals from the clock and memory control 12 as well as control and address signals from the controller 4, whi~h is responsive to commands 15 from the central processing unit 2. The store control logic 13 is basically responsible ~or the comparison of address information received from the controller with stored information in the memory store 14 and serves to control the three basic functions of the matrix switch, i. e., read, write, and search, once a match has been detected between the received and 20 stored address information. The control data output circuit 15 is respon-siYe to the store control logic 13 for forwarding to the controller 4 information stored in the store memory 14 upon request from the controller 40 Thus, the matrix switch provides not only time slot inter-change of data under control of the controller 4, but also provides to the 25 controller 4 upon request data which is stored in the store mernory 14.
- In accordance with the present invention, there is also provided in the matrix switch a pad control circuit consisting of pad store 24 and the digital pads 25. The pad store 24 stores for each assigned cross ` office highway through the expander-concentrator 20 a pad identification 30 which is received from the central processing unit 2 via the controller 4.
This pad identification is then read out to the digital pads 25, which are disposed in the transmission path between the send memory 10 and the receive memory 11, in response to the clock and control signals from the clock and memory control 12.
~3~3~
The digital pads 25 are formed by a programmable read only memory ~PROM) divided into selectable memory areas, each of which represents a re-spective pad. The pads are selected during each time slot in accordance with the pad identification signals received from the pad store 24 and the data points within each particular pad are accessed using as an address the paral-lel DCM data received on the transmission path from the send memory lO. Each of the data points within a particular pad is responsive to a different dig-ital level of input signal and provides an output at an adjusted level in ac-cordance with the required insertion loss to be provided by that pad.
The pad control circuit is capable of providing any amount of pos-itive insertion loss for use in the transmission path. Negative insertion loss (positive insertion gain) can also be introduced via the pad control circuit, since the CPU can store any values in the data points of the respec-tive areas of the PROM forming the respective pads. However, there may be a tendency to clip for large voltage swings when using an eight bit code (the eighth bit usually being a sign bit), and therefore, to determine the pad value required to yield a particular insertion loss, the nominal insertion loss of the system is subtracted from the required loss and the remainder is the loss to be programmed into the PROM.
In order to provide a better understanding of the present invention, the manner in which the invention is specifically applied to the digital branch exchange disclosed in the above-referenced application no. 316,948 will be described as a preferred embodiment; however, it should be understood that the invention has general application to digital transmission systems employing matrix switches and is not restricted to use in the specific sys-tem described or in telephone systems in general.
The clock and memory control circuit 12 is illustrated in greater detail in Figures 4 and 5, and the operation of this circuit can be deter-mined from the timing diagram illustrated in Figure 6. The clock and memory control circuit accepts clock signals from the master clock (Figure 3) and regenerates the internal clock and memory control signals required for time slot interchange and store memory programming. All internal timing is syn-chronized to these input clock signals . ,~ . .
~3~35 The time slot and send data ~rlemory address counter 100 and the receive memory address counter 101 are each eight stage counters which provide up to 256 distinct addresses for memory control (256 time slots). The counter 100 is incremented by the positive going transition 5 of timing signal WCK4 from the master clock applied through Schmitt trigger circuit 102 and gate 103; while, the counter 101 is incremented in a similar manner from the output of Schmitt trigger circuit 102 via gate 104 on lead CCLK. Both of the counters 100 and 101 are synchro~
nized to the zero condition in coincidence with the external load signal 10 supplied by the master clock on lead DF12 supplied to counter 100 via Schmitt trigger circuit 105 and gate 106 on the one hand, and supplied - to counter 101 via Schmitt trigger circuit 107 and gate 108 on the other hand. The counter 100 supplies the address data for the send memory 10 during the input p~rtion of the send memory cycle and continuous address 15 data for the store memory 14. The receive data memory address counter 101 supplies the address for the receive data memory 11 during the output portion of the receive memory cycle.
The send and receive data memories 10 and 11 are time shared for the input-output function and real time data transfer (time slot 20 interchange). In this regard, the control signals RMC and SMC
generated by the receive data memory control 110 and send data memory control 112, respectively, in Figure 4 are the control signals which designate the operating mode for the memories 10 and 11, logic 1 indi-cating input and output, while logic 0 indicates data transfer. The 25 receive data memory control 110 consists of a crossed NOR latch 109 and a D flip-flop 111. A low-going pulse on lead WCK4 from the master clock via Schmitt trigger circuit 102 sets the flip-flop 111 via gate 117 to place a logic 1 on the lead RMC; while, a low-going pulse on lead WCK8 from the system clock resets the latch 109 and provides a logic 0 to the 30 D input of flip-flop 111. The positive-going edge of WCK8 resets the flip-flop and provides a logic ~ on lead F~MC.
The send data memory control 112 operates in a manner similar to the control 110 in that the flip-flop 114 is set on receipt of a low-going pulse on lead WC~4 produced at the output of Schmitt trigger ~3~2~35 circuit 102 via gate 121 and the output of latch 113 to produce a logic 1 on lead SMC. However, the transfer function for the send data memory control 112 is initiated earlier by the positive-going transition of lead WCK7 from the master clock, which resets the latch 113 and the flip-5 flop 114 to place a logic 0 on the lead SMC. The send transfer cycle isinitiated earlier to partially compensate for the memory access time and propagation delay through the cross office expander/concentrator circuit 20.
All other clock signals are directly regenerated from the clock 10 signals received from the master clock with the exception of the receive data memory clock RMWE, which is a double clock pulse produced at the output of gate 117 by both WCK4 and WCK8. The WC~8 component of signal of RMWE is used to erase the receive memory after data output and the WCK4 component of the signal RMWl~ is used to write in 15 the transferred data during the transfer portion of the receive memory cycle.
The pad latch clear pulse DWCK6 is generated at the output of gate 123 from the output of Schmitt trigger circuit 122 in response to the timing signal WCK6. The send memory write pulse DWCK7 i6 20 generated at the output of gate 119 frorn the output of Schmitt trigger circuit 116 in response to the timing signal ~2 from the master clock; while, the write generator strobe signal I:~WCK2 is generated at the output of gate 120 from the output of Schmitt trigger circuit 118.
The clock enable flip-flop signal DWCK4 is merely the regeneration of . 25 the clock signal WCK4 provided from the output of Schmitt trigger circuit 102. The latch receive data memory data-out signal D0 LATCH
is generated ~rom the output of Schrnitt trigger circuit 115 and is the regeneration of the timing signal WCK8.
As seen in Figure 5, the time slot signals T0 - T7 provided 30 from the counter 100 are supplied through buffer circuit 124 on leads A0 - A7 to the store memory 14, as well as to the pad store 24. The : store memory 14, which is illustrated in more detail in Figures 7 and 8contains the address data which controls the time slot interchange during the transfer portion of the send and receive data memory cycles. For this purpose, the store memory 14 comprises twenty-three registers 125 - 147 each of which pro~ides 256 memory loca-tions responsive to an eight bit address. Registers 125 - 133 5 comprise the send store memory and provide for the storage of eight address bits and an active/active bit provided on output leads * when the registers are addressed. The eight address bits permit anyone of the 256 memory locations in the send data memories to be addressed during the data transfer portion of the 10 send data memory cycle. The active/active bit ~ inhibits data transfer when set to the active condition (logic 1). ~he data level condition in the matrix is logic level 1, with data inhibit being indicated by logic 0 or idle condition.
The receive store memory comprises registers 134 -15 142 for storing eight address bits and an active/active bit provided on output leads R0 - R7 and RA when the registers are addressed, and its function is similar to that of the send store memory except that the active/active bit RA deselects the receive data memories when set to the active condition (logic 1) which prevents destruction ; 20 of the data stored in the receive data memories.
The cross offlce highway store memory comprises registers 143 - 1~7 and is capable of storing five address bits.
- Bit 4 selects one of the two eight bit cross office highways from the expander/concentrator 20, while bits 0 - 3 are connected on leads ~ ~ X ~ 3 25 X0 - X3 through drivers lg~ - 151 (Fig. 12) to leads ~-~
providing the st eering address data required by the expander/
concentrator 20.
Data in the store memory 14 is sequentially addressed under control of the time slot and send data memory address 30 counters in the clock and memory control 12. ~he data remains stable except during execution of the store memory write commands issued by the controller 4 and received on leads MSD0 - MSD7 in Figure 7. Time slot interchange is not affected during execution of h~3S
store memory commands except for the obvious case of the .specific time slots involved in a store memory write command.
The pad store 24~ although illustrated separately in Figure 2 for purposes of more clearly indicating those portions of the syætem which relate to the present invention, may be considered as part of the store memory 14 from a functional point of view. The pad store 24 is illuætrated in detail in Figure 9, and comprises three random access memories (RAM) 160, 161J and 162 for ~toring the three bits of a pad identification code which designateæ which pad is to be connected in the transmiæsion path in each cross office time slot. For this purpose the time slot signals A0 - A7 generated by the clock and memory control 12 (Figs. 8 and 9) are applied to each of the RAMs 160, 161, and 162 to address the memory locations thereof for reading the three pad designation bits out on leadæ P0, Pl, and P2, Similarly, data provided the CPU via the controller 4 on leadæ MSD5) MSD6, and MSD7 will be wri$ten into the memories 160, 161, and 162 when the write enable lead XWE is active.
; The address derived from the receive store memories 134 - 142 on leadæ R0 P~7 and R~ are applied to a pair of identical latcheæ 165 and 166 along with the pad deæignation bits P0 P2 from RAMæ 160 - 162 upon receipt of the timing æignal D~CK4 to hold theæe addreæseæ during the firæt portion of the time ælot. Upon receipt of the timing signal DWCK7 during the second half of the time slot, the receive memory address bits R0 - R7 and RA are clocked into a pair of latches 167 and 168 while the pad designation bitæ PS0, PS1, and PS2 are applied to the digital padæ 25.
The matrix æwitch executes eleven distinct commands which basically can be grouped into three fundamental type operations: read, write, and search. Control of the store memory 14 is provided by the control signals SWE, RWE, and XWE provided by the store control logic circuit 13 in response to commands from the controller 4. In the absence of any command from the controller 4, the store control logic 13 will be in the idle condition and time slot interchange in the matrix switch will proceed in accordance with ~3~35 the prior programmed data stored in the send, receive, and cross office store memories indefinitely in response to the successively received time slot signals on leads A0 - A7 from the clock and memory control circuit 12.
The store control logic circuit 13 is illustrated in greater detail in Figure 10. Command execution from the con-troller 4 is initiated when the M;~SEL lead goes low to set the enable flip-flop 169 via Schmitt trigger circuit 170 to provide an enable signal on the lead h'N to the control data output circuit 15, The data received from the controller 4 on the control bus CCD0 -CCD3 indicates the type of operations to be performed, such as search, write-send, read-send, write-receive, read-receive, write-XOH, and read-~H. The control signals on leads CCD0 -CCD2 are applied through gates 171 - 173 to the decoder 175 which decodes these signals and produces one of the outputs SWE, RWE, and XWE, representing the send write enable signal, and receive write enable signal, and the cross office write enable signal for controlling the writing of address data into the store memory 14 and the pad store 24.
At this point, it should be noted that upon generation of the cross office write enable signal XWE at the output of decoder 175 data will be read into ~oth the cross office store memories 143 - 147 (Fig. 8) and the pad store rams 160 - 162 (Fig. 9) from the CPU via the controller 4. In this regard data access to the pad store is gained through the last three bits of the cross office highway data byte appearing on leads MSD5 - MSD7. This elimi-nates the need to provide a separate pad store write command, but requires that the pad store be written at the same time as the cross office store memories 143 - 147. Neither the cross office store-nor the pad store memories can be written independently.
The bus comprising leads M~D0 - MCD7 from the con-troller 4 provides one of the data inputs to the comparator circuit 176 via Schmitt trigger circuits 177 - 184. A data selector 185 supplies to the comparator 176 either the address read from the store memory 14 on leads R0 - R7 or the time slot signals provided from the clock and memory control circuit 12 on leads ~0 - T7 in accordance with the output of gate 186 as determined by the infor-mation provided on leads CCD1 and CCD2 through the Schmitt trigger circuits 172 and 173.
The negative-going transition of DWCK4 applied to enable flip-flop 169 transfers the M~SEL status signal therethrough.
When the lead ~SEL goes low, the flip-flop 169 is set so as to enable the comparator 176. When the signal on DWCK4 is again inverted, the positive-going transition of the inverted clock pulse WCK4 increments the time slot and send data memory address counter 100, the outputs of which are distrib uted on the address bus to the store memory 14 via leads A0 - A7, as seen in Figure 7.
Thus, the store memory addresses are changed sequentially in synchronism with the signal on lead WCK4. As noted previously, there are three basic commands: read, write, and search.
Successful execution of each command requires that the MCD0 -MCD7 data applied through Schmitt trigger circuits 177 - 184 from the controller 4 to the comparator 176 in Figure 10 agrees with the internal data supplied by the matrix store rnemory 14.
When the data compares, a match signal is generated at the out-put of AND gate 187. Under normal conditions, assuming a comparison can be obtained, the maximum time required to find the match in the store is one complete counter and memory cycle.
On the average, it would be expected that the cycle time would be one-half a counter cycle.
For read and write commands, the data on leads MC'D0 -MCD7 from the controller is compared against the counter output on leads T0 - T7 (the store memory address). The match gate is enabled by the read + write + active compare logic signal pro-duced at the output of gate 188 to enable the gate 187. For search commands, the receive store active/active bit on lead RA from the store memory 14 (Fig. 8) is applied to gates 189 and 190 along with 3~
the active/active bit from the controller provided on lead CCD3 through Schmitt trigger 174. The bits must compare to enable the match gate 187.
The details of the control data output circuit 15 are illustrated in Figures 11 and 12. The basic function of this cix cuit is to store the data received from the store memory 14 in response to a request from the controller 4 for review of the stored data. For this purpose, the circuit 15 includes data selectors 191 - 195, as seen in Figure 11. The send data is received from the store memory 14 on leads SO - S7 and SA;
the receive data is provided on leads RO - R.7 and RA; the cross office highway data is applied on leads XO - ~4, and the time slot signals TO - T7 are received from the clock and memory control 12. The data selectors 191 - 195 each r eceive two bits from each - 15 field of data which is selected by the select gate inputs CB1 and CB2 derived from the outputs of gates 172 and 173 in Figure 10.
The data selected by the data selectors 191 - 195 is provided on leads DBO - DB7 and DBA to an output latch circuit 196 comprising ~ a plurality of D type flip-flops into which the data bits are inserted .; 20 for storage in response to the load output signal LDO. The data stored in the latch 196 then can be gated through the gate circuit 197 in response to the enable signal EN onto leads MDOO through MD07, MDOA and M~FIN to the CPU via the controller 4.
The load signal LDO is genreated in Figure 12 at the output of gate 198 in response to receipt of the MATCH signal from the store logic control 13 at the output of gate 187 in Figure 10 along with the timing signaI DWCK2 from the clock and . memory control circuit 12. A finish flip-flop 199 is responsive to - a clock signal DWCK4, the enable signal h~N from the store control loglc circuit 13 at the output of the enable flip-flop 169 in Figure 10 and the MATCH signal at the output of gate 187 in Figure 10 to produce an output on lead M~FIN from the gate circuit lg7 in Figure 11 to the controller 4 indicating that the operation has bee~
completed.
.
The send data memory 10 is illustrated in more detail in Figure 13, and includes a pair of data selector circuits 201 and 202 receiving a first address field comprising the time slot signals ~0 -T7 generated from the clock and memory control 12 and a second 5 address field comprising the send address information S0 - S7 received from the store memory 14. Depending upon the state of the control lead SMC to each of these selector circuits, either the first or the second addre,ss field will be applied by the selector cir-cuits to the output leads FM0 - FM7 to each of a plurality of send data registers 211 - 218, to each of which registers there is also provided one of the data bits received from the data conditioner on leads OB0 -OB7 through Schmitt trigger circuits 203 - 210. The outputs SB0 - SB7 from the send data registers 201 - 210 are pro-vided through gates 220 - 227 to the expander/concentrator 20 OTl 15 leads OM0 - OM7 provided the gates have not been disabled via the actiste/active lead SA from the store rnemory 14.
As indicated in the description of the clock and memory control circuit 12 in Figure 4, the positive-going transition o~
WCK4 initiates the input cycle for the send memory 10 and the 20 output cycle for the receive memory 11 by generating the control signals RMC and SMC at the output of the flip-flops 111 and 114, respectively. A logic 1 on the control lead SMC to the data selectors 201 and 202 in Figure 13 will gate the time slot signal represented by the condition on leads T0 - ~7 to each of the send ~ '~ ~0 - r ~\'1 A 25 data registers 211 - 218 on leads S~E~at the same time that a word is received from the data conditioner on leads OB0 ~ OB7 via Schmitt trigger circuits 203 - 210. The received word is therefore written into the send data registers 211 - 218 upon receipt of the timing signal DWCK7 at the address designated by the time slot 30 signals T0 - T7.
During the transfer cycle when the control lead SMC
goes to logic 0, the data selector circuits 201 and 202 will apply the send address information on leads S0 - S7 to the leads FM0 -FM7 which extend to each of the send data registers 211 - 218.
~1.32~235 Thus, the data stored in these registers at the particular address designated by the leads S0 - S7 will be gated out through gates 220 -227 to the expander/concentrator 20, provided these gates are not inhibited by the condition of lead SA.
The data word gated out of the send data registers 211 -218 in the send data memory 10 are applied through the expander/
concentrator 20 to the digital pads 25, which are illustrated in detail in Figure 14 The PCM data is provided on leads CRB0 -CRB7 to a pair of input latches 230 and 231 where the data word is stored with receiptof the clock signal CCLK.
The digital pads are formed by a pair of 512 by 8 bit bipolar programmable read only memories 232 and 233, each PROM providing four pads of 128 data points each. Each pad preferably provides a different value of insertion loss, although one of the pads may provide zero insertion loss to accommodate those cl~mmunication connections for which the nominal insertion loss of the system is suitable. Each data point within a given pad is responsive to a different level of the data Ln the transmission path to provide an output at a level adjusted by the designated inser-tion loss of the particular pad. Thus, the data word stored in the input latches 230 and 231 is applied on leads PBl - PB7 as an address to both of the PROMs 232 and 233. The least-significant bit PBO of the data word will not be altered, and therefore, it is not applied to the PROMs.
Pad selection is effected on the basis of the selection bits PS0 -PS2 received from the pad store 24. The bit PS2 is a chip select bit which enables either PROM 232 or PROM 233, while bits PS0 and PS1 select one of the four pads in each PROM.
The PROMs 232 and 233 are also enabled at a particular time ` 30 during each tinne slot by the output of cross coupled gates 236 and 237 at DWCK4j the output being disabled at DWCK7. The level adjusted data word is then applied to a pair of output latches 234 and 235 on leads PB0 and PD1 - PD7 at DWCK2, where the adjusted data is then available for transfer on leads CRD0 - C~D7 35 ` to the receive data memory 11.
~3~3S
The receive data memory 11 is similar to the send data memory 10, as indicated in Figure 15. The receive data memory 11 includes data selector circuits 238 and 239 which select.either the receive time slot address generated by the clock and memory control - 5 12 from the receive data memory address co~mter 101 in Figure 5appearing on leads RT0 - RT7 or the receive address data received from the store memory 14 on leads R0 - R7. The selector circuits 238 and 239 are controlled by the control signal l;~MC generated from the output of flip-flop 111 in Figure 4 upon receipt o:E the timing signal WCK4 at the Schmitt trigger circuit 102, as already described.
When the signal RMC is equal to logic 1, the time slot signals appearing on leads RT0 - RT7 are applied by the data selector circuits 238 and 239 to the leads RM0 - RM7 which extend to each of a plurality of receive data registers 240 - 247. Upon generation of the timing signal R.MWE ~rom the output of gate 117 in Figure 4 as a result of either the clock signal WCK4 or the clock signal WCK8, data received from the digital pads 25 on leads CRD0 - CRD7 will be ~tored in the registers 240 - 247 as storage -. locations designated by the receive time slot signals RT0 - RT7.
During the subsequent input cycle, when the control lead RMC is equal to logic 1, the selector cirCuits 238 and 239 will apply the ~` receive address signals ~0 - R7 from the store rnemory 14 to theleads RM0 - RM7 which extend to each of the receive data registers 240- 247.
At this time, on the negative-going transition of WCK8 from the clock and memory control 12, the data stored in the recei.ve data registers 240 - 247 at the address indicated by the receive address leads R0 - R.7 will be transferred out on leads RB0 - R.B7 to the data out latches in Figure 16, where the data is stored in response to receipt of the DO LATCH signal generated from the clock and memory control 12. This data stored in the data out latches 250 and 251 is provided on leads IB0 - IB7 to the data conditioner.
~3~3~
Thus, as seen from the foregoing description, since all PCM data must pass through the pad control circuit, any positive loss or gain which has been prograrnmed into the P~OM can be inserted into any transmission path. In this way, the proper 5 insertion loss for each type of port-to-port connection may be provided in a very simple and reliahle manner.
While I have shown and described an embodiment in accor-dance with the present invention, it is understood that the same is not limited thereto but is susceptible of numerous changes and modi-10 fications as known to those of ordinary skill in the art, and I,therefore, do not wish to be limited to the details shown and des-cribed herein but intend to cover all such changes and modifications as are obvious to those skilled in the art.
In our prior Application No. 316,948 filed November 27, 1978, there is disclosed a digital private branch exchange, in which a pulse code modulation circuit connected to a sending telephone station samples each of a number of input analog ter-5 minations, which may be derived from line circuits, centraloffice trunk circuits, tie trunk circuits, etc. The samples are converted to eight bit pulse code modulation words and the words are multiplexed to provide a serial digital output in a modified D3 channel bank format. h'ach of the samples results 10 in a "frame" of data consisting of one eight bit PCM word for each of the input analog signals and an additional bit used for frame synchronization at the receiving end. The data is sup-plied to a data conditioner, which converts the eight bit seri-al data of D3 format to an eight bit parallel PCM word, and 15 supplies this data to a data switch arrangement.
A typical data switch arrangement as used in digital switching systems includes a plurality of matrix switches along with an expander-concentrator to interconnect the matrix swit-ches for time slot interchange. Data is transferred through 20 the matrix switches and the expander-concentrator by time slot interchange in time slots of a repetitive time frame assigned and controlled by a central processing unit. Each matrix swit-ch generally includes a send data memory and a receive data memory, and the system clock controls the operation of these 25 memories in such a way that data from the data conditioner is applied to and stored in the send memory at the same time that data stored previously in the receive memory is gated out to the data conditioner. During the second half of the clock cyc-le, the data which has been stored in the send memory undergoes 30 time slot interchange by transferring it from the send memory into the receive memory. Thus, data from a send telephone sta-tion will be shifted into the send memory of a first matrix switch during the first half of the clock cycle. During the second half of the clock cycle, the data which as been stored 35 in the send memory of the first matrix switch will be trans-ferred through the expander-concentrator to the receive memory of a second matrix switch, and during the first half of the following clock cycle this data stored in the receive memory ~ .
. . ~ ~
, ,. . , . . :
~32~3t-j of the second matrix switch will be shifted out. The eight bit parallel PCM word received from the second matrix switch will be converted to serial format and outputted to the pulse code modulation circuit which will convert the eight bit PCM
5 word to voice frequency and apply it to the receive telephone station.
Telephone commtmication systems, such as disclosed in the above-mentioned application No. 316,948, for example, are generally designed to provide a nominal insertion 106s for all 10 transmission paths through the system, which provides the pro-per level for most types of connections. However, certain types of calls require an additional insertion loss for proper attenuation, so that, for such calls the nominal insertion loss provided by the system is insufficient. For example, 15 line-to-line connections may require a greater insertion loss than line-to-tie trunk connections and an even greater inser-tion loss than line-to-central office trunk connections.
It is therefore an object of the pxesent invention to provide a selectively controlled digital pad for providing 20 variable insertion loss in a digital transmission system.
The present invention is therefore directed to the improvement in a digital transmission system including a send memory, a receive memory, transfer means connecting said 25 send memory to said receive memory and memory control means for selectively effecting transfer of digital data stored in addressable memory locations of said send memory into selected memory locations of said receive memory to establish selective data paths through said transfer means between inputs of said 30 send memory and outputs of said receive memory, said improve-ment comprising impedance control means connected in said data paths for controlling the insertion loss of said data paths by selectively adjusting the level of said digital data, said impedance control means including programmable memory means for 35 storing a range of adjusted digital values corresponding to a range of levels of digital data carried by said data paths, and means for applying the digital data to said programmable ~ .
:
~132~35 memory means as addresses for the stored adjusted digital values.
Features and advantages of the present invention will become more apparent from a detailed description of an exem-5 plary embodiment thereof, when taken in conjunction with theaccompanying dxawings, in which:
~3~35 Figure 1 is a schematic block diagram of a digital trans-mission network to which the present invention may be applied, Figure 2 is a schernatic block diagram of the matrix switch;
Figure 3 is a waveform diagram illustrating system clock signals;
Figures 4 and 5 are schematic circuit diagrams of the clock and memory control circuit;
Figure 6 is a wave timing diagram relating to the circuit of 10 Figures 4 and 5;
Figures 7 and 8 are schematic circuit diagrams of the store memory;
Figure 9 is a schematic circuit diagram of the pad store ~rming part of the present invention;
Figure 10 is a schematic circuit diagram of the store con-trol ~ogic circuit;
Figures 11 and 12 are schematic circuit diagrams of the control data output circuit;
Figure 13 is a schematic circwit diagrarn of the send data 20 memory;
Figure 14 is a schematic circuit diagram of the circuit pro-viding the digital pads in accordance with the present invention; and Figures 15 and 16 are schematic circuit diagrams of the - ~ receive data memory.
3.~.3~3~
Figure 1 illustrates a typical example of a digital trans~
mission network, of the type disclosed in the above-mentioned ~.-,q~
patent application Serial No. ~1, to which the present invention may be applied. Such a system provides 6iX matrix switches MS0 - MS5 in the common control 1, with each matrix switch being capable of handling data derived from four port groups or three port groups and a miscellaneous cell and another lead from a digital conference circuit. Two pulse code modulation circuits in each port-group provide a ]ine on the port group highway to the digital transmission network. Thus, each of the data condi-tioners D~0 - DC5 has eight incoming lines each carrying serial data associated with twenty-four ports, and converts the serial data to eight bit parallel words and transfers the eight bit parallel words to the asso-ciated matrix switch MS0 - MS5.
~ime slot interchange in the system is effected by the central processing unit 2 through the interrupt encoder 3 and the controller 4, the latter directly controlling the respective matrix switches MS0 - MSS
in accordance with instructions received from the central processing unit 2.
Each matrix switch operates on an essentially standard time-division mu~tiplex concept for time slot interchange. A set of eight memories are used on the send side to receive the eight bit words from the data condi-tioner and a set of eight memories are used on the receive side to store the data required for output to the data conditioner. The m emories are time shared with the first half of the clock cycle being used for input/
- output to the line side interface (data conditioner) and the second half of -- 25 the clock cycle for time slot interchange.
Since there are 192 unique inputs applied to the matrix, only 192 memory locations are utilized for input/output data. However, due to the frame data bit incorporated in the serial data stream, there are in reality 193 time slots available for time slot interchange. I:~uring 3Q the first half of the clock c;ycle, memory addressing is under control of a sequential counter which steps through the 192 memory addresses.
Data for the equivalent line address is clocked into the send memory and from the receive memory at this time. During the second half of the clock cycle, memory addressing is under control of the call store memories which transfer data from the send memory to the receive memory . , .
~3~35 in accordance with the preprogrammed data received from the central processing unit 2 via the controller 4 and stored in the store memories.
The expander-concentrator 20 enables time slot interchan~e between any of six matrix send memories to any one of the six matrix receive memories.
The call store memories in each matrix switch are pro-grammed by the controller 4 which in turn receives its direction from the central processing unit 2. The call store memory consists of twenty-three individual memories. Eight memories store the send port number with a ninth memory used to designate whether the time slot is active or 10 inactive, i. e., reserve. Eight memories store the receive port number with a ninth memory being used to designate the active-inactive status.
Five memories are then provided to store the cross-office highway number through the expander-concentrator 20.
The controller 4, under control of the central processing 15 unit 2, has the capability to write data into any given time slot in the call store memories, read data previously stored in any given time slot, or search the receive store memory to determine the time slot a given receive port number has been stored in. The send active-inactive and receive active-inactive memories provide the ability to ~tore call data in 20 the matrix and reserve time slots while data transfer is inhibited. The expander-concentrator 20 is a space-divided network which permits up to six matrices to ~e interconnected, and consists basically of combinational logic which steers the data by the cross office highway address informa-tion supplied from the matrix cross office memory stores.
:5?igure 2 is a general block diagram of the matrix switch, the principal components of which are the send data memor~ 10, the receive data memory 11, and the store memory 14. The matrix switch is a time division multiplex switch which interchanges eight bit parallel time slots from the input to the output, the matrix having a single eight-bit 30 wide cross office highway output and a dual eight bit wide cross office highway input. Interconnection of a plurality of matrices can be accom-plished by use of the space-divided expander/concentrator 20.
The operating speed of the matrix switch is 1~ 544 M~Iz, the combined effect of the 8, 000 sample per second rate and 193rd framing bit withthe D3 format resulting in 192 input-output time slots and 1~3 switching time slots, which are generated within the clock and memory 5 control 12 along with other control signals necessary to the functioning of the matrix switch. Functionally, the matrix switch performs continuous synchronous time slot interchange between the send data memory 10 and the receive data memory 11 through the expander/concentrator 20 under control of the address data contained in the store memory 14. The matrix is 10 transparent with respect to time slot data, the data out being equivalent to the data in with no restrictions on time slot contents or format.
The store control logic 13 is responsive to the clock and control signals from the clock and memory control 12 as well as control and address signals from the controller 4, whi~h is responsive to commands 15 from the central processing unit 2. The store control logic 13 is basically responsible ~or the comparison of address information received from the controller with stored information in the memory store 14 and serves to control the three basic functions of the matrix switch, i. e., read, write, and search, once a match has been detected between the received and 20 stored address information. The control data output circuit 15 is respon-siYe to the store control logic 13 for forwarding to the controller 4 information stored in the store memory 14 upon request from the controller 40 Thus, the matrix switch provides not only time slot inter-change of data under control of the controller 4, but also provides to the 25 controller 4 upon request data which is stored in the store mernory 14.
- In accordance with the present invention, there is also provided in the matrix switch a pad control circuit consisting of pad store 24 and the digital pads 25. The pad store 24 stores for each assigned cross ` office highway through the expander-concentrator 20 a pad identification 30 which is received from the central processing unit 2 via the controller 4.
This pad identification is then read out to the digital pads 25, which are disposed in the transmission path between the send memory 10 and the receive memory 11, in response to the clock and control signals from the clock and memory control 12.
~3~3~
The digital pads 25 are formed by a programmable read only memory ~PROM) divided into selectable memory areas, each of which represents a re-spective pad. The pads are selected during each time slot in accordance with the pad identification signals received from the pad store 24 and the data points within each particular pad are accessed using as an address the paral-lel DCM data received on the transmission path from the send memory lO. Each of the data points within a particular pad is responsive to a different dig-ital level of input signal and provides an output at an adjusted level in ac-cordance with the required insertion loss to be provided by that pad.
The pad control circuit is capable of providing any amount of pos-itive insertion loss for use in the transmission path. Negative insertion loss (positive insertion gain) can also be introduced via the pad control circuit, since the CPU can store any values in the data points of the respec-tive areas of the PROM forming the respective pads. However, there may be a tendency to clip for large voltage swings when using an eight bit code (the eighth bit usually being a sign bit), and therefore, to determine the pad value required to yield a particular insertion loss, the nominal insertion loss of the system is subtracted from the required loss and the remainder is the loss to be programmed into the PROM.
In order to provide a better understanding of the present invention, the manner in which the invention is specifically applied to the digital branch exchange disclosed in the above-referenced application no. 316,948 will be described as a preferred embodiment; however, it should be understood that the invention has general application to digital transmission systems employing matrix switches and is not restricted to use in the specific sys-tem described or in telephone systems in general.
The clock and memory control circuit 12 is illustrated in greater detail in Figures 4 and 5, and the operation of this circuit can be deter-mined from the timing diagram illustrated in Figure 6. The clock and memory control circuit accepts clock signals from the master clock (Figure 3) and regenerates the internal clock and memory control signals required for time slot interchange and store memory programming. All internal timing is syn-chronized to these input clock signals . ,~ . .
~3~35 The time slot and send data ~rlemory address counter 100 and the receive memory address counter 101 are each eight stage counters which provide up to 256 distinct addresses for memory control (256 time slots). The counter 100 is incremented by the positive going transition 5 of timing signal WCK4 from the master clock applied through Schmitt trigger circuit 102 and gate 103; while, the counter 101 is incremented in a similar manner from the output of Schmitt trigger circuit 102 via gate 104 on lead CCLK. Both of the counters 100 and 101 are synchro~
nized to the zero condition in coincidence with the external load signal 10 supplied by the master clock on lead DF12 supplied to counter 100 via Schmitt trigger circuit 105 and gate 106 on the one hand, and supplied - to counter 101 via Schmitt trigger circuit 107 and gate 108 on the other hand. The counter 100 supplies the address data for the send memory 10 during the input p~rtion of the send memory cycle and continuous address 15 data for the store memory 14. The receive data memory address counter 101 supplies the address for the receive data memory 11 during the output portion of the receive memory cycle.
The send and receive data memories 10 and 11 are time shared for the input-output function and real time data transfer (time slot 20 interchange). In this regard, the control signals RMC and SMC
generated by the receive data memory control 110 and send data memory control 112, respectively, in Figure 4 are the control signals which designate the operating mode for the memories 10 and 11, logic 1 indi-cating input and output, while logic 0 indicates data transfer. The 25 receive data memory control 110 consists of a crossed NOR latch 109 and a D flip-flop 111. A low-going pulse on lead WCK4 from the master clock via Schmitt trigger circuit 102 sets the flip-flop 111 via gate 117 to place a logic 1 on the lead RMC; while, a low-going pulse on lead WCK8 from the system clock resets the latch 109 and provides a logic 0 to the 30 D input of flip-flop 111. The positive-going edge of WCK8 resets the flip-flop and provides a logic ~ on lead F~MC.
The send data memory control 112 operates in a manner similar to the control 110 in that the flip-flop 114 is set on receipt of a low-going pulse on lead WC~4 produced at the output of Schmitt trigger ~3~2~35 circuit 102 via gate 121 and the output of latch 113 to produce a logic 1 on lead SMC. However, the transfer function for the send data memory control 112 is initiated earlier by the positive-going transition of lead WCK7 from the master clock, which resets the latch 113 and the flip-5 flop 114 to place a logic 0 on the lead SMC. The send transfer cycle isinitiated earlier to partially compensate for the memory access time and propagation delay through the cross office expander/concentrator circuit 20.
All other clock signals are directly regenerated from the clock 10 signals received from the master clock with the exception of the receive data memory clock RMWE, which is a double clock pulse produced at the output of gate 117 by both WCK4 and WCK8. The WC~8 component of signal of RMWE is used to erase the receive memory after data output and the WCK4 component of the signal RMWl~ is used to write in 15 the transferred data during the transfer portion of the receive memory cycle.
The pad latch clear pulse DWCK6 is generated at the output of gate 123 from the output of Schmitt trigger circuit 122 in response to the timing signal WCK6. The send memory write pulse DWCK7 i6 20 generated at the output of gate 119 frorn the output of Schmitt trigger circuit 116 in response to the timing signal ~2 from the master clock; while, the write generator strobe signal I:~WCK2 is generated at the output of gate 120 from the output of Schmitt trigger circuit 118.
The clock enable flip-flop signal DWCK4 is merely the regeneration of . 25 the clock signal WCK4 provided from the output of Schmitt trigger circuit 102. The latch receive data memory data-out signal D0 LATCH
is generated ~rom the output of Schrnitt trigger circuit 115 and is the regeneration of the timing signal WCK8.
As seen in Figure 5, the time slot signals T0 - T7 provided 30 from the counter 100 are supplied through buffer circuit 124 on leads A0 - A7 to the store memory 14, as well as to the pad store 24. The : store memory 14, which is illustrated in more detail in Figures 7 and 8contains the address data which controls the time slot interchange during the transfer portion of the send and receive data memory cycles. For this purpose, the store memory 14 comprises twenty-three registers 125 - 147 each of which pro~ides 256 memory loca-tions responsive to an eight bit address. Registers 125 - 133 5 comprise the send store memory and provide for the storage of eight address bits and an active/active bit provided on output leads * when the registers are addressed. The eight address bits permit anyone of the 256 memory locations in the send data memories to be addressed during the data transfer portion of the 10 send data memory cycle. The active/active bit ~ inhibits data transfer when set to the active condition (logic 1). ~he data level condition in the matrix is logic level 1, with data inhibit being indicated by logic 0 or idle condition.
The receive store memory comprises registers 134 -15 142 for storing eight address bits and an active/active bit provided on output leads R0 - R7 and RA when the registers are addressed, and its function is similar to that of the send store memory except that the active/active bit RA deselects the receive data memories when set to the active condition (logic 1) which prevents destruction ; 20 of the data stored in the receive data memories.
The cross offlce highway store memory comprises registers 143 - 1~7 and is capable of storing five address bits.
- Bit 4 selects one of the two eight bit cross office highways from the expander/concentrator 20, while bits 0 - 3 are connected on leads ~ ~ X ~ 3 25 X0 - X3 through drivers lg~ - 151 (Fig. 12) to leads ~-~
providing the st eering address data required by the expander/
concentrator 20.
Data in the store memory 14 is sequentially addressed under control of the time slot and send data memory address 30 counters in the clock and memory control 12. ~he data remains stable except during execution of the store memory write commands issued by the controller 4 and received on leads MSD0 - MSD7 in Figure 7. Time slot interchange is not affected during execution of h~3S
store memory commands except for the obvious case of the .specific time slots involved in a store memory write command.
The pad store 24~ although illustrated separately in Figure 2 for purposes of more clearly indicating those portions of the syætem which relate to the present invention, may be considered as part of the store memory 14 from a functional point of view. The pad store 24 is illuætrated in detail in Figure 9, and comprises three random access memories (RAM) 160, 161J and 162 for ~toring the three bits of a pad identification code which designateæ which pad is to be connected in the transmiæsion path in each cross office time slot. For this purpose the time slot signals A0 - A7 generated by the clock and memory control 12 (Figs. 8 and 9) are applied to each of the RAMs 160, 161, and 162 to address the memory locations thereof for reading the three pad designation bits out on leadæ P0, Pl, and P2, Similarly, data provided the CPU via the controller 4 on leadæ MSD5) MSD6, and MSD7 will be wri$ten into the memories 160, 161, and 162 when the write enable lead XWE is active.
; The address derived from the receive store memories 134 - 142 on leadæ R0 P~7 and R~ are applied to a pair of identical latcheæ 165 and 166 along with the pad deæignation bits P0 P2 from RAMæ 160 - 162 upon receipt of the timing æignal D~CK4 to hold theæe addreæseæ during the firæt portion of the time ælot. Upon receipt of the timing signal DWCK7 during the second half of the time slot, the receive memory address bits R0 - R7 and RA are clocked into a pair of latches 167 and 168 while the pad designation bitæ PS0, PS1, and PS2 are applied to the digital padæ 25.
The matrix æwitch executes eleven distinct commands which basically can be grouped into three fundamental type operations: read, write, and search. Control of the store memory 14 is provided by the control signals SWE, RWE, and XWE provided by the store control logic circuit 13 in response to commands from the controller 4. In the absence of any command from the controller 4, the store control logic 13 will be in the idle condition and time slot interchange in the matrix switch will proceed in accordance with ~3~35 the prior programmed data stored in the send, receive, and cross office store memories indefinitely in response to the successively received time slot signals on leads A0 - A7 from the clock and memory control circuit 12.
The store control logic circuit 13 is illustrated in greater detail in Figure 10. Command execution from the con-troller 4 is initiated when the M;~SEL lead goes low to set the enable flip-flop 169 via Schmitt trigger circuit 170 to provide an enable signal on the lead h'N to the control data output circuit 15, The data received from the controller 4 on the control bus CCD0 -CCD3 indicates the type of operations to be performed, such as search, write-send, read-send, write-receive, read-receive, write-XOH, and read-~H. The control signals on leads CCD0 -CCD2 are applied through gates 171 - 173 to the decoder 175 which decodes these signals and produces one of the outputs SWE, RWE, and XWE, representing the send write enable signal, and receive write enable signal, and the cross office write enable signal for controlling the writing of address data into the store memory 14 and the pad store 24.
At this point, it should be noted that upon generation of the cross office write enable signal XWE at the output of decoder 175 data will be read into ~oth the cross office store memories 143 - 147 (Fig. 8) and the pad store rams 160 - 162 (Fig. 9) from the CPU via the controller 4. In this regard data access to the pad store is gained through the last three bits of the cross office highway data byte appearing on leads MSD5 - MSD7. This elimi-nates the need to provide a separate pad store write command, but requires that the pad store be written at the same time as the cross office store memories 143 - 147. Neither the cross office store-nor the pad store memories can be written independently.
The bus comprising leads M~D0 - MCD7 from the con-troller 4 provides one of the data inputs to the comparator circuit 176 via Schmitt trigger circuits 177 - 184. A data selector 185 supplies to the comparator 176 either the address read from the store memory 14 on leads R0 - R7 or the time slot signals provided from the clock and memory control circuit 12 on leads ~0 - T7 in accordance with the output of gate 186 as determined by the infor-mation provided on leads CCD1 and CCD2 through the Schmitt trigger circuits 172 and 173.
The negative-going transition of DWCK4 applied to enable flip-flop 169 transfers the M~SEL status signal therethrough.
When the lead ~SEL goes low, the flip-flop 169 is set so as to enable the comparator 176. When the signal on DWCK4 is again inverted, the positive-going transition of the inverted clock pulse WCK4 increments the time slot and send data memory address counter 100, the outputs of which are distrib uted on the address bus to the store memory 14 via leads A0 - A7, as seen in Figure 7.
Thus, the store memory addresses are changed sequentially in synchronism with the signal on lead WCK4. As noted previously, there are three basic commands: read, write, and search.
Successful execution of each command requires that the MCD0 -MCD7 data applied through Schmitt trigger circuits 177 - 184 from the controller 4 to the comparator 176 in Figure 10 agrees with the internal data supplied by the matrix store rnemory 14.
When the data compares, a match signal is generated at the out-put of AND gate 187. Under normal conditions, assuming a comparison can be obtained, the maximum time required to find the match in the store is one complete counter and memory cycle.
On the average, it would be expected that the cycle time would be one-half a counter cycle.
For read and write commands, the data on leads MC'D0 -MCD7 from the controller is compared against the counter output on leads T0 - T7 (the store memory address). The match gate is enabled by the read + write + active compare logic signal pro-duced at the output of gate 188 to enable the gate 187. For search commands, the receive store active/active bit on lead RA from the store memory 14 (Fig. 8) is applied to gates 189 and 190 along with 3~
the active/active bit from the controller provided on lead CCD3 through Schmitt trigger 174. The bits must compare to enable the match gate 187.
The details of the control data output circuit 15 are illustrated in Figures 11 and 12. The basic function of this cix cuit is to store the data received from the store memory 14 in response to a request from the controller 4 for review of the stored data. For this purpose, the circuit 15 includes data selectors 191 - 195, as seen in Figure 11. The send data is received from the store memory 14 on leads SO - S7 and SA;
the receive data is provided on leads RO - R.7 and RA; the cross office highway data is applied on leads XO - ~4, and the time slot signals TO - T7 are received from the clock and memory control 12. The data selectors 191 - 195 each r eceive two bits from each - 15 field of data which is selected by the select gate inputs CB1 and CB2 derived from the outputs of gates 172 and 173 in Figure 10.
The data selected by the data selectors 191 - 195 is provided on leads DBO - DB7 and DBA to an output latch circuit 196 comprising ~ a plurality of D type flip-flops into which the data bits are inserted .; 20 for storage in response to the load output signal LDO. The data stored in the latch 196 then can be gated through the gate circuit 197 in response to the enable signal EN onto leads MDOO through MD07, MDOA and M~FIN to the CPU via the controller 4.
The load signal LDO is genreated in Figure 12 at the output of gate 198 in response to receipt of the MATCH signal from the store logic control 13 at the output of gate 187 in Figure 10 along with the timing signaI DWCK2 from the clock and . memory control circuit 12. A finish flip-flop 199 is responsive to - a clock signal DWCK4, the enable signal h~N from the store control loglc circuit 13 at the output of the enable flip-flop 169 in Figure 10 and the MATCH signal at the output of gate 187 in Figure 10 to produce an output on lead M~FIN from the gate circuit lg7 in Figure 11 to the controller 4 indicating that the operation has bee~
completed.
.
The send data memory 10 is illustrated in more detail in Figure 13, and includes a pair of data selector circuits 201 and 202 receiving a first address field comprising the time slot signals ~0 -T7 generated from the clock and memory control 12 and a second 5 address field comprising the send address information S0 - S7 received from the store memory 14. Depending upon the state of the control lead SMC to each of these selector circuits, either the first or the second addre,ss field will be applied by the selector cir-cuits to the output leads FM0 - FM7 to each of a plurality of send data registers 211 - 218, to each of which registers there is also provided one of the data bits received from the data conditioner on leads OB0 -OB7 through Schmitt trigger circuits 203 - 210. The outputs SB0 - SB7 from the send data registers 201 - 210 are pro-vided through gates 220 - 227 to the expander/concentrator 20 OTl 15 leads OM0 - OM7 provided the gates have not been disabled via the actiste/active lead SA from the store rnemory 14.
As indicated in the description of the clock and memory control circuit 12 in Figure 4, the positive-going transition o~
WCK4 initiates the input cycle for the send memory 10 and the 20 output cycle for the receive memory 11 by generating the control signals RMC and SMC at the output of the flip-flops 111 and 114, respectively. A logic 1 on the control lead SMC to the data selectors 201 and 202 in Figure 13 will gate the time slot signal represented by the condition on leads T0 - ~7 to each of the send ~ '~ ~0 - r ~\'1 A 25 data registers 211 - 218 on leads S~E~at the same time that a word is received from the data conditioner on leads OB0 ~ OB7 via Schmitt trigger circuits 203 - 210. The received word is therefore written into the send data registers 211 - 218 upon receipt of the timing signal DWCK7 at the address designated by the time slot 30 signals T0 - T7.
During the transfer cycle when the control lead SMC
goes to logic 0, the data selector circuits 201 and 202 will apply the send address information on leads S0 - S7 to the leads FM0 -FM7 which extend to each of the send data registers 211 - 218.
~1.32~235 Thus, the data stored in these registers at the particular address designated by the leads S0 - S7 will be gated out through gates 220 -227 to the expander/concentrator 20, provided these gates are not inhibited by the condition of lead SA.
The data word gated out of the send data registers 211 -218 in the send data memory 10 are applied through the expander/
concentrator 20 to the digital pads 25, which are illustrated in detail in Figure 14 The PCM data is provided on leads CRB0 -CRB7 to a pair of input latches 230 and 231 where the data word is stored with receiptof the clock signal CCLK.
The digital pads are formed by a pair of 512 by 8 bit bipolar programmable read only memories 232 and 233, each PROM providing four pads of 128 data points each. Each pad preferably provides a different value of insertion loss, although one of the pads may provide zero insertion loss to accommodate those cl~mmunication connections for which the nominal insertion loss of the system is suitable. Each data point within a given pad is responsive to a different level of the data Ln the transmission path to provide an output at a level adjusted by the designated inser-tion loss of the particular pad. Thus, the data word stored in the input latches 230 and 231 is applied on leads PBl - PB7 as an address to both of the PROMs 232 and 233. The least-significant bit PBO of the data word will not be altered, and therefore, it is not applied to the PROMs.
Pad selection is effected on the basis of the selection bits PS0 -PS2 received from the pad store 24. The bit PS2 is a chip select bit which enables either PROM 232 or PROM 233, while bits PS0 and PS1 select one of the four pads in each PROM.
The PROMs 232 and 233 are also enabled at a particular time ` 30 during each tinne slot by the output of cross coupled gates 236 and 237 at DWCK4j the output being disabled at DWCK7. The level adjusted data word is then applied to a pair of output latches 234 and 235 on leads PB0 and PD1 - PD7 at DWCK2, where the adjusted data is then available for transfer on leads CRD0 - C~D7 35 ` to the receive data memory 11.
~3~3S
The receive data memory 11 is similar to the send data memory 10, as indicated in Figure 15. The receive data memory 11 includes data selector circuits 238 and 239 which select.either the receive time slot address generated by the clock and memory control - 5 12 from the receive data memory address co~mter 101 in Figure 5appearing on leads RT0 - RT7 or the receive address data received from the store memory 14 on leads R0 - R7. The selector circuits 238 and 239 are controlled by the control signal l;~MC generated from the output of flip-flop 111 in Figure 4 upon receipt o:E the timing signal WCK4 at the Schmitt trigger circuit 102, as already described.
When the signal RMC is equal to logic 1, the time slot signals appearing on leads RT0 - RT7 are applied by the data selector circuits 238 and 239 to the leads RM0 - RM7 which extend to each of a plurality of receive data registers 240 - 247. Upon generation of the timing signal R.MWE ~rom the output of gate 117 in Figure 4 as a result of either the clock signal WCK4 or the clock signal WCK8, data received from the digital pads 25 on leads CRD0 - CRD7 will be ~tored in the registers 240 - 247 as storage -. locations designated by the receive time slot signals RT0 - RT7.
During the subsequent input cycle, when the control lead RMC is equal to logic 1, the selector cirCuits 238 and 239 will apply the ~` receive address signals ~0 - R7 from the store rnemory 14 to theleads RM0 - RM7 which extend to each of the receive data registers 240- 247.
At this time, on the negative-going transition of WCK8 from the clock and memory control 12, the data stored in the recei.ve data registers 240 - 247 at the address indicated by the receive address leads R0 - R.7 will be transferred out on leads RB0 - R.B7 to the data out latches in Figure 16, where the data is stored in response to receipt of the DO LATCH signal generated from the clock and memory control 12. This data stored in the data out latches 250 and 251 is provided on leads IB0 - IB7 to the data conditioner.
~3~3~
Thus, as seen from the foregoing description, since all PCM data must pass through the pad control circuit, any positive loss or gain which has been prograrnmed into the P~OM can be inserted into any transmission path. In this way, the proper 5 insertion loss for each type of port-to-port connection may be provided in a very simple and reliahle manner.
While I have shown and described an embodiment in accor-dance with the present invention, it is understood that the same is not limited thereto but is susceptible of numerous changes and modi-10 fications as known to those of ordinary skill in the art, and I,therefore, do not wish to be limited to the details shown and des-cribed herein but intend to cover all such changes and modifications as are obvious to those skilled in the art.
Claims (14)
1. In a digital transmission system including a send memory, a receive memory, transfer means connecting said send memory to said receive memory and memory control means for selectively effecting transfer of digital data stored in address-able memory locations of said send memory into selected memory locations of said receive memory to establish selective data paths through said transfer means between inputs of said send memory and outputs of said receive memory, the improvement comprising impedance control means connected in said data paths for controlling the insertion loss of said data paths by selective-ly adjusting the level of said digital data, said impedance control means including programmable memory means for storing a range of adjusted digital values corresponding to a range of levels of digital data carried by said data paths, and means for apply-ing the digital data to said programmable memory means as addresses for the stored adjusted digital values.
2. A digital transmission system as defined in claim 1 wherein said impedance control means is connected between said send memory and said receive memory.
3. A digital transmission system as defined in claim 1 wherein said programmable memory means comprises a memory having at least two groups of memory locations each storing a range of digital values adjusted with respect to said range of levels of digital data by a different amount, and further including, means for selecting one of said groups of memory locations to be addressed by said digital data.
4. A digital transmission system as defined in claim 1 wherein said impedance control means includes a plurality of impedance pads selectively connectable in said data paths between said send memory and said receive memory.
5. A digital transmission system as defined in claim 4 wherein each of said impedance pads comprises a programmable read only memory.
6. A digital transmission system as defined in claim 5 wherein each of said programmable read only memories stores a range of digital values adjusted with respect to a range of levels of digital data carried by said data paths, each of said read only memories providing different amounts of adjustment of said digital data to provide different values of insertion loss in said data paths, and further including, means for selecting said read only memories for connection in said data paths.
7. A digital data transmission system for use in a telephone system including a plurality of subscriber ports to be selectively interconnected by way of data paths through said transmission system, comprising a send memory including a plurality of first data storage locations, timing control means for applying data in digital form from said subscriber ports to said send memory in sequential time slots of a repetitive time frame, a receive memory including a plurality of second data storage locations, transfer means connecting said send memory to said receive memory, store memory control means responsive to said timing control means for transferring data from a selected first data storage location to a designated second data storage location through said transfer means, said timing control means being connected to said receive memory for sending data stored in said second data storage locations to said subscriber ports in the sequential time slots of said repetitive time frame, impedance control means connected in said data paths through said send and receive memories for selectively adjusting the value of said digital data to achieve a desired insertion loss of said data paths, and processor control means responsive to subscriber request signals from said ports for supplying to said store memory control means control data indicating the first and second data storage locations between which data is to be transferred, said impedance control means including pad store means responsive to said control data for storing an indication of the degree of adjustment of said digital data to be effected in each data path to control the insertion loss therein.
8. A digital transmission system as defined in claim 7 wherein said subscriber ports include different types of line circuits and trunk circuits, and said impedance control means includes means responsive to said timing control means and said store memory control means for adjusting the level of said digital data on the basis of the type of subscriber ports interconnected by the data path.
9. A digital transmission system as defined in claim 7 wherein said impedance control means includes programmable memory means for storing a range of adjusted digital values corresponding to a range of levels of digital data carried by said data paths, and means for applying the digital data to said programmable memory means as addresses for the stored adjusted digital values.
10. A digital transmission system as defined in claim 9 wherein said programmable memory means comprises a memory having at least two groups of memory locations each storing a range of digital values adjusted with respect to said range of levels of digital data by a different amount, the output of said pad store means serving to select one of said groups of memory locations to be addressed by said digital data for each data path.
11. A digital transmission system as defined in claim 10 wherein said impedance control means is connected between said send memory and said receive memory.
12. A digital transmission system as defined in claim 7 wherein said impedance control means includes a plurality of impe-dance pads selectively connectable in said data paths between said send memory and said receive memory.
13. A digital transmission system as defined in claim 12 wherein each of said impedance pads comprises a programmable read only memory.
14. A digital transmission system as defined in claim 13 wherein each of said programmable read only memories stores a range of digital values adjusted with respect to a range of levels of digital data carried by said data paths, each of said read only memories providing different amounts of adjustment of said digital data to provide different values of insertion loss in said data paths, and further including, means for selecting said read only memories for connection in said data paths.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US927,067 | 1978-07-21 | ||
| US05/927,067 US4220823A (en) | 1978-07-21 | 1978-07-21 | Selectively controlled digital pad |
| PCT/US1979/000521 WO1980000289A1 (en) | 1978-07-21 | 1979-07-19 | Selectively controlled digital pad |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1132235A true CA1132235A (en) | 1982-09-21 |
Family
ID=41733842
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA331,421A Expired CA1132235A (en) | 1978-07-21 | 1979-07-09 | Selectively controlled digital pad |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4220823A (en) |
| EP (1) | EP0031325A1 (en) |
| CA (1) | CA1132235A (en) |
| WO (1) | WO1980000289A1 (en) |
Families Citing this family (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5932943B2 (en) * | 1979-10-17 | 1984-08-11 | 富士通株式会社 | Signal control method |
| US4320522A (en) * | 1980-05-09 | 1982-03-16 | Harris Corporation | Programmable frequency and signalling format tone frequency encoder/decoder circuit |
| US4389642A (en) * | 1981-07-01 | 1983-06-21 | Kahn William M | Digital matrix switching |
| US4596015A (en) * | 1983-02-18 | 1986-06-17 | Gte Automatic Electric Inc. | Failure detection apparatus for use with digital pads |
| US4731730A (en) * | 1985-04-30 | 1988-03-15 | Smiths Industries Aerospace & Defence Systems Inc. | Universal fuel quantity indicator apparatus |
| JPH04208742A (en) * | 1990-12-04 | 1992-07-30 | Canon Inc | Speech level adjusting device |
| US5179550A (en) * | 1991-03-07 | 1993-01-12 | Loral Aerospace Corp. | System and method for controlling a multi-point matrix switch |
| JP2744357B2 (en) * | 1991-04-23 | 1998-04-28 | キヤノン株式会社 | Private branch exchange |
| US6961943B2 (en) * | 2000-12-06 | 2005-11-01 | Microsoft Corporation | Multimedia processing system parsing multimedia content from a single source to minimize instances of source files |
| US7287226B2 (en) * | 2000-12-06 | 2007-10-23 | Microsoft Corporation | Methods and systems for effecting video transitions represented by bitmaps |
| US7114162B2 (en) * | 2000-12-06 | 2006-09-26 | Microsoft Corporation | System and methods for generating and managing filter strings in a filter graph |
| US6959438B2 (en) | 2000-12-06 | 2005-10-25 | Microsoft Corporation | Interface and related methods for dynamically generating a filter graph in a development system |
| US6912717B2 (en) | 2000-12-06 | 2005-06-28 | Microsoft Corporation | Methods and systems for implementing dynamic properties on objects that support only static properties |
| US7103677B2 (en) * | 2000-12-06 | 2006-09-05 | Microsoft Corporation | Methods and systems for efficiently processing compressed and uncompressed media content |
| US6768499B2 (en) | 2000-12-06 | 2004-07-27 | Microsoft Corporation | Methods and systems for processing media content |
| US7114161B2 (en) | 2000-12-06 | 2006-09-26 | Microsoft Corporation | System and related methods for reducing memory requirements of a media processing system |
| US6774919B2 (en) * | 2000-12-06 | 2004-08-10 | Microsoft Corporation | Interface and related methods for reducing source accesses in a development system |
| US7447754B2 (en) | 2000-12-06 | 2008-11-04 | Microsoft Corporation | Methods and systems for processing multi-media editing projects |
| US6882891B2 (en) * | 2000-12-06 | 2005-04-19 | Microsoft Corporation | Methods and systems for mixing digital audio signals |
| US6954581B2 (en) * | 2000-12-06 | 2005-10-11 | Microsoft Corporation | Methods and systems for managing multiple inputs and methods and systems for processing media content |
| US6983466B2 (en) | 2000-12-06 | 2006-01-03 | Microsoft Corporation | Multimedia project processing systems and multimedia project processing matrix systems |
| US6834390B2 (en) | 2000-12-06 | 2004-12-21 | Microsoft Corporation | System and related interfaces supporting the processing of media content |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3967250A (en) * | 1972-05-22 | 1976-06-29 | Kokusai Denshin Denwa Kabushiki Kaisha | Control system of an electronic exchange |
| US3806658A (en) * | 1972-10-30 | 1974-04-23 | Bell Telephone Labor Inc | Common controlled equalization system |
| IT980928B (en) * | 1973-04-30 | 1974-10-10 | Cselt Centro Studi Lab Telecom | USER AND INPUT EQUIPMENT TO A PCM CENTRAL FOR HIGH SPEED DATA TRANSMISSION CITA |
| US3956593B2 (en) * | 1974-10-15 | 1993-05-25 | Time space time(tst)switch with combined and distributed state store and control store | |
| JPS51132713A (en) * | 1975-05-14 | 1976-11-18 | Hitachi Ltd | Time-division communication system |
-
1978
- 1978-07-21 US US05/927,067 patent/US4220823A/en not_active Expired - Lifetime
-
1979
- 1979-07-09 CA CA331,421A patent/CA1132235A/en not_active Expired
- 1979-07-19 WO PCT/US1979/000521 patent/WO1980000289A1/en unknown
-
1980
- 1980-02-25 EP EP79900907A patent/EP0031325A1/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| WO1980000289A1 (en) | 1980-02-21 |
| EP0031325A1 (en) | 1981-07-08 |
| US4220823A (en) | 1980-09-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1132235A (en) | Selectively controlled digital pad | |
| US4038497A (en) | Hardwired marker for time folded tst switch with distributed control logic and automatic path finding, set up and release | |
| US5347270A (en) | Method of testing switches and switching circuit | |
| US4771420A (en) | Time slot interchange digital switched matrix | |
| US4862452A (en) | Digital signal processing system | |
| AU613123B2 (en) | A packet switching network | |
| CA2051910C (en) | Circuit for testing digital lines | |
| US4521879A (en) | Digital private branch exchange | |
| US4360911A (en) | Digital signal switch system having space switch located between time switches | |
| GB2110507A (en) | Time division switching matrix | |
| GB2066623A (en) | Combined data and speech transmission arrangement | |
| CA2007466A1 (en) | Parallel time slot interchanger matrix and switch block module for use therewith | |
| CA1064599A (en) | Switching and transmission technique using a method and arrangement of channel allocation | |
| CA1197932A (en) | Communication arrangements for distributed control systems | |
| CA1075384A (en) | Conferencing arrangement for use in a pcm system | |
| CA1256540A (en) | Methods of establishing and terminating connections in a distributed-control communications system | |
| JPH0573306B2 (en) | ||
| US3991276A (en) | Time-space-time division switching network | |
| US4719562A (en) | Multiprocessor system for intercommunication of processors | |
| KR0125573B1 (en) | Time-division switching system | |
| US4545053A (en) | Time slot interchanger | |
| CA1128178A (en) | Multiplex time division switching network unit of the "time-time" type | |
| CN1039516A (en) | In digital time switch, realize the method and the device that continue in the switching broadband | |
| US3997728A (en) | Unit for the simultaneous switching of digital information and signalling data in P.C.M. transmission systems | |
| US7254139B2 (en) | Data transmission system with multi-memory packet switch |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |