CA1135398A - Image interpolation system - Google Patents
Image interpolation systemInfo
- Publication number
- CA1135398A CA1135398A CA000324978A CA324978A CA1135398A CA 1135398 A CA1135398 A CA 1135398A CA 000324978 A CA000324978 A CA 000324978A CA 324978 A CA324978 A CA 324978A CA 1135398 A CA1135398 A CA 1135398A
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- CA
- Canada
- Prior art keywords
- image
- pixel
- line
- pixels
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T3/00—Geometric image transformation in the plane of the image
- G06T3/40—Scaling the whole image or part thereof
- G06T3/403—Edge-driven scaling
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/40—Picture signal circuits
- H04N1/40068—Modification of image resolution, i.e. determining the values of picture elements at new relative positions
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/41—Bandwidth or redundancy reduction
- H04N1/411—Bandwidth or redundancy reduction for the transmission or storage or reproduction of two-tone pictures, e.g. black and white pictures
Abstract
IMAGE INTERPOLATION SYSTEM
ABSTRACT OF THE DISCLOSURE
Analog image data pixels are sampled and held to produce a box car wave representative of the image data.
Wave height differences are bridged by linear interpolation, with frequency enhancement imposed at the bridge junctures. The modified image wave is thresholded and sampled at a multiple of the original frequency to provide an image pixel stream comprised of both original image pixels having one or more interpolated image pixels therebetween.
One or more intermediate image lines are interpolated by comparing binary image data, portions of which may be interpolated, on a pixel by pixel or multiple pixel basis one line pair at a time. The pixel comparison produces an address used to identify a specific image pixel pattern from multiple image pixel patterns stored in memory. The image pixel pattern taken from memory is used to form the interpolated intermediate line or lines.
ABSTRACT OF THE DISCLOSURE
Analog image data pixels are sampled and held to produce a box car wave representative of the image data.
Wave height differences are bridged by linear interpolation, with frequency enhancement imposed at the bridge junctures. The modified image wave is thresholded and sampled at a multiple of the original frequency to provide an image pixel stream comprised of both original image pixels having one or more interpolated image pixels therebetween.
One or more intermediate image lines are interpolated by comparing binary image data, portions of which may be interpolated, on a pixel by pixel or multiple pixel basis one line pair at a time. The pixel comparison produces an address used to identify a specific image pixel pattern from multiple image pixel patterns stored in memory. The image pixel pattern taken from memory is used to form the interpolated intermediate line or lines.
Description
1~3S39 i3 This invention relates to an image data handling system, and more particularly, to an image data handling system with data interpolation permitting minimal image input samples while providing increased image output samples for good output image resolution.
Where image data in the form of analog or binary signals is to be handled, the generation of the image data, storage of the data, and transmission of the image data to one or more output stations where the data may be used to produce copies of the original represented by the data, presents conflicting problems in terms of the cost and complexity of the apparatus required versus the quality and resolution of the copies produced. Where one attempts to optimize the quality and resolution of the copies produced, the price paid is usually reflected in increased cost and complexity of the image data producing and handling apparatus, i.e. in the data generating apparatus required to provide image samples or pixels in greater density, in a larger memory to store the image data pending use, and in increased data bandwidth on transmission of the data from one point to another. C~ the other hand, where one attempts to reduce and alleviale cost and simplify the data generating and handling apparatus by making fewer samples of the original, the savings is usually at the expense of decreased image resolution and quality.
This invention in one aspect is a method of handling data representative of an image in pixel form to enhance image output quality and reduce image data storage require-ments and transmission bandwidth, which comprises: pro-viding image pixels representative of an image on a line by ~, ,, :
:1 ~353~8 by line basis; at the input station, interpolating addi-tional image pixels from the image pixels originally scanned; and at an output station, interpolating at least one additional line of image pixels for each line of image pixels from the image pixels previously obtained.
The invention in another aspect relates to a method of interpolating at least one line of image data from at least one known line of image data, comprising:
buffering a block of binary image pixels from the known line to provide an address; addressing a memory having discrete image patterns with the address; outputting the image pattern addressed to provide a portion of the line being interpolated; and, successively repeating the preceeding steps to complete the interpolated line of image data.
According to another aspect of this invention there is provided in a method of interpolating at least one line of image data from at least one known line of image data, the steps comprising: a) buffering a block of binary image pixels from said known line of image data to provide an addr~s-; b) addressing a memory having discrete image pixel patterns therewithin with said address to obtain the preset image pixel pattern corresponding to said address; c) outputting the preset image pixel pattern addressed from said memory to provide a portion of the interpolated line; and d) repeating steps a, b, and c using additional blocks of image pixels from said known line to complete said interpolated line of image data.
According to another aspect of this invention there is provided in the method of interpolating at least one intermediate line of image data from each pair .
of adjoining lines of image data, the steps comprising:
a) buffering at least one binary image pixel from each of said pairs of adjoining lines of image data to provide an address; b) addressing a memory having discrete image pixel patterns therewithin with said address to obtain the preset image pixel pattern corresponding to said address;
c) outputting the preset image pixel pattern addressed from said memory to provide a portion of said intermediate line; and d) repeating steps a, b, and c using additional image pixels from said pairs of adjoining lines of image data to complete said intermediate line.
Other objects and advantages will be apparent from the ensuing description and drawings in which:
Figure 1 is a schematic view showing interpolation of additional image pixels in a serial pixel stream of image data;
Figure 2 is a schematic view showing interpolation of additional image pixels both within a line pair of pixels and of an additional line of pixels between the line ~' Figure 3 is a schematic outline of the image pixel interpolating system of the present invention;
Figure 4 is a schematic view showing details of the linear interpolator and enhancement filter of Figure 3;
Figure 5 is a schematic view showing details of the image line interpolation system of the present invention;
Figure 6 is a timing chart of the clock pulses for the system of Figure 5;
Figure 7 is a schematic illustrating a representa-tive number of the image pixel patterns stored in memoryand the addresses therefor;
Figure 8 is an isometric view of an exemplary raster input scanning mechanism.
-3a-. ~_ Figure 9 is a schematic view of an alternate image line interpolation system;
Figure 10 is a timing chart for the system shown in Figure 9; and Figure 11 is a representative illustration of ima~e pixel patterns for the system shown in Figure 9.
Referring to Figures 1 and 2, there i5 provided a schematic illustration showing interpolation of additional image pixels 12 between real or original pixels 10 in a serial pixel stream 11 ~Fig. 1) and, in Fig. 2, interpolation of an additional image line (Ll 1) between a pair oE image lines (Ll, L2) as performed by the present invention. Pixels herein refer to video image data samples or picture elements and may comprise either an analog or binary representation of the image value at a point. Pixels 10 may, for example be obtained through line by line scanning of an image bearing original 6 by one or more arrays of charge coupled devices 7, commonly referred to as CCD's. One CCD is a Fairchild CCD 121-1728 pixel 2-phase linear array by Fairchild Manufac-turing Company~
One suitable scanning apparatus is shown in Figure 8, and comprises plural CCDs 7, together with lenses 8 supported so that the viewing fields or areas of the ccns 7 overlap one another to assure continuity of scan. CCDs 7 and lenses 8 are mounted Oll a movab]e carriage 9 spacedly disposed below a transparent platen glass 13 upon which the origlnal document 6 to be scanned is placed. A lamp 1~ mounted on the carria~e 9 provides illumlnation with a morror combina-tion 16 provided to guide the light rays reflected from the original document to the lenses 8 and the CCDs 7. A timing control 18 synchronizes actuation of the CCDs with movement of the carriage 9 so that as the carriage moves past the platen and the original document thereon, a succession of line scans oE the original document are made by ~he CCDC;.
~3~3g~
, Further details of the aforesald scanning mechanism may be found in Canadian application Serial No.
301,764 filed April 24, 1978. Other known methods of generating image data or pixels may be envisioned as for example, a TV camera, etc.
The individual pixels o~tained by the scanning apparatus initially comprise analog voltage represen-tations of the gray scale of the area viewed by the individual CCD
elements. The CCD elements are driven by a suitable clock 23 (Fig. 3) such that pixels are generated in a serial pixel stream.
For certain purposes, i.e. image storage, transmission, etc. it is advantageous to provide minimal numbers of pixels. At the same time, too few pixels can have adverse affect on the qua]ity of the image produced.
The present invention permits minimal input resolution yet provides enhanced image output resolution by interpolating additional or extra pixels 12 between original pixels 10 as seen in Fig. 1. In this embodiment, a one-dimensional interpolator 15 interpolates pixels 12 based on the image value of adjoining pixels 10, it being understood that interpolation may be either on an analog or digital (i.eO 1 or 0) image basis.
In the embodiment shown in Figure 2, an additional line Ll 1 is interpolated by a two-dimensional interpolator 17 between line pair Ll, L2 using pixels 10 and pixels 12 or in the alternative original pixels 10 only.
It will be understood that more than one pixel 12 may be interpolated between adjoining pixels 10 of a line.
Similarly, more than one line may be interpolated between . . .
- 11353~3 adjoining line pairs. Interpolation of an additional line or lines may be made from a single line (i.e. Ll) rather than line pair Ll, L2.
- 5a -113S398 h~
~efcrring no~7 t:o the embo-lim~nt shown in ~igure 3, th~ stream of pixels 10 obtained for exam~le ~rom a CCD
scanning Irray 7, is inputted to sample and hold circuit 24, ~hich m~y conpri.se a Datel Cor~. Samr?le And ~Iold Model SE~
circuit. ~n exem,?l~ry input pixel wave form is illustrated at. 25. Sam~le and hold circuit 2a, which is driven in synchron-iz~tion wi.th the pixel streaM by pixel clock 23 operates to sam?]e the voltage lev21 of each pixel 10 an~ to produce a vol.tage 1.evel signal representi.ng the pixel voltac3e over a prcs.et tiMe interval t follo-.~ing which tne next pixel is sampledv The output wave form of sample an~ hold circuit 24 for the exemplary signal inrout is shown in 28 and may be descr .; b2d as a box car wave. The box car signal output of circuit 24 is fed to a linear interpolator 30 where a linear ]-5 i.nterpolati.on is made be-tween ~ifferent pixel. voltage levels over tl~e tim~ i.nterval t. In essence interpolator 30 gene--ates a sloping signal line bridging between different voltage le~els.
The modified box car wave output of interpolator 30 i.s sho~n at 31.
Fro~ interpolator 30, the interpolated signal i.s fed t.o an enhancemont fil.ter 36. Filter 36 accommodates the rela-tively rapid dropoff in light transf~r efficiency of the opLical el.clr.ents in ~he signal generating apparatus i.e. lenses by enhancin~ th~ high frequencies of the signal. The output wave form of enhancement filter 36, for the exemplary signal input, is shown at 37.
~`he enhanced s:ignal 37 is fed to one gate of a ccnvcn-tional com~rator 40 sucn as Signetic's Inc. Moclel. No. ~E 5003 co.n?arator. .~ preselec-ted volta~ threshold level is applied to th~ other input g.lte of compalator 4-0. For siynal voltayes above the threshold level, the output of comparator 40 ls a binary l; for signals be]ow the threshold level, the output of comparator 40 is a binary 0. The output wave form of comparator 40 for the exemplary signal input 25 is seen at 43.
The square wave output of comparator 40 is fed to a conventional D type flip-flop 46 such as Texas Instrument Model 74-174 Flip Flop. A square wave clock signal 48, the frequency of which is a multiple of pixel clock 23 is inputted to flip-flop 46 from a suitable clock 47. In the exemplary arrangement shown wherein an interpolated pixel 12 is to be provided between each original pixel 10, the frequency of clock 47 is twice that of pixel clock 23.
Signal readings are taken off of the rising or leading edge of clock signal 48 to produce a pixel output stream 49 incorporating both original pixels 10 and interpolated pixels 12.
Referring to Figure 4, details of linear interpolator 30 and enhancement filter 36 are thereshown.
Interpolator/filter 30, 36 comprises a conventional lumped parameter delay line or circuit 50 such as Model No.
2214-1000 by Data Delay, Inc. effective to impose a predetermined delay on the box car signal input from sample and hold circuit 2~ as the signal passes from the input terminal of circuit 50 to the output terminal thereof. A
series of voltage taps 54 permit tapping off of the signal after preset incremental delays. A termination resistor 51 inhibits voltage reflections.
Taps 54 of delay circuit 50, which are coupled through resistors 55, 55' to the positive and negative terminal of OP amp 60, provide resistor circuits 56, 57 *1353~3~
coupled to the negative terminal of AMP 60 and resistor circuit 58 coupled to the positive terminal of A*lP 60. OP
amp 60 may comprise any suitable operational amplifier such as an R.C.A. Model No. CA-3100 chip. Resistor circuits 56, 57 each comprise a group of three parallel resistors 55 while resistor circuit 58 comprises a group of four resistors 55', in the exemplary embodiment illustrated.
Leads 65, 66 which couple resistor circuit 56, 57 and resistor circuit 58 to the negative and positive terminal of OP amp 60 have control resistors 68, 69 respectively in series therewith. Lead 66 is coupled through resistor 70 to ground. Feedback to the negative terminal of OP amp 60 is provided by resistor 73.
The signal input to delay circuit 50 progresses through circuit 50 over a predetermined interval~ the length of which is controlled by the design parameters of the delay circuit 50. One suitable interpolation/enhancement rilter has voltage taps 54 at equi-distant points with a delay interval of 75 nano seconds per voltage tap and with resistcrs 55 of 4.0 K
ohms, resistors 55' of 9.75 K ohms, resistor 51 of 500 ohms, resistor 6S of 20.5 Kohms, resistor 69 cf 3.4 K ohms, resistor 70 of 500 K ohms, and resistor 73 of 36 K ohms.
In operation of interpolator/filter 30, 36 on a change in strength of the signal input from sample and hold circuit 24, as for example, an increase between pixel voltage levels, the increased signal voltage wavefront progressively appears at voltage taps 5~ along delay circuit 50. With application of the increased voltage signal to resistors 55 of circuit 56 in succession, the change in input signal strength to the negative terminal of r ~L~L353~3 OP amp 60 causes a drop in the output signal of OP amp 60 (shown at 70 in wave form 37). The output signal of amp 60 then rises as the increased voltage signal is applied successively to the resistors 55' of circuit 56 with resulting change in the input signal to the posltive terminal of OP amp 60 (shown at 71 in wave form 37). As the increased voltage signal proqresses through delay circuit 50 to resistor circuit 57~ the signal input to the negative terminal of OP amp 60 undergoes further change resulting in a second dip ~shown at 72 in wave form 37) in the output signal of OP amp 60. The signal output of OP
amp 60 then stabilizes (shown at 73 in wave form 37) until the next change in the voltage level of the signal input to delay circuit 50.
It will be understood that a decrease in the voltage level of the signal input to delay line 50 produces the opposite effect.
Referring to Figure 5, for line interpolation, binary image data which may or may not include interpolated pixels 12 as aforedescribed, is fed to line interpolator circuit 98 one line pair at a time.
In the exemplary arrangement illustrated, a first line pair, desiynated as Ll, L2 are employed for illustration purposes. It is understood that succeeding 25 line pairs, i.e. lines L2, L3; L3, L4,Ln-ll, Ln etc. are treated in the same manner. And while image data is described herein as being processed in blocks of four pixels at a time, processing o~ other size i.mage data blocks may be readily contemplated. It is further understood that where the original image data is in analog form, the data is converted, as by the interpolation . . ~ .
~13S398 process described heretofore, to binary level (i.e. "1" or "0") image data prior to input to line interpolator circuit 98.
In the arranqement shown in Figure 5, image data is received in serial pixel form on a line by line basis from a data source, as for example, an image scanning apparatus of the type shown in Fisure 8, or from memory storage, etc., on data input bus 99. Image data in bus 99 is inputted via line delay buffer 100 and data bus 103, and directly via buffer bypass bus 107, to input buffers 106, 108 respectively of interpolator circuit 98. Buffer 100 serves in effect to impose a one line delay on the image data to permit a preceeding line (i.e. line Ll) to be compared with the next succeeding line (i.e. line L2) on a pixel by pixel basis. During comparison, as line delay buffer 100 is serially unloaded, the next line (i.e. line L2) is simultaneously loaded into buffer 100 for use in comparing that line (i.e. line L2) with the next succeeding line (i.e. line L3).
A suitable clock 114 provides input pixel clock pulses ~1' address load control pulses ~2' output pixel load control pulses ~3, and output pixel clock pulses ~4.
The wave form of clock pulses ~ ~2~ 03~ ~4 for the image processinq example described herein is shown in Figure 6.
The image data from line delay buffer 100 and in bypass buffer 107 is clocked into input buffer pair 106, 108 on a block by block basis by input pixel clock 01. It will be understood that clock signal ~1' or some other clock signal in synchronism therewith, serves to clock image data from the data source forward in input bus 99 to - , , ~:
1135~9~
load fresh data into line delay buffer 100 and provide data in bypass bus 107.
In the exemplary arrange~ent shown, the image data blocks are four pixels wide. Input buffers 106, 108 comprise se~ial in-parallel out buffers, which in the example illustrated, are four bits wide each to provide an eight bit address to address buffers 122, 124 of pixel pattern memory 125.
On address load control pulse ~2' the content of input buffers 106, 108 is read through data buses 121, 123 into address buffers 122, 124 respectively. Address buffers 122, 124, which comprise parallel in-parallel out buffers, address a specific image bit pattern stored in memory 125.
Memory 125, which may comprise any suitable Random Access Memory (RA~1), Read Only Memory (RO~I~, etc., has various image pixel patterns 127, representative samples of which are illustrated in Figure 7, stored therein. The image data in address buffers 122, 124 addresses the specific image pixel pattern 127 associated with that address. In the exar.ple shown, an eight bit address, the sum of the blocks of image data in input buffers 106, 108, is used.
On output pixel load control pulse ~3, memorv 125 loads, via data buses 129, 131, output buffers 132, 134 with the specific image pixel pattern addressed which in the present example results in buffers 132, 134 each being loaded with a specific four pixel block of image data. At the same time, clock pulse 03 causes the pixel pattern in input buffer 106 to be read into output buffer 118 through data bus 121.
~35398 Output buffers 118, 132, 134 comprise parallel in-serial out buffers. On output pixel clock pul,ses ~4, the pixel image data in buffers 118, 132, 134 is serially unloaded to a suitable output such as a memory (not shown) where the image data, comprising both real and interpolated pixels, may be held pending use as for example by a suitable marking or copying device.
The various buffers of interpoiator circuit 98 may comprise any suitable commercially available buffers.
In the circuit shown, buffers 100, 106, 108, 118, 132, 134 comprise Texas Instruments Model No. 74-195 buffers, and buffers 122, 124 Texas Instruments Model ~lo. 74-175 buffers. Memory 125 comprises Fairchild Inc. R~ Model No.
93-145 chips.
- lla -` 113S398 In the line interpolation arranyement illus~rated in ~igures 5-7, the pixel image output comprises pixels 128 of image data from lineLl, together with positionally equiva-lent pixels 130 of image data for lines Ll-l and Ll-2 taken from memory 125. As described, the image data content of lines Ll-l and Ll-2 is determined by considering the image values of the positional]y equivalent pixels 128 in each of lines Ll, L2. It may, however be desirable when interpo-lating image data for one or more additional lines to base the interpolated image data for the additional line or lines on the image values of one or more pixels outside the posi-tionally equivalent pixels, i.e., on the image values of one or more pixels before and/or after the pixels 128 of lines Ll, L2.
Referring particularly to Figures 9-11, there is shown an example of line interpolation wherein the predicted image pixel patterns for the interpolated line or lines (in the example shown, lines Ll-l and Ll-2) is based upon the image value of both pixels 239 immedia.ely preceeding and succeeding pixels 238, together with the image value of pixels 238. As seen in Figure 11, the exemplary image pixel patterns 227 thereshown each comprise a four pixel block 228 consisting of two pixels for each interpolated line Ll-l and Ll-2.
The memory address for the image pixel patterns 227 comprises an eight pixel address 233 consisting of a block of fo-lr successive pixels from each of adjoining lines Ll, L2, each block of pixels however being made up of additional end pixels 239 and intermediate pixels 238.
The intermediate pixels 238 in the four pixel address block from line Ll also comprises the pixel output portion ~135398 of line Ll. As a result, the pixel output for lines Ll, I.l-l, and Ll-2 comprises intermediate pixels 238 from line Ll and the particular pixel pattern 227 drawn fro~ memory 225 for interpolated lines Ll-l and ~1-2.
In the arrangement shown in Figure 9, image data is received in serial pixel form on a line by line basis from a data source, as described heretofore, and inputted via line delay bufEer 200, data bus 203, and bypass bus 207, to input buffers 206, 208 respectively of the in~.erpolator circuit.
A suitable clock 114' provides input pixel clock pulses 01 " address load control pulses ~2 " output pixel load control pulses 03', and output pixel clock pulses 04'.
The wave form of clock pulses 0i~ 02 ~ 03't 04' for the image processing example described herein is shown in Figure 10.
The image data from line delay buffer 200 and in bypass buffer 207 is clocked into input buffer pair 206, 208 on a block by block basis by input pixel clock 01 " each block being two pixels wide. ClocJc signal ~1 ~ or some other clock signal in synchronism therewith, is also used to clock image data from the data source forward into line delay buf-fer 200 and bypass bus 207.
In the exemplary arrangement shown, input buffers 206, 208 comprise serial in-parallel out buffers, which in the example illustrated, are four bits wide each to provide an eight bit address to address buffers 222, 224 of pixel pattern memory 225.
On address load control pulse ~2 " the content of input buffers 206, 208 is read through data buses 221, 223 into address buffers 222, 224 respectively. Address - . . .. . . ..
' ~ ;
:1135398 buffers 222, 22~, which comprise parallel in-parallel out buffers, address a speci:Eic image bit pattern 227 stored in memory 225, examples of which are shown in Figure 11.
On output pixel load control pulse 03', memory 225 loads, via data buses 229, 231, output buffers 232, 23 with the spccific image pixel pattern addressed which in the present example results in buffers 232, 234 each being loaded with a specific two pixel block of image data. At the same time, clock pulse 03' loads the intermediate pair of pixels in input buEfer 206 into output buffer 218 through data bus 226.
On output pixel clock pulses 04', the pixel image data in buffers 228, 232, 234 is serially unloaded to a suit-able output as described heretofore.
On the succeeding clock pulse 01 ~ two fresh pixels from lines Ll, L2 are loaded into input buffer pair 206, 208 and the foregoing process repeated.
In the line interpolation process of Figures 9-11, the content of the interpolated lines Ll-l and Ll-2 is determined from the image values of the pixels in lines Ll, L2. rrhe portion of lines Ll, L2 looked at for interpolation purposes includes the pair of pixels 238 positionally corres-ponding to the interpolated pixels and a single pi.xel 239 from before and after the pixels 238. It will be understood, however, that the number of pixels 239 looked at may be greater than one and further, that only the pixel(s) before or after the pixels 238 may be looked at. And, while the pixels 238 from lines Ll, L2 and in image pixel patterns 227 are i]lus-trated as bei.ng two pixels wide, the pixel width may range from a low of one pixel to a number greater than the two pixels illus~ra-ted in Figures 9-11.
While in the afo~edescribed arrangements, a pair of intermediate lines (i.e. Ll-l and Ll-2) are interpolated from adjoining pairs, it wi]l be appreciated that the number oE lines interpolated may be as few as one. It will also be understood that the accuracy of the interpolation process decreases with increase in the number of intermediate lines interpolated. ~nd, while interpolation has been described herein using a pair of adjoining lines to predict one or more intermediate lines, the aforedescribed interpolation process may instead employ a single known line as the basis for predicting one or more adjoining lines.
It is understood that the eight pixel address illus-trated, the composition thereof as four pixels from adjacent lines (i.e. lines Ll, L2), and the t~o and four pixel wid~
two line interpolating image patterns stored in memory are exemplary only, and that addresses of various pixel length and composition as well as image patterns of ~arious pi~el length and/or various numbers of interpolated lines may be contemplated instead.
While interpolation of additional pixels 12 may be performed at any point in a data system including the data output station or terminal, since the image data used comprises analog in~age data, preferably such interpolation is performed at the input station. This avoids the ~xpense of storing data in analog form. The image data, which following interpolation is in binary form, may then be stored and/or transmitted. Transmission of the image data from one si~e, i.e. the input station to another site, i.e. an output station, may take place in any suitable manner as known to those skilled ~0 in the facsimile arts for example.
~13S398 .
Line interpolation, which may be performed at any point in a data system including the input station, is pre-ferably performed at the data output station or terminal to reduce data storage needs and transmission bandwidth.
While the invention has been described with refer-ence to the structure disclosed, it is not confined to the details set forth, but is intended to cover such modifications or changes a.s may corne within the scope of the following claims:
Where image data in the form of analog or binary signals is to be handled, the generation of the image data, storage of the data, and transmission of the image data to one or more output stations where the data may be used to produce copies of the original represented by the data, presents conflicting problems in terms of the cost and complexity of the apparatus required versus the quality and resolution of the copies produced. Where one attempts to optimize the quality and resolution of the copies produced, the price paid is usually reflected in increased cost and complexity of the image data producing and handling apparatus, i.e. in the data generating apparatus required to provide image samples or pixels in greater density, in a larger memory to store the image data pending use, and in increased data bandwidth on transmission of the data from one point to another. C~ the other hand, where one attempts to reduce and alleviale cost and simplify the data generating and handling apparatus by making fewer samples of the original, the savings is usually at the expense of decreased image resolution and quality.
This invention in one aspect is a method of handling data representative of an image in pixel form to enhance image output quality and reduce image data storage require-ments and transmission bandwidth, which comprises: pro-viding image pixels representative of an image on a line by ~, ,, :
:1 ~353~8 by line basis; at the input station, interpolating addi-tional image pixels from the image pixels originally scanned; and at an output station, interpolating at least one additional line of image pixels for each line of image pixels from the image pixels previously obtained.
The invention in another aspect relates to a method of interpolating at least one line of image data from at least one known line of image data, comprising:
buffering a block of binary image pixels from the known line to provide an address; addressing a memory having discrete image patterns with the address; outputting the image pattern addressed to provide a portion of the line being interpolated; and, successively repeating the preceeding steps to complete the interpolated line of image data.
According to another aspect of this invention there is provided in a method of interpolating at least one line of image data from at least one known line of image data, the steps comprising: a) buffering a block of binary image pixels from said known line of image data to provide an addr~s-; b) addressing a memory having discrete image pixel patterns therewithin with said address to obtain the preset image pixel pattern corresponding to said address; c) outputting the preset image pixel pattern addressed from said memory to provide a portion of the interpolated line; and d) repeating steps a, b, and c using additional blocks of image pixels from said known line to complete said interpolated line of image data.
According to another aspect of this invention there is provided in the method of interpolating at least one intermediate line of image data from each pair .
of adjoining lines of image data, the steps comprising:
a) buffering at least one binary image pixel from each of said pairs of adjoining lines of image data to provide an address; b) addressing a memory having discrete image pixel patterns therewithin with said address to obtain the preset image pixel pattern corresponding to said address;
c) outputting the preset image pixel pattern addressed from said memory to provide a portion of said intermediate line; and d) repeating steps a, b, and c using additional image pixels from said pairs of adjoining lines of image data to complete said intermediate line.
Other objects and advantages will be apparent from the ensuing description and drawings in which:
Figure 1 is a schematic view showing interpolation of additional image pixels in a serial pixel stream of image data;
Figure 2 is a schematic view showing interpolation of additional image pixels both within a line pair of pixels and of an additional line of pixels between the line ~' Figure 3 is a schematic outline of the image pixel interpolating system of the present invention;
Figure 4 is a schematic view showing details of the linear interpolator and enhancement filter of Figure 3;
Figure 5 is a schematic view showing details of the image line interpolation system of the present invention;
Figure 6 is a timing chart of the clock pulses for the system of Figure 5;
Figure 7 is a schematic illustrating a representa-tive number of the image pixel patterns stored in memoryand the addresses therefor;
Figure 8 is an isometric view of an exemplary raster input scanning mechanism.
-3a-. ~_ Figure 9 is a schematic view of an alternate image line interpolation system;
Figure 10 is a timing chart for the system shown in Figure 9; and Figure 11 is a representative illustration of ima~e pixel patterns for the system shown in Figure 9.
Referring to Figures 1 and 2, there i5 provided a schematic illustration showing interpolation of additional image pixels 12 between real or original pixels 10 in a serial pixel stream 11 ~Fig. 1) and, in Fig. 2, interpolation of an additional image line (Ll 1) between a pair oE image lines (Ll, L2) as performed by the present invention. Pixels herein refer to video image data samples or picture elements and may comprise either an analog or binary representation of the image value at a point. Pixels 10 may, for example be obtained through line by line scanning of an image bearing original 6 by one or more arrays of charge coupled devices 7, commonly referred to as CCD's. One CCD is a Fairchild CCD 121-1728 pixel 2-phase linear array by Fairchild Manufac-turing Company~
One suitable scanning apparatus is shown in Figure 8, and comprises plural CCDs 7, together with lenses 8 supported so that the viewing fields or areas of the ccns 7 overlap one another to assure continuity of scan. CCDs 7 and lenses 8 are mounted Oll a movab]e carriage 9 spacedly disposed below a transparent platen glass 13 upon which the origlnal document 6 to be scanned is placed. A lamp 1~ mounted on the carria~e 9 provides illumlnation with a morror combina-tion 16 provided to guide the light rays reflected from the original document to the lenses 8 and the CCDs 7. A timing control 18 synchronizes actuation of the CCDs with movement of the carriage 9 so that as the carriage moves past the platen and the original document thereon, a succession of line scans oE the original document are made by ~he CCDC;.
~3~3g~
, Further details of the aforesald scanning mechanism may be found in Canadian application Serial No.
301,764 filed April 24, 1978. Other known methods of generating image data or pixels may be envisioned as for example, a TV camera, etc.
The individual pixels o~tained by the scanning apparatus initially comprise analog voltage represen-tations of the gray scale of the area viewed by the individual CCD
elements. The CCD elements are driven by a suitable clock 23 (Fig. 3) such that pixels are generated in a serial pixel stream.
For certain purposes, i.e. image storage, transmission, etc. it is advantageous to provide minimal numbers of pixels. At the same time, too few pixels can have adverse affect on the qua]ity of the image produced.
The present invention permits minimal input resolution yet provides enhanced image output resolution by interpolating additional or extra pixels 12 between original pixels 10 as seen in Fig. 1. In this embodiment, a one-dimensional interpolator 15 interpolates pixels 12 based on the image value of adjoining pixels 10, it being understood that interpolation may be either on an analog or digital (i.eO 1 or 0) image basis.
In the embodiment shown in Figure 2, an additional line Ll 1 is interpolated by a two-dimensional interpolator 17 between line pair Ll, L2 using pixels 10 and pixels 12 or in the alternative original pixels 10 only.
It will be understood that more than one pixel 12 may be interpolated between adjoining pixels 10 of a line.
Similarly, more than one line may be interpolated between . . .
- 11353~3 adjoining line pairs. Interpolation of an additional line or lines may be made from a single line (i.e. Ll) rather than line pair Ll, L2.
- 5a -113S398 h~
~efcrring no~7 t:o the embo-lim~nt shown in ~igure 3, th~ stream of pixels 10 obtained for exam~le ~rom a CCD
scanning Irray 7, is inputted to sample and hold circuit 24, ~hich m~y conpri.se a Datel Cor~. Samr?le And ~Iold Model SE~
circuit. ~n exem,?l~ry input pixel wave form is illustrated at. 25. Sam~le and hold circuit 2a, which is driven in synchron-iz~tion wi.th the pixel streaM by pixel clock 23 operates to sam?]e the voltage lev21 of each pixel 10 an~ to produce a vol.tage 1.evel signal representi.ng the pixel voltac3e over a prcs.et tiMe interval t follo-.~ing which tne next pixel is sampledv The output wave form of sample an~ hold circuit 24 for the exemplary signal inrout is shown in 28 and may be descr .; b2d as a box car wave. The box car signal output of circuit 24 is fed to a linear interpolator 30 where a linear ]-5 i.nterpolati.on is made be-tween ~ifferent pixel. voltage levels over tl~e tim~ i.nterval t. In essence interpolator 30 gene--ates a sloping signal line bridging between different voltage le~els.
The modified box car wave output of interpolator 30 i.s sho~n at 31.
Fro~ interpolator 30, the interpolated signal i.s fed t.o an enhancemont fil.ter 36. Filter 36 accommodates the rela-tively rapid dropoff in light transf~r efficiency of the opLical el.clr.ents in ~he signal generating apparatus i.e. lenses by enhancin~ th~ high frequencies of the signal. The output wave form of enhancement filter 36, for the exemplary signal input, is shown at 37.
~`he enhanced s:ignal 37 is fed to one gate of a ccnvcn-tional com~rator 40 sucn as Signetic's Inc. Moclel. No. ~E 5003 co.n?arator. .~ preselec-ted volta~ threshold level is applied to th~ other input g.lte of compalator 4-0. For siynal voltayes above the threshold level, the output of comparator 40 ls a binary l; for signals be]ow the threshold level, the output of comparator 40 is a binary 0. The output wave form of comparator 40 for the exemplary signal input 25 is seen at 43.
The square wave output of comparator 40 is fed to a conventional D type flip-flop 46 such as Texas Instrument Model 74-174 Flip Flop. A square wave clock signal 48, the frequency of which is a multiple of pixel clock 23 is inputted to flip-flop 46 from a suitable clock 47. In the exemplary arrangement shown wherein an interpolated pixel 12 is to be provided between each original pixel 10, the frequency of clock 47 is twice that of pixel clock 23.
Signal readings are taken off of the rising or leading edge of clock signal 48 to produce a pixel output stream 49 incorporating both original pixels 10 and interpolated pixels 12.
Referring to Figure 4, details of linear interpolator 30 and enhancement filter 36 are thereshown.
Interpolator/filter 30, 36 comprises a conventional lumped parameter delay line or circuit 50 such as Model No.
2214-1000 by Data Delay, Inc. effective to impose a predetermined delay on the box car signal input from sample and hold circuit 2~ as the signal passes from the input terminal of circuit 50 to the output terminal thereof. A
series of voltage taps 54 permit tapping off of the signal after preset incremental delays. A termination resistor 51 inhibits voltage reflections.
Taps 54 of delay circuit 50, which are coupled through resistors 55, 55' to the positive and negative terminal of OP amp 60, provide resistor circuits 56, 57 *1353~3~
coupled to the negative terminal of AMP 60 and resistor circuit 58 coupled to the positive terminal of A*lP 60. OP
amp 60 may comprise any suitable operational amplifier such as an R.C.A. Model No. CA-3100 chip. Resistor circuits 56, 57 each comprise a group of three parallel resistors 55 while resistor circuit 58 comprises a group of four resistors 55', in the exemplary embodiment illustrated.
Leads 65, 66 which couple resistor circuit 56, 57 and resistor circuit 58 to the negative and positive terminal of OP amp 60 have control resistors 68, 69 respectively in series therewith. Lead 66 is coupled through resistor 70 to ground. Feedback to the negative terminal of OP amp 60 is provided by resistor 73.
The signal input to delay circuit 50 progresses through circuit 50 over a predetermined interval~ the length of which is controlled by the design parameters of the delay circuit 50. One suitable interpolation/enhancement rilter has voltage taps 54 at equi-distant points with a delay interval of 75 nano seconds per voltage tap and with resistcrs 55 of 4.0 K
ohms, resistors 55' of 9.75 K ohms, resistor 51 of 500 ohms, resistor 6S of 20.5 Kohms, resistor 69 cf 3.4 K ohms, resistor 70 of 500 K ohms, and resistor 73 of 36 K ohms.
In operation of interpolator/filter 30, 36 on a change in strength of the signal input from sample and hold circuit 24, as for example, an increase between pixel voltage levels, the increased signal voltage wavefront progressively appears at voltage taps 5~ along delay circuit 50. With application of the increased voltage signal to resistors 55 of circuit 56 in succession, the change in input signal strength to the negative terminal of r ~L~L353~3 OP amp 60 causes a drop in the output signal of OP amp 60 (shown at 70 in wave form 37). The output signal of amp 60 then rises as the increased voltage signal is applied successively to the resistors 55' of circuit 56 with resulting change in the input signal to the posltive terminal of OP amp 60 (shown at 71 in wave form 37). As the increased voltage signal proqresses through delay circuit 50 to resistor circuit 57~ the signal input to the negative terminal of OP amp 60 undergoes further change resulting in a second dip ~shown at 72 in wave form 37) in the output signal of OP amp 60. The signal output of OP
amp 60 then stabilizes (shown at 73 in wave form 37) until the next change in the voltage level of the signal input to delay circuit 50.
It will be understood that a decrease in the voltage level of the signal input to delay line 50 produces the opposite effect.
Referring to Figure 5, for line interpolation, binary image data which may or may not include interpolated pixels 12 as aforedescribed, is fed to line interpolator circuit 98 one line pair at a time.
In the exemplary arrangement illustrated, a first line pair, desiynated as Ll, L2 are employed for illustration purposes. It is understood that succeeding 25 line pairs, i.e. lines L2, L3; L3, L4,Ln-ll, Ln etc. are treated in the same manner. And while image data is described herein as being processed in blocks of four pixels at a time, processing o~ other size i.mage data blocks may be readily contemplated. It is further understood that where the original image data is in analog form, the data is converted, as by the interpolation . . ~ .
~13S398 process described heretofore, to binary level (i.e. "1" or "0") image data prior to input to line interpolator circuit 98.
In the arranqement shown in Figure 5, image data is received in serial pixel form on a line by line basis from a data source, as for example, an image scanning apparatus of the type shown in Fisure 8, or from memory storage, etc., on data input bus 99. Image data in bus 99 is inputted via line delay buffer 100 and data bus 103, and directly via buffer bypass bus 107, to input buffers 106, 108 respectively of interpolator circuit 98. Buffer 100 serves in effect to impose a one line delay on the image data to permit a preceeding line (i.e. line Ll) to be compared with the next succeeding line (i.e. line L2) on a pixel by pixel basis. During comparison, as line delay buffer 100 is serially unloaded, the next line (i.e. line L2) is simultaneously loaded into buffer 100 for use in comparing that line (i.e. line L2) with the next succeeding line (i.e. line L3).
A suitable clock 114 provides input pixel clock pulses ~1' address load control pulses ~2' output pixel load control pulses ~3, and output pixel clock pulses ~4.
The wave form of clock pulses ~ ~2~ 03~ ~4 for the image processinq example described herein is shown in Figure 6.
The image data from line delay buffer 100 and in bypass buffer 107 is clocked into input buffer pair 106, 108 on a block by block basis by input pixel clock 01. It will be understood that clock signal ~1' or some other clock signal in synchronism therewith, serves to clock image data from the data source forward in input bus 99 to - , , ~:
1135~9~
load fresh data into line delay buffer 100 and provide data in bypass bus 107.
In the exemplary arrange~ent shown, the image data blocks are four pixels wide. Input buffers 106, 108 comprise se~ial in-parallel out buffers, which in the example illustrated, are four bits wide each to provide an eight bit address to address buffers 122, 124 of pixel pattern memory 125.
On address load control pulse ~2' the content of input buffers 106, 108 is read through data buses 121, 123 into address buffers 122, 124 respectively. Address buffers 122, 124, which comprise parallel in-parallel out buffers, address a specific image bit pattern stored in memory 125.
Memory 125, which may comprise any suitable Random Access Memory (RA~1), Read Only Memory (RO~I~, etc., has various image pixel patterns 127, representative samples of which are illustrated in Figure 7, stored therein. The image data in address buffers 122, 124 addresses the specific image pixel pattern 127 associated with that address. In the exar.ple shown, an eight bit address, the sum of the blocks of image data in input buffers 106, 108, is used.
On output pixel load control pulse ~3, memorv 125 loads, via data buses 129, 131, output buffers 132, 134 with the specific image pixel pattern addressed which in the present example results in buffers 132, 134 each being loaded with a specific four pixel block of image data. At the same time, clock pulse 03 causes the pixel pattern in input buffer 106 to be read into output buffer 118 through data bus 121.
~35398 Output buffers 118, 132, 134 comprise parallel in-serial out buffers. On output pixel clock pul,ses ~4, the pixel image data in buffers 118, 132, 134 is serially unloaded to a suitable output such as a memory (not shown) where the image data, comprising both real and interpolated pixels, may be held pending use as for example by a suitable marking or copying device.
The various buffers of interpoiator circuit 98 may comprise any suitable commercially available buffers.
In the circuit shown, buffers 100, 106, 108, 118, 132, 134 comprise Texas Instruments Model No. 74-195 buffers, and buffers 122, 124 Texas Instruments Model ~lo. 74-175 buffers. Memory 125 comprises Fairchild Inc. R~ Model No.
93-145 chips.
- lla -` 113S398 In the line interpolation arranyement illus~rated in ~igures 5-7, the pixel image output comprises pixels 128 of image data from lineLl, together with positionally equiva-lent pixels 130 of image data for lines Ll-l and Ll-2 taken from memory 125. As described, the image data content of lines Ll-l and Ll-2 is determined by considering the image values of the positional]y equivalent pixels 128 in each of lines Ll, L2. It may, however be desirable when interpo-lating image data for one or more additional lines to base the interpolated image data for the additional line or lines on the image values of one or more pixels outside the posi-tionally equivalent pixels, i.e., on the image values of one or more pixels before and/or after the pixels 128 of lines Ll, L2.
Referring particularly to Figures 9-11, there is shown an example of line interpolation wherein the predicted image pixel patterns for the interpolated line or lines (in the example shown, lines Ll-l and Ll-2) is based upon the image value of both pixels 239 immedia.ely preceeding and succeeding pixels 238, together with the image value of pixels 238. As seen in Figure 11, the exemplary image pixel patterns 227 thereshown each comprise a four pixel block 228 consisting of two pixels for each interpolated line Ll-l and Ll-2.
The memory address for the image pixel patterns 227 comprises an eight pixel address 233 consisting of a block of fo-lr successive pixels from each of adjoining lines Ll, L2, each block of pixels however being made up of additional end pixels 239 and intermediate pixels 238.
The intermediate pixels 238 in the four pixel address block from line Ll also comprises the pixel output portion ~135398 of line Ll. As a result, the pixel output for lines Ll, I.l-l, and Ll-2 comprises intermediate pixels 238 from line Ll and the particular pixel pattern 227 drawn fro~ memory 225 for interpolated lines Ll-l and ~1-2.
In the arrangement shown in Figure 9, image data is received in serial pixel form on a line by line basis from a data source, as described heretofore, and inputted via line delay bufEer 200, data bus 203, and bypass bus 207, to input buffers 206, 208 respectively of the in~.erpolator circuit.
A suitable clock 114' provides input pixel clock pulses 01 " address load control pulses ~2 " output pixel load control pulses 03', and output pixel clock pulses 04'.
The wave form of clock pulses 0i~ 02 ~ 03't 04' for the image processing example described herein is shown in Figure 10.
The image data from line delay buffer 200 and in bypass buffer 207 is clocked into input buffer pair 206, 208 on a block by block basis by input pixel clock 01 " each block being two pixels wide. ClocJc signal ~1 ~ or some other clock signal in synchronism therewith, is also used to clock image data from the data source forward into line delay buf-fer 200 and bypass bus 207.
In the exemplary arrangement shown, input buffers 206, 208 comprise serial in-parallel out buffers, which in the example illustrated, are four bits wide each to provide an eight bit address to address buffers 222, 224 of pixel pattern memory 225.
On address load control pulse ~2 " the content of input buffers 206, 208 is read through data buses 221, 223 into address buffers 222, 224 respectively. Address - . . .. . . ..
' ~ ;
:1135398 buffers 222, 22~, which comprise parallel in-parallel out buffers, address a speci:Eic image bit pattern 227 stored in memory 225, examples of which are shown in Figure 11.
On output pixel load control pulse 03', memory 225 loads, via data buses 229, 231, output buffers 232, 23 with the spccific image pixel pattern addressed which in the present example results in buffers 232, 234 each being loaded with a specific two pixel block of image data. At the same time, clock pulse 03' loads the intermediate pair of pixels in input buEfer 206 into output buffer 218 through data bus 226.
On output pixel clock pulses 04', the pixel image data in buffers 228, 232, 234 is serially unloaded to a suit-able output as described heretofore.
On the succeeding clock pulse 01 ~ two fresh pixels from lines Ll, L2 are loaded into input buffer pair 206, 208 and the foregoing process repeated.
In the line interpolation process of Figures 9-11, the content of the interpolated lines Ll-l and Ll-2 is determined from the image values of the pixels in lines Ll, L2. rrhe portion of lines Ll, L2 looked at for interpolation purposes includes the pair of pixels 238 positionally corres-ponding to the interpolated pixels and a single pi.xel 239 from before and after the pixels 238. It will be understood, however, that the number of pixels 239 looked at may be greater than one and further, that only the pixel(s) before or after the pixels 238 may be looked at. And, while the pixels 238 from lines Ll, L2 and in image pixel patterns 227 are i]lus-trated as bei.ng two pixels wide, the pixel width may range from a low of one pixel to a number greater than the two pixels illus~ra-ted in Figures 9-11.
While in the afo~edescribed arrangements, a pair of intermediate lines (i.e. Ll-l and Ll-2) are interpolated from adjoining pairs, it wi]l be appreciated that the number oE lines interpolated may be as few as one. It will also be understood that the accuracy of the interpolation process decreases with increase in the number of intermediate lines interpolated. ~nd, while interpolation has been described herein using a pair of adjoining lines to predict one or more intermediate lines, the aforedescribed interpolation process may instead employ a single known line as the basis for predicting one or more adjoining lines.
It is understood that the eight pixel address illus-trated, the composition thereof as four pixels from adjacent lines (i.e. lines Ll, L2), and the t~o and four pixel wid~
two line interpolating image patterns stored in memory are exemplary only, and that addresses of various pixel length and composition as well as image patterns of ~arious pi~el length and/or various numbers of interpolated lines may be contemplated instead.
While interpolation of additional pixels 12 may be performed at any point in a data system including the data output station or terminal, since the image data used comprises analog in~age data, preferably such interpolation is performed at the input station. This avoids the ~xpense of storing data in analog form. The image data, which following interpolation is in binary form, may then be stored and/or transmitted. Transmission of the image data from one si~e, i.e. the input station to another site, i.e. an output station, may take place in any suitable manner as known to those skilled ~0 in the facsimile arts for example.
~13S398 .
Line interpolation, which may be performed at any point in a data system including the input station, is pre-ferably performed at the data output station or terminal to reduce data storage needs and transmission bandwidth.
While the invention has been described with refer-ence to the structure disclosed, it is not confined to the details set forth, but is intended to cover such modifications or changes a.s may corne within the scope of the following claims:
Claims (13)
1. In the method of interpolating at least one line of image data from at least one known line of image data, the steps comprising:
a) buffering a block of binary image pixels from said known line of image data to provide an address;
b) addressing a memory having discrete image pixel patterns therewithin with said address to obtain the preset image pixel pattern corresponding to said address;
c) outputting the preset image pixel pattern addressed from said memory to provide a portion of the inter-polated line; and d) repeating steps a, b, and c using additional blocks of image pixels from said known line to complete said interpolated line of image data.
a) buffering a block of binary image pixels from said known line of image data to provide an address;
b) addressing a memory having discrete image pixel patterns therewithin with said address to obtain the preset image pixel pattern corresponding to said address;
c) outputting the preset image pixel pattern addressed from said memory to provide a portion of the inter-polated line; and d) repeating steps a, b, and c using additional blocks of image pixels from said known line to complete said interpolated line of image data.
2. The method according to claim 1 including the step of storing discrete image pixel patterns in memory having a pixel length equal to the pixel length of said address.
3. The method according to claims 1 or 2 including the step of buffering a block of image pixels from said known line having a bit length equal to the bit length ofsaid address.
4. The method according to claim 1 including the step of buffering a predetermined number of binary image pixels from each of two adjoining lines of known image data for use as said address.
5. The method according to claims 1 or 4 including the step of providing in said memory image pixel patterns for producing at least two interpolated lines.
6. The method according to claims 1 or 4 including the step of providing in said memory image pixel patterns for producing at least three interpolated lines.
7. The method according to claim 4 including the step of buffering a block of at least one image pixel from each of said adjoining lines for use as said address.
8. In the method of interpolating at least one intermediate line of image data from each pair of adjoining lines of image data, the steps comprising:
a) buffering at least one binary image pixel from each of said pairs of adjoining lines of image data to provide an address;
b) addressing a memory having-discrete image pixel patterns therewithin with said address to obtain the preset image pixel pattern corresponding to said address;
c) outputting the preset image pixel pattern addressed from said memory to provide a portion of said inter-mediate line; and d) repeating steps a, b, and c using additional image pixels from said pairs of adjoining lines of image data to complete said intermediate line.
a) buffering at least one binary image pixel from each of said pairs of adjoining lines of image data to provide an address;
b) addressing a memory having-discrete image pixel patterns therewithin with said address to obtain the preset image pixel pattern corresponding to said address;
c) outputting the preset image pixel pattern addressed from said memory to provide a portion of said inter-mediate line; and d) repeating steps a, b, and c using additional image pixels from said pairs of adjoining lines of image data to complete said intermediate line.
9. The method according to claim 8 including the step of storing multi-line image pixel patterns in memory,
10. The method according to claim 1 including the step of storing image pixel patterns having a pixel length less than the pixel length of said address.
11. The method according to claim 1 including the step of providing an address comprised of a pixel from said known line positionally corresponding to each pixel of said line of image data to be interpolated together with at least one additional pixel from said known line.
12. The method according to claim 1 including the step of providing an address comprised of a pixel from said known line positionally corresponding to each pixel of said line of image data to be interpolated together with plural additional pixels from said known line, with at least one of said additional pixels preceeding said positionally corresponding pixel.
13. The method according to claim 1 including the step of providing an address in which only a portion of the pixels comprising said address positionally corres-pond to the pixels in said line of image data being inter-polated.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US917,613 | 1978-06-21 | ||
| US05/917,613 US4193092A (en) | 1978-06-21 | 1978-06-21 | Image interpolation system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1135398A true CA1135398A (en) | 1982-11-09 |
Family
ID=25439055
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000324978A Expired CA1135398A (en) | 1978-06-21 | 1979-04-05 | Image interpolation system |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4193092A (en) |
| EP (1) | EP0006351B1 (en) |
| JP (1) | JPS554194A (en) |
| CA (1) | CA1135398A (en) |
| DE (1) | DE2967699D1 (en) |
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| US6002407A (en) | 1997-12-16 | 1999-12-14 | Oak Technology, Inc. | Cache memory and method for use in generating computer graphics texture |
| US6697539B1 (en) | 2000-03-31 | 2004-02-24 | Sharp Laboratories Of America, Inc. | Image scaling by exact 2D implicit polynomials |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US2921124A (en) * | 1956-12-10 | 1960-01-12 | Bell Telephone Labor Inc | Method and apparatus for reducing television bandwidth |
| FR2257183B1 (en) * | 1974-01-04 | 1976-11-26 | Cit Alcatel | FACSIMILE IMAGE TRANSMISSION SYSTEM |
| US4020282A (en) * | 1974-01-14 | 1977-04-26 | General Dynamics Corporation | High density data processing system |
| JPS5185619A (en) * | 1975-01-27 | 1976-07-27 | Nippon Telegraph & Telephone | |
| US4068266A (en) * | 1976-06-03 | 1978-01-10 | Xerox Corporation | Statistical resolution conversion technique |
| US4032977A (en) * | 1976-06-03 | 1977-06-28 | Xerox Corporation | Gray scale interpolation technique |
| DE2640157C2 (en) * | 1976-09-07 | 1982-10-07 | Philips Patentverwaltung Gmbh, 2000 Hamburg | Method and arrangement for redundancy-reducing coding of pictures |
| US4117470A (en) * | 1976-10-08 | 1978-09-26 | Data General Corporation | Data bit compression system |
| GB1567990A (en) * | 1976-10-21 | 1980-05-21 | Western Electric Co | Digital transmission of pictures |
| US4149091A (en) * | 1977-05-02 | 1979-04-10 | Xerox Corporation | Scanning apparatus |
-
1978
- 1978-06-21 US US05/917,613 patent/US4193092A/en not_active Expired - Lifetime
-
1979
- 1979-04-05 CA CA000324978A patent/CA1135398A/en not_active Expired
- 1979-06-13 JP JP7454279A patent/JPS554194A/en active Granted
- 1979-06-14 EP EP79301138A patent/EP0006351B1/en not_active Expired - Lifetime
- 1979-06-14 DE DE7979301138T patent/DE2967699D1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0006351B1 (en) | 1990-08-29 |
| JPS6361826B2 (en) | 1988-11-30 |
| DE2967699D1 (en) | 1990-10-04 |
| US4193092A (en) | 1980-03-11 |
| EP0006351A1 (en) | 1980-01-09 |
| JPS554194A (en) | 1980-01-12 |
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