CA1143820A - Computerized press controls - Google Patents

Abstract

ABSTRACT
A computerized press control includes a set of counters countable in real time as the associated press cylinder rotates to enable the press control system to readjust the inspection zone, wherein the mark to be sensed on the web can be expected to be found, on a per revolution basis of that cylinder and to dynamically alter the length of the inspection window on a per revolution basis to enable the press control system to control color registration in spite of wide variations in press speed or conditions of the web.

Description

SPECIFICATION
The invention pertains to an apparatus for the purpose of monitoring or controlling the register ~f a printing press or cut-off unit.
Devices for controlling the register of printing presses are known from the pr:Lor art. A circumferential control system is disclosed in United States Patent No.
3,949,282~ A lateral register control system is disclosed in llnited States Patent No. 4,135,664.
Additionally, the Gravure-Research Institute has conducted research into the problem of improved control of printing presses and has issued a series of reports dis-closing the results of these research efforts. Report No. M-52, which was presented in November of 1975, deals with the problem of programmed printing press control.
Report No. P-39, which was presented in November of 1974, deals with the problem of monitoring and controlling printing presses by means of a computer system.
Previous attempts at improve~ digital press

2~ controls have either been controls of fairly limited capability such as disclosed in the '644 and '282 patents or have been quite elaborate and expensive digital control systems. There has been a need for an improved control system, which is relatively inexpensive, but which pro-vides improved control and which could be connected into a higher level supervisory apparatus.
The invention comprises an apparatus and a method for monitoring or controlling an associated printing press or cut-off unit where marks printed on the web are to be sensed and compared to a pre-stored set-point;

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The inventive apparatus includes a digital processor with a parallel, bidirectional data bus and a parallel, unidirectional address bus. Read-only memory units, and read/write memory units can communicate with the processor by means of the address and data buses. A
switch input port and a display panel output port are also connected to the address and the data buses. The switch input port provides a means whereby switch settings can be used to establish system control parameters. The display panel output port provides a means where the con-trol system can turn on and off indicator lights to in-form the operator of the status of the unit. A motor control port, also connected to the address bus and data bus, converts an error signal generated by the digital processor into appropriate motor control signals to drive a web or cylinder compensator so as to minimize the magni-tude of the error. A communication port connected to the address bus and the data bus provides a facility whereby the digital processor can communicate with a higher level press monitoring apparatus. A real time data input port including a plurality of counters provides a means whereby encoder signals, generated as the cylinder of the associated press or cut-off unit rotates may be counted, on a real time basis. The counted encoder pulses enable the pro-cessor to determine where, with respect to a givenrevolution of the associated cylinder, a sensed mark on the web is located.
An operator can establish a set-point when the associated printing press or cut-off unit is running with an acceptab:Le register. Once a set-point has been ~38ZV

established, the processor determines, on a per revolution basis, of the associated printing press or cut-off cylinder where the next mark on the web is to be expected.
Having determined where the mark is to be expected, which corresponds to the position, with respect to the cylinder, of the previous mark, a window is established. The window is centered with respect to the expected location of the mark. Signals from the sensor unit at the web, correspond-ing to the latest mark on the web that is being sensed, are enabled during the time interval of the window to inter-rupt the processor. After being interrupted, the pro-cessor determines the location of the sensed mark on the web based on the number of encoder counts in a counter.
This value may be compared to the set-point value and the difference between the two used to establish an error indicator. The error indicator can be used to then drive a compensator motor ~or the purpose of minimizing that error. Alternately, the difference between the set-point and the sensed mark can be merely monitored and trans-mitted to a supervisory system through the communicationsport.
The inventive apparatus recalculates the posi-tion of the window for each revolution of the cylinder of the associated press or cut-off unit. The inventive control system can thus respond to movement of the sensed mark on the we~ due to transient conditions such as speed changes of the press or pasted-oversections of web due to the start o~ a new roll of web material, Additionally, the inventive control system reinitializes the width of the window on a per revolution basis and can dynamically ~38~0 adjust the width of the window Oll a per revolution basis of the associated cylinder. Further, the inventive control can on a per revolution basis transmit data to its associated supervisory control system concerning the performance of the press or cut-off unit which it is monitoring or control-ling. The inventive control system can also receive data from its associa-ted supervisory control system for the purpose of dynamically readjusting its control parameters.
If the inventive control system is operating as a mark-to-mark register control, the two marks being sensed on the web can be located on opposite sides of the cylinder of the associated printing press or cut-off unit.
According to a first broad aspect of the present invention, there is provided a control system for determining the relative location of members of a plurality of marks previously placed on a moving web, with respect to a set-point, the marks are sensed by a web sensor as the web moves in a selected direction across a rotating cylinder, the control system comprising:
means to establish a length of an inspection window, corresponding to a selected amount of cylinder rotation, for each revolution of the cylinder, means to enable the web sensor, starting when a reference mark on the cylinder is at a previously selected point during the present rotation of the cylinder, and for an amount of rotation corresponding to said length of said inspection window; means for determining the location of a sensed mark from said plurality of marks on the web sensed during the time interval when the web sensor is enabled; means for determining a selected point to be used to enable the web sensor during the next revolution of the cylinder;
means for compar;ng the set-point to said determined location of the sensed mark.
According to a second broad aspect of the present invention, there is provided a method to continuously control the location of a plurality of marks on a web, sensed by a web sensor, with respect to a set-point as the web moves in a selected direction across a rotating cylinder comprising the steps of: selecting, for each revolution of the cylinder, an amount of cylinder rotation during which the web will be examined for the presence of a mark; enabling the web sensor at a previously de~ermined cylinder position for the selected amount of cylinder rotation; sensing a mark while the web sensor is enabled; determining the position of the mark sensed while the web sensor is enabled; comparing the position of the sensed mark to the set-point; adjusting a compensation means to minimize any difference between the position of the sensed mark and the set-point; and determining a cylinder position whereat the web sensor is to be enabled on the next revolution of the cylinder, based on the most recently determined location of the sensed mark on the web.
According to a third broad aspect of the present invention, there is provided a method of mark-to-mark register control to control the dif-ference between corresponding members of two pluralities of marks on a web, sensed by first and second web sensors, as compared to the difference between two set-point marks as the web moves in a selected direction across a rotating cylinder comprising the steps of: selecting for each revolution of the cylinder, first and second amounts of cylinder rotation during which the web will be examined for the presence of a mark; enabling the first web sensor at a first, previously determined, cylinder position for the first amount of cylinder rotation; determining the position of a mark, in the first plurality of marXs, sensed while the first sensor is enabled; enabling the second web sensor at a second, previously determined, cylinder position for the second amount of cylinder rotation; determining the position of a mark, in the second plurality of marks sensed while the second sensor is enab:Led; forming a difference between the positions of the two sensed marks; comparing the formed difference in the positions of said two sensed marks to the difference in the positions of the two set-point marks; adjusting a compensation means to minimize any variation ~B

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between the two compared differences; determining firs-t and second cylinder positions where~t the first and second web sensors are to be en~bled on the next revolution of the cylinder, based on the most recently determined locations of the sensed marks on the web.
A plurality of the inventive control systems may be connected together by a means for linking so as to be able to communicate with a remote means for supervision. Each control system may be ordered by the remote means for supervision to either send selected data to the remote means for supervision or received selected data from that remote means for supervision. In this manner, by means of the remote means for supervision, the operation of each member of the plurality of control systems can be monitored and new parameters can be supplied to any member of the plurality of control systems as desired.
The invention will now be described in greater detail with reference to the accompanying drawings, in which:
FIGURE 1 is a control system block diagram.
FIGURES 2A-2G disclose a control system schematic diagram.
FIGURE 3 is a timing diagram disclosing the operation of the com-munications port.
FIGURES 4A and 4B are timing diagrams showing the transmission of the external data bus.
FIGURE 5 is a schematic diagram of the AC motor drive electronics.
FIGURES 6A-6D disclose a schematic diagram of the DC motor drive electronics.
FIGURE 7 is a timing diagram disclosing operation of the conditioning and control circuits.
FIGURE 8 is a schematic diagram illustrating the method of dynamically resetting the inspection ~one for each revolution of the cylinder.
FIGURE 9 is a :Elow diagram of the operation of the control system in 3Q the mark-to-reference mode.
FIGURE 10 is a flow diagram of the control system in the single ~{~ ~ -5a-

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scanner nnark-to-nark mocle.
FIGURE 11 is a flow diagram of the control system in the dual scan-ner mark-to-mark mode.
FIGURE 12 is an over-all flow chart of the control sequence.

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FIG. 13 is a ~low chart o~ the interrupt hand:Ler control sequences.
FIG. 1~ is a flow chart of the monitor ta~k.
FIG. 15 appearing on the same sheet as FIG. 8 is a ~low chart o~ the ~ront panel taFk.
FIG. 16 is a ~low chart of the control task.
FIG. 17 is a flow chart of the scanner interrupt routine.
FIG. 18A is a flow chart of the open window routine.
FIG. 18B is a flow chart of the set window routine.
FIG. 19 appearing on the same sheet as FIG. 17 is a flow chart of the operating system.
FIG. 20 is a flow chart of the initialization routine.
FIG. 21 is a flow chart of the real time clock inter-rupt routine.
FIG. 22 is a schematic of a plug-in multi-digit switch module usable to establish a set-point.
FIG. 23A is a planar frontal view of a display panel for a circumferential control.
FIG. 23B is a planar frontal view of a display panel for a lateral register control.
FIG. 24 is a schematic of the drive electronics connected between the control system of FIG. 2 and either the display panel FIG. 23A or the display panel FIG. 23B to drive the indicator lights.

TABLE_l HEX ADnRESS DEVICE
0000-,07 FF 2716A

.
.

8~) lB00-lFFF 2716D
2000-20FF 8155A ~RAM) 2100-21FF 8155B (RAM) 2200-22FF 5101 (C~OS RAM) 2300 8255 Port A (HIB) 2301 8255 P~rt B "
2302 8255 Port C "
2303 8255 CONTROL "
2406 DISPLAY STRO~E

3A00 AUTOt~AN

4001 8253B COUNTER-l 4003 8253B~MODE

: 8001 8253A COUNTER-l ~003 B253A~B C

TA~LE 2 [DC MOTOR TABLE]

Press Speed G A I N

50 ' RPM<100 14 23 45 90 100 ~ RPM<150 15 28 52 95 150 < RPM<200 17 33 60 100 200 ~ RPM<250 20 38 64 105 10250 < RPM<300 23 43 68 110 , ..
300 < RPM<350 25 46 69 113 350 < RPM<400 28 50 71 117 400 < RPM<450 30 53 77 120 450 < RPM<500 33 57 83 123 15500 < RPM<550 34 ~0 84 124 550 < RPM<600 36 63 86 126 600 < RPM<650 38 66 87 126 650 ~ RPM<700 40 70 88 127 700 < RPM<750 40 72 89 127 20750 < RPM 40 75 90 127 Not by way of limitation but by way of dis-closing the best mode of practicing our invention and by way of enabling one of ordinary skill in the art to practice our invention there are disclosed in Figs. 1 through 24 several different embodiments of our inven- -tion.

. .

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Fig. 1 is a system block diagram of a printing press or cut-off control 5 organized around a digital processor 7. The processor 7 has a parallel, sixteen-bit, address bus ~, and a parallelr eight-bit, data bus 11.
The address bus 9 and the data bus 11 interconnect a read-only memory 13, a read-write memory 15, a switch input ; and real-time clock port 17, a communications port 19 connec.ted to an external, parallel data bus 20, a display panel port 21, a motor control port 23, connected via motor drive electronics 24a to a compensator motor 24b, and a real-time input port 25 which receives real time information from an associated printing press or cut-off apparatus.
The real-time input port 25 receives information signals on lines 27 and 29 from a web scanner A or from a pair of scanners A and B. The scanners are located adja-cent the web at the press or cut-off apparatus. The real-time port 25 also receives a press cylinder reference signal on a line 31, and a pulse stream from a press encoder on a line 33. The signals on the lines 27 through 33 are conditioned by signal conditioning circuits 35, 37, 39~ .
A conditioned press cylinder reference signal on a line 31 provides gating signals to an encoder counter 43, associated with Scanner A and an encoder counter 45, associated with Scanner B. A press cylinder reference signal on the line 35a will force encoder counters 43, 45 to an initial preset count. Conditioned encoder pulses on a line 35b are utili~ed to count down the encoder counters 43, 45, a pair of delay counters 47, 49 for Scan-ner ~ and Sc~nner B, and window counters 51, 53 for Scan-_g_ ner A and Scanner B, respectively.
The conditioning circuit 37 associated with Scanner A provides gating signals on a line 55 which can be utilized to trigger down-counting of the delay counter 47 for Scanner A from a preset value. Similarly, the conditioning circuit 39 associated with Scanner B provides gating signals on a line 57 to initiate down-counting the delay counter ~9 associated with Scanner B from a preset value.
The delay counter 47 associated with Scanner provides gating signals on a line 59 to initiate down counting of the window counter 51 associated with Scanner A from a preset ~alue. The delay counter 59 for Scanner B
provides gating signals on a line 61 to initiate down-I5 counting of the window counter 53 associated with Scanner B
from a preset value.
~ he control system 5 of Fig. l may be utilized to control both circumferential and lateral mark-to-mark register of the image being placed on the web at an adja-cent printing press. The control system 5 can be used tocontrol circumferential mark-to-reference register of the associated web, Additionally, the control system 5 of Fig. 1 can be utilized to control the register at an adjacent cut-of~ station or to continuously monitor the quality of the graphic arts product being produced on an overall basis at a final quality control station. Final-ly the communications port l9 of the control system 5 of Fig. 1 permits that system to be interrogated with respect to the press related parameters which are being measured during each repeat of the graphics art material which is 382~

being laid down by the adjacent press or cut-off input.
This information may be suppl:ied to a supervisory system which is connected to the comrnunications port 19 via the external communications bus 20.

CONTROL SYSTEM ELECTRONICS
. . .
Fig. 2 is a detailed electronic schem~tic of the control system 5 shown in block diagram form in Fig. 1.
Fig. 2 includes sheets Fig. 2A-2G which can be assembled as indicated to form a complete schematic. In Fig. 2 the processor 7, which in the exemplary system is an Intel - 8085A type processor is shown connected to the data bus 11.
The data bus 11 is a parallel eight-bit bidirectional data bus. In the case of the exemplary system of Fig. 2 the eight-bit parallel data bus 11 is shown connected to data bits D0 to D7 of the processor 7. The address bus 9 of Fig. 1 is shown in two parts 9a, 9b in Fig. 2. Section 9a is generated through an eight-bit parallel D-type latch 63 which is enabled by a timing control line 65 when the processor 7 puts Address Bits 0 through 7 out on the same eight pins as are used to provide signals for the data bus 11. The second section 9b of the address bus 9 which represents the higher order eight-bits of the address is brought out on a separate set of lines from the processor 7.
Connected to the data bus 11 and the address bus 9 of the processor 7 in Fig. 2 is the read-only memory 13.
The read-only memory 13 comprises a series of programmed read-only memories ~PROMS] each of which is 2048 words long by eight-bits wide. Each of the memories 67, 69 could A~ 30 be~Intel 2716 type read-only memory. Other types of plug ~r~aol~rf ar~ -11-3~20 compatible read-only memories can ~lso be used. Addition-al address and control signals are brought into the memories 67, 69 through a series of address and control lines 71. Additional read-only memory modules 70a, 70b can be added to expand the control storage to 8k, eight-bit words. Stored in the read-only memory chips 67, 69 and unalterable by the processor 7 is a predetermined control sequence of binary ones and zeroes.
The read-write memory 15 in Fig. 1 is shown in lo Fig. 2 as a pair of 256 word by ~our-bit random access memories 73, 75. The memories 73, 75 operate in parallel and provide 256 bytes of read-write storage. Each of the memories 73, 75 is connected to the data bus 11 and the lower order part 9a of the address bus. A set of additional control lines 77a, 77b is associated with each of the memories 73, 75. The memories 73, 75 are shown in Fig. 2B
as~Intel type SlOlL-l Memories. Any other compatible read-write memory type could also be used. The read-write memories 73,75 are used to store various parameters of the control system 5 which might be changed from time to time.
Additionally, a circuit 15 is associated with the two memories 73, 75. The circuit 15 includes a 3.4 volt lithium battery 81a, a filter capacitor 81b, and two diodes 81c and d. The purpose of the circuit 15 is to provide a source of fail-safe ~oltage to retain the state of the volatile memories 73, 75 in case the system power supply, represented schematical-ly at 83, is turned off or for some other reason p~wer fails. In this instance, the diode 81d would decouple the circuit 15 from the failed power supply 83 and the battery 81a would continue to provide a supply ~ f~e~ k -12-3~3~0 of DC power to the memories 73, 75 insuring that their contents remain intact. This iS a particularly important feature in those cases where it is for so~e reason desirable to shut down contro] system 5 and then bring it back up with exactly the same set of parameters and in exactly the same condition it was in at the time it was shut down.
The switch input and real time clock port 17 of Fig. 1 is shown in Fig. 2B as comprising an ~ntel type 8155 input/output port 85. Dip switches 87, 89 and switch cable connectors 91 with associated header 92 provide a source of switch inputs to the port 85. The input/output port 85 is used exclusively as an input port to receive information from the digital input switch modules 87, 89 and the set of lines 91 which are connected to what is effectively a set of five switches on the operator panel of the control system 5~ Connected to the input port 85 in parallel with the lines 91 is the header or cable connec-tor 92 which would permit an additional source of signals to be connected in parallel with the five lines 91 for maintenance or test purposes. The settings of the switches 87, 89 are determined by the control system in-staller and represent a default set of parameters which are initially read each time the control system has power applied to it. The bits which can be set by the switch 87 correspond to:
1) The Advance - retard offset value associated with each sensed depression of the advance-retard rocker switch on the operator panel.
2) The Error zone of the system.

v 3) The Dead zone of the system.

4) The system Gain.
The bits which can be set by the switch 89 correspond to:
1) Number of avera~es to be used in calculating error signal to be sent to the press compen-sator.
~) The control mode, circumferential mark-to-reference, mark-to-mark or lateral.
3) Web color.
4) Edge or center. Scanning Mode.

5) Width of the Window.

6) The number of encoder pulses/revolution of the press cylinder.
Additionally, the input port 85 includes a four-teen bit down counter which is utilized by the control system 5 as a real time clock. The real time clock within the input port 85 generates an interrupt on a line 93 (See Fig. 2C) every ten milliseconds. The line 93 is connected to a vectored interrupt RST 7.5 of the processor 7. The value which is set into the fourteen bit down counter in the input port 85 is determined by the system control sequence which is hardwired into the PROMS 67 through 69.
A down-counting clock signal is provided to the clock on the input port chip 85 by a flip-flop 94a (See Fig. 2C) which is connected to the clock-out signal line of the processor 7. In addition to the eight bit bidirectional data bus 11 which is connected to the input port 85 for the purpose of receiving signals from either the port ~, port B
or the port C of the 8155 chip a group of control signals 95 is also provided to the input port 85.

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The communications port 19 of Fig. 1 is shown is Fig. 2D as comprising an input/output port 100, an Intel type 8255 chip, a six bit comparator 102, National type 8136, a set of address switches 104 which establish àn address of the control system 5 with respect to the external data bus 20, an eight bit buffer chip 106 type 74LS244, a set of eight differential driver receiver circuit~ 108, type 75117, which buffer the eight bit parallel data section 20a of the external data bus 20, a set of three additional line driver receiver elements 110 through 114, type 75117, which buffer the command lines 20b for the external data bus 20, the four-bit counter elements 116, 118, type 74LS393, two D-~lip-flop elements 120, 122, type SN74LS74, a set o~ inverters 124 through 132, type SN74LS04, a set of NOR gates 134 through 140, type SN74LS02, a set of NAND gates 142 through 148, type SN74LS00, and an AND gate 150, type SN74LS08. The detailed operation of the communications port 19 will be discussed subsequently.
The display panel port 21 o~ Fig. 1 is shown in Figs. 2D and 2E as a set of twelve lines, eight data lines 160 and four control lines 162 which are connected to selected lights on the display panel.
The motor control port 23 of Fig. 1, shown in Fig. 2E comprises an Intel 8155 type input/output port chip 164 which is connected to the data bus 11 and which also is connected to a group of control lines 166, The input/output port chip 164 has an eight-bit parallel output Port A to which is connected the set ~f data lines 3G 160 (Fig~ 2E) which is in turn connected to the display panel to specify which light or indicator is to be ener-2~ r~e~a~^k ~14~320 gized. A second bus 162 (Fig. 2D) specifies which of the columns of lights at the display panel is to be illuminated and also includes a strobe line 162a to be used by the display panel electronics.
The control system 5 can use as the compensator motor 24b either a DC or an AC motor. The DC ~rive output will be described first. The input/output port chip 164 includes a Port B with a seven-bit parallel output bus 168 which is connected to a digital to an~log converter 170, Y ~ 10 a ~Motorola chip type MC1408. The output Port B provides seven bits of magnitude on the bus 168 to the digital to analog converter 170. The digital magnitude is converted to an error volta~e in an operational amplifier 172, buf-fered in a second operational amplifier 174, and divided so as to provide a differential DC drive signal in a pair of operational amplifiers 176, 178. A series of resistor elements 171 provides feedback and biasing for the opera-tional amplifiers 172-178. The operational amplifiers 176, 178 provide differential drive for a DC motor on a pair of lines 180. The lines 180 are connected to a DC motor drive circuit. The DC motor can, in turn, be connected to a web compensator or a cylinder compensator on the associated press. Polarity information is broughtouton a line lB2 which is also connected through Port B of the input/output port chip 164. The signal on line 182 is inverted by the element 183 and buffered by the element 183b.
A second source of output to drive an AC motor is provided from the input/output chip 164 by a pair of D-flip-flops 184, 186, type SN74LS74, a Schmitt Trigger gate ~o 194, and a set of open collector NAND gates 188, 190, type SN74LS38.
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A 120-Hertz clock input signal is applied on a line 196 to the gate 194. A pair of output lines 198, 200 provide switching signals to an AC motor control circuit. By means of triggering a pair of triacs from the si~nals on the lines 198, 200, an AC synchronous motor may be stepped a number of pulses corresponding to the count loaded into the down counter of the input/
output port chip 164. Each pulse on the line 196 causes the AC motor to move, in a selected direction, one step and also counts down the motor displacement count in the output chip 164. Polarity is again dictated by the value of the signal on the line 182. As in the case of the DC
motor, the AC motor may be connected to a web compensator or to a cylinder compensator.
A set of circuits 202 receives inputs on a pair of lines 204, 206 from the tachometer of the associated DC ~otor and provides outputs on a pair of lines 208 which contain directional feedback information. The lines 208 can be sensed through a Port C of the input/output port 164. The feedback in~ormation on the lines 208 can be examined by the digital processor 7 and can, in turn, be used to drive the display panel to indicate the direction that the DC drive motor is turning.
The circuit 5 includes an auto/manual flip-flop 210 (~ig. 2F) which is set and/or reset through an auto/
manual switch on the display panel. Additionally, there is a one-shot 212 (Fig. 2E) type 9602, which is triggered by the proc~ssor 7 on a line 214 each time there is a real time clock interrupt. If the one-shot 212 has been trig-gered and if the flip-flop 210 is set in the auto position, ; ,~

~382~:) a gate 215 will drive an optically coupled diode-transistor combination 216 to cause the transistor 216 to conduct which is, in turn connected to an auto relay circuit in the motor drive electronics to permit the contr~l system 5 to run the compensator motor.
The conditioning circuits 35 o~ Fig. 1 are shown in Fig. 2G as a 75115 dual differential receiver circuit.
Differential reference signals are received on the lines 31 and differential encoder pulses are received on the lines 33 by the conditioning circuits 35.
The conditioning and control circuits 37 of Fig. 1 are shown in Fig. 2G and include a potentiometer 220, opera-tion amplifiers 222, 224, transistors 226 through 230, a Schmitt tr~gger 232, a series of resistors 233 through 252, a series of diodes 254 through 258, a series of capa-citors 260 through 262, a gate 264, an inverter 266 and a pair of flip-flops 268 and 270. The conditioning and control circuits 39 are identical to the conditioning and control circuits 37.
The real time counters 43 through 53 of Fig. 1 are shown in Fig. 2F as a pair of counter chips 280, 282.
Each of the chips 280, 282 is an 8753 Intel type chip which includes three down counters. The 280 chip includes the encoder counter 43 for Scanner A, the encoder counter 45 for Scanner B, and the window counter 51 for Scanner A.
The chip 282 includes the delay counter 47 for Scanner A, the delay counter 49 for Scanner B, and the window counter 53 for Scanner B~
The control circuit 5 as shown in Fig. 2 also includes a set of three address decode elements 290 through 294, Each of the elements 290 through 294 is connected to Z~

selected members oE the adclress lines in the higher order portion 9b oE the address bus 9. I'he decoder chips 290-294 generate decoded address signals to be utilized by the remainder of the control circuitry in the con-trol 5.
Each of the chips 290 through 294 is an SN74LS138 type chip. Additional ~ates 296 through 30~ are connected to the processor 7 and the address decoder chip 294 to further decode addresses placed on the address bus 9 by the processor 7. ~ates 300-304 provide decoded address signals for the strobe line 162a.
Table I lists a sample set of de~ice addresses. A
power fail interrupt is available through a one-shot 306 which detects a power failure and which generates a trap signal which can be sensed by the processor 7.
The processor 7 requires a selected source of clock signals which is shown in Fig. 2. It will be under-stood that the various electronic elements of Fig. 2 require one or more sources of power to operate properlyO These sources of power are frequently indicated on Fig. 2 in a conventional fashion. Where no power indication is shown with respect to a given element, such as the Auto-Manual flip-flop 210, it will be understood that the power required to operate that chip properly, as specified by the manu-facturer is to be provided.
OPERATION OF THE CO~MUNICATIONS PORT 19 The communications port 19 of the control system 5 provides a facility whereby the control system 5 can communicate with and receive information from other units.
In particular, the external data and control line bus 20 may be connected to a master unit which has a communications port which is comparable in structure to the port 19.

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When the communications port 19 is in a quiescent, or a non-active state, a remote processor or a master con-trol unit can be caused to apply an eight-bit byte of data to the parallel external data bus 20a and a signal to the command valid line, CMV, of the control signal bus 2Ob.
The byte of eight-bit parallel data includes a two-bit command code and a six-bit device address. The byte is sensed by the differential driver chips 108, passed through the tri-state buffer devices 106, and appears at an internal data bus 20c.
If the upper six bits of the eight-bit data word, the address portion, on the bus 20c correspond to the setting of the switches 104, the six-bit comparator 102 senses this equality and generates a signal on a line 102a which is one input to the NAND gate 144. A second input to the NAND gate 144 on a line 114a comes from the dif-ferential line driver and receiver 114 which sense the signal on the CMV line from the remote control unit. The high signals on the lines 102a and 114a generate a downgoing signal on an output line 144a of the NAND gate 144. The downgoing signal on the line 144a strobes the eight bits on the bus 20c into the port B of the input/output chip 100.
The operation of strobing the eight bits of data from the parallel data bus 20c into the port B of the chip 100, generates an interrupt on line lOOa which is connected to the interrupt input INT of the processor 7.
The process of strobing data into the port B
of the input chip 100 is the only action which generates the INT interrupt signal to the processor 7. In response to that signal, the processor is trapped to the location 38 ~EX and reads the data in port s of the input chip 100 which corxesponds to reading the data at HEX address 2301.
Upon receipt of the eight bits of data from the port B, the processor exa~ines at the two ~east signifi-cant bits, bits 0, 1, which can have one of the four states:
00, 01 (listen command), 10 ~talk command), 11. The commands 00, 11 are not used.
The listen mode corresponds to the control system 5 being ordered to receive data from the external bus 20a.
The talk command re~uires the control system 5 to supply data to the remote processor on the external bus 20a.
If the processor 7 determines that a listen command has been issued, it will enter the listen mode and prepare to receive two bytes of data from the external data bus 20a. Immediately upon receipt of the listen command, the processor 7 will address the location 3800 HEX. This produces a downgoing signal on a line 124a which clears the four-bit counter 116. So long as the most significant bit, the D-bit, of the four-bit counter 116 is reset ! clock pulses on a line 134a are permitted to pass through the NOR gate 134 and count the counter 116. When ; the C-bit of the counter 116 goes high, the gate 130 provides an outgoing signal to the differential driver 110 generating an acknowledge (ACK) signal on the ACK line of the control bus 20b, The outgoing differential driver 110 is enabled whenever the flip-flop 120 is set by an upgoing signal from the B-bit of the counter 116.
~ig. 3 is a timing diagram which shows the counting sequence of the flip-flops Ar B, ~, D in the four-bit counter 116, the flip-flop 120 and the related genera-~L3~ZV

tion of the acknowledge signal on the ACK line by the differential transmitt~r 110.
The remote processor then puts the first o~
the two bytes of data expectecl by the local processor 7 onto the parallel data bus 20a. Simultaneously, it sup-plies a data valid signal on the command line DAV. The data valid signal on the line DAV is sensed by the differ-ential receiver 112 which is enabled normally, passed through the NAND gate 146 as the D-bit of the four-bit counter 118 is normally in a high state, passed through the AND gate 150 and used to strobe the port A of the input chip 100.
The eight bits of data on the bus 20a have concurrently passed through the buffer circuits 106 and appear in para-llel on the bus 20c. The processor 7 has been polling the chip 100 and when it senses that its input buffer full flag has been set due to the fact that the port A has been strobed, it will read the port A by reading the address 2300 HEX which will gate the eight bits in the port A onto the eight-bit data bus 11 and into the processor 7. Having received the first of the two expected bytes of data, the processor 7 again readsthe address 3800 HEX which generates a second signal on the ACK line to the remote processor.
The remote processor places the second byte on the external data bus lines 20a along with a second data available signal on the DAV lines which again strobes the port A.
The processor again reads the second of the two expected bytes of data and generates a signal on the ACK line to complete the incoming data transfer. At this point, the processor 7 reverts to its standby state of listening again.

The data receipt sequence is summarized in Fig. ~A, Signals generated by a remote unit are identL~ied with a capital "M". Signals generatecl by the control unit 5 are identified with a label "C5". The "COMMAND" byte from the remote unit is followed by two data bytes from the remote unit. In the instance where the command code detected by the processor 7 is a "talk" or transmit code, each byte of data to be transferred is written to HEX
location 2300 which corresponds to port A of the input/
output port chip 100. When port A of the chip 100 is loaded, ; a line 142a connected to one input of the gate 142 has a low signal thereon. The processor 7 then generates a 3900 HEX address which corresponds to generating a downgoing signal on a line 126a which provides an input to the inver-ter 126 which clears the four-bit counter 118. Immediately thereafter, the clock signal on a line 136a starts counting the counter 118. As shown in Fig. 3, a data available signal, DAV is generated during a time interval where the C-bit of the 118 counter is low and when the B-bit of that same counter is hi~h. Simultaneously, since the D-bit of the 118 counter is low, the gate 142 is enabled which outputs a high signal on a line 142b disabling the buffer chip 106 and the data on the bus 20c is transmitted through the differential drivers 108 to the external data bus 20a during the time interval that the differential drivers 108 are enabled through the buffer 132, which corresponds to the time interval when ~he flip-flop 122 is set.
When the remote processor senses the data avail-able signal on the DAV lines, it generates an acknowledge signal on the ACK line which is transmitted through the differential receiver 110, the gate 148, which is enabled .. .' ' :
.

due to the fact that the counter 116 is in its quiescent state with the D-bit high, through the gate 150 to strobe the A port of the chip 100. The local processor 7 con-tinually poles the input buf~er flag on Port A of the input/output chip 100, and upon sensing the port A having been strobe~, the local processor 7 outputs the next byte of data using the above disclosed sequence.
~utgoing data transmissions to the bus 20 can be as long as required by the local processor 7. The data transmit sequence is shown in Fig. 4B. The "COMM~ND"
byte from the remote unit, is followed by two bytes of data from the control unit 5.
The six-bit address code, corresponding to bits 2 through 7 of the external data bus 20a permits a total of 64 different press control units to be connected to the external bus 2Oa. Each of the press control units, corresponding to the press control unit 5, has its own unique address code set by the switches 104~ Any press control unit 5 may be taken off line by use of a switch 104a which blocks the comparator 102 from ever sensing an address on the six bits of the bus 20c corresponding to the switches 104.
It should be noted that the above described ` communications protocol reql~ires that whenever a unit strobes a control line, the DA~ line or the CMV line, it waits for a command response to the ACK line from the other unit on the bus before proceeding.
MOTOR DRIVE ELECTRONI`CS
~n AC motor may be used as the compensator 24b in the press control system 5 of Fig. 2 to minimize the w24-3~3Z(3 press error. Fig. 5 shows one exemplary AC motor drive circuit. It has been found that a synchronous Slo-Syn motor may be pulsed much like a stepping motor to produce the desired incremental number of steps.
The motor drive circuitry of Fig. 5 includes a transformer 320 with a primar~ and with a center tapped secondary, photodiodes 322, 324 which are optically coupled to phototransistors 326, 328, rectifier diodes 330, 332, optically triggerable silicon controlled rectifiers 334, 336 which are optically coupled to photodiodes 338, 340, bidirectional driver silicon controlled rectifiers (TRIACs) 334a, 336a, a motor enabling relay Kl, a relay energizing transistor 342, along with biasing and current limiting resistors 344 through 364.
The transformer 320 has its primar~ connected across a source of 60 Hertz AC voltage and has its secondary wired to the diodes 3Z2, 324, 330 and 332 to form a recti-fier. The photodiodes 322, 324 alternately cause the associated phototransistors 326, 328 to conduct, thereby generating a 120 Hertz signal on the line 196 of Fig. 5 which is fed back to the corresponding line on the sheet Fig. 2E. The rectified AC signal on the line 370 is applied through the resistors 350 and 354 to the anodes of the photo silicon controlled rectifiers 334, 336. The cathode of one of the corresponding photodiodes 338, 340 connected to the lines 198, 200 respectively is grounded in synchron:ism with the voltage on the line 370 at a 120-Hertz rate. The line which is grounded is selected based on the polarity set at the line 182 and the gate 183a which enables one of the gates 188, 190. Thus, depending on which gate 188, 190 of Fig. 2E is enabled, that grounded zo signal on the line 198 or the line 200 causes the associa-ted photodiodes 338, 340 to conduct. The associated photo silicon controlled rectifier 334, 336 is also caused to conduct which in turn triggers an associated driving TRIAC 334a and 336a. Depending on which of the TRIACs 334a, 336a is triggered, if the relay coil Kl has been energized the Slo-Syn synchronous motor will rotate either clockwise or counterclockwise.
The relay coil Kl is energized through the transistor 342 via the line 218 from Fig~ 2E. So long as the transistor 34~ conducts due to the ~act that the line 217 from Fig. 2E is high, the relay coil Xl will be ener-gized and will cause the Kl relay contacts of E'ig. 3 to assume the energized position which is just opposite to the position shown in Fig. 5. A press go-down contact Gl is also shown in Fig. 3 which can force the relay coil Kl to become deenergized, thereby disconnecting the Slo-Syn synchronous motor from the control system 5.
The display panel advance retard switch is shown in Fig. 5 connected through the contacts of the relay Kl such that if the Kl relay coil is not energized the operator will be able to directly control the compensator motor 24b.
DC MOTOR DRIVE ELECTRONICS
An alternate form of the motor drive electronics 24~ is shown in Fig. 6. The motor drive electronics of Fig. 6 represents a velocity control system for use where the motor 24b is a DC motor.
The motor drive electronics of Fig. 6 includes a pair of power transformers 400, 402, a pair of pulse ~3~0 transformers 404, 406, bridge rectifiers 408 through 412, silicon controlled rectifiers (SCR) 414 and 416, voltage regulators 418 through 424, transistors 426 through 444, optically coupled light emitting diode-transistor pairs 446, 448, operational amplifiers 450 through 464, diodes 466 through 476, a transient suppressor 478, capacitors 480a through 480t, resistors 484a through 488u, potentiome-ters 490a through 490c and light emitting diodes 492, 493.
The motor drive circuitry of Fig. 6 provides a relatively constant field voltage to the motor 24b. ~C
input powér is supplied at a pair o~ terminals 495. The AC input power is rectified in the bridge rectifier 408 and fed through a fuse Fl to the field F2 of the motor 24b.
With current flowing in the field F2 of the motor 24b, the transistor 426 will conduct due to bias from the diodes 466, 467. ~ith the transistor 426 conducting, the light emitting diode 446a will conduct and will emit light which is sensed at the base of its corresponding photo-transistor 446b. Before a signal can be generated at the armature of the motor 24b, it is necessary that there be a field cur-rent flowing. The resistors 484a, b limit the current that flows in the diode 446a. The element 478 is a transient suppressor which limits any transients generated by the field F2.
A phase variable, half-wave rectified alternating signal is generated and supplied to the armature of the DC
motor 24b. Once of the SCRIs 414, 416 is selectively turned on to produce either a clockwise or a counterclock-wise rotation of the armature of the motor 24b. The selected SCR 414, 416 is synchronized with the phase of the AC input power. Synchronization i5 provided by the transistors 428-434.
The power and isolation transformer 400 provides power to the bridge rectifier 410 which in combination with the resistor 484e and the capacitor 480a forms a floating power supply which is not connected to the DC co~mon at the line 496. A full wave rectifier including the diodes 468, 469 generates a series of 120 ~z pulses on the line 497.
The 120 Hz pulses on the line 497 are coupled through the switching transistors 428, 430. The output of the tran-sistor 430 continually restarts a ~iller integrator with an emitter-follower output which includes the transistors 432, 434. The output of the Miller integrator circuit at the emitter of the transistor 434 is a 120 Hz saw-tooth wave form which has approximately 1 17 volt variation in the ramp voltage. This 17 volt, 120 Hz ramp signal is used to synchronize the two comparators 452, 454 with the phase of the AC input on the lines 495. The potentiometer 490b provides a low end adjustment to the ramp.
The operational amplifier 450 and its associated circuitry form a 1 kHz oscillator which generates 1 kHz, 0 to 5 volt pulse train on a line 498 when the photo transistor 446b is enabled, due to the field current. The line 498 is connected to the strobe input o~ each of the comparators 452, 454. The comparators 452, 454 are enabled whenever there is a pulse on the line 498.
The more positive output from the Miller integra-tor circuit, at the junction of the resistors 484k and 4841 is connected by a line 499a to the negative side of the operational amplifier 452. The more negative side of the ~3t32~) output of the integrator-type circuit is connected by a line 499b to the positive input of the operational ampli-fier 454. Velocity error signals on a line 499c are con-nected to the positive input of the operational amplifier 452 and the negative input of the operational amplifier 454. Based on the results of the comparison at the operational amplifiers 452 and 454 either the comparator 452 or the comparator 454 attempts to go high. When strobed at the line 498, the comparator 452 or 454 generates a string of 1 kHz pulses, synchronized with the phase of the AC input voltage.
The synchronized pulse train on llne 452a or 454a causes either the transistor 436 or 438 to switch at a 1 kHz rate. The primary of the pulse transformer 404a or 406a thus has a repetitive pulse generated across it which in turn is coupled to the secondary 404b, 406b of the associated transformer to trigger the appropriate SCR 414, 416. Depending on which of the two SCRs 414, 416 is turned on, the armature of the motor 24b will turn either one direction or the other.
The resistor 484d and the capacitor 480s limit the application of high speed transients to the two SCR's 414, 416-to prevent spurious turn on.
Tachometer feedback from the DC motor 24b, which has a built-in tachometer associated with it, is brought into the servo-electronics 24a along a pair of lines Tl and T2. The resistors 486i through 4861, the potentiometer 490c and the capacitors 480q, 480r ~orm a summing point where the input tachometer feedback from the lines Tl, T2 is algebraically added to the input velocity signals coming from either the advance/retard switch at the display panel or from the operational amplifiers 176, 178 along the lines 180 of Fig. 2. If the control system 5 is running in the automatic mode, the relay RY is energized and the relay contacts Ry are switched from their quiescent state.
In the automatic mode, the differential analog voltage on the lines 180 can be summed with the tachometer eedback on the lines Tl and T2. If on the other hand, the control system 5 is operating in the manual mode, a voltage from the advance/retard switch at the front panel corresponding to the switch being moved to the advance or retard condition, is summed with the tachometer feedback on the lines Tl, T2.
The tachometer feedback signal is a particularly noisy signal. The capacitors 480O and 480p are used to provide some filtering of the summed error signal. The operational amplifiers 456, 458 are connected as high impedance amplifiers with differential inputs so as to not load the tachometer feedback signal on the lines Tl and T2. Additionally, the operational amplifiers 456, 458 have a high common mode rejection ratio so as to minimize tachometer noise. The operational amplifier 460 is connected as an inverter. The two output operational amplifiers 4~2, 4~4 operate as comparators. One of the comparators 462, 464 will provide drive current to its associa~d_output transistor 440, 442 depending on which direction the DC motor 24b is actually rotating.
If one of the transistors 440 or 442 is conductin~, its associated l:ight emitting diode 492, 493 is also conducting and will be emitting light. The emitters of the transistors ZV

440, 442 are connected by the lines 204, 206 to the optically coupled diode-transistor pairs 202 of Fig. 2.
The signals on the lines 204, 206 provide a low voltage corresponding to the dlrection of rotation of the armature of the motor 24b. This low voltage enables the correspond-ing light emitting diode of the diode-transistor pairs 202 to conduct and provides a signal which can be sensed at the input port C of the input port element 164.
In order to activate the automatic/manual relay coil RY shown in Fig. 16, the emitter of the photo-transistor 216 in Fig. 2 is grounded and a signal is brought from the collector of the transistor and connected at the line 218a of Fig. 16. When the line 218a is grounded, the light emitting diode 448a conducts and emits light which causes the photo transistor 448b to conduct. The transistors 448b and 444 are connected as a Darlington pair. When the transistor 448b conducts, the transistor 444 conducts.
In this case, the reIay coil RY has a voltage of approxi-mately V volts applied across it, thereby energizing the relay. In this condition, with the coil RY energized, the associated relay contacts are switched so that the servo system of Fig. ~ receives differential analog signals on the lines 180 from the control system of Fig. 2.
A series of voltages is generated by the regula-tors 418 through 424. The regulators 418-424 are powered by the power transformer 402 whose output is rectified by the diodes 470, 471 and the bridge rectifier 412. The transformer 402 may be set for 110 or 220 volt operation by adjusting the jumpers 402a. The transformer 400 may be set for 110 or 220 volt operation by adjusting the jumpers 400a.

It should be noted that the conditioned tachometer feedback signals on the lines 204, 206 provide a signal to the control system 5 which indicates actual rotation of the output shaft of the compensator motor 24b. This signal is sensed by the processor 7 and used to enable turning on lights at the operator display panel through the display panel port 21.
OPER~TION OF CONDITIONING AND CONTROL CIRCUITS 37 .
The operation of the conditioning and control 10 circuits 37 will be described with respect to the timing diagram shown in Fig. 7. In Fig. 7, the topmost waveform represents a scanner input on the line 27 from Scanner A
to the conditioning and control circuits 37. The waveform shown at the top of Fig. 7 represents an input from a scanner where a black mark on a light web has been sensed.
The second waveform on Fig. 7 is the inverted and ampli-fied output of the operational amplifier 222. The third waVeform on Fig. 7 is the inverted output from the opera-tional amplifier 224. The output from the operational amplifier 224 has the same polarity as does the signal on the scanner input line 27. The fourth waveform on Fig. 7 is the signal at the collector of the transistor 228. This signal swings between positive five volts and ground. The th waveform on Fig. 7 is an inverted signal which is seen 2~ at the collector of transistor 230. The sixth waveform on Fig. 7 corresponds to the ~owngoing signal at the collector of transistor 228 after that signal has been differentiated.
The seventh waveform on Fig. 7 corresponds to the down-going signal at the collector of the transistor 230 after that signal has been differentiated. The eighth waveform x3~

on Fig. 7 represen~s a pair of positive going pulses at the output of the gate 232~ Each positive going pulse corresponds to either a leading edge or a trailing edge of the scanner input on the line 27.
Waveform number 9 on Fig. 7 is a downgoing signal from the negated side of ~lip-flop 268. Flip-~lop 268 i~ the "Mark Sensed" flip-flop and is set each time a pulse appears at the output of the gate 232, provided that the pulse has occurred during the window or inspection zone for Scanner ~. Waveform number 10 is the asserted output of the "Mark Sensed" flip-flop 268.
During the time interval which corresponds to the window or inspection zone, the input on a line 51a the output of the window counter 51 for Scanner A, to the inver-ter 266 will be low or approximately zero volts. The output of the gate 266 on a line 266a will be high. The signal on the line 266a is connected as one of the inputs to the gate 264. The other input to the gate 264 is connected to the output from the Schmitt Trigger gate 232. Thus, the leading or trailing edge pulses generated at the output of the gate 232 are ANDED with the presence of the inspection zone.
When there is a pulse at the output of the gate 232 during the inspection zone interval, the gate 264 is enabled and clocks the input to the flip-flop 26~. When the flip-flop 268 is set, an interrupt is generated at the interrupt line RST 6.5 corresponding to the Scanner A interrupt by the line 268b.
The operation of the conditioning and control circuits 39 associated with the Scanner B are exactly the sa~e as previously discussed for the conditioning and con-trol Gircuits 37.

32~

OPERATION OF REAL TIME -COUNTERS 43 T~IROUGH 53 The encoder counter 43 associated with Scanner A
and the encoder counter 45 associated with Scanner B which are located in the chip 280, are always counted down from a maximum number of encoder counts per revolution of the associated cylinder, either 20000 or 40000. The encoder counter 43 and the encoder counter 45 are each set to a maximum number of counter per revolution 20000 or 40000 each time a reference signal is sensed on the line 31.
During a revolution of the associated press cylinder the counters 43, 45 are counted from their maximum value down to 0. At the end of the current revolution of the press cylinder they are reset to their maximum value and again counted down. If only one scanner, Scanner A is being used, encoder counter 45 does not perform any function. The delay counter 47 associated with Scanner A and which is implemented on the chip 2~2 in Fig. 2 is gated to start counting from a preset count down to ~ by a pulse trans-mitted through the gate 265. Whenever the flip-flop 268 has been set, corresponding to a mark having been sensed dur1ng a window or an inspection zone, a downgoing signal is transmitted along a line 268a, through the gate 265 and to a gate input of the counter 47 triggering the down count-ing of that counter The counter 47 is counted down by clock pulses on the line 47 from the press encoder. When the dèlay counter 47 associated with the Scanner A has counted to 3, it generates the signal on the line 59 which g~tes the window counter 51 associated with the Scanner A.
The window counter 51 is always present to the number of counts corresponding to the length of the inspection zone 1~4~8~0 or the inspection win~ow. The window counter 51 once gated on is counted down to 0 by the encoder pulses on the line 35b. An output signal on the line 51a from the win-dow counter 51 is coupled through the inverter 266 and provides one input to the gate 264. During the time inter-val when the window counter 51 associated with Scanner A
is being counted to 0, the siqnal on the line 51a is essentially at Q volts. The output of the inverter 266 is thus high and the signal on the line 266a enab~es the gate 264. Additionally, the high signal on the line 266a can be supplied through an inverter 266b to provide a window signal to a lateral control circuit corresponding to the control circuit of Fig. 2.
A typical se~uence o~ operation associatable with the encoder counter 43, the delay counter 47, the window counter 51 and the digital processor 7 would include the following steps: at a selected period of time, the window counter 51 associated with the Scanner A is gated and it starts counting down from its maximum count towards 0.
The process of gating the window counter 51 outputs a low signal on the line 51a, which is coupled through the inverter 266 and connected by the line 266a to the gate 264. The gate 264 is enabled by the high signal on the line 266a. The next mark is sensed to generate a positive going pulse at the output of the Schmitt trigger gate 232.
This positive going pulse will be coupled through the gate 264 and will clock the flip-flop 268. When the flip-flop 268 is clocked, it is set and applies an upward going signal to the interrupt applying RST 6.5 of the processor 7.
The inner applying RST 6.5 is associated with an interrupt having been generated by Scanner A. Simultaneously, ~3~3~0 on the line 268a, the flip-flop 268 will apply a low going signal which is transmitted to the gate ~65 and which triggers the delay counter 47 associated with Scanner A. The delay counter ~7 had previously been preset to a specified num~er. The processor 7 in responding to interrupt from the Scanner A puts out an address on the higher order half of the addre;;s bus 9b with the bits A14 and A15 set to a "ONE". The bit A14 set to a "ONE" is coupled through a line 295a to an inverter 296a and to the ~ip select line input of the chip 282. Simultaneously, the output bit on the line A15 is coupled throu~h a line 295b through the inverter 296b to the not chip selected input of the 280 chip. When the elements 28~, 282 are not selected the contents of each of the counters, 43, 45, 51 and 47, 49, 53, respectively, are blocked from being counted further by the encoder pulses on the line 47. The processor 7 is now able to interrogate the delay counter 47 associated with the Scanner A to determine what its count was at the time that _ounter was latched. The latched value of the encoder counter 43 may also be determined by the processor 7. The processor can subtract the initial value from which the delay counter 47 started counting from the latched value just read from the delay counter 47.
The purpose of this calculation is to determine the number of counts the counter 47 has been counted down during the time interval between when the flip-flop 26~ generated an intexrupt signal on the line 2~b and the time when the processor 7 was able to respond to that interrupt signal.
The difference between the initial value of the delay counter 47 and the final value as just read by the digital 1~3i 3~

processor 7 corresponds to the latency interval. The processor can then determine the precise value of the leading ed~e of the mark, in encod~ir counts, by adding to the value of the encoder counter 43 which has just been read by the processor 7 the delta calculated instep E
above between the initial and the latched valued of the delayed counter 47. The processor 7 can then issue a clear A instnlction on the line 268c which will reset the two flip-flops 268, 270. H) The processor 7 can then determine the new value to be set into the delay counter 47 so that when the delay counter 47 has been counted down to 0, the window, which is determined by the window counter 51 will be precisely centered with respect to the now present location of the mark. Assuming that an encoder is being used which generates 20000 counts per revolution of the associated press cylinder Fig. 8 schematically in-dicates that the count to be set into the delay counter so that the window will be centered with respect to the loca-tion of the most recently detected mark corresponds to the number of encoder counts per revolution, 20000, minus the present location of the mark minus 1/2 the window width, the number of counts in the window counter, plus the present location in encoder counts corresponds to the value to which the delay counter 41 should be set. I) The processor 7 can then load the delay counter 47 with the count which has just been calculated. J) The processor 7 then initiates down counting of the delay counter 47 by issuing an address on the upper half of the address bus 9b which is decoded and which generates a pulse on a line 265a, the start delay-A line. This pulse is transmitted through the gate z~

265 and gates on the delay counter 47 associated with Scanner A.
The above process can be repeated c~clically to continuously monitor the present location o~ the mark being sensed and also to continuously reset the location of the window so that it continues to be centered around the most recent location of the mark. This is a parti-cularly important feature during transient periods perhaps when the press is speeding up or slowing down where the location of the mark might tend to shift with respect to the window. By dynamically readjusting the location of the window with respect to each sensed mark, the mark will stay within the inspection zone even during these transient intervals.
OVERVIEW OF CONTROL SYSTEM OPERATION
Figures 9 through 11 disclose the overall opera-tion of several different embodiments of the control system 5. Fig. 9 is a flow diagram of the sequence of operations associated with a mark to reference register control or a mark to reference cut-off control. Fig. 10 is an overall block diagram of a mark-to-mark, single scanner register control. Fig. 11 is an overall block diagram of a mark-to-mark, dual scanner register control.
The register controls of Fig. 9, 10 each uses a single scanner to sense marks on the web which are placed serially one after the other on the web. The circumferential regis-ter control of Fig. 11 is for use in installations where two scanners are used, and the marks are placed next to one another on the web.
With reerence to Fig. 9, assuming that the 3B~

control system 5 is running in the automatic mode with a set point previously selected, at a selected paint in time, the window counter for Scanner A, 51, is enabled, and it ; starts to count down due to conditional press encoder signals on the line 47. Subsequently, the control 5 can sense a mark from Scanner A which is transmitted on the line 27 to the conditioning and control circuits 37. This mark must be sensed before the window counter 51 has been counted all the way down to zero.
If the mark has not been sensed before the window counter 51 has been counted to zero, the control system 5 enters an error routine which drops the control system out of the automatic mode by resetting the auto/
manual flip-flop 210 and energizing an error, failsafe, light on the front panel.
When a mark has been found, assuming that the window counter 51 has still not counted all the way down to zero, the location of that mark, which is determined based on the count in the encoder counter 43 for Scanner A
and a correction as discussed previously to compensate for latency in the response time of the processor 7, is stored in random access memory. The window counter 51 is then reset to the original preselected length of the window. Additionally, the delay counter 47 for Scanner A
is set to a calculated initial value such that when the delay counter 47 has been counted down to zero, and the window counter 51 is enabled, the window defined by the time interva:L it takes to count the window counter 51 from its preset value down to zero will be centered about the location of the latest mark detected by the control system 5. The downcount of the delay counter has been ` ' , `

enabled, and conditioned encoder pulses from the line 35bstart to count down the delay counter 47 for ~canner A.
Subsequently, the processor calculat~s a new value of error which corresponds to the di~ference between the prestored set point (SP) and the location of the newest mark detected. Once the latest error value is calculated, an average error value over thP last one, two, four or eight cylinder revolutions can be calculated. The number of error values used to determine the average error value is initially selected by the settings of the "AVE"
dip switches 89.
Once an average error value has been determined, that value is adjusted for the gain of the system which is initially set by the "GAIN" dip switches 87, and the speed of rotation of the press cylinder whose register is being controlled if the compensator motor 24b is a DC
motor. If the compensator motor 24b is an AC motor used as a stepping motor, only an adjustment for gain is made.
The ad~usted gain is then output along the-data bus 11 to the motor control port 23. The sign of the error value determines the direction in which the motor drive electronics 24a causes the motor 2~b to rotate. In the case where the compensator 24b is a DC motor, the signal supplied through the digital to analog converter 170 defines a velocity parameter for that motor. In the case where an AC synchronous motor is used as the compensator motor 24b, the error signal output through the motor control port 23 corresponds to a position displacement of the motor.
Subsequent to supplying adjusted error to the compensator 2~b, the system 5 waits until the delay --~0--3B2~

counter 47 for Scanner A h~ been counted d ~ to zero. Once the delav counter ~7 has been counted down to zero, the window counter 51 is again gated to repeat the control process.
secause of the fact that the delay counter 47 is set dynamically on each revolution the window which is defined by the count set into the window counter 51 for the Scanner A is dynamically readjusted in time as the sensed marks move back and forth along the cylinder due to varying speeds and web conditions.
The block diagram of Fig. 9 corresponds to either a register control wherein a single mark is compared to a reference or corresponds to a cut-off control where a single mark is compared to a reference.
Fig. 10 is a flow diagram which shows the operation of a circumferential mark-to-mark register control, using a single scanner. The information flow, as shown in Fig. 10 assumes that control system 5 is in the automatic mode with a previously established set point.
In this case, the previously established set point cor-responds to the difference between the two set point marksat the time the set register switch at the front panel was pressed by the operator.
At a selected point in time, the window counter 51 is gated that it can be counted down by the conditioned encoder pulses on the line 35b. During the time the window counter 51 is being counted down, the control system 5 can sense a mark. If a mark is sensed, which will be the first mark, before the window counter has been counted down to zero, the location of that mark in encoder counts is stQred in a selected location in random access memory, Aclditionally, a second mark to be sensed so long as the window counter 51 has not been counted down to zero.If a second mark has been sensed, its location in encoder counts, is determined and stored in memory. If the system detects that the window counter has counted down to zero without having detected either a first or a second mark, it will enter the error routine which will light up the failsafe light on the front panel and which will tak~ the system out of the automatic mode by resetting the auto/
manual flip-flop 210.
Assuming the two marks have been properly detected during the time the window counter 51 was being counted down to zero, the window counter 51 is then reset to count corresponding to the desired length of the window.
Additionally, a value is calculated and set into the delay counter 47 which will generated by the window counter 51 around the latest two sensed marks. In this mode of operation, the length of the window corresponds to the interval between the two set point marks plus either 124 or 250 encoder counts which can be set initially by the "WINDOW" dip switch 89. The system 5 then enables downcounting of the delay counter 47 by the press encoder pulses.
A new error value is calculated which corresponds to the difference between the offset of the two set point marks (DSP) and the offset between the two marks which have just been sensed. The system 5 can then calculate an average error depending on the selected number 1, 2, ~ or - 8 average. Once an average error value has been selected, it can be adjusted for gain and press speed (in the case of a DC motor) and the adjusted error can be output 3B~O

through the motor control port 23, through the motor drive electronics 24a to the compensator motor 24b. When the system 5 senses that the delay counter 47 for Scanner A has been counted down to zero, it will re-enable down-counting of the window counter 51, thus restarting the loop.
It sho~lld be noted that, as in the case of Fig. 9, the mark-to-mark single scanner register control system of Fig. 10 dynamically readjusts the value in the delay counter 47 on a per revolution basis so that the window, to be used in the next revolution, is centered about the two most recently sensed marks. Thus, if the sensed marks start to move with respect to the set point marks, due to variations in press system parameters, the mark sensing window will dynamically follow them, enabling the system 5 to continue to track the location of the mark.
Fig. 11 discloses the information flow in the control 5 when it is used to control register, on a mark-to-mark basis utilizing two Scanners A, B. In this instance, the marks are placed on the web laterally with respect to one another so that two independent Scanners A, B are necessary to detect them. Scanner A is offset laterally with respect to Scanner B. The control system 5, in this mode of operation, senses whether the delay counter 47 for scanner A has been counted down to zero. It also senses whether the delay counter for Scanner B, 49, has been counted down to zero. Whenever the delay counters 47, 49 go to zero, they enable their respective window counters 51, 53. The conditioned press encoder signals "
on the line 35b may then start to count down each of the ~ 43-2() enable window counters. While the window counter 51 for Scanner A is running, mark A can be sensed, If it is sensed before the window counter 51 has been counted to zero, its location in encodex counters is determined and stored in random access memory. If mark A has not been sensed bef~re the contents of the window counter 51 for Scanner A has been counted down to zero, the system 5 en-ters an error routine, turning on the failsafe signal and resetting the auto-manual flip-flop 210.
While the window counter 53 for the Scanner B
is being counted down toward zero, a mark s can be sensed.
If the mark s is sensed before the window counter 53 has been counted down to zero, its location in encoder counts is determined and stored in random access memory. If a mark B has not been sensed before the window counter 53 has been counted down to zero, the system 5 enters an error routine corresponding to that previously described.
In this mode of operation, the Scanner A is set to sense a mark which will come later in time than the mark sensed by the Scanner s. Thus, once the mark A has been sensed, implicitly both marks have been sensed, assuming the system is operating properly. After the mark A has been sensed, the window counters 51, 53 are re-set corresponding to the preselected length of the window.
This is determined by the setting of the "WINDOW" dip switch 89. Subsequently, the delay counters 47 and 49 for Sc~nners A and B, respectively, are again set with a count such that when they are counted down to zero the windows determined by the window counters 51, 53 will be centered with respect to the two marks A and B just ''a3~

sensed. The two delay counters 47, 49 are then enabled, and the conditioned encoder signals on the line 3Sb are permitted to count the counters 47, 59 down toward zero.
The system 5 can then calculate a new value which corresponds to the difference between the offset of the set point marks (DSP) and the offset between the two marks A and B which have just been sensed. The new error value can be averaged with the previously determined error values, and the averaged error value can then be adjusted for gain and press speed, assuming the compensa-ting motor 24b is a DC motor. The adjusted error value can then be output through the motor control port 23, through the motor drive electronics 24b to drive the web or cylinder compensator motor 24b. The system S will then wait until one of the delay counters 47 or 49 has been counted down to zero.
As in the case of the operation of the embodiment shown in Fig. 9 and Fig. 10, the system 5, when operating as shown in Fig. 11, is able to dynamically readjust the location of the window for both Scanner A and Scanner B
by dynamically readjusting the values set into the delay counter 47 or the delay counter 49 on a per revolution basis of the printing cylinder.
DESCRIPTION OF THE CONTROL SEQUENCE
Fig. 12 are flow diagrams of the control sequences used by the processor 7. These control sequences are stored unalterable by the processor 7 in the read only memories 67, 69. Fig, 12 is an overall block diagram o~
the control sequence for the system 5. When power is first applied to the system 5, a power up interrupt is generated, and the processor 7 jumps through location zero to the start of the operating system, which is hard wired into the read-only memory 13. The operating system then executes an initialization sequence which reads the settings of the dip switches 87, 89, sets up the para~
meters on the real time clock which is located in the input port 17, and zeroes out the 512 bytes of random access memory in the output port 164 and the input port 85.
The initialization sequence then returns control to the operating system which then initializes the flags to run the three primary systems tasks, the monitor task, the control task, and the front panel task. The monitor task and the front panel task are each run in sequence after each 10 millisecond real time clock interrupt, or tick, generated by the real time clock in the input port 17. If the moni-tor task or the front panel task posts the control task or sets appropriate flags, after the monitor task has com-pleted execution of its required operations, the control task will be executed before the front panel task is executed again.
Generally, it is the function of the monitor task.to monitor the operation of the real time counters, it is the function of the control task to actually generate the ne.cessary error values and provide output to the motor control port 23, and it is the function of the front panel task to sense switch inputs from the display panel.
Fig. 13 is a block diagram showing an overall view of the six interrupt driven control sequences within the control system 5. The.left-most interrupt sequence in Fig. 13 is a power~up interrupt sequence which merely 3Q forces the processor 7 to begin executing at location æero.

BZ~

The next interrupt routine is the Scanner B interrupt routine which, when an interrupt signal is sensed on the interrupt line RST S.5 by the processor 7 due to Scanner B
having sensed a mark, the processor 7 is forced to execute the Scanner B interrupt handler sequence starting at loca~
tion 2C hexidecimal. Similarly, in response to Scanner A
having sensed a mark, the Scanner A interrupt routine, due tQ having sensed the signal at the interrupt port RST 6.5 of the processor 7 forces the processor 7 to start executing the Scanner A interrupt handler routine at location 34, hexidecimal. The real time clock interrupt handler routine responds to a real time clock interrupt on the line RST 7.5 of the processor 7 which forces the processor 7 to start executing the real time clock interrupt routine starting at location 3 C hexidecimal. The external bus interrupt handler senses an interrupt generated by the external bus 20 on the line labelled INT of the processor 7 and forces the processor 7 to start executing the external bus interrupt service routine at location 38 hexidecimal. A
2D last interrupt service routine, the power fail interrupt routine a power fail signal on the line labelled TRAP of the processor 7 which forces the processor 7 to start executing the power fail interrupt service routine at the location 24 hexidecimal.
The power up interrupt and the power fail inter-rupt both turn control over to the operating system, The Scanner A interrupt routine, the Scanner B interrupt routine, the real time clock interrupt routine and the external bus interrupt routine all return control to the routine which is previously being executed at the time the processor 7 3~

detected that respective interrupt.
Fig. 14 is a block diagram showing the operation of the monitor task. The mon:itor task, which is entered from the operating system, first calculates the antular velocity of the associated printing press cylinder. Recall, that the monitor task is exec~ted immediately after each real time clock interrupt. Once the monitor task is started, it reads the value in the encoder counter 43 for Scanner A
and compares it to the value previously stored, which was read from the encoder counter 43 of Scanner A the last time `~ the monitor task was executed. Since each real time clock interrupt occurs 10 milliseconds after the previous inter-rupt, the monitor task is now able to calculate the angular velocity of the associated printing press.
Once this velocity has been calculated using the current value read from the encoder counter 43 from ; Scanner A and the previous value read from the encoder counter 43 of Scanner A, the monitor task checks to see whether the press is running at over 1800 rpm. Generally speaking, the press will never run over 1800 rpm, and if it does appear to be running over 1800 rpm, the system is probably suffering from a defective encoder. The monitor system then flags a status bit indicating that either the encoder is defective or the press has been stopped and posts the control task. The last thing the monitor does then is update a revolution counter which simply provides a software count of a continuing number of revolutions of the press. The monitor task then returns to the operating system.
If the press does not appear to be running at over 1800 rpm, the monitor system then checks to see whether it is running under 50 rpm. If the press is run-ning under 50 rpm, it turns on the "go down" light on the front panel, indicating that the press is being turned off.
In this instance, control is impossible, and the monitor system exits through the same path as if it is sensed that the press was running over 1800 rpm. If the press appears to be running below 1800 rpm but above 50 rpm, the monitor system checks to see whether or not there has been an encoder failure detected during the last 10 times that the monitor task has been run. If during the last 10 milli-seconds the monitor has detected that the press has been either running over 1800 rpm or under 50 rpm, it is necessary that the monitor routine be executed a total of 10 times without either condition being detected before it proceeds with its f~er processing. If there has been a recent encoder failure sensed, the monitor routine merely updates the revolution counter and then exits.
If there have been no recently detected encoder failures, the monitor task then checks to see whether or not the next mark button on the front panel has been depressed. If the monitor routine senses that the next mark button has been depressed, when the system is running in the manual mode, it processes that request by calling a routine which will load the window counter 51 for Scanner A
with its maximum count to provide the longest possible window. Then, the monitor routine will check to see if the next mark has been found. If no mark has been found, the monitor routine exits, updating the revolution counter if appropri~te and returns to the monitor. After each real ~38~0 time clock interrupt when the monitor senses that an in-completed next mark request has been made, it will again check to see if a next mark has been found. The monitor will continue trying to find a next mark until one is found. Once the system has found the next mark, corxe-sponding to the Scanner A interrupt routine having been called in response to a signal on the line RST 6.5 of the processor 7, the monitor will post the control task which will cause it to be run by the operating system at the completion of the return from the monitor.
If a ne~t mark has not been requested, the moni-tor checks to see if the system has gone by the window.
That is to say, it checks to see whether or not the value in the encoder counter 43 for the Scanner A is greater than the sum of one-half of the count which is loaded into the ~indow counter 51 plus the encoder count which had been stored for the mark which was sensed in the last revolution.
If the monitor determines that the window has not been closed, it will then go on to see whether or not it should set an auto flag which corresponds to whether or not the auto/manual flip-flop 210 is set to the auto mode and whether or not the speed is above 50 rpm. If the conditions are appropriate to enter the auto mode, the "automatic"
indicator light on the front panel will be turned on, if necessary the monitor will update the revolution counter, and then it will exit.
If, on the other hand, the monitor determines that we have passed the window, it first checks to see whether or not we have reset the window. This corresponds to the process of setting the delay counter 47 for Scanner A

~43~

and the window counter 51 for Scanner A to the value of the delay counter which will center the window about the most recently detected mark and the value of the window counter 51 to that settin~ which has been previously read on the dip switch 89. The down counting of the delay counter 47 by the encoder pulses from the press on the line 35b is also enabled. The window is only reset once each revolu-tion, and if it has been set, the monitor checks to see whether or not a mark has been detected this revolution.
If so, it posts the control task and then exits.
Fig. 15 is a flow diagram of the front panel task sequence. When started by the operating system, the front panel task performs a debounce test on each of the dis-play panel switch closures which are sensed through the input port 17. The debouncing test includes checkin~ to see if a given switch bit has been on for the past two real time clock interrupts. If so, that is considered a valid switch closure. If not, the switch closure is recorded, but no action is taken on it. I~ no valid switch closures were indicated, the front panel task merely decrements a time-out counter which limits the rate of change of the set point by the advance and retard switches on the front panels.
In the manual mode, the advance and retard set point switches directly operate the compensator motor 24B. In the auto-matic mode, the advance and retard set point switches incre-ment and decrement the current set point by ~n amount set on the "ADVANCE RETARD COARSENESS" dip switch 87. This limits the rate at which an operator can vary the set point of the system.
If a valid switch closure has been detected, the ~L~4~8;~

front panel task then determines which switch closure has occurred. If the advance or the retard switches have been depressed, the set point is either advanced or retarded, respectively. In the manual mode, this consists of ad-vancing or retarding the motor 24b directly. In the automatic mode this consists of incrementing or decrement-ing the previously stored set point value by the amount determined by the dip switch 87. The auto/manual switch provides a signal which in turn can be used by the processor

7 to set or reset the auto/manual flip-flop 210.
If the control 5 is in the manual mode, when the front panel task senses that the set register button for the front panel has been depressed, it takes as a new set point the location of the most recently sensed mark, if the system S is operating in the mark-to-reference mode, or the offset between the two most recently sensed marks if the system is operating in a mark-to-mark mode. The new set point is established immediately by the front panel task and the operator could continue to run with the con-trol 5 in the manual mode for a period of time if he so chose~ At some point when the operator is satisfied with the regi3ter of the associated pressj he then depresses the auto/manual switch which puts the control 5 in the auto-matic mode, wherein it will directly control the motor 24b.
If the front panel task senses that the next mark switch has been depressed, which is only active when the control system 5 is in the manual mode, it sets a flag which is sensed by the monitor task. The monitor task will then process the next mark request. After the appropriate action has been taken depending on which switch has been :; ' - , .

3~

depressed, a time-out counter for the advance or retard switch is decremented to limit the rate of change of the current set point. The front panel task then returns con-trol to the operating system.
Fig. 16 is a flow chart of the control task which is called by the operating system based on flags which are set by the monitor task or the front panel task. On power up, the control task initializes flags associated with the scanner status. At that point the control task returns to the operating system and waits until it is called or posted. On return from the operating system, the control task initially checks to see whether or not a special request has been made of it. If a bad encoder has been sensed, corresponding to a procedure error, the control task re-enters its initialization segment, and then subsequently returns to the operating system. If the system 5 has been placed in the automatic mode by the operator, the control task then causes the processor 7 to execute a control sequence which is labelled "automatic control" in Fig. 12. If the control task senses that no mark has been detected, corresponding to the fact that the window has been closed, that is the window counter 51 for Scanner A has been counted down to zero without a mark having been sensed or the window counter 53 for Scanner B
has been counted down to zero without a mark being sensed, the control task will then check to see whether or not a next mark has been requested. If so, it returns to the operating system and waits until the monitor task can process that request and post the control task again. If no next mark request has been made, the control task 3~3~0 simply turns out the central column of lights on the control panel corresponding to the error indicator and again returns control to the operating system and waits to be posted. If, on return from the operating system, the control task has not detected any special request has been made corresponding to being in the manual mode, it puts itself back in the wait state and waits to be posted and again returns control to the operating system.
When the control task has been called by the operating system in response to either the monitor task or the front panel task, it first checks to see if a special result has been requested. If no mark has been detected, the control task checks to see if a next mark request has been made. If so, it is processed. If a procedure error is detected, the error indicator is turned off and the control task returns to the operating system.
~f the automatic mode is detected, the control sequence labelled "AUTOMATIC CONTROL" iS executed.
Initially, in the "AUTOMATIC CONTROL" sequence the ~auto/manual flip-flop 210 will be set indicating that the automatic mode has been entered. At this point, the control task again waits to be posted. The control task does not access the real time data represented in the counters 43 through 53 directly. Rather, this is the function of the monitor task. The monitor task determines the position of the marks to be sensed on the web each ~evolution. Having found the mark or marks, the monitor task posts the control task which returns to entry point C from the operating system.
The control task, fro~ entry point C, checks to see whether there is a hardware problem or whether the operator has released the auto/manual button and returned the control 5 to the manual mode or whether there is an indication that a mark has not been sensed on this revolution. If there are any problems, the control task turns out the error indicator signals, the central column of lights on the operator panel and resets the system hardware, and particularly the auto/manual flip-flop 210 to manual for manual operation. It then returns to the operating system and waits to be posted to re-enter through entry point B.
If there are no problems, the control task then calculates and saves the error. The error calculation is dependent on the mode of operation of the control system 5.
The desi~ed control mode is set on the "CONTROL MODE" dip ; switches 89 and may be read by the processor 7. Tn a circumferential register-to-register control mode, three different types of control are possible. In a lateral con-trol mode or in a cut-off control mode, there will only be one mode of operation.
Where the control system 5 is being used as a circumferential control and the mode of operation is mark-to-reference, the error calculation is formed by subtracting the present location of the mark from the set point value. If the control system 5 is operating as a circumferential mark-to-mark control module, the difference ~ between the two measured marks is subtracted from the - difference between the set point marks to determine the error.
A cut-off control module uses the same error ;

~ -55-~4~20 calculation as a circumferential register control module would use in a mark-to-set point control mode.
A lateral register control module would use essentially the same error calculation as would a circum-ferential mark-to-mark registration system except that in the lateral control system an additional step is necessary to first eliminate any circumferential errors.
Once the control task has calculated and saved the present error, it performs any necessary averaging, and then displays on the central panel of lights on the display panel the fact that there is an error and the fact that the compensator 24b is being driven in a direction to minimize that error. Finally, the control task supplies to the motor control port ~3 an eight-bit error consisting of a sign and seven bits of magnitude which is then output through motor control electronics 24a to the compensator 24b.
Fig. 17 is a block diagram of one of the scanner interrupt routines. The Scanner A, interrupt routine and the Scanner B interrupt routine are identical. The two merely respond to different scanner signals. When a scanner interrupt routine is entered in response to having received either a leading edge or a trailing edge from Scanner A on the line 27 or from Scanner B on the line 29, the interrupt routines first latch and then read the values in the encoder counter 43 and the delay counter 47 associated with Scanner A or the encoder counter 45 and the delay counter 49 associated with Scanner B. The scanner interrupt routine then makes a determination, based on the conditi4n of the leading or the trailing edge flip-flop 270 and also on the setting of "WEB COLOR" dip switch 89, whether or not the mark which has been sensed is a light mark on a dark web, or a dark mark on a light web so that it will be possible to make a decision as to whether or not a leading or a trailing edge of the mark has been sensed.
If the edge which has been sensed is a leading edge, and if it is one that is a desired leading edge, the scanner interrupt routine removes the latency time interval which e~ists between the instant the interrupt occurred due to the scanner signal on the line 27 and the time when the encoder counter 43 for the Scanner A was read.
Similarly, if the interrupt routine is for the purpose of handling interrupts in the Scanner B, the latency time interval between when the scanner signal was sensed on the line 29 and when the encoder counter 45 associated with Scanner B was read is removed to determine the true position of the sensed mark with respect to the top dead center position of the cylinder in encoder pulses. Once the correct position of the leadinq edge of the mark has been determined, the scanner interrupt routine returns control to the interrupted routine.
If the scanner interrupt routine senses that an undesired mark has been sensed within the window, one which either leads or trails the desired mark by more than a preset amount, that leading edge or trailing edge is rejected and the location of that mark is not saved.
S:imilarly, if the scanner interrupt routine determines that a trailing edge rather than a leading edge has heen detected, if that is a desired trailing edge, its true position can be calculated and saved.
Fig. 18A is a flow chart of the open window routine. The open window routine is a control sequence 3~32V

which is called by the monitor as part of its processing of a "next mark" request. The open window routine first checks to see whether the window, corresponding to the count in the selected window counter 51 or 53 has been opened. If this is the ~irst time through the window routine and the window has as yet not been opened in response the the next mark request, the open window routine deter-mines what the length of the present window is, and set the appropriate delay counter, 47 or 49, so that its associated window counter, 51 or 53, will not start downcounting until a selected amount of time has occurred after the present mark has been sensed. This is to ensure that we do not start looking for the next mark until the present mark has passed the Scanner A or the Scanner B. The selected window counter 51 or 53, is then set to its largest possible count.
This corresponds to the window being opened as far as pos-sible. The appropriate delay counterr 47 or 49, is then started which will, when it counts to zero, gate the associ-ated window counter, 51 or 53, so that the encoder pulses on the line 35b will start counting down the appropriate window counter 51 or 53. At this point, the open window routine then returns to the monitor.
Alternately, if the open window routine is entered from the monitor, and it senses that the window has already been opened the maximum amount, it simply checks to see whether or not the window is closed. This corresponds to checking whether or ~ot the appropriate window counter, 51 or 53, has counted down to zero. If so, it merely resets the counter 51 or 53 to its maximum value again.
A flow diagram of the set window routine appears in Fig. 18B. There is a set window routine associated with ~58-:~43~

each of the window counters 51, 53. The set window routine is called by the mo~litor task on a per revolution basis of the printing cylinder, whenever the monitor task determines that we have passed the window. The set window routine first sets the selected value into the window counter 51 or 53 associated with the Scanner A or the Scanner B. The selected value associated with the window counter 51 or 53 is determined in part by a setting of the "WINDOW" dip switch 89, as well as the control mode. In a mark-to-reference control mode whether a register operation is beingcarried out or whether a cut-off operation is being carried out, the window counter is merely proportional to the setting on the "WINDOW" dip switch 89. In a mark-to-mark type operation, the window counter 51 or 53 is set to a value which corresponds to the distance for the offset between the two set point marks and the setting on the "WINDOW" dip switch 89. Once the window counter has been set, the delay counter 47 or the delay counter 49 is set with a value such that the window determined by the corresponding window counter 51 or 53 will be centered with respect to the posi-tion of the presently detected mark. The delay counter 47 or ~9 is then started.
Fig. 19 is a block diagram of the control sequence corresponding to the operating system. On start-up, the operating system gets a pointer for the task control table and initializes the task control table. The operating system then transfers control to a routine which is des-cribed in Fig. 20, and which initializes the control 5.
Upon return fxom the initialization routine, the operating system points to the start of the task table, and then checks to see whether the current task should be run. If so, it turns control over to the task, either the monitor;

' ~ 1~3B~(~

the control task or the front panel task. If that task is not to be run, the operating system then checks the next entry in the table. I~ that task is to be run, it turns control over to that task. If not, it checks the next entry at the table. When the operating system gets to the end of the table, it goes back to the beginning of the table and starts over. The task table only has three tasks in it, the monitor task, the control task, and the front panel task. On a return from any task which has gone into a wait state, the operating system saves that task's return address and checks the next entry in the table.
However, as a practical matter, the panel task and the monitor task once started run to completion except where the processor 7 responds to interrupts. As a result, the front panel and the monitor task each have only one entry point. Only the control task has more than one entry point.
Fig. 20 is a flow diagram of the hardware initial-ization routine which initializes the control 5. Upon entry from the operating system, the initialization routine zeroes the random access memory in the output port chip 164 and the input port chip 85. The random access memories 73, 75 are never disturbed. The random access memories 73, 75 are used to sotre information such as the set point, and other information which is desirable to have available in case of a power failure or a shut-down so that the press can be brought up to its previous operating conditions immediately.
The hardware initialization routine then sets up the real time clock in the input port chip 85 to generate an inter-rupt every 10 milliseconds, and it reads the settingsof the dip switches 87, 89 and saves them. Further, the hardware initialization routine resets the control flip-flop 210 to 3~0 the manuaL state and then sets a software mode flat, to whatever state it was in, automatic or manual, be~ore the power failed. The initialization routine also sets up the external bus communications port 19. If the control system 5 is being used as a register control unit, it can receive or transmit information along the bus 20. If the control system 5 is being used only as a cut-off unit, the communication bus 20 is replaced with a set of thumb-wheel switches which can be used to set up an initial set point for cut-off. The settings of the dip switches 87, 89 are decoded. Using the settings of the dip switches 87, 89 an encoder parameter, either 20,000 or 40,000 pulses per cylinder revolution for register control can be set up, and a window parameter corresponding to either 124 or 250 encoder counts can also be set up. Subsequently, the encoder counters 43, 45 are initialized with the correct 20,000 or 40,000 encoder counts and the window counters 51, 53 are initialized with the correct 124 or 250 encoder counts. The initialization hardware routine also checks to see whether the motor 24B is a DC type motor or an AC type motor. Control is then returned to the operating system.
Fig. 21 is a block diagram of the real time clock interrupt routine. When the real time clock counter in the input port chip 85 counts down to zero and generates an interrupt the interrupt handle first saves the old value read from the encoder converter 43 and reads a new value. These two values c~n be used by the monitor routine to determine press speed. The fail-safe one-shot 212 is also retriggered by a signal from the "SOS" output port of the processor 7.
Finally, the routine updates the task control table to 3~32V

indicate that a real time clock interrupt has recently been received. Control is then returned to the inter-rupted routine.
THE ERROR AVERAGING ROUTINE
The error averaging routine executed by the control task has been designed to optimize the performance of the control system 5 independently of the mode o~
operation o~ the control system. The error averaging process can involve 1, 2, 4 or 8 averages which are selected by setting the "AVE" dip switches 89. Based on the selected number of averages, a buffer of length 1, 2, 4 or ~ random access memory locations is maintained, wherein the last 1, 2, 4 or 8 error values, including a sign are stored. Each time a new value of error is calculated by the control task, the newest value is added into a running total which is maintained of the contents of the 1, 2, 4 or 8 location buffer and the oldest value is subtracted out. Thus, a cumulative total of the selected number of averages is maintained. This cumulative total is then divided by the preset number of averages to form an average error.
Once an average error has been formed, a compari-son is made between the absolute value of the most recently formed average error and the absolute value of the last error value. The control task then establishes a base error by selecting the smaller of the absolute value of the average error or the absolute value of the latest error as a base value, and takes as a sign the sign of the latest error value. Once the base error has been determined, a dead zone value, determined by the setting 3~3~0 of the "DEAD ZONE" dip switches 87, is subtracted off of the magnitude of the base error. The magnitude of the base error could be reduced to zero i it is small. Finally, a comparison is made between the sign of the latest base error and the sign of the previous base error. If the two signs are different, the magnitude of the present base error is set to zero.
The purpose of the above defined process is to provide an average base error which is a damped base error and which will enable the control system 5 to follow variations of the associated printing press more closely and with less overshoot.
Once the adjusted base error with its associated sign has been determined, the control task adjusts that base error to provide optimal performance of the compensa-tor motor 24. Four different gain settings may be entered into the control system 5 through the "GAIN" dip switches 87.
If a DC motor is being used as the compensator 24B, the base error value is adjusted before being supplied to the motor drive port by means of the values in Table 2. Depending on the gain set by the dip switches 87 and depending on the sensed press speed, a value is selected off of Table 2.
These values are hard-wired into the read-only memory of the control unit 5.
If the base error has a value greater than or equal to 6, the above defined value selected from Table ~ is used directl~ and output to the motor control port 23 along with the associated sign. If the base value is equal to 5, the above defined value selected from Table 2 is divided by 2 before it is supplied to the motor control port 23.

If the magnitude of the base error is equal to 3 or 4, the value selected from Table 2 is divided by ~. If the magni-tude of the base error is equal to 1 or 2, the magnitude of the base error selected from Table 2 is divided by 8.
If the base error is equal to zero, then the motor is turned off.
Once the adjusted base value is determined based on Table 2, the sign of the unadjusted base error is associ-ated with it. The adjusted base error and sign is then sent to the motor control port 23 which supplies it to the motor drive electronics 24a to drive the compensator motor 24b.
If the compensator 24b is an AC motor, the value of the "GAIN" dip switches 87 is checked. Depending on the value of those switch settings, 1, 2, 3 or 4, the base error is iteratively added to itself as many times as the gain switches are set to. Thus, it is added to itself either once, twice, three times or four iimes. (This is equivalent to a multiplication of from 1 to 4 based on the settings of the gain switches and the dip switch.) This value, corresponding to displacement steps of the synchron-ous motor is supplied by the processor to the motor control port 23, An error value associated with a DC motor and an error value associated with an AC motor are both calculated by the control task and both are output to the motor con-trol port 23, one after the other. Then, depending on which type of motor is connected to the control system 5, the appropriate error which has been output drives that motor, Z1(3 PLUG-IN THUMB WHEEL SWITCHES
. _ _ For those instances, such as in a cut-off c~n-trol, where it is desirable to be able to introduce an initial set point based on a physical measurement of the web a plug-in thumb wheel module shown schematically in Fig. 22, is available which can be connected to the ex-ternal bus 20 of the control 5.
As shown in Fig. 22, the plug-in module in-cludes eight four line data selector chips 500, 502, thum~ wheel switches 504 through 510, gates 516 through 522, counter elements 526, 528, normally closed control switch 530, resistQrs 532, 534 and capacitor 540.
The outputs of the data selector chips 500, 502 which include two binary coded decimal numbers are first loaded into the input port A of the input port chip 100 and then into an input port B of the input port chip 100.
When the normally closed switch 530 is opened, a strobe A signal is generated on a line 550 which is con-nected to device 112 at pins 3 and 6. This provides a signal which strobes the l's and lO's BCD numbers from the : chips 500, 502 into the input port A. Subsequently, the gate 518, the resistor 534, the capacitor 540 and counter elements 526 and 528 generate a strobe B pulse on a line 552 which is connected to device 114 at pins 3 and 6 which strobes the lOO's and the lOOO's BCD numbers from the data selector chips 500, 502 into the port B of the chip 100.
The processor 7 can then respond to an inter-rupt signal generated on the line lOOa due to having loaded the input ports A and B of the chip 100. The value read in through the chip 100 from the set point switches 504 through 510 can be used to estahlish initial set point value for a cut-off unit.
VISUAL DISPLAY PANEL AND ASSOCIATED
DRIVE ELECTRONICS
Fig. 23a is a planar frontal view of a display panel 600 usable with the control system 5 and which is connected to the display panel port 21. The display panel 600 had three columns of lightable indicators 603 through 607. The indicator lights in the columns 603 through 607 are controllable through the display panel port 21 by the digital processor 7.
Each of the indicators in the column 603 displays one aspect of the status of the control system 5. The "auto" indicator is illuminated whenever the control system 5 has sensed that the operator has entered the automatic mode. In the automatic mode, under normal operating con-ditions, the web or cylinder compensator motor 24b is con-tinuously attempting to minimize the error between the set point and the sensed web indicia. The "manual" indicator is illuminated whenever the control system 5 is operating in the manual mode. In the manual mode, the control system 5 is merely monitoring the difference between the sensed indicia on the web and the current set point. One of the indicators "advance", "retard" is illuminated whenever the control system 5 is operated in the manual mode, and whenever the two-position advance/retard switch 610 is de-pressed from its quiescent condition to indicate to the control syst:em 5 that the motor 24b is to be either advanced or retarded. The "ready" indicator is illuminated whenever the control system 5 is receiving press encoder pulses, ~L438~V

cylinder reference signals and web scanner signals.
The "set up" indicator is illuminated wh~never the compensator has been moved to a pxedetermined set-up position.
In the column 607 each of the indicators indi-; cates some abnormal status of the control system 5. The "failsafe" indicator is illuminated whenever the control system 5 is not receiving all the necessary input signals or the press speed drops below 50 RPM. The "go-down" indi-cator is illuminated whenever the press is running below 50 RPM. The "scan one" or "scan two" indicators are illuminated whenever the control system 5 does not receive a scanner input signal is not received during a window.
The "comp limit" indicator is illuminated whenever the compensator motor has moved the compensator against a limit switch.
The "off line" indicator is illuminated whenever the control system 5 has been taken off line with respect to the external control bus 20. This is accomplished by closing the switch 104a thus insuring that the control system 5 will never respond to the appearance of its address on the parallel eight-bit external data bus 28.
The center column of indicators 605 is illumina-ted by the processor 7 to indicate whether or not the associated printing press or cut-off unit is out of regis-ter and to indicate which direction the web or cylinder compensator motor 24b is attempting to move to bring the system back into register~ The central indicator 612 is a green indicator which is turned on whenever the control system 5 senses that the associated printing press or 32~

cut-off unit is running in register. The top and bottom indicators 614, 618 are red indicators which are illuminated by the processor 7 whenever an out-of-register condition is sensed. The arrows 620, 622 are illuminated whenever the processor 7 is attempting to bring the associated press or cut-off unit back into register.
Each of the indicators in the columns 603 through 607 is a backlite indicator which is not visible to the oper~tor under n~rmal lighting conditions until the associated backlighting source of illumination has been turned on by the proeessor 7.
In the lower half of the panel 600, will be found the AUTO/MANUAL switch 630 which is a spring loaded momentary push button switeh which the operator can manually depress to enter the automatie mode or to return to the manual mode.
A NEXT MARK switch 634 is a spring loaded push-button type switch, which an operator manually depresses, in manual mode, to indicate to the processor 7 that it should seleet the next mark it deteets as a set point. A SET REG. push-button 636 is a spring loaded pus~button switch whieh the operator - manually depresseswhen in the manuaL mode to inform the proeess-or 7 that the mark, or marks, eurrently being sensed are to be taken as the set point. Eaeh of the switches 610, 630 through 636, is eonneeted to the set of wires 91 and can be sensed through the port C of the switeh input port 85.
Fig. 23b is a front planar view of a lateral register operator display panel 650. The display panel 650 is very eomparable to the panel 600. The panel 650 includes a set of switehes 652 through 658 whieh have the same functions as the eorresponding set of switches 610, . , ~ . . .

o 630 through 636 of the display panel 600. In the panel 650, the switch 654 is labelled "IN/OUT". This switch corresponds in function to the ADVANCE/RET~RD switch 610 of the panel 600. A dif~erent label has been utilized to emphasize the lateral change being brought about in the associated printing press or cut-off unit by depressing the switch 654. A set of three indicator columns 660, 662 and 666 c~rresponds to the set of indicator columns 603 through 607 of the display panel 600. The indicators in the columns 660, 666, correspond to the same set of indicators previous-ly discussed in the columns 603 through 607. In the case of the lateral register control display panel 650, the out of-register or in-register condition is shown by the hori-zontal set of lights and arrows 662, which also emphasizes the lateral nature of that control operation.
Fig. 24 is a schematic of the drive electronics which are to be connected between the control system 5 of Fig. 2 and the display panel indicator lights of either Fig. 23a or Fig. 23b. Fig. 24 shows a set of data lines DD0 through DD7, 160, corresponding to the eight data lines 160 of Fig. 2E. Bits which are output through the output ~us 160 by the processor 7, which are set to a 1, correspond to lights in the column 603 through 607 or 660 through 666, which are to be lit. Also shown in Fig. 24 is a set of control lines 162, corresponding to the decoded address control lines 162 of Fig. 2D. The three lines 162 labelled center, left, right of Fig. 24 identify which column of lights is to be lit on the panel 600, 650.
The CENTER line 162b corresponds to an address which is generated by the processor 7 whene~er the center column of lights 605 or 662 on the front panel 600, 650 is to be lit. The indicator LEFT line 162c corresponds to a decoded address from Fig. 2 which has essentially zero volts on it whenever the left-most column of lights 603 of 660 is to be lit. The RIGHT line 162d in Fig. 2~
has a low voltage on it whenever the right-most column 607 or 666 is to be lit~ The strobe line 162a of Fig. 24 has a low-going pulse on it whenever one of the addresses 162b through 162d has been selected and is also low. The drive circuitry of Fig, 24 includes further a set of posi-tive OR gates 700, 702, 704 and 706. Each of the gates 702 through 706 functions as an AND gate in this instance, and generates a positive-going output on the trailing edge of the strob~ signal on the line 162a. The output of the gate 702 or 704 or 706 is a clock input for a corresponding eight-bit register element 710 through 714. When clocked by one of the gates 702 through 706, the corresponding register element 710 through 714 stores in a series of parallel D-flip-flops the bit pattern on the lines 160.
These bits are output through a set of parallel lines 710a, 712a or 714a through a set of buffer driver elements 710b, 712b or 714b to drive one of the sets of lights 716, 718, 720. The set of lights 716 corresponds to the column 605, or 662. The set of lights 718 corresponds to the column 603 or 660. The set of lights 720 corresponds to the column 607 or 666.
It should be noted that while the control system 5 has been described in terms of having various alternate functions such as a circumferential register control function or a lateral register control function, the control o system 5 is also capable of performing ~oth a circum-ferential and a lateral register control function within the same unit. To accomplish this, two circumferential marks could be sensed by Scanner A and two lateral marks could be sensed by Scanner B. The processor 7 could execute both the circumferent:ial command sequence and the lateral command sequence based on having received inter-rupt signals from the two sensors. Error signals could be supplied to two motors through ~he two motor drive ports shown in Fig. 2.
A plurality of the control system 5, each member of the plurality being associated with one of a serially arranged group of press units, may be connected together via the external eight-bit parallel data bus 20. Each of the control systems 5 which is linked to the parallel data bus 20 can send information to a remote means for super-vision along the data bus 20 or can receive information from the remote means for supervision from the data bus 20.
A selected digital processor 7, which is communicating with the remote means for supervision via the data bus 20, which is a means for transmission of selected data, has associated therewith manually setable address selection means 104.
Additionally, there is a disabling means 104a associated with each processor 7 which can take that control system 5 off of the external bus 20. When the disabling means 104a is operational, the associated control system 5 will not sense its address when it appears on the bus 20. A means for linking which could consist of a set of parallel wires connecting the data bus 20 between each member 5 of the plurality of control systems and a remote means for super-vision will enable each of the control systems 5 to communicate with thè remote means for supervision. The remote means for supQrvision could include a programmed digital processor or could be a hard wired device for receiving and transmitting data to and from the control systems 5.
One particularly important use of the remote means for supervision is to be able to send a new set of parameters to an addressed control system 5 to alter its control characteristics. These might include the size of the counts which are to be loaded into the window counters, such as the counters 51 or 53, or perhaps information to vary the preselected gain of a given control system 5.
Alternately, each of the control systems 5 which is linked to the remote means for supervision can be interrogated by that remote means for supervision to determine what its control parameters are and among other things what the si~e of the error is between the set point and the marks currently being sensed.
Attached hereto is a Table 3 which is a listing of the control codes which would be inserted into t~ read-only memory 13 to cause the control system 5 to function as a circumferentiàl register control. The circumferential register control program of Table 3 can function in either a mark-to-reference mode or a mark-to-mark mode of the types discussed previously in the specification. The mode of operation is determined by setting the base character-istics on the input port 17. Table 3 has a series of addresses whose four most significant hexidecimal digits will be found in the left-most column of Table 3. The least significant hexideclmal digit is represented by ~3B~

the top-most row in Table 3 extending hor.izontally from zero to F. The control code to be stored at each location defined by the left-most three hexidecimal digits in Table 3 in combination with the least significant hexi-decimal digit, extending hori.zontally across the top-most row of Table 3, will be founcl at the intersection of the row determined by the most significant three hexidecimal digits and the column determined by the least sign.ificant hexidecimal digit.
Table 4 represents a set of hexidecimal control codes which are inserted into the read-only memory 13 to cause the control system 5 to act in a mark-to-reference cut-off control mode as discussed previously. Table 4 is read exactly the same way as Table 3. Those entries in either Table 3 or Table 4 where no hexidecimal digits are shown represent storage locations in the read-only memory 13 which are not used.

~38~

~ABLE 3 ~3I ~-ls~er C~ntrol PAGE OI

: 5 OOI

003 C3 3F 00 C3BD 0~ C354 02 ES
00~ D5 F5 AFD3 C3 De 805F DBBO 57DB ~0 6F DB 40 005 67 D3 33 D3 3D C5 ~7 3A OD 22 E6 10 78 CA 6I 00 00~ 2F Es OICA D7 00 3A 7620 B7CA B7 DI 3D 32 76 003 2A 72 20 I9 EB 2A6320 I9DA ~D00 E8FI 87 CA

~ OOA AF fi4C2 A~ OI 3A7i20 95FA A6OI EB22 I5 22 : 15 OOB C3 B7 01 3A 56 20FEOB CADI 003~ A620 B7 C2 OOD EB 22 !I22 C3 B7 OI 3A ~ 20 47 3A 7B 20 B8 CA
: OOE B7 OI DAB7 OI 3D 32 7820 F5FB CDA2 DD EB 2~
OOF 72 20I9 EB 2A ~3 20 I9 D~ FC 00 E8 FI B7 CA 07 OII 3E ~0 D3C3 DB 8I5F DB8I 57D8 4I6E DB 4I 67 0I2 DB 33 D33F C5 473A OD22 E6iO 7BCA 30 OI 2F
0I3 E6 02 CA7C OI 3A7.720B7 CAB7OI 3D 32 77 20 0I6 76 01 E8 2A I9 22 CD 3A OD. AE B4 C2 BO 01 3~ 7I

OI9 A2 OD EB2A 74 20I9 EB2A 6320 I9DA AO Ol EB

OIB 3A77 20 3C 32 77 20 CI FI Dl EI FB C9 F5 3E 04 OID 47 02 3A OI 23E603 FE02 CA 2002 FE OI C2 ~7 : OIE 02 D3 38 CD 9602FE 04C2 04 02 CD 96 D2 B7 32 ~ 020 22 C3 00 00 FE OICC DA DC FE 02 CC EO OC FE 03 : 02I CC 90 OC FE 05 CC13 ODFE 08 CC BF OC C3 48 02 022 D6 ~B 2I 06 22 DE 3B 7E 23 32 00 23 D3 39 3A 02 023 23 E6 20 C2 3D 02 ~D C2 2E 02 C3 4B 02 3A 00 23 024 D5 C2 27 02C3 48 0200CI ~I EI3E 05 F3 32 03 025 23 FI FB C9F5 D5 E52~58 20 22SA 20 CD 3F OC
026 ~2 58 20 20F6 ~CEE 80 30 F~ 2A 5A 20 EB 2A 58 02B 3A 57 20 3C 32 5~ 20. CD 3C 03 20 E6 83 F6 4B F3 029 30 E ~ D I F I F3 C9 DE 3B 3A 02 23 E6 20 C2 A8 02 02A OD C2 9B 02 D1 C3 ~8 D2 3A OD 23 D3 38 C9 II 00 02B 00 2A 5E 20 CD CA OD ~D D7 02 CD CA OD CD CA OD
02C CD D~ 02 CD D7 02 CD CA OD CD D7 02 EB 3A OD 22 02D E6 80 C8 CDCA. ODC9 CD CA CD EB 19 EB C9 .F3 3I
5C 02E 50 20 CD ElD7 2I 03 00 7D 21 81 20 22 7F 20 EB
02F2I EA OD 23 23 4E 23 a6 23 EB 23 7- 23 70 23 EB

`

zo TABLE 3 (CO`ITINUED) ~31 l~s~ster CDntrol PAGE 02 O 1 2 3 q 5 ~5 7 8 9 A B C D E F
030 3D C2 F3 D2 Cl)02 D8r~ C3 25 03 2A 7F20 77 FB
031 23 D 173 23 72 2A ?F20 23 23 23 22 7F20 23 7E
032 23 B~SC2 78 03 21 8120 22 7F 20 2A 7F20 7E B7 033 C2 15 03 23 31 50 20SE 23 56 EB E9 E51 5 21 ~I
034 20 7E 87 F2 ~1703 3423 7E 23 B6 23 C241 03 Fl 035E I C9 3A 7A 20 32 7~20 32 7B 20 3A 5620 FE OC
0 036 C2 ~SC03 3A 7A 20 3217 20 32 79 20 CD~51 04 FA

039 20 C3 83 03 CD .76 04 22 D~ 22 22 1D22 2A 15 22 03A 22 19 22 2A 1.122 22~8 22 nA 8C 03 CD9D OB 3A
038 56 20 FE OC CC EF OB3E 00 32 A6 20 CDtSI 04 DA
03C 8C D3 FA 8C 03 CD 6104 Dl 8C 03 FA BC03 CD 61 03D 04 DA 8C 03 FA 8C D33EI B CD 9C 07 CDbl 04 FA
03E 02 04 DA IFB03 C2 OB04.3A A6 20 87 C27B 03 CD
03F B4 09 32 OB 22 CD 7A09 C3 I)C03 3A A620 B7 C2 041 3A C3 OB 04 CD 61 04CA~16 04 FA 4~504DA 46 04 0~2CD. B4 09 32 08 22 CDF6 09 CD 7A 09 47E6 7F 4F
043 3~ 52 20 81 F2 38 OAJl.F4F 7B E6 BO Bl32 20 22 046 . 03 El 22 9B 20 3E. 7F CD OB 03 3~ 90 20 B7 ~A 91 04720.I F 2A 98 20 E9 3A 5620 B7 CA CC 04 FE 08 CA

049EB2A I ~22 CD DB 04 D82A I 22 Ea 2A 15 22 CD
04ADB04 CO EB 2A 6~ 20 EBCD A2 OD C9 2A 19 22 EB
04B2A15 22 CD DB 04 D8 2A1.122 EB 2A 15 22 CD DB

04D2A1.1 22 CD DB 04 DB 2~1.122 C9 CD 3A OD B7 CO

04FC93E FF CD OB 03 CD 4109 ~F 32 90 20 06 08 2A
0505820 EB 2A 63 20 2B IS~DAt8 05 2A 5E 20 3A 60 05120a7 C2.~8 05 EB 2A 65.2D19 DA A8 05 06 04 2A
0526720 19 3E 08 DA 33 05CD C7 07 3E 01 32 9~$ 20 053C3~8 05 CD DO 07 AF 32g4 20 3A 0F 20 B7 CA 6C
4 054053D 32 8F 20 C3 D6 ~0'7 78 32 D3 22 3A 07 22 E6 0570332 OEI22 3A 07 22 F6D2 32 07 22 3A JM 20 .FE
95902C2 B4 OS 3Jl77 20 1.73A76 20 130C2 9F 05 2A
0597E120 36 t)O 3E 01 32 9320 32 92 20 C3 06 07 3A
- 05A~IE%0 ~7 .3A 10 22 90 FE03 DA 06 07 .3E 01 32 A6 05B20C3 O~S07 2A 11 22 EB2A 5B 20 CD 3A OD E17 C2 05C~906 EB 2A ~S920 CD A2OD DA 95 06 3A P3 20 B7 05DCAD~S 05 F2 95 06 3A A620 FE 01 CA IA 06 3E 01 5 0 05E32C~:~ 20 CD 5~DOB 3A 7~520~7 31l77 20 80 C2 45 ~.~43820 TABLI: 3 (Ct).~TI'11,3:D) Y3~ Re.,lstor Cc-nSrol PAGE 03 0603~ 00 AF 32 ~ 20 3E 03 CD DO 07 2A 15 22 22 19 06122 2A 1 J22 22 18 22 C3 ~5 06 3A 7A 20 32 76 20 05232 78 20 3A 56 20 FE OC C2 3~ 06 3A 71 20 32 77 0~320 32 79 20 CD ~3 OB 3E D2 32 A6 20 3A ID 22 32 064 8 20 C3 06 07 3E 01 32 91 20 05 00 lA 76 20 B7 055C~ 55 06 0~ 02 3A 77 20 B7 78 CA SF D6 F6 01 32 06B32 76 20 32 78 20 C3 95 06 3,~ 93 20 B7 FA 95 06 06~E8 2A 58 20 CD 3A OD B7 C2 CE 06 EB 2h 159 20 CD
O~BA2 OD DA DA 06 3A 92 20 87 CA BF 06 F2 DA 05 CD
06CEF OB 3A 7A 20 32 77 20 32 79 ~0 C3 DA 06 3A 92 06E07 3E 20 CD DO 07 3~ 07 22 F6 O~ 32 07 22 3A 94 06F20 B7 C2 06 .073A 05 22 B7 CA ~I D7 3E 01 32 90 07020 3E 0~ CD ~D 07 2~ 5C 20 EB 2~ 58 20 CD 31~ OD
0714.73/~ 8L)20 B7 78 32 BD 20 CA F 1 04 B7 C2 F 1 04 0723~ 10 22 3C 32 .ID22 C3 Fl 0:1 3E FF 32 90 20 3E
07304 CD h6 07 3E 20 CD C7 07 C9 CD 92 07 3E FF CD
074OB 03 3~ A5 20 4~ 3A A4 20 32 A5 20 AO ~7 DB 2B
07532 ~4 20 2F ~0 CA 6C 07 IF DC EO OC IF DC DA OC
D7~5 I F DC 90 OC I FDC 13 OD I F DC BF OC 3A JU 20 3D
077FA BF 07 32 A7 20 SA 86 D7 FE ~ 9 C2 8F 07 3E 03 0793D 07 C9 C5 47 3A ~A 20 BO C3 A3 07 C5 2F 47 3A
07AA~.20 AO 32 AA 20 D3 31 32 06 24 Cl C9 C5 47 3A

.07C D3 31 32 OS 24 Cl C9 C5 47 3A ~C 20 80 C3 D7 07 07DC5 2F 47 3A AC 20 ~0 32 AC 2D D3 31 32 03 24 C l 07EC9 Dl 21 00 20 Ql 00 02 AF 7.7 23 08 78 Bl C2 E8 080EB E9 3E 19 30.lE DllD3 2C 3E 6F D3 2D 3E CO D3 08128 3A IF 22 B7 C2 22 OB D8 29 .32. OC 22 DB 2A 32 08330 DB 33 E6 0~ CA 3D Q8 D3 3A C3 31 08 3E FF CD

0863E D5 32 03 23 2A OC 22 CD D5 OD CD l~FOD 32 50 OBAE5 3A OD 22 E6 80 2 IF6 OD C~ AF 08 2 IFE DD 06 08B04 5F 23 55 23 E3 73 23 :7223 E3 05 C2 a 1 08 E I
08C3A OD 22 E6 SO 21 '?C00 C~ CE 08 2 IFA 00 22 59 09D20 22 ~B 20 7D.OF 32 70 20 IF 32 7J 20 3A DD 22 08F20 3A 56 2D ~FEOC C2 FF Da 20 E6 J:EF6 08 30 CD

~438Z(;~

~ABLE 3 (CO.~lTII~UI:D) Y~l ae~lster Control I~ACJE 04 U 1 2 3 4 5 6 7 8 9 A e c D E F

0913E 14 F8 76 3D r2 13 09 F3 DB 30 E6 40 3E01 C2 09223 09 AF 32 6E 20 AF CD 33 09 3E 32 n3 433E 72 0~3D3 ~13 C9 D3 32 D3 34 AF D3 35 3E C3 D3 30D3 3B
t~94 C9 F5 3~ ~SE 20 87 C2 7B 09 3E 05 CD 9C07 DB 33 095E~ 08 C2 63 09 3A 6F 20 B7 3E 04 C2 60 093E 02 os~cn 93 D7 DE~33 E~ 10 C2 78 D9 3A 6F 20 B73E 02 DP7C2 75 09 3E 04 CD 93 07 Fl C9 C5 .FS47 E67F 4F

099A9 09 Fl Cl C9 F5 3E 19 CL)9C 07 Fl C9 F53E 01 O9AC3 AC 09 F5 3E 10 C3 AC 09 F5 3E OB cn 9509 CD
09B93 07 Fl C9 E5 1)52A 11 22 EB 3A 56 20 B7CA D7 09C09 2A 15 22 CD 3A on B7 C2 D3 09 EB 2A ~120 EB
O9DCLI~2 OD 22 ID 22 EB 2A 09 22 EB CD 3A OD11 81 09EFF 19 D2 E1309 21 00 00 tl 7F 00 19 B7 C~F2 09 09F3E 80 B5 Dl El C9 C5 D5 E5 4F E6 7F CA OCOA 79 2 0 OAOE6 80 ~7 3A A3 20 E~S80 AB C2 61 OA 21 9B20 3A
OAIV~ 20 5F 16 OD 19 3C J.7 3A 55 20 AO 32 9A20 46 OA279 E6 7F IF 77 2A 96 20 EB ~5826 00 CD A2OD 5F
OA3i6 0:) 19 22 96 20 3A 54 20 3D FA ~3 OA Cl)CA O;) OA4C~ 39 OA 79 Bl~ D2 ~9 OA 6F 7D B7 06 01 CA52 OA

OA6O~ 3A A3 20 EE BO 32 A3 20 7.9E6 7F 5F 1600 21 OA994 OA E6 BO 6F 3A A3 20 E6 80 32 A3 20 7DEl Dl OAACl C9 E5 D5 C5 F5 47 3A 6E 20 B7 CA C9 OA78 E6 OAC02 CA C6 OA 3E 04 CD 93 07 3A 6F ~0 B7 CAn4 0~\
OAD78 EE 80 47 2A OE 22 AF Ea 21 32 00 CD A2OD DA
O~EEB OA 3C FE OF DA D8 OA 07 07 4F 3A 53 2031) 81 OAF5F 16 00 21 06 OE 19 4E .78E6 7F CA 75 OBFE 06 OBOFA 05 OB 3E 06 5F .2146 OE 19 5E 79 C3 11OB E17 OBIIF ID F2 OF 08 4F .7BE6 80 Bl D3 .32.75 E67F CA
OB23E D3 5f 16 00 3A 53 20 21 00 00 19 3D C22B OB
OB37D D3 3~ 7C F6 80 D3 35 3E C3 D3 30 D3 3BFl Cl OB4Dl El C9 E5 D5 C5 F5 3E 01 32 6D 20 3 92 D3 C3 OB52A ~1 20 .7DD3 ~127C D3 82 7D D342 7C D3 42 2A
OB613 22 3A 56 20 FE 03 C2 ~D OB 2A 15 22 EBF3 CD
5~7~'4DC CD.3F OC CD 54 OC 3A 70 20 C6 D2 1600 5F
OBB19 22 72 20 22 74 20 7D D3 40 ~C D3 4D 7DD3 ~1 OB9. 7C D3 41 D3 3C D3 3E FEIFl Cl Dl E1 C9E5 D5 C5 OBAF5 3J~ 5tS2D FE OB C2 B4 OB 2A ID 22 EB 2A69 20 OBB19 22 6B 20 3E B2 D3 83 2A bEi20 7D D3 827C D3 OBDEB CD 74 OC CD 3F OC CD 54 OC 22 :7220 7DD3 40 09E7C Dl ~10D3 3C AF 32 aD 20 FB Fl Cl nl ElCQ E5 08FD5 C5 .F53E B2 D3 ~3 2~ 5B 2D 7D D3 42 7CD3 42 382~

TA~LE 3 ~co~lTI~ r~D) )3I ~lster C~ntrol PAGE 05 O J 2 3 4 5 o 7 8 9 A B C D E F
OCO F32/~I5 22 E~CD ?4 OC CD 49 OC CD 54 OC 22 74 OCI 207D D3 41.7CD3 41 D3 3E AF 32 6D 20 F~ FI CI
O-ZDl ElC9 F5 E5 3E3A 113 83 3E ?A D3 e3 2A ~I 20 or3 .?D D3 80 7CD3 BD 7D D3 8I ?C D3 BI EI FI C9 AF
OC4 D383 DB BO 6FDB 8D IS7C9 3E 40 D3 83 DB BI ~F

0^6 6I20 I9 EB 2A70 20 26 00 I9 CD 98 on E8 2A 6I
OC7 20I9 09 C9 2~5E 20 4C D6 00 cr)CA OD CD CA OD
OCB C[~CA OD CD CA OD CD CA. on o~ CD 98 OD 44 ~n C9 OC9 F53E 2B CD ~607 31 05 22 B7 3A 07 22C~, AE OC
OCA E603 32 D7 22AF ~2 D5 22 3E 08 C3 BA OC F6 04 OCB 3207 22 3E 0132 U5 22 3E 20 cn AD o? FI C9 Fs OCC 3A05 22 B7 C2D8 OC 3A A6 20 B7 C2 18 O^ 3E 0 1 O^D 32A6 20 2A 7B20 3~ 00 FI Cs 2I 02 oo C3 E3 oC
OCE 2IOI OI 22 ~820 F5 3A 05 22 B7 C~ Iî OD 2A A8 ODO 5020 26 00 CD67 DD F3 22 09 22 Fo ~E 32 32 ~7 ODI 20FI C9 3A 0522 B7 CO 2~ I~ 22 3A 56 20 B7 CA

OD3 2019 22 ~B 20 B 22 09 22 C9 C5 DS E5 CD A2 0~
OD4 D2~8 OD EB 2Aol 20 I9 4D 44 DI EI E5 CD ~2 OD
ODS D25B OD EB 2A61 20 I9 59 50 CD AD on3E OI DA
OD6 o4OD EB AF DICI C9 D5 F5 B7 C2 7E OD CD A2 OD
OD7 CDAD 0~ DA 7BOD EB 2A 6I 20 I9 F.In Ics 19 cn OD8 ADOD D~ 90 ODEB 2A 6I 20 CD ~D OD EB D2 95 OD
OD9 E52A 63 20 I9FI DI C9 F5 7n 2F 6F 7C 2F 67 23 ODA FIC9 C5 ~7 .7B45~F 7A 9C 67 78 Cl C9 C5 47 7D

ODC IF6F FI C9 F5EB 29 EB FI C9 F5 .7CE6 80 CD BA
ODD OD84 6? FI C97D CD CA OD CD CA OD E6 03 C9 E6 ODE 0747 AF 37 1.705F2 E4 OD C9 50 20 FI 04 50 20 OEI 3~5F 1.1 2I 3Ca4 I4 26 40 69 I7 2B 44 6E I9 2E
OE2 ~5.71IC 32 47JS IE 35 ~D.78 21 39 53 78 22 3C
OE3 547C 24 3F.567E 26 42 57 .7E 28 46 5B 7F 28 48 OE~ 59,7F28 4B 5A7F 08 D3 03 D2 02 OI 00 OEA
OEB
OEC
OED
OEE
OEF

~3t320 TABL~ 4 ~31 CU -C~S CDntro~ PAGE 01 0 12 3 ~ 516 7 8 9 A B C DE F
O O;) C3 F2 01 0041)5 F5 AF D3 C3 D8 80 5F DB 80 57 DB 40 6F DB .10 00720 F: OC B7 FAB3 00 B5 C b3 D0 CD oeDA E3 2A

~ 47 3A ?2 20 E~8 CA DB o221 ID2 C3 DE 003.~ 71 20 0 DE~ 22 13 22 C~ DEo203A9 7E~20A62 20 19 D~Dl 00 00EDl El FB C9 F5 3E04 32 0323 F~ C~ D5 E53A 00 00F23 4F 3A 01 23 473A 05 22i37 C2 ~4 01 3~OD 22 010E6 B0 C2 1~ 01 79OF OF OFOF ~Eo OF IF 78OF OF
011OF OF~17 E6 F0 81~IF.7B E6DF 47 AF t:D 5001 3A
0120D 22 E6 '30 C2 2E01 EB CD~9 0A C`3 3201 CD BF
013pA EB 2A $2 2D 19CD 5D OA22 09 22 22 1522 3E
01401 32 AO 20 El DlCl 3E D5F3 32 03 23 FlFB C9 01521 00 00 11 10 27CD 6E 017a 11 E8 03 CD76 01 017C8 19 3D C3 6E 0IFE DA D8~C9D76 01 IE 01FE 00 01856 20 CD 50 02 20E6 83 F648 F3 30 1 DlFl F8 01ECD EB 01 fi BF DCD EB 01EB C9 C 8F DEB IS~

D2373 2 23 FE 2 Dl73 23 722A 75 FD C3 3902 A
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TABLF 4 (CO:ITI;~UED~
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03703 2~ 66 2019 3E IO DA 8503 CD 5F 05 3EOI 32 0338D 20 C3 gA03 CD ~B 05 ~F32 sn 20 3A 5g20 B7 03,~ 2~ 74 2036 00 3E 20 CD6B 05 3E 0~ 32B~ 20 C3 03C03 2A 74 203h 00 3E D~ 328C 20 C3 BC 043~ B8 03D20 47 3A 8720 90 .FE D5 D~BC Od 3E OI 329F 20 03cC3 BC 04 2~I J 22 EB 2A 5720 CD FF 09 B7C2 BC
03F04 EB 2A ~820 CD 67 OA DA.98 0~ 3A 8C 20B7 CA
04005 0~ F2 9804 3A 9F 20 FEOI CA Aa 04 3EOI 32 0~,1 8C 20 CDD6 OB .3A ~J 20B7 C2 62 04 3A.73 20 32 0427 I20 32 .7220 3A AO 20 FED2 CJ~3 I04 AF32 AO

044I.I22 22 I522 C3 9F 04 3A73 20 32 7I 2032 72 04732 AO 20 3E20 CD 5F D5 CDEl 04 2A 74 2036 00 049F~ 98 04 ~EFF 32 BC 20 3A3B 20 B7 C2 BC04 3E
04AOB CD ~B ~3t. 8D 20 B7 C2BC 04 3A 05 22B7 CA
04BB7 04 3E OI32 ôA 20 3E 02CD 5F 05 2A 5B20 EB
04C2A 57 20 CDFF 09 ~7 3A 8620 B8 CA 47 0378 32 04D86 20 3~ ~720 3C 32 87 20C3 47 03 3E FF32 8A
04E20 3E 02 CD~8 05 3E 08 CD5F 05 C9 CD 4405 3E

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05 I BA 09 I FDC 70 09 J FDCF3 09 I FDC 9F09 3A Al D5220 3D FA 4 I05 32 .~ I 20 CA3~ 05 FE I 9 C24 I OS

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055~7 3~ A~, 20AO 32 A4 20 D331 32 06 24 CIC9 C5 056~7 3t.A5 2030 C3. ~F 05 C52F 47 3A AS 20AO 32 1~57 A5 20 D33I 32 05 24 ClC9 Dl 2I 00 200~ 00 02 058AF 77 23 OB7B 9 I C2 80 D521 7A 20 23 ~323 22 05974 20 2~ 2323 22 7~ 20 EB.E9 3E i9 30 3EDA D3 05932 OD 22 DB2B E~ 20 32 6C20 3E C13D3 30DB 33 05CE~ 0-1 C~. C~t)5 D3 3A C3 BE05 3E FF CD AE05 CD

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o~l 3~ 52 20 rD 9A 0~ 3C 32 53 20 CD 9A OA 32 54 20 D~3 2I BB DA CA 39 D6 2I C3 OA 06 ~4 5E 23 56 23 E3 064 73 23 72 23 E3 05 C2 3B D6 El 3A OD 22 E6 40 21 065 3E 00 C~ 58 06 21 IC 00 22 6B 20 7D OF 32 6D 20 065 IF ~2 ~E 20 3E 01 32 73 20 CD 18 09 CD 2A 09 22 067 57 20 22 SB 20 3E OA CO 99 06 3E 14 FB 7s 3D C2 o~ 7D 0~ F3 DB 30 E6 ~0 3E 0I C2 8D C6 AF 32 ~B 20 06A 3E C3 D3 30 D3 3B C9 F5 3A 6B 20 ~7 C2 DE 06 3E
06B OA CD 4E 05 DB 33 E6 OB C2 C4 06 3A ~C 20 B7 3E
06C 02 C2 C6 ~6 3E 08 CD 45 05 DB 33 E6 JO C2 DE 06 06D 3A 6C 20 B7 3E 08 C2 ~B 06 3E 02 CD 45 D5 Fl C9 06E C5 F5 ~7 E6 7F ~F 3A 51 20 89 F4 03 07 F2 F8 06 06r 78 B7 F4 09 07 FC OF 07 F1 C1 C9 F5 3E 15 cn 4E
070 D5 F1 C9 F5 3E D4 C3 12 07 F~ 3E 0I C3 12 07 F5 072 2A 1.1 22 CD FF 09 11 81 FF .19 D2 30 07 21 00 00 073 .11 7F 00 19 B7 CA 3A D7 3E 80 35 Dl El C9 C5 D5 074 ES ~F E~ 7F CA 54 07 .79 E6 BO 47 3A 9C 20 E6 80 075 AB C2 A9 07 21 94 20 3A 93 20 5F ~6 00 19 3C 47 077 EB 6B 2~ 00 CI) 67 DA 5F J6 00 I9 22 8F 20 3A 54 078 20 3D FA BB 07 CD ~F OA C3 81 07 79 BD D2 91 07 079 6F 7D B7 06 0I CA 9A 07 06 00 3A 9C 20 E6 ao BO

07B 20 .79 .E6 7F 5F 16 00 21 94 20 3A 55 20 73 23 3n D?E E6 80 32 9C 20 7D E1 Dl Cl C9 E5 D5 C5 F5 47 3A

OBO 05 C3 11 08 78 E6 8D 3E 02 CA OE 08 3E 08 CD ~5 081 05 3A 6C 20 a7 CA IC 09 7a EE 80 47 2A OE 22 AF

D83 07 D7 4F 3A 53 20 3D 81 SF 16 00 21 ~B OA 19 4E
084 ~8 E6 ~F CA 5D OB .FE 06 FA 4D 08 3E 06 5F 21 OB
OB5. OB 19 SE 79 C3 59 08 B7 .IF In F2 57 oa 4F .78 Eb D86 80 Bl D3 32. 78 E6 7F CA B6 OB SF 16 00 3A B3 20 088 3E C3 D3 30 D3 38 F.l Cl Dl E1 C9 5 D5 C5 F5 3A
: 45 089 5A 20 87 3E 01 32 6A 20 C2 C7 OB 3E 82 D3 Y3 2A
08A 60 ~0 ~D D3 82 7C n3 82 2A 11 22 EB F3 CD 54 09 08B CD 2A D9 CD 3~ 09 EB 2A 68 20 19 2~ 6F 20 7D D3 08C ~0- 7C D3 40 C3 CE OB DB 33 E6 20 CA Dl OB D3 3C
.OBD FB F~ Cl Dl 1 C9 E5 D5 C5 F5 3E B2 D3 83 2A 6B
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~31 ~ut-c~ ContrDl PAGc 04 O I 2 3 4 5 6 7 8 9 A B r D E F
090CD 34 0922 6F 20 7D D3 40 7C D3 40 D3 3c AF 32 0~`16A 20 FBFl Cl DI EI C9 F5 E5 3E 3A D3 B3 2A 60 09220 .7D D380 7C D3 30 EI FI C9 AF D3 83 DB 80 6F
093DB BO ~7C9 CD FF 09 B7 CA 4309 CD 5D OA EB 2A
: 094 60 2D I9EB 2A 6D 20 26 00 19 CD 5D OA EB 2A 60 : 09j 20 I9 09C9 2A 5D 20 4C 06 00 CD BF OA CD 6F OA
096 cn 8F OA CD. 8F OA CD 8F OA 09 CD 5D 0~ ~4 ~D C9 097 F5 3E05 CD ~B 05 3A OS 22 B7 3~ 07 22 CA BE 09 099 32 07 22 3E OI 32 05 22 3E O.I CD 5F DS FI C9 F5 ~)9B 32 9F 20 2A 74 20 30 00 Fl C9 21 DB 00 C3 C3 09 09C 2I 02 O.I 22A2 20 .F5 3A 05 22 B7 CA .tI 09 2A A2 O9E 50 20 26 OD CD 2C OA F3 22 09 22 FB 3E 32 32 ~I
09F 20 FI C9 3A 05 22 E~7 CO 2A II 22 22 09 22 C9 C5 OAO D5 E5 CD57 OA D2 OD DA EB 2A 60 20 1.94D 44 DI
t)A.I EI E5CD157 OA D2 ID OA EB 2A 60 20 19 59 50 CD
OA2 72 OA 3EOI DA 29 OA E8 AF Dl CI C9 1)5F5 B7 C2 OA3 43 OA CD67 OA CD 72 OA DA 40 0~ EB 2~ 60 20 19 OA4 F.l DIC9 I9 CD 72 OA DA 55 OA EB 2A ~0 20 CD 72 OA5 OA EB D25~ OA EB 2A 62 20 I9 Fl ~I Cg F5 7D 2F
OA6 bF 7C 2F67 23 FI C9 C5 47 7B 95 6F 71 9C 67 78 OA7 CI C9 C547 7n 93 7C 9A~J8 CI C9 F5 29 Fl C9 F5 01',8 B7 7f`IF67 7D IF ISFFI C9 .FS EB 29 E5 .FI C9 F5 OAA OA E6 03CD E6 07 47 AF 37 I7 05 F2 A9 0~ C9 50 OA3 20 47 0350 20 66 02 50 20 EC ~-I DO 07 30 F8 A8 OAC Fl) EFFF 88 13 78 EC 24 FA D6 FF 00 00 00 00 OE

OAE 2B 44 6EI9 2E 45 7I lC 32 17 .75 1E 35 4D 78 2I
OAF 39 53 7B22 3C 54 7C 24 3F~ 50 7E 26 42 57 7E 28 OBO 46 58 7F 28 48 59. 7F 28 4B 5A 7F 08 03 93 02 02 OBS

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~3820 While various modifications and suggestions might be proposed by those skilled in the art, it will be understood that we wish to include within the patent warranted hereon all such modi.fications and suggestions and changes as reasonably come within our contribution to the art.

Claims (34)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A control system for determining the relative location of an indicia on a web, detected by a means for sensing, with respect to a set-point as the web moves in a selected direction across a rotating cylinder in a printing or cut-off unit, the control system comprising: means for selecting an inspection window length, for each revolution of the cylinder, said selected inspection window length corresponds to a selected amount of rotation of the cylinder; means for enabling the means for sensing starting at a previously selected cylinder position and for said selected amount of cylinder rotation corresponding to said length of said inspection window; means for determing the location of an indicia on the web sensed while the means for sensing was enabled; means for storing said determined location of the sensed indicia; means for establishing a selected cylinder position, to be used during the next revolution of the cylinder; said selected cylinder position corresponds to said determined location of the sensed web indicia reduced by a selected amount of cylinder rotation;
means for comparing the set-point to said determined loca-tion of the sensed indicia.

2. The control system according to claim 1 inclu-ding further: a parallel, bi-directional, means for trans-mission of data connected between said means for determining the location of the indicia on the web and said means for storing.

3. The control system according to claim 2 including further: means for selecting a new set-point corresponding to a selected point located anywhere on the circumference of the cylinder.

4. The control system according to claim 3 in-cluding further: means for communication, connected to said means for transmission of data, to receive selected data from or to transmit selected data to a means for supervision.

5. The control system according to claim 3 including further: means for forming an error value, with a sign, proportional to the difference between the set-point and said determined location of the sensed indicia; means for sensing said error value and for driving a means for compensation connected to the printing or cut-off unit, so as to minimize said error value.

6. The control system according to claim 5 wherein said means for forming an error value includes:
means for forming a running average error, with a sign, based on the latest error value and a selected number of error values formed during each of a corresponding number of prior revolutions of the cylinder.

7. The control system according to claim 6 wherein said means for forming a running average includes further: means to compare the magnitude of the running average error to the magnitude of the most recent error value and to select the smaller magnitude as a base error value and to associate the sign of the most recent error value with the base error value.

8. The control system according to claim 6 wherein said means for forming an error value includes further: means for adjusting said running average error value to compensate for the rotary speed of the cylinder and for a preselected system gain.

9. The control system according to claim 4 includ-ing further: means to store selected control system parameters during a time interval when power has been removed from said control system to permit said control system to be restarted with said selected parameters once power has been restored.

10. A control system for determining the relative location of members of a plurality of marks previously placed on a moving web, with respect to a set-point, the marks are sensed by a web sensor as the web moves in a selected direction across a rotating cylinder, the control system comprising: means to establish a length of an inspection window, corresponding to a selected amount of cylinder rotation, for each revolution of the cylinder;
means to enable the web sensor, starting when a reference mark on the cylinder is at a previously selected point during the present rotation of the cylinder, and for an amount of rotation corresponding to said length of said inspection window; means for determining the location of a sensed mark from said plurality of marks on the web sensed during the time interval when the web sensor is enabled;
means for determining a selected point to be used to enable the web sensor during the next revolution of the cylinder; means for comparing the set-point to said deter-mined location of the sensed mark.

11. The control system according to claim 10, including: manually operable means to establish a new set-point and wherein said means to establish the length of an inspection window includes means to dynamically enlarge the length of the inspection window to a select maximum value while a new set-point is being established.

12. The control system according to claim 11, wherein: said means to establish the length of an inspec-tion window includes means to dynamically shorten the length of the inspection window from said selected maximum value to a preselected, smaller, value, once a new set-point has been established.

13. The control system according to claim 10, including: means for receiving selected operating para-meters from a selected supervisory apparatus and means for sending selected operating parameters to the supervisory apparatus.

14. The control system according to claim 13, including a manually setable means for establishing an initial set of control system operating parameters.

15. The control system according to claim 13, including: means to form an error value based on a differ-ence between the set-point and the determined location of the sensed mark and, drive means, connected to a compensa-tor element which is adapted to vary the relative location of the sensed mark with respect to the set-point, said drive means is responsive to said error value to adjust the compensator element so as to minimize said error value.

16. The control system according to claim 10, wherein the set-point corresponds to a difference between two selected set-point marks and wherein members of two pluralities of marks on the web are to be sensed, the control system comprising further: means for determining the location of a second sensed mark, from said second plurality of marks, sensed during the time interval when the web sensor is enabled; means for forming a difference between said two determined locations and for comparing that difference to the difference between the two selected set-point marks.

17. The control system according to claim 16 including further: means to form an error value based on a difference between said two determined locations and the difference between the two selected-set-point marks;
drive means, connected to the compensator means adapted to vary the difference between said two determined locations, said drive means is responsive to said error value to adjust the compensator means to minimize said error value.

18. A control system for determining the relative location of an indicia on a web, detected by a means for sensing, with respect to a set-point as the web moves in a selected direction across a rotating cylinder in a printing or cut-off unit, the control system comprising: means for digital processing; bi-directional, parallel means for data communication connected to said digital processor; means for storing a plurality of selected command sequences, said means for storing is connected to said means for data communication; said means for storing said command sequences is adapted such that each of said selected command sequences is accessible by said processor but said command sequences can not be altered by said digital processor; read-write means for storing data, said read-write means for storing is connected to said means for data communication, said read-write means for storing stores selected data such that each piece of selected data is accessible and alter-able by said processor; manually setable data input means, connected to said means for data communication, and adapted to be manually setable to establish selected operating parameters; bi-directional external communication means, connected to said bi-directional parallel means for data communication, and adapted to transmit data to or receive selected data from an external means for supervision;
means for supplying an error signal to a drive means, said means for supplying is connected to said bi-directional means for data communication; means for continuously determining the location of the cylinder with respect to a reference, connected to said bi-directional means for data communication; first means for establishing an amount of cylinder rotation during which the means for sensing is to be enabled, said first means is connected to said bi-directional means for data communication and is dynami-cally alterable by said digital processor during each revo-lution of the cylinder; first means for determining a selected rotary position of the cylinder at which the means for sensing is to be enabled during a given revolution of the cylinder, said first means for determining is connected to said bi-directional means for data communica-tion and is dynamically alterable by said digital processor during each revolution of the cylinder; said means for digital processing is adapted to cooperate with said read-write means for storing data, said first means for estab-lishing and said first means for determining to: enable the means for sensing starting from said selected rotary posi-tion of the cylinder for a period of time corresponding to the amount of cylinder rotation established by said first means for establishing, to, subsequently determine the location of the indicia on the web detected while the means for sensing is enabled, to subsequently compare the set-point to the determined location of the indicia on the web and to subsequently determine a selected rotary position of the cylinder, to be used by said first means for determining on the next revolution of the cylinder, as the rotary position at which the sensing means is to be enabled.

19. The control system according to claim 18 for determining the off-set between two indicia on the web detected by the means for sensing and a second means for sensing and for comparing the off-set to the off-set between the set-point and a second set-point, the control system including further: second means for establishing an amount of cylinder rotation during which the second means for sensing is to be enabled, said second means is connected to said bi-directional means for data communication and is dynamically alterable by said digital processor during each revolution of the cylinder; second means for determining a second selected rotary position of the cylinder at which the second means for sensing is to be enabled, during a given revolution of the cylinder; said second means for determining is connected to said bi-directional means for data communication and is dynamically alterable by said digital processor during each revolution of the cylinder;
said means for digital processing is further adapted to:
enable the second means for sensing starting from said second selected rotary position of the cylinder for a period of time corresponding to the amount of cylinder rotation established by said second means for establishing, to subsequently determine the location of the second indicia on the web detected while the second means for sensing is enabled, to subsequently compare the offset between the set-point and a second set-point to the offset between the determined locations of the first and second indicia on the web, and to subsequently determine first and second selected rotary positions of the cylinder, to be used by said first and second means for determining on the next revolution on the cylinder, as the rotary posi-tion at which the sensing means and the second sensing means are to be enabled.

20. A method to continuously control the location of a plurality of marks on a web, sensed by a web sensor, with respect to a set-point as the web moves in a selected direction across a rotating cylinder comprising the steps of:
selecting, for each revolution of the cylinder, an amount of cylinder ortation during which the web will be examined for the presence of a mark; enabling the web sensor at a previously determined cylinder position for the selected amount of cylinder rotation; sensing a mark while the web sensor is enabled; determining the position of the mark sensed while the web sensor is enabled; comparing the position of the sensed mark to the set-point; adjusting a compensation means to minimize any difference between the position of the sensed mark and the set-point; and determining a cylinder position, whereat the web sensor is to be enabled on the next revolution of the cylinder, based on the most recently determined location of the sensed mark on the web.

21. The method according to claim 20, wherein the step of adjusting the compensator means includes the steps of: forming an error value, having a sign and a magnitude, based on the difference between the location of the sensed mark and the set-point; averaging the most recent error value with error values determined during a selected number of previous, consecutive, cylinder rotations; comparing the magnitude of the most recently formed average error to the magnitude of the most recent error value and selecting the smaller magnitude as a base error value; associating with the base error the sign of the most recent error value;
comparing the sign of the most recently formed base error to the sign of the base error formed during the preceding revolution of the cylinder and setting the magnitude of the present base error to zero if said two signs are different;
modifying the average error value based on at least a preselected value of system gain; driving the compensation means, based on the modified average error value, to minimize the difference between the set-point and the position of the sensed mark.

22. The method according to claim 21, wherein the average error value is modified, based on both the sensed speed of the cylinder and the pre-selected value of system gain.

23. A method of mark-to-mark register control to control the difference between corresponding members of two pluralities of marks on a web, sensed by first and second web sensors, as compared to the difference between two set-point marks as the web, moves in a selected direction across a rotating cylinder comprising the steps of: selecting for each revolution of the cylinder, first and second amounts of cylinder rotation during which the web will be examined for the presence of a mark; enabling the first web sensor at a first, previously determined, cylinder position for the first amount of cylinder rotation; determining the position of a mark, in the first plurality of marks, sensed while the first sensor is enabled; enabling the second web sensor at a second, previously determined, cylinder position for the second amount of cylinder rotation; determining the position of a mark, in the second plurality of marks sensed while the second sensor is enabled; forming a difference between the positions of the two sensed marks; comparing the formed difference in the positions of said two sensed marks to the difference in the positions of the two set-point marks;
adjusting a compensation means to minimize any variation between the two compared differences; determining first and second cylinder positions whereat the first and second web sensors are to be enabled on the next revolution of the cylinder, based on the most recently determined locations of the sensed marks on the web.

24. The control system according to claim 18 wherein said means for supplying an error signal to a drive means comprises: electronic means to rotate an output shaft of a compensator motor through an angular displace-ment proportional to the magnitude of said error signal.

25. The control system according to claim 18 wherein said means for supplying an error signal comprises:
electronic servo means to rotate an output shaft of a compensator motor at an angular velocity proportional to the magnitude of said error signal.

26. The control system according to claim 25, where-in said electronic servo means includes feedback means to supply a signal to said means for digital processing indi-cating actual rotation of the output shaft of the compen-sator motor.

27. A multi-computer press control system for use with a plurality of serially arranged press units adapted to apply indicia of various colors to a moving web including:

a plurality of digital processing units; each member of said plurality is associated with a press unit and includes at least, digital means for processing; digital storage means; means for sensing a set of manually input control system parameters; means for sensing, in real-time, signals from the associated press unit; bi-directional, digital, parallel bus means for communication connected to, said digital means for processing, said digital storage means, said means for sensing a set of manually input control system parameters, and said means for sensing in real-time;
means for transmission of selected data, under the control of said digital means for processing, connected to said parallel bus means, each of said means for transmission includes a manually setable address selection means adapted to be manually set to specify a selected address for said control unit; means for linking, adapted to be connected to said means for transmission of each of said press control units; means for supervision, connected to said means for linking, and adapted to transmit an address, along said means for linking, to be sensed by a press control unit with a corresponding, preset address, said means for supervision includes means to transmit a command to said addressed press control unit requesting said addressed press control unit to send selected data to said supervisory means or to receive selected data from said supervisory means.

28. The press control system according to claim 27 wherein: at least some of said digital processing units include means for driving a compensator motor connected to the associated press unit to minimize registration errors in the associated press unit.

29. The press control system according to claim 27 wherein said address selection means includes manually setable means to inhibit recognition of said previously selected address.

30. The press control system according to claim 27 wherein an addressed digital processing unit includes means to sense a command, sent by said means for super-vision, to send selected data to said means for super-vision; collect said requested, selected, data and transmit said data to said means for supervision.

31. The press control system according to claim 27 wherein an addressed digital processing unit includes means:
to sense a command, sent by said means for supervision, to receive selected data from said means for supervision, to receive said selected data from said means for supervision and to replace previous parameter values of said addressed digital processing unit with said received data from said means for supervision.

32. The press control system according to claim 30 wherein: a selected one of said digital processing units is a quality control monitoring unit and includes: means to sense the registration of indicia of various colors previously applied to the web, means to store data indica-tive of said sensed registration connected to said means to sense the registration, and upon sensing a command sent by said supervisory means, to send selected data, to send said stored data indicative of said sensed registration to said means for supervision.

33. The press control system according to claim 32, wherein said means for supervision includes means for visually displaying said data indicative of said sensed registration.

34. The press control system according to claim 31, wherein said means for supervision includes manually setable means to enter said selected data to be sent from said means for supervision to said addressed digital processing unit.