CA1148252A - Solid state digital audio scrambler system for teletransmission of audio intelligence through a television system - Google Patents

Abstract

31 47,601 ABSTRACT OF THE DISCLOSURE
An audio scrambler digitally samples a continu-ous audio signal, scrambles the derived samples and in-serts at least one scrambled sample in the unoccupied region of the video signals of a video system for trans-mission line per line as an analog composite audio-video signal. A RAM device is used for this purpose which has the digital samples stored sequentially, then read at ran-dom. A special memory arrangement is used as a scratchpad in order to insure that while addressing the RAM at random there will be no repetition, nor omission of a particular address. Provision is made for the insertion of more than one sample per video line, in-particular while transmit-ting severe audio signals on the same video system. The same technique is used at the receiver end for unscram-bling the samples once extracted from the video lines.

Description

1 47,601 SOLID STAT~ DIGITAL AUDIO SCRAMBLER
SYSTEM FOR TELETRANSMISSION OF AUDIO
INTELLIGENCE THROUGH A TELEVISION SYSTEM
BACKGROUND OF T~IE INVENTION
The invention relates to encryption apparatus for audio communication through a television system. Audio security is as important as video security. With the advent of satellite links, private two-way audio channels - that can be associated with a video channel are desirable, for instance for business teleconferences. Secure audio scramblers are already known for telephone lines. With video channels, however, advantage can be taken of the television system facilities to reduce the cost of scramb-ling the audio signal in particular by using the randomiz-ing and synchronizing capability of video scramblers already present. Also, speech quality in the scrambling-descrambling process may be improved so as to exceed the telephone-line bandwidth. It is also important to allow for more than one audio system with the same installation.
It is known to scramble a digit stream as part of a video digital transmission system. See for instance "Digital Transmission Techniques" by G.M. Drury pp. 37-49 20 in IBA Technical Review (Great Br~itain) 1976 Vol. 9.
It is known from United Sta-tes Patent 3,958,077 of J. Ross et al. to generate pseudo-random numbers with digital shift registers. The patent also shows how to perform pseudo-random scanning in a television system.
In a scrambled television system, U.S. Patent No. 3~717~20~ of V. R. ~opf et al. shows that for sub-: ' ' ~, ., . ~

.

2 47,~
scription purposes coded signals have been associated ~it~l the transmitted video signals. This is also shGwn fo-r unscrambling in U.S. Patent No. 4,070,693 of H. B. Shut-terly.
A pseudo-random genera-tor is disclosed in U.S.
Patent No. 3,681,708 oE M. E. Olmstead.
It is known from U.S. Patent No. 3,105,114 of W.
Koenig to divide into segments a signal and to introduce selected time delays be-tween such segments for scrambling effect.
U.S. Patent No. 3,659,0~6 of Angleri et al. dis-closes a message, in binary form, being scrambled in a psuedo-random fashion by logically combining bits.
From U.S. Patent No. 3,731,197 of J. E. Clark it is known to sample an information-bearing signal and to read the samples in a prearranged abnormal order to obtain unintelligible secured signals.
U.S. Patent No. 3,824,467 of R. C. French shows an audio signal divided into segments which are rearranged into a new sequence before transmission. Encoding-decoding is provided by binary pseudo-random addressing of storage devices. Each storage device transmits its stored time element while storing a new time element.
U.S. Patent No. 3,921,151 of G. Guanella teaches dividing an audio signal into segments of equal time intervals which are temporarily stored. Scrambling of the segments by reading-out in a random pattern is achieved so that at each location there is no repetition, nor omis-sion.

3 U.S. Patent No. 3,773,977 of G. Guanella, which patent is related to aforementioned U.S. Patent No.
3,921,151, shows the use of coinciding aperiodic cipher signals from which control signals are derived for deter-mining the storage elements, together with automatic monitoring of the occupancy to avoid omissions, or repe-ti-tions.
It is known from U.S. Patent No. 3,819,852 of Peter ~olf to transmit an audio signal in -time-compressed ~ 5 ~ 47,~1 form during the period o-f a line in the vertical blankin~
interval of a television system.
The object of the present invention is to add an audio scrambler to a television system, while using to a maximum extent the video installation for sc~ambling and unscrambling in the transmission and reception of an audio message.
SU~ARY OF THE INVENTION
The invention resides in sampling an audio signal to derive samples at a rate which is proportional to the video line rate; in scrambling at random the order of such samples; and in inserting at least one of the scrambled samples into an unoccupied portion of each of the video line signals being transmitted. The synchroni-zation p-ulses of the video system are used to clock the sampling, scrambling and inserting steps of such scram-bling process.
According to the invention, in a television system transmitting video line signals during successive television fields separated by vertical blanking spaces, apparatus is provided for scrambling a continuous audio signal derived from an audio source. The apparatus in-cludes means for sampling the continuous audio signal at a rate which is proportional to the rate of the video lines.
Thus, in a 525-line standard video system where, typi-cally, 480 samples are being sensed per time frame of 1/30 sec., two alternate sample storage devices of 240 loca-tions each are used. The sampling ra-te will be 480/525 time the television video line rate. This means that all 3 the samples can be read-out in 1/60 sec. from each storage device, alternately, while there is a one-to-one relation-ship be-tween the video lines being transmitted and the inserted samples. It is also possible to extract twice, or three times this number of samples and to establish a relation of 2 to 1, or 3 to 1, with respect to the occur-ring video lines.
When scrambling, the samples are reordered in accordance with a pseudo-random pattern, and they are z

4 47,~1 successively inserted, while being read out in such scram~
bled order from the storage devices, into each of the passing video lines, one, two or even three at a time, as earlier-mentioned.
The insertion of one, or more samples, is ef-fected within an unoccupied portion, e.g. blanking level, of the video signal, thus, after the synchronization interval and the color burst, and before -the front edge of the active line, or video signal proper, thereby taking advantage of the unoccupied region which in the standard 525 lines video system, for instance, starts, approxi-mately, 9 ~ s after the horizontal pulse has been initi-ated.
The unscrambling process follows at the receiver , 15 end the exact reverse procedure. The audio samples are iextracted one-by-one from the video signals, they are assembled to form a segment after being unscrambled and put together ~ reordered to reconstruct the original continuous audio signal.
The scrambling and unscrambling method is pre-ferably achieved through digital techniques, taking advan-tage of binary treatment and the use of solid state de-vices, such as RAM devices and PROM devices, as will appear from a consideration, hereinafter, of -the preferred embodiment of the invention.
Another object of the invention is to provide digital ~udio scrambler in a television system in which digital treatment is organized around a central control ; logic, preferably a microprocessor, for sorting out binary 3 samples of audio at random and for inserting at least one sample in each video signal as it is being transmitted.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 shows curves which are typical (a) of a segment of audio signal; (b) of the derived audio samples;
-35 (c) of the scrambled samples; and (d) of the video signal after insertion of one audio sample;
Figure 2 is the audio scrambler according to the invention at the transmitter side of a television system;

z 47,~1 Figure 3 shows with curves key instants esta~-lished hy the timer of Figure 2 ~*e~ for storing, reading and latching of samples;
Figures 4A and 4B show.,at ~e television field

- 5 scale7the timing ~n the insertion process;
Figure 5 shows circuitry of the television system coupled with the insertion circuitry of the audio scrambler;
Figure 6 is the audio unscrambler according to the invention as applied at the receiver side of the television system in correlation with the audio scrambler of Figure 2;
Figure 7 shows with curves two modes of insert-ing three audio samples into a video line;
Figure 8 shows circuitry used in the context of Figure 7 for inserting three consecutive audio samples in one video signal where three audio sources are to be transmitted; and Figure 9 shows the timing of the command signals used in Figure 8 for the insertion of three consecutive samples.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Apparatus has been designed for concurrently performing within a television system the following opera-tions:
sampling of a continuous audio signal;
scrambling of the derived samples; and inserting into each video line at least one of the scrambled samples.
The operations are achieved in synchronism with the occurrence of the video lines, and the insertion is effected within a non-occupied por-tion of each transmitted video signal.
Referring to Figure 1, curve (a) shows a segment of audio signal AB, which is 1/60 sec. long. Curve (b) indicates 240 audio samples derived from the segment AB of audio under (a). Curve (c) represents scrambled samples derived after curve (b). Curve (c) shows one audio sample ~ ~7,~01 inserted at the beginning of a video line already includ-ing a synchronizing pulse and a color b-ust. The active portion lasts 51.4 microseconds and follows a 9.9 micro-seconds interval, including the 1.~ sec. synchronizing pulse signal. It appears from curve (d) that a three microsecond interval is available for the insertion into the video line of at least one scrambled sample, in accor-dance with the present invention.
Referring to Figure 2, it will now be shown 1) how the audio signal segment AB~ received on line 55, is being sampled; 2) how -the derived samples are being scram-bled; and 3) how the insertion of a scrambled saMple takes place in timing with the occurrence of an available space within a video line.
5The circuit of Figure 2 comprises the following sections:
An audio sampling section centered around the phase locked loop PLL and circuits 51, 52 which are a sample and hold circuit, and an analog-to-digital conver-ter, respectively.
A sample scrambling section centered around random address counter 72 and random access memory 61.
The samples from the audio sampling section are initially ~ stored in a first in-first out (FlFO)memory 53, which - 25 operates as a buffer eleme~t between the sampling opera--tion and the sequential ordering of the sample into ~AM
61. Scrambling results from reading at random the samples stored into ~AM 61. Sequential s-toring is effected when a data selector 175 is in mode B for addressing the RAM, while random reading is performed by addressing the RAM
through data selec-tor 175 in the mode A.
Figure 2 includes also a timer section which is synchronized with a monovibrator 122 of 5 ~s delay and a monovibrator 123 of 50 ~s delay, both triggered by a horizontal pulse H at the rate of the video lines. The timer action establishes permissible and prohibited time intervals for stages of operation of the sample scrambling section in relation to the horizontal pulse and the field z 7 47,~1 of scanning.
A clock signal of 7-16 MHz appears on line 8 for clocking the addressing process.
Figure 2 also includes a microprocessing section centered around microprocessor 100 and control program ROM
module 110. This section conditions the reading, scram-bling and insertion operations within the permissible time intervals established by the timing section.
The interface between the video signals and audio samples for insertion and transmission is shown in Figure 4.
The sample and hold circuit 51 of Figure 2 receives the audio signal from line 55 through a 6 kHz low pass filter 56. The samples are converted into digital numbers by A/~ converter 52, and such digital numbers are temporarily stored into a first-in first-out (FlFO) device 53, starting with the vertical blanking pulse. Device 53 is read out under control from line 92 on a first-in first-out basis (FlFO). Circuits 51, 52 and 53 are clocked from line 58 at a frequency of 14.4 kHz by a clock signal obtained from a phase-locked loop (PLL), itself fed with a 7.16 MHz signal from line 57.
The stored samples are read continuously from FlFO device 53 to be stored sequentially (sequential coun-ter 151 and date selector 175 in mode B) into a Random Access Memory (RAM) 61. RAM 61 is in two sections, alter-nately used for storing and reading like taught in U.S.
Patent No. 4,070,693 of Shutterly.
Typically A/D converter 52 is a solid state device known as DATEL EHlOB providing 8 bits per sample.
The FlFO device 53 is of the type 3351 having 40 x 9 locations~ The two RAM sections of circuit 61 are ob-tained from a single solid s-tate device known as "Memory-Nine F93415 RAMSI' having: a data input pin 15 multiplexed wi~h the nine output terminals of the FlFO device (shown by lines 59 and 60~; a data output pin 7 connected to the 8 bit input (line 91 in Figure 2) from a Por-t #5 and a Port #2; a 9-bit address (8 bits on line 165 from data 5~
8 47,6~1 selector 175, plus one most significant bit on line 165' from exclusive OR gate 152 for determining which of the two sections of the RAM is to be used) on pins 2-6, and 9-12.
RAM device 61 stores the samples received from line 60 in their natural order into locations defined by a Write-address received from sequential counter 151 and via line 153 from data selector 175, in the Write-mode (B~.
In order to effect scrambling, these samples, when read-out, are extracted in a random fashion as given by the addresses from Random ROM 174 through data selector 175 in the P~ead-mode A. The way such randomness is achieved will now be described by reference to Random Access Counter 72 and Random ROM 174.
A random code on line 71 causes Random Access Counter 72 to output on lines 73, 74 and 75 an 8-bit address which is at random. However, it is necessary to avoid, for true randomness, tha-t one location in the Random Access Memory 61 be sought and used twice, or that one be omitted, since all the samples read out from FlF0 53 must be stored in and read out of the RAM univocally in whatever order. It is observed here that Random ROM 174 is responsive via line 73 to Random Address Counter 72 and that it outputs into RAM 61, when data selector 175 is in the A mode. Circuit 174 is used to dissociate the random-ness of the audio scrambling from the randomness of the code of line 71 which may be used elsewhere, for instance for scrambling the video.
~ hile using a different approach, the method of preventing repetitions or omissions in the address of line 73, is similar in concept to what is disclosed in the aforementioned Patent No. 3,921,151 of Guanella. A dis-tinctive feature is found, however, in the way two Address Memory devices 76, 77 are used as scratch pads, alter-nately, to store from 74 and 75, respectively, the randomaddress proposed by circuit 72, on line 73. Alternation in the operation of devices 76, 77 is obtained by lines 158, 156, respectively, which have opposite binary bi-ts.

9 ~7,601 One memory stores, while the other is under er~s-ure. rh~
outputs 78, 79 from the memories are checked by h~TD de-vices 80, 81, respectively, against the bits of lines lSg 3 159. When a duplication occurs between the binary state to be stored and the binary state already at the location, AND gate 80 (or 81), OR gate 84 (by line 82, or 83) and, AND gate 86 (via line 85), pass the clock signal of line 88, thereby to clock and advance Random Access Counter 72.
Random Access Counter 72 will thus be advanced to the next location each time a location is found to be already "occupied" as a result of a previously operative addres~, and such advance will be repeated until an "empty" loca-tion has been found.
Referring to the curves of Figure 3, the H-pulse of line 121 establishes on the front edge thereof an initial time from which a 5 ~s delay (curve (d)) and a 50 ~s delay (curve (e)) are generated by the respective monovibrator 122, 123 of Figure 2. The random code number (which may be derived from a random generator used to scramble the video signals) is formed on line ~ . It appears as an 8-bit word ready for setting counter 72 after a delay shown by curve (b). When the 5 ~s delay has taken place (curve (e)), by line 124 the random number is stored into counter 72. For all the 240 lines of one field of scanning (one is the odd numbered lines, the other for the even numbered lines) as established by the vertical rate pulse of line 154 and the field period flip-flop 155, the most significant bit of the RAM address is determined and passed through Exclusive-OR gate 152 onto line 165'. The status of line 165'is shown by c-urves (h) or ~i) of Figure 3. Data selector 175 changes from the B mode into the A mode after 50 ~s, by lines 126 and 148. As a resultg as shown by curve (g) the sample indi-cated by the address is derived from lines 91 and 128 at ~ 35 the request of the microprocessor.
- The insertion of a sample concurrently with the occurrence of a video line, requires consideration of the timer section of Figure 2.

' . ' ;

z 47~01 Timing for the insertion of the audio samples into the outgoing TV lines is determined b~ counting cycles of the 7.16 MHz clock of lines 88, 133 by reference to the beginning of each TV line as indicated by the H-pulse of line 121. The 5 ~ sec. monovibrator 122 sets a flip-flop Timer 131 to start clocking from line 133, via AND gate 132, an 8-bit Counter 135 which by line 134 has been initiall~ set to count 64. Count 128 is detected at 137 to set a flip-flop timer 141, and count 142 is de-tected at 138 to reset the flip-flop timer 141, while resetting by line 139 the flip-flop timer 131. This results in opening by line 143 an AND gate 144 to produce on line 146 an Insert Audio signal. The timing of counter 135 and timer 141 establishes a window starting exactly 9 ~s after the H-pulse, e.g., the window matches the unoccupied portion of the vi,deo line (see Figure 1). Now, a sample latched in latch 102 of Figure 2 is derived for insertion from outpu-t line 105, when the insertion is permitted by the window of line 146, as will be shown hereinafter.
As seen from microprocessor 100 through Ports #l to #5, the control logic is as follows:
The outputted data on line 91 are passed through Port #5 onto the 8-bit data bus 101 of microprocessor 100.
The sample after processing by the microprocessor is passed through Port #4 to be stored into audio output latch 102, as an 8-bit word. From there, as earlier mentioned, insertion takes place by line 105. The logic for enabling the insertion is by line 145 through Port #3.
This decision takes into account the signal of line 125 which is indicative of an occurring video line and the signal of line 127 which is indicative of the vertical blanking space, both received through Port #2. Port #2 also receives the signal of line 126 which au-thorizes the address search, and informs the processor when to call for the sample of the RAM -from lines 91 and 128. Port #3 transmits more commands from microprocessor 100. One of these is the address clock of line 160 for Address Mem-8'~ ~Z
11 47,601 ories 76, 77, ~nd sequential counter 151, by 161. Port ~3, by lines 95 and 166, al~o causes clocking of the addresses in Random Address Counter 72 and wrlting at the addressed locations of the FlF0 data ~rom line 60. By line 92 the stored samples are clocked out of FlF0 53.
Lines 93 and 94 load the multiplier code latch 103 and the audio output latch, respectively.
Referring to Canadian patent application Serial No. 348,578 filed March 27, 1980 by Harold B. Shutterly, Figure 2 also shows a feature ~or reducing noise in the transmission of t~e samples inserted by the audio scrambler.
To this e~fect, the microproces~or call~9 via Port #1 ~nd line 59, ~or the samples stor~d in the FlF0 circuit 53.
These are treated digitally and logically by the micropro-cessor in accordance with the control program module 110.From an evaluation o~ the samples deri~ed within 1/60 s~c., (i.e., segment AB) which form a gro~p to be scrambled by : the Random Access Memory 617 the microprocessor establishes the average signal and calculates a correction factor applied discriminately to the ~ample~. This operation is g~ted via Port ~1, by lines 92 ~nd 149, and the result is a multiplied 8-bit ~ample and a ~-bit multiplier code which are passed by Port #4 onto line 104. The multiplier code is latched into multiplier code latch 103 to be sent on line 106 for trans-mission as a code to be u~ed in reverse when a cor-rective factor will be applied to the audio data at th~
receiver end.
The o~erall scheme ~or audio sample scrambling and audio s~mple insertion in the video lines wlll now be explained in detail in the light of the foregoing con-siderations by reference to the elements of the circuitry of Figure 2~
The ~crambling of the audio signal is produced by ~ampling the input s~gnal at a sufficiently high fre-quency (line 58) to preserve the signal content, and thentransmltting the æa~ples in a pseudo-random order. me audio signal is bandlimited to 6 kHz and then sampled at a ~825Z
12 47,601 rate of 14,400 samples per ~econd, with the result that 240 samples are produced in each one-~ixtieth o~ a second corresponding to a ~ield period (circuit 155~ Each group of 240 samples is first-stored in F1F0 circuit 53, then collected in the random-access memory 61, to be read out of the memory in the ~ollowing one-sixtieth of a second in a pseudo~random order. m e proces~ i5 continuous so that in each one-sixtieth of a second 240 new samples are collected in one section o~ the memory, while the 240 previous samples are read out from the other section of the memory~ A completely di~erent pseudo-random readout sequence i~ used ~or eaoh group of 240 samples.
The samples are tran~mitted in analog form as part of the scrambled TV waveform. In the illustration o~
15 Figure 2 9 each group of 240 samples is transmitted in one TV field at a rate of one sample per active TY line. Each audio sample is inserted at the beginning of a TV line, following the color burst tFigure 1).
The effect o~ re-ordering the audio samples in an essentially random ~ashion i~ to convert the slgnal into a noise-like form that contains none of the frequency characteristics required for intelligibility.
Descramblin~ at an authorized receiv~ iæ accom-pllshed by reversing the scrambling process. The samples are recovered from the received video and then sorte~ out In groups of 240 per ~ield by a random-access memory. Pseudo-random addressing o~ th~ memory during the storage process restores the order o~ the sample~ in the memory to the original sequence. The descrambled audio is then obtained by reading the s mples out o~ the memory in -~3 13 ~7,601 consecutive order and srnoothing them in a lowpass filter.
There are three primary factors that contribute to the high level of security of this scrambling techni-que:
51. The minimal size of the signal elements that are interchanged. Individual signal samples, once out of sequence, provide little~ or no information7 about the original neighboring samples; there is no "slope" or other correlation information present.
102. The range of positional interchange is over a time period of one-sixtieth of a second. Consequently, any frequency component down to 60 Hz can be completely ~4~ destroyed by the pseudo-random sample interchange.
3. The use of a completely different pseudo-random interchange sequence in each one-sixtieth of a second. This very greatly increases the difficulty of unauthorized descrambling by trial and error methods. If a given one-sixtieth of a second audio segment can be descrambled, no informa-tion is obtained about the correct sample sequence in other segments. More importantly, if several one-sixtieths of a second segments of audio be descrambled simultaneously in order to obtain a recog-nizable sound, the number of possible sample orders to be tried increases exponently with the number of segments.
25One important feature of this scrambling techni-que is that the processing time delay required both for scrambling and ~escrambling is only one-sixtieth of a second, or 16.67 milliseconds. On a two-way satellite communication link the total loop delay due to scrambling 3Oand descrambling is 4 x 16.67 or 66.68 milliseconds. This is important becawse experiments have shown that two-way voice communication is impaired -for total loop delays greater than 600 milliseconds. The subjective effect of longer delays has been described by Bell Labs as "sticky"
communications. Since the round trip propagation time for satellite links is about ~80 milliseconds, it is essential for this application that the processing delays for scram-bling and descrambling be as small as possible.

82 S~
14 47,601 The audio scrambler samples ~he input audio signal 240 times in each TV ~ield period and stores the samples in order into a memory. m e samples that are stored in one field period are read out in the next ~ield period in a random order and transmitted at a rate of one per active TV line.
As shown in Figure 2, by the phase locked loop circuit PLL, the input audio signal from line 55 is band limited to frequencies below 6 kHz and is sampled at a rate of 14.4 kHz. The audio sampling clock i~ generated by means of the phase-lockedloop PLL driven ~rom a 7.16 MHz clockO This clock signal can be generated ~ithin the video scrambler if the system provideæ for video scrambling.
Such clocking arrangement produces exactly 240 audio samples during each TV field period. The samples are converted from analog form to 9-bit digital words which are stored initially into the ~irst-in? first-out memory (F1F0) circuit 53. Curcuit 53 acts as a buffer between the input samples and the remainder of the scrambling system. The samples are processed at TV line rate during the active lines of each TV field period~
The readout o~ audio samples ~rom circuit 53 is controlled by microproces~or (100) by means of a clock pulse o~ line 92 from Port #~. Typically~ mlcroprocessor 100 1s a 8 x 300 device~ m e microprocessor uses the H-pulse o~ line 121 ~derived from the ~ideo line sync) and the Vertical Interval signal o~ line 127, as timlng re~er-ences~ The H-pulse triggers the 5 sec. monovibrator 122 which produces on line 125 a "Beginning of Line" signal to ~0 Port #2. me pre~ence of this signal on l~ne 125, in the ab~ence of a Vertical Interval signal on line 127~ indi-cates to the microprocessor an active ~ideo line.
In general~ at the beginning of an active line the microprocessor clocks a sample out o~ the F1~0 circuit 53 and, Yia the ~Irite Enable signal of line 166 from Port ~3, loads the sample into the RA~I (Random Access Memory) 61. The output of the 50 sec. monovibrator 123 holds data selector 175 in the B mode~ so that the Rl~l is addressed by the Sequential Counter 151 duri~g loading o~ each 47,~01 sample from the F1F0 circuit 53. The Se~uential Counter 151 is reset on line 159 by the Vertical Rate pulse ~rom the video scrambler~ so that sequential addressing can start at zero at the beginning of each TV ~ield period.
Sequential counter 151 ls advanced by the microprocessor ~ia line 161 by one count near the end of each active line until, at count 239~ the 240th sample is loaded into RU~1I 61.
Each sample ~rom F1F0 circuit 53 is also loaded via line 59 into the microproces~or, via Port #1. In accordance with the teachings of the aforementio~ed copend-ing application, the microprocessor determines the maximum amplitude m~ltiplier for noise reduction. When all of the 240 samples have been evaluated, the microprocessor contains a lis~ (in ~ym~olic ~orm) o~ all the multipliers that are applicable to one, or more, o~ the 240 sam~les. For example, i~ multipliers 4, 16, and 32 are in the list, this indicates tha-t all o~ the 240 sample amplitude~ in RAM 61 can be multiplied by 4, while soms can be multi-plied ~y 16 and some by 329 Since the smallest multiplier is 4, in thls instance, ~t i5 the multiplier applicable to all the amples. It is 4 ~rhich is retained for use during the sample multiplication process~ The multiplication takes place ln the microproce~sor during the read-out of the samples from RAM 61.
Althou~h RA~ 61 has 1024 locations of 9-bits, it is actually div~ded ~nto two memory section~ uslng only 240 locations in each section. me sections are used al~ernately~ During each field period, one memory sectio~
stores 240 samples in sequence 9 ~hile 240 sample~ are be~ng read-~ut ~n p~eudo-random order from the other memory sectionO The most lgn~icant bit (MSB) in the R~
address, which appear~ on line 165', is u~ed to swltch RAM 61 between the tW9 memory sections~ me output of the 50,4sec. monovibrator 123 goes to Exclusive-OR de~ice 152 together wlth the output of the Field period flip~flsp 155 to produce the MSB addres3 bit o~ line 165. In each active video line period, one sample is written into the memory section which has been selected during the 50,4sec. pulse.
~, ,.

16 47,~
After this, the other memory section i5 selected ~or writing and one sarnple is read out from the first one.
The effect of the field period signal on lines 157 and 165, (whic~ reverses at field rate, ( curves (h) (i) of Figure 3) is to interchange the two memories at field rate. Thus the memory section written into during one field period is read-out during the next, etc.
The pseudo-random addresses used in reading out samples from R~M 61 are determined by pseudo-random num-bers which are assumed to be generated in a random-code-generator for video scrambling. The random code numbers are fed by line 71 into Random Address Counter 72. At the beginning of each video line, the count of the Random Address Counter 72 is preset to the current 8-bit pseudo-random number from the video scrambler. The counteroutput addresses two 256 ~ 1 bit Address Memories 76, 77 and a Random ROM 174 that, in turn,`addresses RAM 61 through Data Selector 175 when the latter is the A mode (curve (f) of Figure 3). The Random ROM 174 contains the numbers 0 to 239 arranged in a randomly selected sequence.
When addressed by the Random Address Counter 72 -the ROM
merely interchanges each address in the range 0 to 239 with another address in the same range. This totally dissociates the audio scrambling code from the video scrambling code.
The two Address Memories 76, 77 are used as aforesaid to prevent any pseudo-random read-out address from being used more than once in a given field period.
Since they have 256 locations, a detector 170 is used to reset circuit 72 when 240 locations have been used. The 8-bit numbers that are preset (see curve (c) in Fig. 3) into the Random Address Counter 78 are essentially random, and consequently there is nothing to prevent any parti-cular number ~rom occurring several times during the read-out of 240 samples from RAM 61. If this happened, one or more samples stored in the R~M would be read out several times, while other samples would not be read out at all. To prevent this, a record is kept in the Address ~` ~
~8 Z ~
17 47,601 Memories 76, 77 of each address used to read-out a ~a~ple.
~nese Address Memories are used alternately, one in one ~ield period, the other in the next field period. The data inputs to the two memories are provided by the com-5 plementary outputs on lines 158, 156 o~ the Field Period flip-flop 155. The record is kept by storing a "1l' at each address that ls used ~or accessing a sample from the RAM. After a sample has been read from R~M 61 into Port #5 by microprocessor 100, a Write Enable signal is sent via line 160 to clock both Address Memories, via Port #~.
Consequently, a "1" is written (on line 158 for instance) into the active memory~ whlle a "0" is (on line 156 in this case) written into the inactive memory. mux, as the active Address Memory is gradually being ~illed during the RAM read-out process, the alternate Address Memory is being cleared for use in the next field period.
~hen the Random Addre~s Counter 72 is preset (curve (c) of Fig. 3) to an address that has been used previously in the same ~ield period, the active Address 20 Memory opens AND Gate 86, thereby permitting the 7.16 MHz clock to advance via line 87 the Random Addres~ Counter 72 to the next address. Clocking continues until an unused address is reached. me Address memory, then, closes AND
Gate 86.
me process o~ searching ~or the next random address is initiated by the microprocessor during the 5 ~sec~'~eginning o~ Line" signal on line 125 (curve (d) o~
F1g. 3). The Write Enable ~ignal of line 166 that stores a sample ~rom F1F0 circuit 53 in RAM 61 also initiates by line 95 the addre~s search by ~etti~g Random Search ~lip-96. mi~ remo~es an inhibit si~nal from ~ND Gate 86, whlch permits clocking of the Random Address Counter 72 by the 7.16 MEIz clock signal o~ line 88.
During clocking of the Random Address Counter 72, the addres~ may be advanced beyond 239 into the 240 to 255 range. A150 the counter may be preset initially to a count beyond 239. Since there are no samples stored outside of the 0 to 239 r~nge o~ the RAM, an out-of-range ,~

Z

Detector 170 is used to reset the Random Addre~3 Counter to zero~ the search then continues for a valid, unused address.
The maximum search time required to locate a valid address is 35.7,xsec. The remainder of the 50 ~sec.
Delay can therefore be used by the microprocessor in each active TV line period as an indication that the Rl~ is addressed by a valid address. A sample is then read (see curve (g) in Fig. 3) into the microprocessor via Port #5 and Port ~2. The amplltude o~ each sample is, there, multiplied by the multiplier which has been determined from the group of 240 sa~ples as it was stored into the RAM during the pre~ious field periodO Each multiplied sample is outputted through Port #4 to the Audio Output Latch 102, where it is held ~or insertion at the beginning of the next video line.
While ~igure 3 shows with curves, b~ reference io an H-p~lse, the ~ampling and scrambling proce~s at the scale of the video lines, Figures 4A and 4B æhow the overall proceæs at the sc~le o~ the video frames for successive audio segments AB and A'B', each 1~60 sec.
long~ Figure 4A shows the vertical blanklng space. Fig-ure 4B shows two successive fields of a ~ideo frame. The operative steps are readily recognized from a considera-tion of the steps of Flgure ~ and the explanations alreadypro~ided.
The insertion of one digital sample in a ~ideo line will now be considered by reference to lines 105 and 146 o~ Figure 2 and to the block diagram of Figure 5 which ~hows the interface be~ween the video lines to be trans-mitted and the audio sample to be lnserted~ Referring to Figure 5, sync separator 22 detects the horizontal pulse from the video signal o~ line 21, which triggers a hori-z~ntal pulse generator 24 providing on lines 2~ and 121 ths H-pul~e signal sf Figure 2. The H-pulse is sho~
inputted vla line 121 into the 9f~s delay timer of Figure 2 providing one input to ~ND device 144 ~rom which is outputted on line 146 the Insert Audio 5ample Signal of Figure 2~ Signal 19 47,601 VERT whlch determlnes the vertical blQnk~ng space o~
Figure 4A is, as generally known, der~ved by counting at 30 the video lines in a Yideo frame defined by frame pulse generator 26. Counter 30 is inputting into four detec-tors: 32 detects line 522, 33 detects line 17, 34 detects line 259, and 35 detect~ line 280. Flip-flops 36 and 37, associated with the fir~t and second pair of detectors, go into OR device 44 to generate th~ blanking ~pace pulses YERT on line 45 wh~ch a~ter inverting to ~ERT are gating on line 145 AND gate 144~
The video signal of line 21 is converted into digital by A/D converter 47~ The in~ertion of the audlo samples ~nto the outgoing video lines is e~fected digital-ly. m e timing is determined by counting cycles of the 7~16 MHz clock from the begi~nlng o~ each video line (H-pulse). The audio sample from line 105 is inserted in response to signal 146 switching a data selector 31 from the 8-bit video signal o~ line 48 to the output 105 of the Audio Output Latch 102. The audio sample is converted from digital-to-analog form, along with the video signal, in the video D/A converter 38. At count 142 by detector 138 FFl Timer flip-flop 131 (Fig. 2) FF2 and Timer flip-flop 141 (Fig. 2) are reset to end the audio insertion. me wlndow for insertion o~ an audio sample has a duration of approximately 2 ~ sec., which provides a margin of error for locating the samples in the descrambler of approximately ~5 ~sec.
~ro additional signals are also inserted in the ~crambled video signal~
One is th~ multipller factor K, mentioned in the a~oremen~ioned co-p~nding application, which is trans-mitted aæ a 3-bit code along with the video synchroniza-tlon ~nformatlon. It i~ inserted during the vertical interval immediately preceding the actiYe TV lines con-taining the audlo 3amples that are multiplied ~y the factor K, m e 3-bit code representing the multiplier is trang~erred from the microprocessor via Port ~4 to the Multlplier Code Latch 130, from where lt is automatically lnserted via llne 106 by means o~ a conventional circuitry 4~ 5~
47,~01 within the ~ideo system~
The other additional signal is an artificial audio sample also explained in the aforementioned copend-ing application. Generated by hhe microprocessor this additional signal is set to the mean audio signal level M
~171 i~ the range is ~rom 0 to 255). Transmission o~ this reference-level sample is possible because there are actually 242 active TV lines in each field~ thus two more than the number of lines used for insertion of an audio sample. me first ac~ive line in each field is not used ~or audio transmissionO When this i5 the case, the Insert Audio signal of line 146 is blocked by an inhibit signal appearing on line 145 from the microprocessor thus block-ing the AND Gate 144~ The second active line i~ used to transmit the reference~level sample M in the same way as any o~ the audio sample~
In essence the audio descrambler reverses the process used in the scr~mbler9 where audio samples are written into a memory in sequence and then read out in pseudo-random order~ In the descrambler~ a~ter the sam-ples are recovered from the received scrambled TV wave-form, they are ~itten into a memory in pseudo-random order and then read out in se~uence. This returns the samples to the correct sequential order to produce the descrambled audio signal.
Figure 6 is a block dlagram o~ the audio de-scrambler which at the receiver side of the television system corresponds to the audio scrambler of Figure 2 ~or the transmitter. Blocks which indicate a similar function in the reverse process have been given, wherever possible, the same reference ~umeral raised by 200 where the re~erence numeral o~ Fig. 2 has one or two digits~ raised by 100 where it has three digits. Thus, the equivalent of the Random Address Counter 72 is now 272,while Random Access Memory 61 becomes 261, vertical rate pulse line 154 is 254, and so on.
An understanding o~ the circuit of Figure 6 is straightforward in the llght o~ the explanations given ~or the audio scrambler circuitry o~ Figure 2. Some original feat~res in the audio unscrambler should, how-21 47,601 ever, be mentioned as ~ollows:
In the audio descrambling system o~ Figure 6, the input signal consists of 8-bit video signal samples, at a 14.32 I~Hz data rate which are derived on line 203 ~fter conversion to digital form (the A/D converter is not shown)~ The video samples that represent the audio pulse on each active video llne are located at the exact time by means of a digital timer. m e timer sectio~
comprises circuit elements 2227 223, 231, 232, 235 and 241.
mey are very similar to those of the timer in the audio scrambler of Fig~ 2. me timer starts at the H-pulse and counts 67 cycles of the 7.16 MHz clock of line 288, then initiates the loading o~ input signal samples.
Alternate samples are latched into an Audio Sample Latch 204 by means of a properly timed 7.16 MHz clock~ Each latched s~mple is then transferred to an Input F1F0 (first-in, f$rst-out memory) circuit 353. In each active video line, the ~npu~ F1F0 circuit 353 stsres the video samples representing the received audio pulse until they can be processed by the microprocessor. It automa~ically blocks out further inputs when it is full.
As a result, 16 samples are selected from the 920 samples scanned at a 14.32 ~Hz rate along the ~deo signals, ~Jhich coincide in time with the passing of the inserted audio sample within the window defined by the timer section. Of these 16 samples, the mlcroprocessor retains only one of every two. Thus, the microprocessor 200 individually clocks eight video samples (representing one audio sample~ out of the Input FlF0 circuit 35~ by line 354, into Port ~1 then, into the microprocessor. The eight sample~ are summed up and divided by eight. Thls lmproves the signal-to-noise ratio o~ the received sample. The ~irst such audio ~ample recei~ed in each field is the reference signal set to the mean audio signal level. This particular signal is stored in the microprocessor and is used, before dividing the amplitudes of the following audio samples. The divisor that is used is specified by the 3-bit multiplier code which had been transmitted. A
~.

2 S~
22 47,601 new multiplier code appllcable to a new segment o~ audio is loaded into Port #2 of the microprocessor during each vertical interval~ A "Multiplier Code Ready" s~gnal ~s supplied to the microprocessor via Port #2 -to initiate the loading of each multiplier.
The search for a pseudo-random addres~ for the Random Access Memory (RAM) 261 proceeds in parallel with the integration of the input video samples and the ampli-tude division process in the microprocessor. me pseudo-random addresses are generated in exactly the same manneras for the audio scrambler of Figure 2. The random code genera~or typically is one used in a video descrambler, It is synchroni7ed with the generator in the associated video scrambler and so produces an ldentical sequence of numbers. ~sing these numbers as starting points, the audio descrambler generates a ~equence ~ pæeudo-random addresses that are identical to those generated in the audio scrambler~ The microprocessor 200 use~ the end of the 50~ sec. period derived from monovibrator 223 on line 226, as an indication that a valid p~eudo-random address has be~n found in each actlve video line. The microprocessor then loads a processed audio sample, via Port ~4 and line 205, into RAM 261 at the selected address. Since the address is the sam0 address that was u~ed ln the scrambler to read the sample from a ~ ~, this process returns each sample to its original ~equential order within RhM 261.
Like in the audio scrambler o~ Figure 2, RAM 261 is operated as two separate 240 sample memories~ In each field per~od, while one memory is loaded with 240 samples using pseudo-random addre3ses, ~he second memory ls read o~t sequentially. RAM 261 is addressed by a Sequential Counter 251 during the 50~ sec. delay period, and the microprocessor clocks (via Port ~3) one sample ~rom the ~AM into Output Msmory (F1F0) circu~t 253 at the beginning of each active ~ideo line. The samples are clocked into ; circuit Z53 at line rate and ar~ clocked out at a uniform rate of 14.4 kHz~ Again, this is just the reverse of the process used in the audio scrambler of Fig. 2.
~' ~8Z5Z

The output clock on line 25~ is generated by me~ns of a phase locked loop PLL in exactly the same l,lay that the input F1F0 clock o~ line 58 is generated in the audio scrambler o~ Figure 2. me 9-bit samples ~rom the Output F1F0 circuit 253 are converted into analog by a D/A
converter 352, the output is lowpass filtered at 356 to recover the original baseband audio signal.
The invantion provides for the use o~ more than one audio signal to be transmitted, and/or the transmis-sion o~ more than one audio sample inserted in each videollne. For these designs 7 the ~ollowing considerations apply:
The first consideration in extending the current signal secure audio channel system to two or three secure channels is the format of the æcrambled output signal.
The most direct extension of the aforestated ~ormat is to add one additional audio pulse on each active TV line ~or each additional audio channel; this format is illustrated in Figure 7 by curve (a).
This arrangement, however~ can result in cross-talk between the audlo channels ~ecause o~ the limited time available on each line ~or audio pulses~ Typically 9 the single-channel audio system just described uses approximate-ly ~sec. for the single audio pulse on eaoh active line.
mis allows for 1~sec. of pulse lntegratio~ at the reoeiver to improve the signal-to-noise ratio~, and + 0~5 sec. for positional tolerance~ The line time available ~or audio pulses con~ists of part of the line blanking period and part of both ends o~ the acti~e llne period. m e ends of the active line can be deleted because they are not seen due to overscanning on TV monitors, m e maximum tlme that can be used for audio i8 about 3~sec., since 105~sec.
are already used for repeating video samples in the scram-bled video waveform. I~ sec. audio pul~es are used in a three-channel system, the receiver integration time will probably have to be cut to 0.5~4secO, and the pulse posi-tioning requirements will be quite critical i~ crosstalk is to be avoidedO
, ,~
,~ }, . . ~, ~ S~
2~ 47,~01 The crosstalk problem can be avoided by the format indicated by curve (b) of Figure 7. Here eacln active TV line carries three consec-]tive samples ~for a three-channel system) of only one of the audio si~nals.
This format can be produced by using a pseudo-random ad-dress to locate the first sample in the RAM and then following it with the next -two samples in sequence.
With this format, any crosstalk between samples is equivalent to a small reduction in bandwidth and will not effect intelligibility. This is true for crosstalk caused by timing errors in the descrambler as well as for signal transient effects. If, for example, eight video samples are integrated in the descrambler -to forrn one audio sample, a timing error might result in six video samples from one of the input audio pulses being added to two video samples from an adjacent audio pulse. Since contiguous samples are usually similar in amplitude, this crosstalk would have little effect except for some atten-uation of the highest audio frequencies.
There are different ways in which -the audio samples can be interlaced in the TV field with this for-mat. One is simply to alternate the audio signals; that is, one active line contains three samples of audio #l;
the next line, three samples of audio #2; the next line, three samples of audio #3, etc. A second way would be to divide each TV field into -three audio fields; the first 80 lines carry 240 samples of audio #1, the second 80 lines carry 240 samples of audio #2, etc.
Referring to Figure 8, a block diagram shows how the circuit of Figure 2 can be modified for the insertion of three consecutive samples, with three audio sources providing three different continuous audio signals.
Referring to Figure 8, circuitry is shown for storing audio samples into RAM 61 from three different audio sources, A-udio #1, Audio #2 and Audio #3, and for deriving three consecutive samples of each audio source after scrambling in-to RAM 61, each triplet of samples being inser-ted in an occurring video line after latching 47,~01 into audio output latch 102 and when insertion is trig-gered by line 146. Only relevant portions of the cir-cuitry of Figure 2 have been shown in Figure g. hll circuit elements relative to the timer section have been, for the sake of clarity, represented by one block respon-sive to the H-pulse of line 121 and outputting the proper 9 microsecond delayed signal on line 143 to ~D ~ate 144.
The microprocessor is shown with the data bus 101 and all its Ports. The distinctive portions are as follows:
The three audio sources are sampled by respec-tive sampling circuits, each equivalen-t to the combination of sample and hold circuit 51 and A/D converter 52 of Figure 2. The sample clock contains the phase locked loop PLL and is the same as in Figure 2, being common to the three audio channels. This clock also controls three FlF0 circuits 53', 53 " and 53 "' which are the same as circuit 53 of Figure 2. A data s~elect~r 404 derives three consec-`' utive samples from the ~ in each successive positions corresponding to inputs 401, 402, 403, thereby to output 20 three samples on lines 59 and 60 to Port #1 and to RAM 61 like in Figure 2. The three positions of data selector ; 404 correspond to three successive video lines. These are defined by two bit lines 410, 411 from a 2-bit ring coun-ter 407 triggered by the H-pulse. The ring counter estab-lishes three successive states due to AND device 412 which in a feedback loop resets the counter after each succes-sion of three sta-tes. A multiplexer 405 responds to three pulses on line 92 from the microprocessor (like in Figure 2~ to derive three control lines 92', 92 " , 92 " ' for the respective FlF0 (instead of one per video line, or H-pulse, in Figure 2). RAM 61 has been chosen to have 204 locations capacity, thereby to allow 240 samples to be stored, or read-out, in a 256 x 4 = 1024 array with an eleven-bit address. The most significant bit (MSB) is on 35 line 165' (like in Figure 2), the 8-bit address defines the locations for storage or random read-out and the 2 additional bits are in fact the least significant bits used to identify the three consecutive samples of the 26 47~60 curren~ video line. Insertion of the ~irst sample takes place automatically ~Ihen by l~ne 146 the ~lindow is initiated. me microprocessor knows starting of ~he window n~ne microseconds from the B-pul~e (see Figure 9) by line 414 from line 146 to Port ~2 and, therefore, it can clock twice more, by the bits o~ lines 165, 165', the insertion of two more samples (see again the window for insertion shown in Figure 9).
Additional secure audio channels can be provided by using parallel single-channel circuit boards. The only changes required are those required for the changed scram-bler output signal ~ormat and ~or the descrambler input signal format. Most of these changes could be made in the instruction sequences controlling the 8 x 300 micropro-cessors.
A two-channel audio capability can be provided by time-sharing the single-channel circuitry~ me analog-to-digital converter and digital-to-analog converter both are capable of operating at more than twice ~he current speed and could there~ore be time-shared~ The random access memory has exactly ~he capaclty required ~or two audio channels. Both channels could use the same pseudo-random addressing. In this regard, it is assumed that the 8 x 300 microprocessor is fast enough to process two audio signals in each TV line period. It is therefore possible to have a two-channel audio capability with a negligible increase in circuitry~
The audio scrambler/descrambler according to the invention of~ers a cha~nel bandwidth whioh is twice that o~ commercial audio scramblers and the degree o~ security attained is extremely high. me number of dif~erent se-quences o~ audio samples that are posslble in each TV
~ield period i5 240 factorialg or 4 x 10486, a number so large that it e~ectively eliminates trial and error ~5 decoding, At the same time, the spectrum o~ the scrambled signal resembles that of random noise, so that neither time domaln or ~requency domain analysis appear to provide useful in~ormation for unauthorized decoding .
-The followlng page is A1 -Al 47,601 APPENDIX
8 x 300 Mieroprocessor Programs The mieroprocessor instruction sequence for the audio scrambler of Figure 2 is listed in Table 3, and for the descrambler of Figure 6 is listed in Table 4. Details of the instruction set and the microprocessor arehiteeture are given in Chapter "Mieroproeessor" pages 61-72 of the Signeties Data Manual (eopyright 1976, Signeties Corpora-tion, 811 East Arques Avenue, Sunnyvale, California 94086). Reference to one of these is essential for under-standing the instructions.
The code in the tables is 6-digit octal, but in the binary code used in the equipment the 2nd and 5th most significant octal digits are represented in binary code by only 2 bits. This results in 16-bit instructions. For example, Table 1, Code ~ in octal and binary is as fol-lows:

6-Digit Octal: 5 22 1 13 - 16-Digit Binary: 101 10010 001 01011 The fourth column of the tables lists the 8-bit port that is involved in the operation specified by the instruction. There are five ports, denoted Pl to P5, with Pl, P2, and P5 assigned to the "left bank" and P3 and P4 assigned to the "right bank". One port in each bank ean be seleeted, that is, made aetive, at a time. The active port in each bank stays active until another port in the same bank is seleeted.
The eight individual input-outputs of each port are labeled 0, 1, 2, 3, 4, 5, 6, and 7. The notation P3,

7 refers to the seventh posi-tion of P3. The functions of - the scrambler por-ts are listed in Table 1, and those of - the deserambler ports, in Table 2.

, , ' .

A2 47~601 Pl < 8 MSB from FlFO
Pl, 7 is LSB

1 < Beginning of line 2 < Ver-tical In-terval 3 < FlFO data ready 6 <
2 LSB from RAM
7 <
P3 0 ~ Latch multiply code : 1 > Clock Sequential Counter &
Write Enable to address RAMS
2 > Insert Audio Enable 3 > La-tch output data : 5 6 > Write Enable to RAM and Start Address Search 7 > FlFO clock, Port 1 BlC signal P4 > 8-bit output data to latch, 3-bit multiply code to latch PS ~ 8 MSB from RAM

A3 47,501 Pl < 8-bit input data from Input FlFG
Pl, 7 is LSB
P2 0 < Random Address search in progress 1 < H. Pulse (beginning of line) 2 < Vertical interval 3 < FlFO data ready 4 ~ Multiply code ready < ~
6 < ~ 3-bit multiply code 7 <J

1 > 2 LSB to RAM

2 >
3 ~ Start random address search 4 > Load Output FlFO
> Clock Sequential Counter 6 > Load RAM
7 ~ FlFO Clock, Port #l BIC Signal P4 > 8 MSB to RAM
P5 not used z A4 47,601 TABLE 3 - SCRAMBLER _ X 300 PR9GRAM
Address Description Code Port 3 O> AUX 6 00 0 00 4 SEL. P3 6 17 0 03 3 AUX~ P3 0 00 0 37 3 6 SEL. P2 6 07 0 02 2 7 NZT (B.Line) 9 5 21 1 11 2

8 JMP 191 7 00 5 37

9 NZT (Vert.Int.) 11 5 22 1 13 . 12 NZT (Data Rdy) 14 5 23 1 16 2 14 SEL. P3 6 17 0 03 3 Clock FlFO 6 37 1 01 3 17 Clock FlFO 6 37 1 00 3 18 NZT (B.Line)18 5 21 1 22 2 19 W.E.~ RAM: 6 36 1 01 3 R.Addr.Start W.E.> RAM 6 36 1 06 3 21 Sel. Pl 6 07 0 01 '? O
, z ~5 47,6al The meanings of the te-rms in the Descripti~n column of Tables 3 and 4 are explained by the following examples. The notations R3, R4, P~6, etc., refer to 8-bit -internal r~gisters in the microprocessor: .
NOP No operation AUX Internal register. Contains second term for all arithmetic operations.
SEL.P3 Select port 3 NZT (B.Line) 9 Non-zero transfer: If Beginning of Line Signal is present, jump to ad-dress 9, else advance to next address in sequence.
JMP 191 Jump to decimal address 191 101B ~ R4 Load binary 101 in internal register R4 Clock FlFO Output a logical 1 to the FlFO

Clock FlFO Output a logical o to the FlFO
XEC (Mult.Code)+l Execute instruction at address given by the sum of the multiply code, the current address, and 1.
Add Rl, 4~ R3 Cyclicly shift contents of internal register Rl four positions to the right, add to AUX, and place in inter-nal register R3.
lllB~ P4, 7 Place lll binary in port 4 with least significant bit in position 7 of the port.
P4,7,5~ R6 Move 5 bits from port 4 with LSB from position 7, into R6.
XOR Pl,7,0> R3 Exclusive-OR 8-bits of port l (posi-tion 7 is LSB) with content of AUX and place in R3.

- The following page is 27 -

Claims (4)

47,601 CLAIMS:

1. In a television system transmitting on a line-per-line basis a plurality of video signals during regular periodical time intervals, an audio scrambler apparatus for securely transmitting at least one continuous audio signal with said television system comprising:
means for sampling said audio signal during succes-sive said periodical time intervals to derive a predetermined number of audio samples;
means for scrambling said derived audio samples to derive scrambled audio samples; and means operative on a line-per-line basis for inserting at least one derived scrambled audio sample into a selected portion of a video signal for transmission therewith by said television system;
an audio unscrambler apparatus responsive to the transmitted video signals comprising:
means responsive to the successively received video signals for extracting during one said regular periodical time interval successive received audio samples;
means for unscrambling said received audio samples in accordance with a pattern which is reverse of the processing pattern of said scrambling means;
means responsive to said unscrambled audio samples to form a continuous signal during an associated one of said regular periodical time intervals;
means for deriving with said audio samples an indication of the mean value thereof and of the deviations thereof is magnitude from such mean value;
means for determining a multiplier coefficient applicable to all of said derived audio samples;
means for multiplying said deviations by said multiplier coefficient and for adding said mean value to provide amplified audio samples;
the amplified audio samples being transmitted as said inserted audio samples together with an indication of said multiplier coefficient and said mean value;

47,601 with the audio unscrambler apparatus including:
means responsive to the received audio samples and to said indication relative to said multiplier coef-ficient and mean value for determining deviations of said amplified samples from said mean value and for dividing said deviations by said multiplier coefficient to provide an audio sample which is substantially the same as with the original audio signal whereby the transmission reception over said communication channel is free from noise.

2. Apparatus for inserting scrambled audio samples in a television system on a line-per-line basis by insertion of at least one audio sample in a selected time portion of an active television line; comprising:
a main random-access-memory (RAM) device for storing audio samples in a sequence as received in the Write mode of said main RAM device, and for deriving scrambled audio samples to be inserted from said RAM device in the Read mode;
a pseudo-random generator for generating pseudo-random addresses;
a counter responsive to said pseudo-random generator for storing a generated pseudo random address as an initial counter state;
said main RAM device using a generated pseudo-random address from said counter when in the Read mode under time control in relation to said selected time portion of an active video signal;
auxiliary random access memory (RAM) means responsive to said counter for indicating in different storing locations use by said main RAM device for all pseudo-random addresses derived from said counter;
means for comparing a new pseudo-random address with every indication of a used pseudo-random address in said auxiliary RAM means to detect any repetition between new and used pseudo-random addresses;
said counter being advanced sequentially to a subse-47,601 quent counter state when a repetition is detected;
with said comparing means being operative in relation to a television line during another time interval thereof than said selected time portion for insertion;
whereby every new pseudo-random address is checked for omission and repetition by said comparing means within a time interval representing the duration of a television line before being used by said main RAM device in the Read mode.

3. The apparatus of claim 2 with said auxiliary RAM means comprising a first and a second auxiliary RAM device;
said counter being operative with both said first and second auxiliary RAM devices;
said comparing means being operative with one of said first and second auxiliary RAM devices, alternately, each in relation to one alternative television line, the other being erased at the same location for which said one auxiliary RAM device has an indication registered of the use of the asso-ciated pseudo-random address by said main RAM device.

4. The apparatus of claim 2 with said audio sam-ples being associated with a selected grouping of television lines for insertion;
with said auxiliary RAM means having at least as many locations as said groupings;
with said counter and comparing means being actuated at a frequency rate which is larger than the television line rate multiplied by the number of television lines per group-ing.