CA1149518A

CA1149518A - Hollow multilayer printed wiring board and process for manufacturing same

Info

Publication number: CA1149518A
Application number: CA000352692A
Authority: CA
Inventors: Keiji Kurosawa; Kenji Yamamoto; Mitsuo Yamashita; Hisami Mitsui; Ayako Miyabara; Kiyotaka Miyagawa; Takayoshi Imura
Original assignee: Fujitsu Ltd
Current assignee: Fujitsu Ltd
Priority date: 1979-05-24
Filing date: 1980-05-26
Publication date: 1983-07-05
Also published as: WO1980002633A1; ES8202470A1; EP0028657B1; EP0028657A1; ES499461A0; DE3072112D1; EP0028657A4; US4528072A; US4368503A; JPS55156395A; ES8202469A1; ES499462A0; JPS5739559B2

Abstract

-64-HOLLOW MULTILAYER PRINTED WIRING BOARD AND PROCESS FOR MANUFACTURING SAME ABSTRACT OF THE DISCLOSURE A hollow multilayer printed wiring board and a process for manufacturing the same are provided. The hollow multi-layer printed wiring board is comprised of a plurality of printed substrates, superposed upon each other with a predetermined space therebetween, each of which substrate has a signal conductor pattern formed on at least one surface thereof and a land conductor pattern formed on at least one surface thereof. Each substrate has plated through holes in the land conductor pattern, each of which holes is in line with another plated through hole of at least one of the neighboring substrates to form a through hole or an interstitial via hole. A layer of a low melting point metal is formed at least on the upper and lower end surfaces of each plated through holes, which layer serves as a through connection between two or more signal conductor patterns of the substrates and as an interlayer adhesion between the substrates. The superposed substrates, except for at least one surface substrate, are made of a thermally resistant organic synthetic resin sheet or an insulation--treated metal.

Description

HOLLOW MULTILAYER PRINTED WIRING BOARD
AND PROCESS FOR MANUFACTURING SAME

TECHNICAL FIELD

This invention relates to a hollow multilayer printed wiring board and a process for manufacturing the multilayer printed wiring board. By the term "hollow multilayer 5 printed wiring board" used herein is meant a multilayer printed wiring board which comprises at least two insulating material substrates, on each of which a conductor pattern or patterns are formed, the conductor pattern or patterns being interconnected as may be required, and each of which substrate is spaced apart a pretermined distance from the adjacent substrate or substrates, said space being filled with an insulative gas or liquid.

BACKGROUND ART

The trend toward producing transistors, integrated 1~ circuits and other electronic devices and parts of small sizes in recent years has required a substantial increase in the wiring density of the multilayer printed wiring boards by reducing spaces between the parts. For this requirement, substrates having an enhanced dimentional stability must be used. Furthermore, the signal aonductor patterns must be arranged close to each other, which results in the following defects. First, electrical signals of a signal pattern are transferred to another neighboring signal pattern and interfere with the signals . :.

2 --therein or produce noise, that is, the occurrence of a so-called crosstalk phenomenon arises. Secondly, the parts, particularly where they are directly bonded to the substrate~ cause a temperature rise in the surface of the substrate, thereby influencing the characteristics of the parts and the substrate, and occasionally damaging the parts.
Most conventional multilayer printed wiring boards are prepared by laminating substrates, having formed thereon conductor patterns, by interposing an adhasive layer comprised of glass fibers impregnated with a prepolymer of a thermosetting resin between the substrates.
The adhesive layer used, however, must satisfy many require-ments, such as good thermal resistance, low shrinkage upon curing and good moldability. With an increase in the packaging density, it becomes more and more difficult to manufacture the composite structure by using the adhesive layer of thermosetting resin-impregnated glass fibers.
DISCLOSURE OF THE INVENTION
It is, therefore, the main object of the present invention to provide multilayer printed wiring boards which exhibit good thermal resistance, as well as enhanced dimensional stability, and improved transmission and cooling characteristics, as compared with the prior art.
Other objects and advantages of the present invention will be apparent from the following description.
In one aspect of the present invention, there is provided a hollow multilayer printed wiring board which - : :
, ,. . . . , ~.

B

comprises a plurality of substrates superposed upon each other with a predetermined space therebetween filled with an insulative gas or liquid, with or without an interposed spacer or spacers, each of which substrates has a signal conductor pattern formed on at least one surface thereof and a land conductor pattern formed on at least one surface thereof. Each substrate has plated through holes in the land conductor pattern~ each of which holes is in line with another plated through hol~ of each of the neighbor-ing substrates or of at least one of the neighboringsubstrates to form a plated through hole or an interstitial via hole a layer of a low melting point metal is formed at least on the upper and lower end surfaces of the plating layer defining each plated through hole, which low melting point metal layer serves as a through connection between two or more signal conductor patterns of the substrates and as an interlayer adhesion between the substrates. The superposed substrates, except for at least one surface substrate, are made of a thermally resistant organic synthetic resin sheet or an insulation-treated metal sheet.
In another, aspect of the present invention, there are provided processes for manufacturing the above-mentioned hollow multilayer printed wiring board. A first process 5 comprises the steps of:
preparing a plurality of substrates made of a thermally resistant organic synthetic resin sheet or an insulation-treated metal sheet, each substrate having a signal conductor pattern formed on at least one surface thereof and a land conductor pattern formed on at least one surface thereof and further having plated through holes in the land conductor pattern, a layer of a low melting point metal being formed at least on the upper and lower end surfaces of each of the plating layers defining the plated through holes; and then, superposing the substrates upon each other so that each of the plated through holes is in line with another plated through hole of each of the neighboring substrate or of at least one of the neighboring substrates, followed by applying a pressure and a heat sufficient for melt-adhering the substrate having the low melting point metal layer to the neighboring substrate or substrates.
A second process comprises the steps of:
preparing printed substrates made of a thermally resistant organic synthetic resin sheet or an insulation--treated metal sheet, each substrate having a signal ..
conductor pattern on at least one surface thereof and a land conductor pattern on at least one surface thereof, and further having a layer of a low melting point metal formed at least on said conductor pattern;
superposing the substrates upon each other so that the land conductor pattern having the low melting 25 point metal layer of each substrate is in contact with the land conductor pattern or patterns having the low melting point metal layer of the neighboring substrate or substrates, followed by applying a pressure and a heat su~ficient for ,' ' - '; ' , , melt-adherin~ the substrate having the low melting point metal layer to the neighboring substrate or substrates, and; then, boring through holes in the melt-adhered land 5 conductor patterns of the superposed substrates, followed by forming plating conductor layers on at least the inner walls of the through holes to complete plated through holes serving as a through connection between the two or more signal conductor patterns of the superposed substrates.
BRIEF DESCRIPTION OF DRAWINGS
FIGS. lA through lD schematically represent, in cross-section, the sequential steps of manufacturing a hollow multilayer printed wiring board according to one preferred embodiment of the process of the present invention;
FIGS. 2A through 2G schematically represent, in cross-section, the sequential steps of manufacturing a hollow multilayer printed wiring board according to another preferred embodiment of the process of the present invention;
FIGS. 3A through 3C schematically represent, in cross-section, the sequential steps of manufacturing a hollow multilayer printed wiring board according to still another preferred embodiment of the process of the present invention;
FIGS. 4A through 4C schematically represent, in cross-section, the sequential steps of manufacturing a modified hollow multilyaer printed wiring board having a non-hollow multilayer printed wiring board substrate;
FIGS. 5A through 5F schematically represent, in . ~

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cross-section, the sequential steps of prepariang a printed substrate having through holes;
FIGS. 6A through ~F schematically represent, in cross-section, the sequential steps of preparing another 5 printed substrate having through holes;
FIGS. 7A through 7G schematically represent, in cross-section, the sequential steps of preparing still another printed substrate having through holes; and, FIGS. 8A through 8H schematically represent, in cross-section, the sequential steps of preparing still another printed substrate having through holes.
FIGS. 9A through 9D schematically represent, in cross-section, the sequential steps of preparing another printed substrate used in the present invention;
FIGS. 10A through lOH schematically represent, in cross-section, the sequential steps of forming a conductor pattern on a substrate;
FIG. llA schematically represents, in cross-section, one example of the printed substrates used in the present invention; and, FIGS. llB through llE schematically represent, in cross-section, the sequential steps of preparing the printed substrate shown in FIG. llA.
BEST MODE FOR CARRYING OUT THE INVENTION
The substrates used for the construction of the hollow multilayer printed wiring board of the invention, except for at least one surface substrate, are made of a thermally resistant organic synthetic resin sheet or an ¢"`~t~

insulation-treated metal sheet. The organic synthetic resin used includes, for example, a polyimide resin, an epoxy resin and a triazine resin. The insulation-treated metal used includes, for example, anodically oxidized metals, such as anodically oxidized aluminum, magnesium, titanium and thallium, and; metal sheets having insulation material layers deposited thereon, such as an iron sheet coated with an organic synthetic resin or an inorganic insulating material and an iron sheet sputtered with a non-conductive material. The most preferable insulation--treated metals are those which are prepared by anodically oxidizing a metal and, then, depositing an insulation material layer on the anodically oxidized metal. In general, an anodically oxidized insulation layer is homo-geneous. However, when the thickness of the anodicallyoxidized insulation layer is increased in order to enhance its mechanical strength and insulation reliability, pin holes are liable to occur in the insulation layer. In contrast, an insulation layer formed by coating or sputtering exhibits poor homogeneity, although it can be made desirably thick. The insulation-treated metals prepared by the combination of anodic oxidation with deposition of an insulation material layer are advantageous in that the insulation layer is relatively homogeneous and can be made into the desired thickness.
In the hollow multilayer printed wiring board of the present invention, a through connection between the two or more conductor patterns and an interlayer adhesion between . . . . ~ . , ~;

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' the superposed substrates are achieved by using a low melting point metal. By the term "low melting point metal" used herein is meant a metal which possesses a melting point lower than the temperature at which the substrate is adversely affected to a considerable extent.
The low melting metal includes, for example, a simple metal such as gold and tin and alloys su~h as tin-lead, cadmium-zinc, tin-lead-silver, lead-silver, tin-zinc and cadmium-silver.
Typical examples of the hollow multilayer printed wiring board of the present invention and processes for manufacturing them will now be illustrated with reference to the accompanying drawings.
FIGS. lA through lD exemplifies the hereinbefore mentioned first process wherein plated through holes are formed in printed substrates made of a thermally resistant organic synthetic resin and, then, the printed substrates are superposed upon each other.
Referrin~ to FIG. lA, a ceramic substrate 1 is used as the surface substrate, and two intermediate substrates 2 and 4 made of a thermally resistant organic synthetic resin, such as a polyimide or an epoxy resin, are positioned so that a spacer 3 made of a similar organic synthetic resin is interposed between them. Each of the substrates 1, 2 and 4 has a signal conductor pattern 6 on at least one surface thereof and a land conductor pattern 7 on at least one surface thereof. The spacer 3 has land conductor patterns 7 on both surfaces thereof. The signal conductor .

pattern 6 formed on the lower surface of the substrate 2 is sandwiched between conductors of a first ground conductor pattern 8 electrically isolated from the signal conductor pattern 6 and formed on the same surface of the substrate on which the signal conductor pattern 6 is formed. Further-more, the signal conductor pattern 6 formed on the lower surface of the substrate 2 is covered with a second ground conductor pattern 9, which is electrically isolated from the signal conductor pattern 6 and formed on the upper surface of the spacer 3 confronting the substrate 2. The second ground conductor pattern g has an area sufficient for covering the signal conductor pattern 6 and the con-ductors of the first ground conductor pattern 8, formed on the confronting surface of the substrate 2.
Referring to F~G. lB, through holes 10 are bored in the land conductor pattern 7 of each of the substrates 1, 2 and 4 and the spacer 3. The substrates and the spacer, having the through holes 10 perforated therein, are then subjected to electroless deposition to form a conductor deposition layer 11 over the entire surface of each substrate or spacer, including the inner walls of the through holes, so that the substrates and the spacer can be subjected to electroplating. If desired, an electroplating conductor layer (not shown) may be formed on the electroless deposition conductor layer 11.
Referring to FIG. lC, a plated resist 14 is formed by conventional means on the portions, on which no land conductor pattern has been formed, to a thickness greater ' ~ ~ : ,;' '; ' ~; :

than that of electroplating conductor layers to be latex formed thereon. Then, a first through hole conductox plating layer 12 is formed on the inner walls of ~he through holes 10 and on at least part of the land conductor 5 pattern 7. The first through hole conductor plating layer 12 serves as a through connection between signal conductor patterns and a support for the superposed substrates and spacer, when the substrates and spacer are superposed to construct the hollow multilayer printed wiring board. Thereafter, a second through hole plating layer 13 of a low melting point metal is formed on the first through hole conductor plating layer 12 while the plated resist 14 still remains. The second through hole plating layer 13 serves as a through connection between signal conductor patterns, a support for the superposed substrates and spacer, and an interlayer adhesion, when the substrates and spacer are superposed upon another. It also serves as a resist when each substrate or spacer is etched after the resist 14 is removed therefrom. It is preferable that the second through hole plating layer 13 have a thickness such that the second through hole plating layer 13 does not flow out when heat and pressure are applied thereto in the subsequent step of lamination.
Usually, the thickness of the second plating layer 13 may be approximately 5 to 10 microns.
Referring to FIG. lD, the plated resist 14 (shown in FIG. lC) is removed and, then, portions of the electroless deposition layer 11 (shown in FIG. lC), which portions are :`
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not covered by the first and second through hole plating layers 12 and 13, are removed by means of flash etching.
The substrates 1, 2 and 4 and the spacer 3 are correctly brought into superposed position by utilizing reference registering holes (not shown), which are previously formed in each of the substrates and spacer, and then, adhered together under the application of heat and presure. Here, the heat applied should be of a quantity sufficient to ~elt the second through hole plating layer 13.
If desired, a side wall or walls 16 made of an organic synthetic resin or a metal are formed on the side periphery of the superposed substrates and spacer, thereby to seal the spaces between the superposed substrates and spacer.
Each sealed space may be filled with an insulative liquid or gas, which serves as a cooling medium, in order to enhance the cooling performance of the hollow multilayer printed wiring board. If the dielectric constant of the liquid filled in the sealed spaces is suitably selected, it is possible to freely set not only the cooling performance but also the dielectric constant of the whole multilayer printed wiring board.
Referring to FIGS. 2A through 2G, illustrating the sequential steps of manufacturing the hollow multilayer printed wiring board from insulation-treated metal sheets, first, through holes 18 are bored in a metal sheet 17 by means of, for example, drilling, laser or chemical etching (FIG. 2A). The sheet 17 is made of a metal which is capable of being readily anodically oxidized, such as . . .
-aluminum, magnesium, titanium or thallium.
Secondly, the entire surface of the bored metal sheet 17 including the inner walls of the through holes 18 is ano-dically o~idi~ed to form an insulation film layer 19 serving a substrate for supporting a conductor pattern thereon (FIG.
2B, the upper figure). Alternatively, the insulation film layer 19 may be formed by depositing an insulation material onto the metal sheet, for example, by coating the metal sheet with an organic synthetic resin or an inorganic insulation material, or by ~put~ering the metal shee~O An optimum insulation-treated metal sheet is prepared by first ano-dically oxididizing the metal sheet to form the anodically oxidized insulation film layer 19 and, then, depositing an insulation material 20 thereon (FIG. 2B, the lower figure).
Thirdly, a conductor layer 21 is formed on the entire surface of the insulation-treated metal sheet including the inner walls of the through holes 18 (FIG. 2C). The formation of the conductor layer 21 may be effected by conventional procedures, such as electroless deposition, printing, ion plating and vapor deposition. These procedures may be employed alone or in combination. If desired, the sheet having the conductor layer 21 formed thereon may be electro-plated to increase the thickness of the conductor layer 21.
Fourthly, the sheet is laminated with a photosensitive plastic resin or inorganic matPrial layer, followed by pattern exposure and development, thereby to form a resist pattern 22 covering the portions other than those on which the intended conductor pattern is to be formed (FIG. 2D).

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Fifthly, a conductor layer 23 is formed on the region where resist does not exist, including the inner walls of the through holes by electroplating or printing (FIG. 2E).
If desired, both surfaces of the conductor-formed sheet are subjected to a smoothing treatment. Then, a low melting point metal (not shown~ is deposited onto the conductor layer 23 by electroplating, printing or vapor deposition.
Sixthly, the resist 22 (shown in FIG. 2E) is removed and, then, the exposed portions of the conductor layer 21 (shown in FIG. 2E) are removed by means of flash etching to obtain a printed substrate 27 (FIG. 2F). When the con-ductor layer 23 is formed by printing a conductor paste in the preceding fifth step, the printed conductor paste is dried, and then, the resist 22 and the portions of the con-ductor layer 21 are removed as mentioned above, and finally,the dried printed conductor paste is heated at a sintering temperature to form a metallized conductor layer 23.
Finally, a plurality of the printed substrates 27 and one or more spacers 28 are superposed in a manner such that a spacer 28 is interposed between every two printed substrates 27. The superposed substrates and spacer or spacers are adhered together by applying either heat and pressure or laser, thereby melting the low melting point metal layer to obtain a hollow multilayer printed wiring board. The spacer 28 may be prepared in a manner similar to that mentioned above with reference to the preparation of the substrate 27. If desired, the spaces present between the superposed substxates may be sealed by forming a side wall or -.
, - 14 ~

walls 30 on the side periphery of -the hollow multilayer printed wiring board. Furthermore, the side wall or walls 30 may be bored in order to fill the sealed spaces with a suitable insulative gas or liquid.
FIGS. 3A through 3B e~emplifies the hereinbefore mentioned second process wherein printed substractes having no plated through holes are superposed upon each other and, then, plated through holes are bored in the superposed substrates. Referring to FIGS. 3A through 3B, three substrates 31, 32 and 33 are used which are prepared from substrates each having conductor foils formed on both surfaces thereof. Each of the three substrates has a conductor pattern or patterns on at least one surface thereof. Namely, as illustrated in FIG. 3A, each of the two surface substrates 31 and 32 has a conductor foil 35 remaining on one surface thereof and a land conductor pattern 36 and a signal conductor pattern 37 on the other surface thereof. The intermediate substrate 33 has land conductor patterns 36 and signal conductor patterns 37 on both surfaces thereof. A plated layer 38 comprised of an alloy having a relatively high meltin~ point is formed on all of the land conductor patterns 36. The three substrates 31, 32 and 33 are superposed upon another as shown in FIG. 3A, and then, adhered together by applying heat and pressure sufficient to melt the plated alloy layer 38.
Thereafter, through holes 39 are bored in the superposed land conductor pattern portions 36 ~FIG. 3B). Then, the adhered substrates are subjected to panel plating to ;

, 5~8 deposit a conductor 40 on the inner walls of the through hole 39, and thereafter, the adhered substrates are subjected to plating with an alloy having a melting point lower than that of the plated alloy layer 38. Then, the conductor foils 35 on the surfaces of the substrates 31 and 32 are etched to form surface signal conductor patterns 41. Whereby, a hollow multilayer printed wiring board of a closed type is obtained (FIG. 3C).
In view of the thermal resistance of the hollow multilayer printed wiring board of the invention, it is preferable that at least one of the substrates located on the surfaces of the multilayer printed wiring board be made of an inorganic thermally resistant material, such as ceramics or an insulation-treated metal, as illustrated in FIGS. lA, 3A and 4A (mentioned below). This is advantageous particularly where parts are directly bonded to the multi-layer printed wiring board upon packaging.
Furthermore, at least one of the substrates of the multilayer printed wiring board of the invention may be a non-hollow multilayer printed wiring board. One example of the multilayer printed wiring board having as one substrate a non-hollow multilayer printed wiring board is illustrated in FIG. 4C. Referring to FIG. 4C, the hollow multiplayer printed wiring board has a substrate of a non-hollow multilayer printed wiring board 68 of a thermally resistant organic resin material and a surface substrate 69 of ceramics, the two substrates being superposed upon each other with a predetermined space therebetween and bonded ' ~
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- ?~ 5~3 by low melting point metal layers 75 and through hole plating layers 76 formed on the inner walls of the through holes.
The hollows multilayer printed wiring board of FIG. 4C
is manufactured by the sequential steps illus~ra~ed in FIGS. 4~ through 4Co Namely, a ceramic substrate having a conductor foil 67 formed on its upper surface and a land conductor pattern 71, a signal conductor pattern 70 and a first ground conductor pattern 72 formed on the lower surface is prepared (FIG. 4A). A non-hollow multilayer printed wiring board 68 having a land conductor pattern 71 and a second ground conductor pattern 72' formed on its upper sur~ace and a conductor foil 67 formed on the lower surface is prepared (FIG. 4A). Both the ceramic substrate 69 and the multilayer printed wiring board 68 have through lS holes 73 bored in the land conductor patterns. The signal conductor pattern 70 formed on the lower surface of the substrate 69 is sandwiched between conductors of the first ground conductor pattern 72 electrically isolated from the signal conductor pattern 70 and formed on the same surface, and furthermore, the second ground conductor pattern 72' is formed on the upper surface of the multilayer printed wiring board 68 so that the ground conductor pattern 72' covers the signal conductor pattern 70.
Referring to FIG. 4B, the confronting surfaces of the ceramic substrate 69 and the multilayer printed wiring board 68 are plated with a low melting point metal 75 on the land conductor patterns 71 and on the peripheral edge portions thereof, and then, the ceramic substrate 69 and .

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the multilayer printed wiring board 68 are adhered to each other by applying pressure and heat thereto.
~ eferring to FIG. 4C, the superposed ceramic sub-strate 69 and multilayer printed wiring board 68 are 5 plated with a conductor on the inner walls and upper and lower end portions of the through holes 73 to form through hole plating conductor layers 76. Simul-taneously therewith, surface signal conductor patterns 77 are formed on the upper surface of the ceramic substrate 69 10 and on the lower surface of the multilayer printed wiring board 68. The low melting point metal layer 75 forming the side peripheral wall of the superposed substrates serves as a barrier for preventing both an electrolyte used in the step of forming the through hole plating layers 76 and an etchant used in the step of forming the surface signal conductor patterns 77 from penetrating into the space between the two substrates.
In order to minimize the occurrence of a crosstalk phe-nomenon, reduce the apparent dielectric constant of the hol-low multilayer printed wiring board and enhance the impedancethereof, the hollow multilayer printed wiring board of the invention may be of one of the following two structures.
The first structure is such that, as hereinbefore described with reference to FIGS. lA and 4A, the signal 25 conductor pattern formed on the surface of each substrate is sandwiched between conductors of a first ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed, and said signal conductor pattern is covered with a second ground conductor pattern electrically isolated from the signal conductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the substrate having the signal conductor pattern; said second ground conductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern. Referring to FIGS. lA
through lD, although the above-mentioned first structure is formed with respect to a portion of the signal conductor pattern 6 formed on the lower surface of the suhstrate 2, similar structures may be formed with respect to other portions of the signal conductor pattern formed on the same surface of the substrate 2 or the signal conductor patterns formed on the other substrates.
The second structure is such that the signal conductor pattern formed on at least one surface of each substrate is covered with a ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed. One e~ample of the second structure is illustrated in FIG. llA. In FIG. llA, a signal conductor pattern 62 formed on a substrate 61 is covered with a ground conductor pattern 64 formed on the same substrate 61. The signal conductor pattern 62 is electrically isolated from the ground conductor pattern 64~
i.e., there is an air space 66 between the signal conductor , - .:. . . .
:

pattern 62 a.nd the ground conductor pattern 64.
The structure illustrated in FIG. llA is manufactured by the sequential steps illustrated in FIGS. llB through llE.
The substrate 61 having the signal conductor pattern 62 5 and a ground conductor pattern 62' ~ormed on one surface thereof is prepared by a conventional patterning procedure (FIG. llB). A resist 63 is formed on the signal conductor pattern 62 by screen printing or another conventional coating or laminating procedure, which resist is soluble in a suitable solvent (FIG. llC). The ground conductor pattern 62' is not coated with the resist 63. Then, the ground conductor pattern 64 is formed on the entire surface of the substrate 61 including the region coated with the resist 63 (FIG. llD). The formation of the ground conductor pattern 64 may be effected by a conventional plating procedure. Thereaf-ter, the ground conductor pattern 64 is etched by photoetching to form holes 65 for removing the resist 63 therethrough (FIG. llE). Then, the resist 63 is dissolved in a solvent and removed through the holes 65, thereby to obtain a substrate of the structure illustrated in FIG. llA. This substrate may be used as it is.
Alternatively, the space 66 (shown in FIG. llA) between the ground conductor pattern 64 and the signal conductor pattern 62 may be filled with an insulating oil, which has a suitable dielectric constant and other electrical properties, and is chemically stable for impedance matching.
The printed substrates used for manufacturing the hollow multilayer printed wiring board of the invention by .
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the hereinbefore-mentioned second process, i.e., the substrates each having a signal conductor pattern on at least one surface thereof and a land conductor pattern on at least one suface thereof, and further having a layer of 5 a low melting point metal formed on said conductor pattern, but having no plated through holes, as illustrated in FIG. 3A, can be prepared by one of the following four processes.
A first process comprises the steps of:
(i) laminating or coating with a resist substrate having conductor foils formed on both surfaces thereof, followed by patterning the resist to form a resist pattern;
(ii) plating the resist-formed substrate with a low melting point metal to form low melting point metal 15 plating layers on the regions on which the signal conductor pattern and the land conductor pattern are to be formed;
(iii) removing the resist from the substrate; and then, (iv) etching the substrate to remove the exposed 20 portions of the conductor foils.
A second process is similar to the above-mentioned first process except that the resist-formed substrate obtained by the step (i) is, prior to the step (ii), plated with a conductor to form plating conductor layers 25 on thè regions on which the signal conductor pattern and the land conductor pattern are to be formed.
A third process comprises the steps of:
(i) laminating or coating with a resist a ' substrate having conductor foils formed on both surfaces thereof, followed by patterning the resist to form a resist pattern;
(ii) etching the resist-formed substrate to 5 remove the exposed portions of the conductor foils;
(iii) removing the resist from the substrate; and then, (iv) forming layers of a low melting point metal on at least the so formed land conductor pattern.
A fourth process comprises the steps of:
(i) laminating or coating with a resist a substrate having conductor foils formed on both surfaces thereof, followed by patterning the resist to form a resist pattern;
(ii) electroplating the resist-formed substrate to form electroplating conductor layers on the regions on which the signal conductor pattern and the land conductor pattern are to be formed;
(iii) removing the resist from the substrate;
(iv) etching the substrate to remo~e the conductor foils; and then, (v) forming layers of a low melting point metal on at least the so formed land conductor pattern.
The printed substrates used for manufacuturing the 25 hollow multilayer printed board of the invention by the hereinbefore mentioned first process, i.e., the substrates having a signal conductor pattern formed on at least one surface thereof and a land conductor pattern on at least "`
i' , one surface thereof and further having plated through holes in the land conductor pattern, layers of a low melting point metal being formed at least on the upper and lower end surfaces of each of the plating layers defining the plated through holes, can be prepared by one of the following processes.
A first process comprises the steps of:
(i) preparing a substrate having through holes therein;
(ii) subjecting the substrate to electroless plating to form an electroless plating conductor layer on the entire surface of the substrate including the inner walls of the through holes;
(iii) laminating the electroless-plated substrate 15 with a resist followed by patterning the resist to form a resist pattern;
(iv) electroplating the resist-formed substrate to form electroplating conductor layers on the regions on which a signal conductor pattern and a land conductor 20 pattern are to be formed and on the inner wall of each through hole;
(v) plating the electroplating conductor layer--formed substrate with a low melting point metal to form layers of the low melting poing metal on at least the 25 electroplating conductor layers formed on the upper and lower land portions of each through hole;
(vi) removing the resist from the substrate;
and then, ' .. :

(vii) etching the substrate to remove the exposed portions of the electroless plating conductor layer.
One example of the above-mentioned first process is hereinbefore described with reference to FIGS. 2A through 2F.
The steps (i) through (vii) in the above-mentioned first process correspond to FIGS. 2A through 2F as follows.
Step (i) : FIGS. 2A and 2B, Step (ii) : FIG. 2C, Step (iii) : FIG. 2D, Steps (iv) and (v1 : FIG. 2E, and Steps (vi) and (vii): FIG. 2F.
A second process is similar to the above-mentioned first process except that the step (v) of forming low melting point metal layers is carried out after the final etching step (vii). That is, the second process comprises the steps of:
(i) preparing a substrate having through holes therein;
(ii) subjecting the substrate to electroless plating to form an electroless plating conductor layer on the entire surface of the substrate including the inner walls of the through holes;
(iii) laminating the electroless-plated substrate with a resist followed by patterning the resist to form a resist pattern;
(iv) electroplating the resist-formed substrate to form electroplating conductor layers on the regions on which a signal conductor pattern and a land conductor pattern are to be formed and on the inner wall of each through hole;
(v) removing the resist from the electroplated substrate;
(vi) etching the substrate to remove the exposed portions of the electroless plating conductor layer; and then, (~ii) forming layers of a low melting point metal on at least the upper and lower land portions of each 10 through hole.
A third process comprises the steps of:
(i) boring through holes in a land conductor pattern of a substrate having a signal conductor pattern on at least one surface thereof and the land conductor 15 pattern on at least one surface thereof;
(ii) subjecting the substrate to electroless plating to form an electroless plating conductor layer on the entire surface of the substrate including the inner walls of the through holes;
(iii) laminating the electroless-plated substrate with a resist followed by patterning the resist to form a resist pattern;
(iv) electropiating the resist-formed substrate to form electroplating conductor layers on the inner wall and upper and lower land portions of each through hole;
(v) plating the electroplating conductor layer-formed substrate with a low melting point metal to form layers of the low melting point metal on at least the .
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electroplating conductor layers formed on the upper and lower land portions of each through hole;
~vi) removing the resist from the substrate; and then, (vii) etching the substrate to remove the exposed portions of the electroless plating conductor layer.
One example of the above-mentioned third process is hereinbefore described with reference to FIGS. lA through lC.
The steps (i) through (vii~ in the above-mentioned third 0 process correspond to FIGS. lA through lC as follows.
Steps (i) and (ii) : FIGS. lA and lB, Steps (iii), (iv) and (v): FIG. lC, and Steps (vi) and (vii) : not shown.
A fourth process is similar to the above-mentioned third process except that the step (v) of forming low melting point metal layers is carried out after the final etching step (vii). That is, the fourth process comprises the steps of:
(i) boring through holes in a land conductor pattern of a substrate having a signal conductor pattern on at least one surface thereof and the land conductor pattern on at least one surface thereof;
(ii) subjecting the substrate to electroless plating to form an electroless plating conductor layer on the entire surface of the substrate including the inner walls of the through holes;
liii) laminating the electroless-plated substrate with a resist followed by patterning the resist to form a B

resist pattern;
(iv) electroplating the resist-formed substrate to form electroplating conductor layers on the inner wall and upper and lower land portions of each thereof hole;
(v) removing the resist from the electroplated substrate;
(vi) etching the substrate to remove the exposed portions of the electroless plating conductor layer;
and then, (vii) forming layers of a low melting point metal on at least the upper and lower land portions of each through hole.
A fifth process comprises the steps of:
(i) laminating with a resist a substrate having 15 conductor foils formed on both surfaces thereof, followed by patterning the resist to form a resist pattern;
(ii) boring through holes in the resist-~ormed substrate;
(iii) electroplating the substrate to form 20 electroplating conductor layers on the regions on which a signal conductor pattern and a land conductor pattern are to be formed and on the inner wall of each through hole;
(iv) plating the electroplating conductor layer-25 ~formed substrate with a low melting point metal to formlayers of the low melting point metal on at least the electroplating conductor layers formed on the upper and lower land portions of each through hole;

- , ,~ :; "
~:.

- ~ ~` :' i ' ~v) removing the resist from the substrate; and then, (vi) etching the substrate to remove the exposed portions of the conductor foils.
One example of the above-mentioned fifth process is illustrated in FIGS. 5A through 5F. Referring to FIGS. 5A
through 5F, a thermally resistant organic synthetic resin substrate 100 having conductor foils 100a on both surfaces thereof is prepared tFIG. 5A). A resist 101 is printed on the substrate 100 to form a resist pattern such that the conductor foils 100a are exposed in the portion 102, on which a signal conductor pattern is to be formed, and in the portions 103, on which lands and through holes are to be formed (FIG. 5B). Through holes 104 are formed (FIG. 5C).
The substrate is subjected to electroplating to form conductor layers 105 (FIG. 5D). The electroplated substrate is plated with a low melting point metal to form layers 106 of the low melting point metal on khe electroplating conductor layers 105 (FIG. 5D). The resist 101 is removed (FIG. 5E). Then, the substrate is subjected to flash etching to obtain a printed substrate pl having a signal conductor pattern 107' and through hole plating layers 107 (FIG. 5F). It is to be noted that, in the electroplating step illustrated in Fig. 5D, the conductor 105 is not 25 directly deposited on the inner walls 104a of the through holes 104, but the conductor 105 once deposited on the portions of the upper and lower conductor foils 100a sur-rounding the through holes 10~ grows and finally covers ::

, the entire inner walls 104a as shown in FIG. 5D.
A sixth process is similar to the above-mentioned fifth process except that the step (iv~ of forming the low melting point metal layers is carried out after the final S etching step (vi). That is, the sixth process comprises the steps of:
(i) laminating with a resist a substrate having conductor foils formed on both surfaces thereof, followed by patterning the resist to form a resist pattern;
(ii) boring through holes in the resist-formed substrate;
(iii) electroplating the substrate to form electro-plating conductor layers on the regions on which a signal conductor pattern and a land conductor pattern are to be formed and on the inner wall of each through hole;
(iv) removing the resist from the electroplated substrate;
(v) etching the substrate to remove the exposed portions of the conductor foils; and then, (vi) forming layers of a low melting point metal on at least the upper and lower land portions of each through hole.
A seventh process comprises the steps of:
(i) laminating with a resist a substrate having conductor foils formed on both surfaces thereof, followed by patterning the resist to form a resist pattern;
(ii) boring through holes in the resist-formed substrate;

(iii) electroplating the substrate to form electro-plating conductor layers on the region on which a signal conductor pattern is to be formed and on the inner wall of each through hole;
(iv) plating the electroplating conductor layer--formed substrate with a low melting point metal to form layers of the low melting point metal on at least the electroplating conductor layers formed on the upper and lower end portions of each through hole;
tv) removing the resist from the substrate; and then, (vi) etching the substrate to remove the exposed portions of the conductor foils.
One example of the above-mentioned seventh process is illustrated in FIGS. 6A through 6F. Referring to FIGS. 6A
through 6F, a substrate 100 having conductor foils 100a on both surfaces thereof is prepared (FIG. 6A). A resist 101 is printed on the substrate 100 to form a resist pattern such that the conductor foils 100a are exposed only in the portion 102 on which a signal conductor pattern is to be formed (FIG. 6B). Through holes 104 are formed (FIG. 6C).
The substrate is subjected to electroplating to form electroplating conductor layers 105 (FIG. 6D). The electro-plated substrate is plated with a low melting point metal to form layers 106 of the low melting point metal on the electroplating conductor layers 105 (FIG. 6D). The resist 101 is removed (FIG. 6E). Finally, the substrate is subjected to etching to obtain a printed substrate P2 - ' ":' '"'. ' ~'-' :. . ,;, , :.:
.' ~, . . . ~ :. ;

having a signal conductor pattern 107' and a landless through hole plating layers 108 (FIG~ 6F). The printed substrate P2 has no land around each through hole plating layer. In the above-mentioned electroplating step, the conductor 105 deposited on the portions of the conductor foils lOOa exposing to the through holes grows and finally covers the entire inner walls of the through holes (FIG. 6D).
An eight process is similar to the above-mentioned seventh process except that the step (iv) of forming the low melting point metal layers is carried out after -the final etching step (vi). That is, the eighth process comprises the steps of:
(i) laminating with a resist a substrate having conductor foils formed on both surfaces thereof, followed by patterning the resist to form a resist pattern;
(ii) boring through holes in the resist-formed substrate;
(iii) electroplating the substrate to form electro-plating conductor layers on the region on which a signal conductor pattern is to be formed and on the inner wall of each through hole;
(iv) removing the resist from the electroplated substrate;
(v) etching the substrate to remove the exposed portions of the conductor foils; and then, (vi) forming layers of a low melting point metal on at least the upper and lower end portions of each through hole.

A ninth process comprises the steps of:
(i) laminating a substrate having conductor foils formed on both surfaces thereof, with a first resist, onto which a conductor is capable of being deposited by electroless plating and then, with a second resist, onto which a conductor is incapable of being deposited by electroless plating, to form a resist pattern;
(ii) boring through holes in the resist-formed substrate;
(iii) subjecting the substrate to electroless plating to form electroless plating conductor layers on the region on which a signal conductor pattern is to be formed and on the inner wall of each through hole;
(iv) electroplating the substrate to form electro-plating conductor layers on the electroless plating conductorlayers;
(v) plating the electroplating conductor layer-formed substrate with a low melting point metal to form layers of the low melting point metal on at least the electroplating conductor layers formed on the upper and lower end portions of each through hole;
(vi) removing the resist from the substrate; and then, (vii) etching the substrate to remove the exposed portions of the conductor foils.
One example of the above-mentioned ninth process is illustrated in FIGS. 7A through 7G. Referring to FIGS. 7A
through 7G, a substrate 100 having conductor foils 100a on , , . .' . : ' ' ' .
, y~

both surfaces thereof is prepared (FIG. 7A). The substrate 100 is laminated with first photoresists (dry film) lOla and then with second photoresists (dry film) lOlb (FIG. 7B).
The first photoresists lOla have a property such that a 5 conductor is capable of being deposited thereon by electro-less deposition, and the second photoresists lOlb have a property such that a conductor is incapable of being deposited thereon by electroless deposition. The photo-resist-laminated substrate is light-exposed and then 10 developed to form a resist pattern such that the conductor foils lOOa are exposed in the portion 102 of the conductor foils on which a signal conductor pattern is to be formed (FIG. 7C). Through holes 104 are formed (FIG. 7D). The substrate is subjected to electroless plating to form 15 conductor layers 109 on the exposed portions of the first photoresists lOla (FIG. 7E). The substrate is subjected to electroplating twice to form first conductor plating layers 110 and low melting point metal plating layers 111 (FIG. 7F). The second resists lOlb and the first resists 20 lOla are removed, followed by flash etching, thereby to obtain a printed substrate P3 having a signal conductor pattern 112 and landless through hole plating layers 113 (FIG. 7G).
As a modification of the above-mentioned ninth process 25 explained with reference to FIGS. 7A through 7G, the lamination of the first photoresists lOla may be omitted when the signal conductor pattern 112 and the landless through hole plating layers 113 may be thin. In this modification, a longer time is necessary for the formation of the electroless plating layers 109 as compared with the above-exemplified ninth processO
A tenth process is also a modification of the above--mentioned ninth process. The tenth process is similar to the ninth process except that the step (v) of forming low melting point metal layers is carried out after the final etching step (vii). Thus, the tenth process comprises the steps of:

(i) laminating a substrate having conductor foils formed on both surfaces thereof, with a first resist, onto which a conductor is capable of being deposited by electroless plating and then, with a second resist~ onto which a conductor is incapable of being deposited by electroless plating, to form a resist pattern;
(ii) boring through holes in the resist-formed substrate;
(iii) subjecting the substrate to electroless plating to form electroless plating conductor layers on the region on which a signal conductor pattern is to be formed and on the inner wall of each through hole;
(iv) electroplating the substrate to form electro-plating conductor layers on the electroless plating conductor layers;
(v) removing the resist from the substrate;
(vi) etching the substrate to remove the exposed portions of the conductor foils; and then, (vii) forming layers of a low melting point metal .

'.

on at least the upper and lower end portions of each through hole.
An eleventh process is another modification of the above-mentioned ninth process explained with reference to S FIGS. 7A through 7G. The eleventh process comprises the steps of:
(i) laminating with a resist a substrate having conductor foils formed on both surfaces thereof, followed by patterning the resist to foxm a resist pattern;
(ii) boring through holes in the resist-formed substrate;
(iii) subjecting the substrate to electroless plating to form an electroless plating conductor layer on the entire surface of the substrate including the inner walls of the through holes;
(iv) removing the uppermost and lowermost portions of the electroless plating conductor layer to expose the uppermost and lowermost portions of the resist;
(v) electroplating the resist-exposed substrate to form electroplating conductor layers on the region on which a signal conductor pattern is to be formed and on the inner wall of each through hole;
(vi) plating the electroplating layer-formed substrate with a low melting point metal to form layers of the low melting point metal on at least the electroplating conductor layers formed on the upper and lower end portions of each through hole;

(vii) removing the resist from the substrate; and then, (viii) etching the substrate to remove the exposed portions of the electroless plating conductor layer.
The above-mentioned eleventh process is illustrated in FIGS. 8A through 8G. A substrate 100 having conductor foils lOOa on both surfaces thereof (FIG. 8A) is laminated with photoresists lOla having a property such that a conductor is capable of being deposited thereon by electro-less plating (FIG. 8B). The photoresists lOla are light--exposed and developed to form a resist pattern such that the conductor foils lOOa are exposed in the portion on which a signal conductor pattern is to be formed and in the portions 103 on which lands and through holes are tc be formed (FIG. 8C). Through holes 104 are formed (FIG. 8D).
The substrate is subjected to electroless plating to form a conductor plating layer 114 (FIG. 8E). The conductor plating layer 114 extends over the entire surface of the surface, and therefore, the portions of the conductor plating layer 114, which portions are formed on the upper-most and lowermost surfaces of the resists lOla, are removed, for example, by polishing or using an adhesive tape (FIG. 8F). Instead of removing the portions of the conductor plating layer 114, an insulative material such as a resin may be coated on the uppermost and lowermost surfaces of the conductor plating layer 114. The substrate is then subjected to electrolating to form conductor plating layers 115 (FIG. 8G). The resists lOla are removed, followed by flash etching, thereby to obtain a printed substrate P4 having a signal conductor pattern 117', land-formed through hole plating layers 117 and landless through hole plating layers 118 (FIG. 8H).
A twelfth process is similar to the above-mentioned eleventh process except that the step (vi) of forming the low melting point metal layers is carried out after the final etching step (viii). Thus, the twelfth process comprises the steps of:
(i) laminating with a resist a substrate having conductor foils formed on both surfaces thereof, followed by patterning the resist to form a resist pattern;
(ii) boring through holes in the resist-formed substrate;
(iii) subjecting the substrate to electroless plating to form an electroless plating conductor layer on the entire surface of the substrate including the inner walls of the through holes;
(iv) removing the uppermost and lowermost portions of the electroless plating conductor layer to expose the uppermost and lowermost portions of the resist;
(v) electroplating the resist-exposed substrate to form electroplating conductor layers on the region on which a signal conductor pattern is to be formed and on the inner wall of each through hole;
(vi) removing the resist from the electroplated substrate;
(vii) etching the substrate to remove the exposed portions of the electroless plating conductor layer; and then, (viii) forming layers of a low melting point metal on at least the upper and lower end portions of each through hole.
The above-mentioned fifth through twelfth processes are advantageous over the above-mentioned first through fourth processes in the following point. The first through fourth proceeses involve the electroplating step between the through holes-forming step and the resist pattern-forming step. In these processes, the substrate is subject to dimensional change in the electroplating step due to moisture absorption and temperature change, and therefor, the resist pattern formed becomes not in correct alignment with the through holes. For this reason, it is difficult to minimize or omit the land conductor portions in the substrate in order to produce a multilayer printed wiring board having a high density. In contrast to the first through fourth processes, in the above-mentioned fifth through twelfth processes, no dimensional change of the substrate occurs between the resist pattern-forming step and the through hole-forming step, and thus, the resulting substrate can be advantageously used for the manufacture of a multilayer printed wiring board of a particularly high density. In the above-mentioned ninth and tenth processes, the light-exposed photoresists are developed (FIG. 7C). However, this development is carried out prior to the formation of the through holes 104. Therefore, the '~
:; . :., moisture absorption of the substrate occurs only to a negligible extent, and thus, the resist pattern can be in correct alignment with the through holes.
In the process of manufacturing the multilayer printed wiring board of the invention, it is desired or required to enlarge the thickness of portions of the land conductor pattern surrounding the through holes bored in each substrate as compared with the thickness of the other portions of the land conductor pattern, in order to obtain the desired interlayer distance between the respective substrates.
This is advantageously achieved by a process which comprises the steps of:
(i) forming a first conductor pattern on a substrate, and then, (ii) a resist is formed on portions of the first conductor pattern, followed by forming a second conductor pattern on the other portions of the first conductor pattern on which the resist has not been formed. This process will be described in the following with reference to FIGS. 9A through 9D.
Referring to FIGS. 9A through 9D, a substrate 80 having conductor foils 81 formed on both surfaces thereof is bored to form through holes, and then, the entire surface of the substrate including the inner walls of the through holes is electroplated to form a conductor layer 82 (FIG. 9A). A first resist 83 is formed on the conductor--plated substrate 81 by a procedure wherein a photoresist is laminated thereon followed by light exposure and development r~

- 39 ~

or a screen printing procedure, and then, the substrate is electroplated to form a first conductor pattern 84 (FIG. 9B).
Thereafter, a second resist 85 is formed on the first resist 83 and on portions of the first conductor pattern 84, and then, the substrate is electroplated to form a second conductor pattern 86 on the other portions of the first conductor pattern 84 on which portions the second resist 85 has not been formed (FIG. 9C). Then, the substrate is plated with a low melting point metal to form layers 88 of a low melting point metal on the second conductor pattern 86 (FIG. 9C). Finally, the first resist 83 and the second resist 85 are removed from the substrate, and then, the substrate is subjected to flash etching thereby to obtain a printed substrate shown in FI~. 9D, which has thicker conductor portions than the other conductor portions. In the above-mentioned process, it is preferable that, prior to the formation of the second resist 85, the predominant surfaces of the first resist 83 and the first conductor pattern 84 formed on the substrate are subjected to leveling by polishing the predominant surfaces, for example, by using a sand paper. Such leveling enhances the bond strength of the second resist 85 and the uniformity in thickness of the first conductor pattern 84 . The above--mentioned process for preparing a printed substrate having thick conductor portions and thin conductor portions can be applied to any of the hereinbefore-mentioned processes for the preparation of printed substrates.
The formation of a conductor pattern or patterns on . .

.

~"~3~ t~

the substrate may be effected by an additive process, a substractive process and other conventional processes~
However, the semi-additive process, described below, is most preferable in order to obtain a conductor pattern of a high precision. The semi-additive process comprises the following sequential steps (i) through (vii), which steps are diagrammatically illustrated in FIGS. lOA through lOH.
(i) A surface of an aluminum foil 90 is roughened by means of, for example, etching or anodic oxidation (FIG. lOA).
(ii) The roughened surface 90' is plated with a thin conductor layer 91 (FIG. lOB). This plating may be of either dry or wet type. The thickness of the conductor layer 91 is preferably less than 2 microns, more preferably less than 0.5 micron.
(iii) If desired, the exposed surface of the thin eonduetor layer 91 is ehemieally treated.
(iv) The eonductor-plated aluminum foil is superposed on a substrate 92 so that the conductor layer 91 faees the substrate 92, and then, adhered together by applying heat and pressure (FIG. lOC).
(v) The aluminum foil is removed while the thin eonduetor layer 91 remains on the substrate 92 (FIG. lOD).
The removal of aluminum is effected by mechanical peeling or chemical etching. The obtained substrate 92 having the thin eonduetor layer 91 may be treated by a eonventional semi-additive proeess as follows.
(vi) The substrate 92 having the thin conduetor layer 91 is coated or laminated with a photoresist 93, and an artwork film 94 is placed on the photoresist 93, followed by light exposure (FIG. lOE) and development of the photo-resist 93 to remove portions of the photoresist 93 in the pattern region 95 (FIG. lOF).
(vii) A plating conductor layer 96 is formed in the pattern region 95 (FIG. lOG), and then, the photoresist 93 is removed and finally, portions of the thin conductor layer 91 present in the non-pattern region are removed by etching to obtain the substrate 92 having a conductor pattern 97 (FIG. lOH).
The conductor layer 91 formed on the substrate 92 by the above-mentioned steps (i) through (v) (FIGS. lOA
through lOD), is characterized in that it can be far thinner than a conductor layer formed by a conventional procedure. Therefore, the portions of the conductor layer 91 present in the non-patterned region can be removed within a short period of time in the above-mentioned et~hing step (vii) (FIGS. lOG and lOH), and thus, the conductor 96 does not become thin during the etching step.
The advantages of the hollow multilayer printed wiring board of the present invention are summarized as follows.
(i) The hollow multilayer printed wiring board has ~5 through hole conductor plating layers serving as an inter~
layer adhesion and a through connection between the printed substrates and, hence, exhibits good heat dessipation and enhanced dimensional stability. This is in a striking . . , , !

.~ '. ' ~ ' ";

' `', contrast to a conventional non-hollow multilayer printed wiring board having a structure such that the printed substrates are adhered to each other by interposed glass cloths inpregnated with a partially cured synthetic resin.
The synthetic resin-impregnated glass cloths exhibit great shrinkage upon curing.
(ii) The hollow multilayer printed wiring board exhibits good thermal resistance. This is particularly true when the surface substrates are made of an inorganic material such as ceramics or an insulation-treated metal and the intermediate substrates are made of an insulation--treated metal. Therefore, parts can be directly bonded to the surface of the hollow multilayer printed wiring board.
(iii) The occurrence of a crosstalk phenomenon can be minimi~ed particularly when the hollow multilayer printed wiring board has a structure such that the signal conductor is covered or surrounded with ground conductors.

'

Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A hollow multilayer printed wiring board which comprises a plurality of superposed substrates, each substrate having a signal conductor pattern formed on at least one sur-face thereof and a land conductor pattern formed on at least one surface thereof, and being superposed upon each other with a predetermined space therebetween filled with an insulative gas or liquid, and each substrate having plated through holes in the land conductor pattern, each of which plated through holes is in line with another plated through hole of each of the neighboring substrates or of at least one of the neighbor-ing substrates to form a plated through hole or interstitial via hole, a layer of a low melting point metal being formed at least on the upper and lower end surfaces of the plating layer defining each plated through hole, which low melting point metal layer serves as a through connection between two or more signal conductor patterns of the substrates and as an interlayer ad-hesion between the substrates, and the superposed substrates, except for at least one surface substrate, being made of a thermally resistant organic synthetic resin sheet or an in-sulation-treated metal sheet.

43

3. The printed board of claim 1, wherein a spacer having land conductor patterns formed on both sides thereof is inter-posed between the neighboring substrates so that there is provided predetermined spaces between the spacer and the neigh-boring substrates, said spacer having plated through holes in the land conductor patterns, each of which plated through holes is in line with plated through holes of the neighboring sub-strates to form the through hole or interstitial via hole.

4. The printed board of claim 2, wherein a spacer having land conductor patterns formed on both sides thereof is inter-posed between the neighboring substrates so that there is provided predetermined spaces between the spacer and the neigh-boring substrates, said spacer having plated through holes in the land conductor patterns, each of which plated through holes is in line with plated through holes of the neighboring sub-strates to form the through hole or interstitial via hole.

5. The printed board of claim 1 or 2, wherein said in-sulation-treated metal sheet is an anodically oxidized metal sheet.

6. The printed board of claim 3 or 4, wherein said in-sulation-treated metal sheet is an anodically oxidized metal sheet.

7. The printed board of claim 1 or 2, wherein said in-sulation-treated metal sheet is a metal sheet having an insula-tion material layer deposited thereon.

8. The printed board of claim 3 or 4, wherein said in-sulation-treated metal sheet is a metal sheet having an insula-tion material layer deposited thereon.

9. The printed board of claim 1 or 2, wherein said in-sulation-treated metal sheet is prepared by anodically oxidizing a metal sheet and then, coating or laminating the anodically oxidized metal sheet with an insulation material.

10. The printed board of claim 3 or 4, wherein said in-sulation-treated metal sheet is prepared by anodically oxidizing a metal sheet and then, coating or laminating the anodically oxidized metal sheet with an insulation material.

11. The printed board of claim 1 or 2, wherein said thermally resistant organic synthetic resin sheet is formed of a polyimide, an epoxy resin or a triazine resin.

12. The printed board of claim 3 or 4, wherein said thermally resistant organic synthetic resin sheet is formed of a polyimide, an epoxy resin or a triazine resin.

13. The printed board of claim 1 or 2, wherein at least one of the surface substrates is made of an inorganic thermally resistant material.

14. The printed board of claim 3 or 4, wherein at least one of the surface substrates is made of an inorganic thermally resistant material.

15. The printed board of claim 1 or 2, wherein said insulation-treated metal sheet is an anodically oxidized metal sheet, and wherein at least one of the surface substrates is made of an inorganic thermally resistant material.

16. The printed board of claim 3 or 4, wherein said insulation-treated metal sheet is a metal sheet having an insulation material layer deposited thereon, and wherein at least one of the surface substrates is made of an inorganic thermally resistant material.

17. The printed board of claim 1 or 2, wherein said insulation-treated metal sheet is prepared by anodically oxidizing a metal sheet and then, coating or laminating the anodically oxidized metal sheet with an insulation material, and wherein at least one of the surface substrates is made of an inorganic thermally resistant material.

18. The printed board of claim 3 or 4, wherein said insulation-treated metal sheet is prepared by anodically oxidizing a metal sheet and then, coating or laminating the anodically oxidized metal sheet with an insulation material and wherein at least one of the surface substrates is made of an inorganic thermally resistant material.

19. The printed board of claim 1 or 2, wherein said thermally resistant organic synthetic resin sheet is formed of a polyimide, an epoxy resin or a triazine resin, and wherein at least one of the surface substrates is made of an inorganic thermally resistant material.

20. The printed board of claim 3 or 4, wherein said thermally resistant organic synthetic resin sheet is formed of a polyimide, an epoxy resin or a triazine resin, and wherein at least one of the surface substrates is made of an inorganic thermally resistant material.

21. The printed board of claim 1 or 2, wherein the thermally resistant material is a ceramic or an insulation-treated metal.

22. The printed board of claim 3 or 4, wherein the thermally resistant material is a ceramic or an insulation-treated metal.

23. The printed board of claim 1 or 2, wherein said insulation-treated metal sheet is an anodically oxidized metal sheet, and the thermally resistant material is a ceramic or an insulation-treated metal.

24. The printed board of claim 3 or 4, wherein said in-sulation-treated metal sheet is an anodically oxidized metal sheet, and the thermally resistant material is a ceramic or an insulation-treated metal.

25. The printed board of claim 1 or 2, wherein said in-sulation-treated metal sheet is a metal sheet having an insula-tion material layer deposited thereon, and the thermally re-sistant material is a ceramic or an insulation-treated metal.

26. The printed board of claim 3 or 4, wherein said in-sulation-treated metal sheet is a metal sheet having an insula-tion material layer deposited thereon, and the thermally re-sistant material is a ceramic or an insulation-treated metal.

27. The printed board of claim 1 or 2, wherein said in-sulation-treated metal sheet is prepared by anodically oxidiz ing a metal sheet and then, coating or laminating the anodi-cally oxidized metal sheet with an insulation material, and the thermally resistant material is a ceramic or an insulation-treated metal.

28. The printed board of claim 3 or 4, wherein said in-sulation-treated metal sheet is prepared by anodically oxidiz-ing a metal sheet and then, coating or laminating the anodically oxidized metal sheet with an insulation material, and the thermally resistant material is a ceramic or an insulation-treated metal.

29. The printed board of claim 1 or 2, wherein said thermally resistant organic synthetic resin sheet is formed of a polyimide, an epoxy resin or a triazine resin, and the thermally resistant material is a ceramic or an insulation-treated metal.

30. The printed board of claim 3 or 4, wherein said thermally resistant organic synthetic resin sheet is formed of a polyimide, an epoxy resin or a triazine resin, and the thermally resistant material is a ceramic or an insulation-treated metal.

31. The printed board of claim 1 or 2, wherein at least one of the surface substrates is made of an inorganic thermally resistant material, and the thermally resistant material is a ceramic or an insulation-treated metal.

32. The printed board of claim 3 or 4, wherein at least one of the surface substrates is made of an inorganic thermally resistant material, and the thermally resistant material is a ceramic or an insulation-treated metal.

33. The printed board of claim 1 or 2, wherein said insulation-treated metal sheet is an anodically oxidized metal sheet, and wherein at least one of the surface substrates is made of an inorganic thermally resistant material, and the thermally resistant material is a ceramic or an insulation-treated metal.

34. The printed board of claim 3 or 4, wherein said insulation-treated metal sheet is a metal sheet having an insulation material layer deposited thereon, and wherein at least one of the surface substrates is made of an inorganic thermally resistant material, and the thermally resistant material is a ceramic or an insulation-treated metal.

35. The printed board of claim 1 or 2, wherein said insulation-treated metal sheet is prepared by anodically oxidizing a metal sheet and then, coating or laminating the anodically oxidized metal sheet with an insulation material, and wherein at least one of the surface substrates is made of an inorganic thermally resistant material, and the thermally resistant material is a ceramic or an insulation-treated metal.

36. The printed board of claim 3 or 4, wherein said in-sulation-treated metal sheet is prepared by anodically oxidiz-ing a metal sheet and then, coating or laminating the anodically oxidized metal sheet with an insulation material and wherein at least one of the surface substrates is made of an inorganic thermally resistant material, and the thermally resistant material is a ceramic or an insulation-treated metal.

37. The printed board of claim 1 or 2, wherein said thermally resistant organic synthetic resin sheet is formed of a polyimide, an epoxy resin or a triazine resin, and wherein at least one of the surface substrates is made of an inorganic thermally resistant material, and the thermally resistant material is a ceramic or an insulation-treated metal.

38. The printed board of claim 3 or 4, wherein said thermally resistant organic synthetic resin sheet is formed of a polyimide, an epoxy resin or a triazine resin, and wherein at least one of the surface substrates is made of an inorganic thermally resistant material, and the thermally resistant material is a ceramic or an insulation-treated metal.

39. The printed board of claim 1 or 2, wherein at least one of the substrates is a non-hollow multilayer printed wiring board.

40. The printed board of claim 3 or 4, wherein a ceramic substrate having a signal conductor pattern formed on at least one surface thereof and a land conductor pattern formed on at least one surface thereof is superposed at a predetermined space on a non-hollow multilayer printed wiring board made of a thermally resistant organic synthetic resin material and having a land conductor pattern on at least one surface thereof con-fronting to the ceramic substrate, said ceramic substrate having through connection pads or plated through holes in the land conductor pattern or patterns, each of which through con-nection pads or plated through holes is in line with a plated through hole in the land conductor pattern on the non-hollow multilayer printed wiring board to form the through hole or interstitial via hole.

41. The printed board of claim 1 or 2, wherein said in-sulation-treated metal sheet is an anodically oxidized metal sheet, and wherein at least one of the substrates is a non-hollow multilayer printed wiring board.

42. The printed board of claim 3 or 4, wherein said in-sulation-treated metal sheet is an anodically oxidized metal sheet, and wherein at least one of the substrates is a non-hollow multilayer printed wiring board.

43. The printed board of claim 1 or 2, wherein said in-sulation-treated metal sheet is a metal sheet having an insula-tion material layer deposited thereon, and wherein at least one of the substrates is a non-hollow multilayer printed wiring board.

44. The printed board of claim 3 or 4, wherein said in-sulation-treated metal sheet is a metal sheet having an insulation material layer deposited thereon, and wherein at least one of the substrates is a non-hollow multilayer printed wiring board.

45. The printed board of claim 1 or 2, wherein said in-sulation-treated metal sheet is prepared by anodically oxidizing a metal sheet and then, coating or laminating the anodically oxidized metal sheet with an insulation material, and wherein at least one of the substrates is a non-hollow multilayer printed wiring board.

46. The printed board of claim 3 or 4, wherein said in-sulation-treated metal sheet is prepared by anodically oxidizing a metal sheet and then, coating or laminating the anodically oxidized metal sheet with an insulation material, and wherein at least one of the substrates is a non-hollow multilayer printed wiring board.

47. The printed board of claim 1 or 2, wherein said thermally resistant organic synthetic resin sheet is formed of a polyimide, an epoxy resin or a triazine resin, and wherein at least one of the substrates is a non-hollow multilayer printed wiring board.

48. The printed board of claim 3 or 4, wherein said thermally resistant organic synthetic resin sheet is formed of a polyimide, an epoxy resin or a triazine resin, and wherein at least one of the substrates is a non-hollow multilayer printed wiring board.

49. The printed board of claim 1 or 2, wherein at least one of the surface substrates is made of an inorganic thermally resistant material, and wherein at least one of the substrates is a non-hollow multilayer printed wiring board.

50. The printed board of claim 3 or 4, wherein at least one of the surface substrates is made of an inorganic thermally resistant material, and wherein at least one of the substrates is a non-hollow multilayer printed wiring board.

51. The printed board of claim 1 or 2, wherein said insulation-treated metal sheet is an anodically oxidized metal sheet, and wherein at least one of the surface substrates is made of an inorganic thermally resistant material, and wherein at least one of the substrates is a non-hollow multi-layer printed wiring board.

52. The printed board of claim 3 or 4, wherein said insulation-treated metal sheet is a metal sheet having an insulation material layer deposited thereon, and wherein at least one of the surface substrates is made of an inorganic thermally resistant material, and wherein at least one of the substrates is a non-hollow multilayer printed wiring board.

53. The printed board of claim 1 or 2, wherein said insulation-treated metal sheet is prepared by anodically oxidizing a metal sheet and then, coating or laminating the anodically oxidized metal sheet with an insulation material, and wherein at least one of the surface substrates is made of an inorganic thermally resistant material, and wherein at least one of the substrates is a non-hollow multilayer printed wiring board.

54. The printed board of claim 3 or 4, wherein said in-sulation-treated metal sheet is prepared by anodically oxidizing a metal sheet and then, coating or laminating the anodically oxidized metal sheet with an insulation material and wherein at least one of the surface substrates is made of an inorganic thermally resistant material, and wherein at least one of the substrates is a non-hollow multilayer printed wiring board.

55. The printed board of claim 1 or 2, wherein said thermally resistant organic synthetic resin sheet is formed of a polyimide, an epoxy resin or a triazine resin, and wherein at least one of the surface substrates is made of an inorganic thermally resistant material, and wherein at least one of the substrates is a non-hollow multilayer printed wiring board.

56. The printed board of claim 3 or 4, wherein said thermally resistant organic synthetic resin sheet is formed of a polyimide, an epoxy resin or a triazine resin, and wherein at least one of the surface substrates is made of an inorganic thermally resistant material, and wherein at least one of the substrates is a non-hollow multilayer printed wiring board.

57. The printed board of claim 1 or 2, wherein the thermally resistant material is a ceramic or an insulation-treated metal, and wherein at least one of the substrates is a non-hollow multilayer printed wiring board.

58. The printed board of claim 3 or 4, wherein the thermally resistant material is a ceramic or an insulation-treated metal, and wherein at least one of the substrates is a non-hollow multilayer printed wiring board.

59. The printed board of claim 1 or 2, wherein at least one of the surface substrates is made of an inorganic thermally resistant material, said thermally resistant material is a ceramic or an insulation-treated metal, and wherein a ceramic substrate having a signal conductor pattern formed on at least one surface thereof and a land conductor pattern formed on at least one surface thereof is superposed at a predetermined space on a non-hollow multilayer printed wiring board made of a thermally resistant organic synthetic resin material and having a land conductor pattern on at least one surface thereof con-fronting to the ceramic substrate, said ceramic substrate having through connection pads or plated through holes in the land conductor pattern or patterns, each of which through con-nection pads or plated through holes is in line with a plated through hole in the land conductor pattern on the non-hollow multilayer printed wiring board to form the through hole or interstitial via hole.

60. The printed board of claim 3 or 4, wherein at least one of the surface substrates is made of an inorganic thermally resistant material, said thermally resistant material is a ceramic or an insulation-treated metal, and wherein a ceramic substrate having a signal conductor pattern formed on at least one surface thereof and a land conductor pattern formed on at least one surface thereof is superposed at a predetermined space on a non-hollow multilayer printed wiring board made of a thermally resistant organic synthetic resin material and having a land conductor pattern on at least one surface thereof con-fronting to the ceramic substrate, said ceramic substrate hav-r' IL.

ing through connection pads or plated through holes in the land conductor pattern or patterns, each of which through con-nection pads or plated through holes is in line with a plated through hole in the land conductor pattern on the non-hollow multilayer printed wiring board to form the through hole or interstitial via hole.

61. The printed board of claim 1 or 2, wherein said signal conductor pattern is covered with a ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed.

62. The printed board of claim 3 or 4, wherein said signal conductor pattern is covered with a ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed.

63. The printed board of claim 1 or 2, wherein said insulation-treated metal sheet is an anodically oxidized metal sheet, wherein said signal conductor pattern is covered with a ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the sub-strate as that on which the signal conductor pattern is formed.

64. The printed board of claim 3 or 4, wherein said in-sulation-treated metal sheet is an anodically oxidized metal sheet, wherein said signal conductor pattern is covered with a ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed.

65. The printed board of claim 1 or 2, wherein said in-sulation-treated metal sheet is a metal sheet having an in-sulation material layer deposited thereon, wherein said signal conductor pattern is covered with a ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed.

66. The printed board of claim 3 or 4, wherein said in-sulation-treated metal sheet is a metal sheet having an insula-tion material layer deposited thereon, wherein said signal conductor pattern is covered with a ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed.

67. The printed board of claim 1 or 2, wherein said in-sulation-treated metal sheet is prepared by anodically oxidizing a metal sheet and then, coating or laminating the anodically oxidized metal sheet with an insulation material, wherein said signal conductor pattern is covered with a ground con-ductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed.

68. The printed board of claim 3 or 4, wherein said in-sulation-treated metal sheet is prepared by anodically oxidizing a metal sheet and then, coating or laminating the anodically oxidized metal sheet with an insulation material, wherein said signal conductor pattern is covered with a ground conductor pattern electrically isolated from the signal con-ductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed.

69. The printed board of claim 1 or 2, wherein said thermally resistant organic synthetic resin sheet is formed of a polyimide, an epoxy resin or a triazine resin, wherein said signal conductor pattern is covered with a ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed.

70. The printed board of claim 3 or 4, wherein said thermally resistant organic synthetic resin sheet is formed of a polyimide, an epoxy resin or a triazine resin, wherein said signal conductor pattern is covered with a ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed.

71. The printed board of claim 1 or 2, wherein at least one of the surface substrates is made of an inorganic thermally resistant material, wherein said signal conductor pattern is covered with a ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal con-ductor pattern is formed.

72. The printed board of claim 3 or 4, wherein at least one of the surface substrates is made of an inorganic thermally resistant material, wherein said signal conductor pattern is covered with a ground conductor pattern electri-cally isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed.

73. The printed board of claim 1 or 2, wherein said insulation-treated metal sheet is an anodically oxidized metal sheet, and wherein at least one of the surface sub-strates is made of an inorganic thermally resistant material, wherein said signal conductor pattern is covered with a ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed.

74. The printed board of claim 3 or 4, wherein said insulation-treated metal sheet is a metal sheet having an insulation material layer deposited thereon, and wherein at least one of the surface substrates is made of an inorganic thermally resistant material, wherein said signal conductor pattern is covered with a ground conductor pattern electri-cally isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed.

75. The printed board of claim 1 or 2, wherein said insulation-treated metal sheet is prepared by anodically oxidizing a metal sheet and then, coating or laminating the anodically oxidized metal sheet with an insulation material, and wherein at least one of the surface substrates is made of an inorganic thermally resistant material, wherein said signal conductor pattern is covered with a ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed.

76. The printed board of claim 3 or 4, wherein said insulation-treated metal sheet is prepared by anodically oxidizing a metal sheet and then, coating or laminating the anodically oxidized metal sheet with an insulation material and wherein at least one of the surface substrates is made of an inorganic thermally resistant material, wherein said signal conductor pattern is covered with a ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed.

77. The printed board of claim 1 or 2, wherein said thermally resistant organic synthetic resin sheet is formed of a polyimide, an epoxy resin or a triazine resin, and wherein at least one of the surface substrates is made of an inorganic thermally resistant material, wherein said signal conductor pattern is covered with a ground conductor pattern electri-cally isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed.

78. The printed board of claim 3 or 4, wherein said thermally resistant organic synthetic resin sheet is formed of a polyimide, an epoxy resin or a triazine resin, and wherein at least one of the surface substrates is made of an inorganic thermally resistant material, wherein said signal conductor pattern is covered with a ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed.

79. The printed board of claim 1 or 2, wherein the thermally resistant material is a ceramic or an insulation-treated metal, wherein said signal conductor pattern is covered with a ground conductor pattern electrically isolated from the signal con-ductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed.

80. The printed board of claim 3 or 4, wherein the thermally resistant material is a ceramic or an insulation-treated metal, wherein said signal conductor pattern is covered with a ground condutor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed.

81. The printed board of claim 1 or 2, wherein at least one of the surface substrates is made of an inorganic thermally resistant material, said thermally resistant material is a ceramic or an insulation-treated metal, and wherein a ceramic substrate having a signal conductor pattern formed on at least one surface thereof and a land conductor pattern formed on at least one surface thereof is superposed at a predetermined space on a non-hollow multilayer printed wiring board made of a thermally resistant organic synthetic resin material and having a land conductor pattern on at least one surface thereof confronting to the ceramic substrate, said ceramic substrate having through connection pads or plated through holes in the land conductor pattern or patterns, each of which through connection pads or plated through holes is in line with a plated through hole in the land conductor pattern on the non-hollow multilayer printed wiring board to form the through hole or interstitial via hole, wherein said signal conductor pattern is covered with a ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed.

82. The printed board of claim 3 or 4, wherein at least one of the surface substrates is made of an inorganic thermally resistant material, said thermally resistant material is a ceramic or an insulation-treated metal, and wherein a ceramic substrate having a signal conductor pattern formed on at least one surface thereof and a land conductor pattern formed on at least one surface thereof is superposed at a predetermined space on a non-hollow multilayer printed wiring board made of a thermally resistant organic synthetic resin material and having a land conductor pattern on at least one surface thereof confronting to the ceramic substrate, said ceramic substrate having through connection pads or plated through holes in the land conductor pattern or patterns, each of which through connection pads or plated through holes is in line with a plated through hole in the land conductor pattern on the non-hollow multilayer printed wiring board to form the through hole or interstitial via hole, wherein said signal conductor pattern is covered with a ground conductor pattern electrically isolated from the signal conductor and formed on the same surface of the substrate as that on which the signal conductor pattern is formed.

83. The printed board of claim 1 or 2, wherein said signal conductor pattern is sandwiched between conductors of a first ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the sub-strate as that on which said signal conductor pattern is formed, and said signal conductor pattern is covered with a second ground conductor pattern electrically isolated from the signal conductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the substrate having the signal conductor pattern, said second ground conductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern.

84. The printed board of claim 3 or 4, wherein said signal conductor pattern is sandwiched between conductors of a first ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the sub-strate as that on which said signal conductor pattern is formed, and said signal conductor pattern is covered with a second ground conductor pattern electrically isolated from the signal conductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the sub-strate having the signal conductor pattern, said second ground conductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern.

85. The printed board of claim 1 or 2, wherein said in-sulation-treated metal sheet is an anodically oxidized metal sheet, wherein said signal conductor pattern is sandwiched between conductors of a first ground conductor pattern electrically isolated from the signal conductor-pattern and formed on the same surface of the substrate as that on which said signal conductor pattern is formed, and said signal con-ductor pattern is covered with a second ground conductor pattern electrically isolated from the signal conductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the substrate having the signal conductor pattern, said second ground conductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern.

86. The printed board of claim 3 or 4, wherein said in-sulation-treated metal sheet is an anodically oxidized metal sheet, and wherein said signal conductor pattern is sand-wiched between conductors of a first ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which said signal conductor pattern is formed, and said signal conductor pattern is covered with a second ground conductor pattern electrically isolated from the signal conductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the substrate having the signal conductor pattern, said second ground conductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern.

87. The printed board of claim 1 or 2, wherein said in-sulation-treated metal sheet is a metal sheet having an insula-tion material layer deposited thereon, and wherein said signal conductor pattern is sandwiched between conductors of a first ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the sub-strate as that on which said signal conductor pattern is formed, and said signal conductor pattern is covered with a second ground conductor pattern electrically isolated from the signal con-ductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the substrate having the signal conductor pattern, said second ground conductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern.

88. The printed board of claim 3 or 4, wherein said in-sulation-treated metal sheet is a metal sheet having an insula-tion material layer deposited thereon, and wherein said signal conductor pattern is sandwiched between conductors of a first ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the sub-strate as that on which said signal conductor pattern is formed, and said signal conductor pattern is covered with a second ground conductor pattern electrically isolated from the signal conductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the substrate having the signal conductor pattern, said second ground conductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern.

89. The printed board of claim 1 or 2, wherein said in-sulation-treated metal sheet is prepared by anodically oxidiz-ing a metal sheet and then, coating or laminating the anodically oxidized metal sheet with an insulation-material, and wherein said signal conductor pattern is sandwiched between conductors of a first ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which said signal conductor pattern is formed, and said signal conductor pattern is covered with a second ground conductor pattern electrically isolated from the signal conductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the substrate having the signal conductor pattern, said second ground con-ductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground con-ductor pattern.

90. The printed board of claim 3 or 4, wherein said in-sulation-treated metal sheet is prepared by anodically oxidizing a metal sheet and then, coating or laminating the anodically oxidized metal sheet with an insulation material and wherein said signal conductor pattern is sandwiched between conductors of a first ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which said signal conductor pattern is formed, and said signal conductor pattern is covered with a second ground conductor pattern electrically isolated from the signal conductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the substrate having the signal conductor pattern, said second ground conductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern.

91. The printed board of claim 3 or 4, wherein said thermally resist-ant organic synthetic resin sheet is formed of a polyimide, an epoxy resin or a triazine resin, and wherein said signal conductor pattern is sandwiched between conductors of a first ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which said signal conductor pattern is formed, and said signal conductor pattern is covered with a second ground conductor pattern electrically isolated from the signal conductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the substrate having the signal conductor pattern, said second ground conductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern.

92. The printed board of claim 3 or 4, wherein said thermally re-sistant organic synthetic resin sheet is formed of a polyimide, an epoxy resin or a triazine resin, and wherein said signal conductor pattern is sandwiched between conductors of a first ground conductor pattern electrically isolated from the signal con-ductor pattern and formed on the same surface of the substrate as that on which said signal conductor pattern is formed, and said signal conductor pattern is covered with a second ground conductor pattern electrically isolated from the signal con-ductor pattern and formed on the confronting surface of the sub-strate or spacer adjacent to the substrate having the signal conductor pattern, said second ground conductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern.

93. The printed board of claim 1 or 2, wherein at least one of the surface substrates is made of an inorganic thermally resistant material, and wherein said signal conductor pattern is sandwiched between conductors of a first ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which said signal conductor pattern is formed, and said signal con-ductor pattern is covered with a second ground conductor pattern electrically isolated from the signal conductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the substrate having the signal conductor pattern, said second ground conductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern.

94. The printed board of claim 3 or 4, wherein at least one of the surface substrates is made of an inorganic thermally resistant material, and wherein said signal conductor pattern is sandwiched between conductors of a first ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which said signal conductor pattern is formed, and said signal conductor pattern is covered with a second ground con-ductor pattern electrically isolated from the signal con-ductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the substrate having the signal conductor pattern, said second ground conductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern.

95. The printed board of claim 1 or 2, wherein said insulation-treated metal sheet is an anodically oxidized metal sheet, and wherein at least one of the surface sub-strates is made of an inorganic thermally resistant material, and wherein said signal conductor pattern is sandwiched be-tween conductors of a first ground conductor pattern electri-cally isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which said signal conductor pattern is formed, and said signal conductor pattern is covered with a second ground conductor pattern electrically isolated from the signal conductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the substrate having the signal conductor pattern, said second ground conductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern.

96. The printed board of claim 3 or 4, wherein said in-sulation-treated metal sheet is a metal sheet having an in-sulation material layer deposited thereon, and wherein at least one of the surface substrates is made of an inorganic thermally resistant material, and wherein said signal con-ductor pattern is sandwiched between conductors of a first ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which said signal conductor pattern is formed, and said signal conductor pattern is covered with a second ground conductor pattern electrically isolated from the signal conductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the substrate having the signal conductor pattern, said second ground conductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern.

97. The printed board of claim 1 or 2, wherein said in-sulation-treated metal sheet is prepared by anodically oxidiz-ing a metal sheet and then, coating or laminating the anodi-cally oxidized metal sheet with an insulation material, and wherein at least one of the surface substrates is made of an inorganic thermally resistant material, and wherein said signal conductor pattern is sandwiched between conductors of a first ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which said signal conductor pattern is formed, and said signal conductor pattern is covered with a second ground conductor pattern electrically isolated from the signal conductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the substrate having the signal conductor pattern, said second ground conductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern.

98. The printed board of claim 3 or 4, wherein said insulation-treated metal sheet is prepared by anodically oxidizing a metal sheet and then, coating or laminating the anodically oxidized metal sheet with an insulation material and wherein at least one of the surface substrates is made of an inorganic thermally resistant material, and wherein said signal conductor pattern is sandwiched between conductors of a first ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which said signal conductor pattern is formed, and said signal conductor pattern is covered with a second ground conductor pattern electrically isolated from the signal conductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the substrate having the signal conductor pattern, said second ground con-ductor pattern having an area sufficient for covering the sig-nal conductor pattern and the conductors of the first ground conductor pattern.

99. The printed board of claim 1 or 2, wherein said thermally resistant organic synthetic resin sheet is formed of a polyimide, an epoxy resin or a triazine resin, and wherein at least one of the surface substrates is made of an inorganic thermally resistant material, and wherein said signal conductor pattern is sandwiched between conductors of a first ground conductor pattern electrically isolated from the signal con-ductor pattern and formed on the same surface of the sub-strate as that on which said signal conductor pattern is formed, and said signal conductor pattern is covered with a second ground conductor pattern electrically isolated from the signal con-ductor pattern and formed on the confronting surface of the sub-strate or spacer adjacent to the substrate having the signal conductor pattern, said second ground conductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern.

100. The printed board of claim 3 or 4, wherein said thermally resistant organic synthetic resin sheet is formed of a polyimide, an epoxy resin or a triazine resin, and wherein at least one of the surface substrates is made of an inorganic thermally resistant material, and wherein said signal con-ductor pattern is sandwiched between conductors of a first ground conductor pattern electrically isolated from the signal con-ductor pattern and formed on the same surface of the substrate as that on which said signal conductor pattern is formed, and said signal conductor pattern is covered with a second ground conductor pattern electrically isolated from the signal con-ductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the substrate having the signal conductor pattern, said second ground conductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern.

101. The printed board of claim 1 or 2, wherein the thermally resistant material is a ceramic or an insulation-treated metal, and wherein said signal conductor pattern is sand-wiched between conductors of a first ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which said signal conductor pattern is formed, and said signal conductor pattern is covered with a second ground conductor pattern electrically isolated from the signal conductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the substrate having the signal conductor pattern, said second ground conductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern.

102. The printed board of claim 3 or 4, wherein the thermally resistant material is a ceramic or an insulation-treated metal, and wherein said signal conductor pattern is sandwiched be-tween conductors of a first ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which said signal conductor pattern is formed, and said signal con-ductor pattern is covered with a second ground conductor pattern electrically isolated from the signal conductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the substrate having the signal con-ductor pattern, said second ground conductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern.

103. The printed board of claim 1 or 2, wherein at least one of the surface substrates is made of an inorganic thermally resistant material, said thermally resistant material is a ceramic or an insulation-treated metal, and wherein a ceramic substrate having a signal conductor pattern formed on at least one surface thereof and a land conductor pattern formed on at least one surface thereof is superposed at a predetermined space on a non-hollow multilayer printed wiring board made of a thermally resistant organic synthetic resin material and having a land conductor pattern on at least one surface thereof con-fronting to the ceramic substrate, said ceramic substrate having through connection pads or plated through holes in the land conductor pattern or patterns, each of which through con-nection pads or plated through holes is in line with a plated through hole in the land conductor pattern on the non-hollow multilayer printed wiring board to form the through hole or interstitial via hole, and wherein said signal conductor pattern is covered with a ground conductor pattern electri-cally isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed, and wherein said signal conductor pattern is sandwiched between conductors of a first ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the sub-strate as that on which said signal conductor pattern is formed, and said signal conductor pattern is covered with a second ground conductor pattern electrically isolated from the signal conductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the substrate having the signal conductor pattern, said second ground con-ductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern.

104. The printed board of claim 3 or 4, wherein at least one of the surface substrates is made of an inorganic thermally resistant material, said thermally resistant material is a ceramic or an insulation-treated metal, and wherein a ceramic substrate having a signal conductor pattern formed on at least one surface thereof and a land conductor pattern formed on at least one surface thereof is superposed at a predetermined space on a non-hollow multilayer printed wiring board made of a thermally resistant organic synthetic resin material and having a land conductor pattern on at least one surface thereof confronting to the ceramic substrate, said ceramic substrate having through connection pads or plated through holes in the land conductor pattern or patterns, each of which through connection pads or plated through holes is in line with a plated through hole in the land conductor pattern on the non-hollow multilayer printed wiring board to form the through hole or interstitial via hole, and wherein said signal conductor pattern is covered with a ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed, and wherein said signal conductor pattern is sandwiched between conductors of a first ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same sur-face of the substrate as that on which said signal conductor pattern is formed, and said signal conductor pattern is covered with a second ground conductor pattern electrically isolated from the signal conductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the substrate having the signal conductor pattern, said second ground conductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern.

105. A process for manufacturing a hollow multilayer printed wiring board which comprises the steps of:
preparing a plurality of printed substrates made of a thermally resistant organic synthetic resin sheet or an insulation-treated metal sheet, each substrate having a signal conductor pattern formed on at least one .
surface thereof and a land conductor pattern on at least one surface thereof and further having plated through holes in the land conductor pattern, a layer of a low melting point metal being formed at least on the upper and lower end surfaces of each of the plating layers defining the plated through holes; and then, superposing said printed substrates upon each other so that each of the plated through holes is in line with another plated through holes of each of the neighboring substrates or of at least one of the neighboring substrates, followed by applying a pressure and a heat sufficient for melt-adhering the substrate having the low melting point metal layer to the neighboring substrate or substrates.

106. A process according to claim 105, wherein said printed substrate is prepared by a process comprising the steps of:
(i) preparing a substrate having through holes therein;
(ii) subjecting the substrate to electroless plating to form an electroless plating conductor layer on the entire surface of the substrate including the inner walls of the through holes;
(iii) laminating the electroless-plated substrate with a resist followed by patterning the resist to form a resist pattern;
(iv) electroplating the resist-formed substrate to form electroplating conductor layers on the regions on which a signal conductor pattern and a land conductor pattern are to be formed and on the inner wall of each through hole;
(v) plating the electroplating conductor layer--formed substrate with a low melting point metal to form layers of the low melting point metal on at least the electroplating conductor layers formed on the upper and lower land portions of each through hole;

(vi) removing the resist from the substrate; and then, (vii) etching the substrate to remove the exposed portions of the electroless plating conductor layer.

107. A process according to claim105, wherein said printed substrate is prepared by a process comprising the steps of:
(i) preparing a substrate having through holes therein;
(ii) subjecting the substrate to electroless plating to form an electroless plating conductor layer on the entire surface of the substrate including the inner walls of the through holes;
(iii) laminating the electroless-plated substrate with a resist followed by patterning the resist to form a resist pattern;
(iv) electroplating the resist-formed substrate to form electroplating conductor layers on the regions on which a signal conductor pattern and a land conductor pattern are to be formed and on the inner wall of each through hole;
(v) removing the resist from the electroplated substrate;
(vi) etching the substrate to remove the exposed portions of the electroless plating conductor layer; and then, (vii) forming layers of a low melting point metal on at least the upper and lower land portions of each through hole.

108. A process according to claim 105, wherein said printed substrate is prepared by a process comprising the steps of:
(i) boring through holes in a land conductor.
pattern of a substrate having a signal conductor pattern on at least one surface thereof and the land conductor pattern on at least one surface thereof;
(ii) subjecting the substrate to electroless plating to form an electroless plating conductor layer on the entire surface of the substrate including the inner walls of the through holes;
(iii) laminating the electroless-plated substrate with a resist followed by patterning the resist to form a resist pattern;
(iv) electroplating the resist-formed substrate to form electroplating conductor layers on the inner wall and upper and lower land portions of each through hole;
(v) plating the electroplating conductor layer--formed substrate with a low melting point metal to form layers of the low melting point metal on at least the electroplating conductor layers formed on the upper and lower land portions of each through hole;
(vi) removing the resist from the substrate; and then, (vii) etching the substrate to remove the exposed portions of the electroless plating conductor layer.

109. A process according to claim 105, wherein said printed substrate is prepared by a process comprising the steps of:
(i) boring through holes in a land conductor pattern of a substrate having a signal conductor pattern on at least one surface thereof and the land conductor pattern on at least one surface thereof;
(ii) subjecting the substrate to electroless plating to form an electroless plating conductor layer on the entire surface of the substrate including the inner walls of the through holes;
(iii) laminating the electroless-plated substrate with a resist followed by patterning the resist to form a resist pattern;
(iv) electroplating the resist-formed substrate to form electroplating conductor layers on the inner wall and upper and lower land portions of each through hole;
(v) removing the resist from the electroplated substrate;
(vi) etching the substrate to remove the exposed portions of the electroless plating conductor layer; and then, (vii) forming layers of a low melting point metal on at least the upper and lower land portions of each through hole with a low melting point metal.

110. A process according to claim 105, wherein said printed substrate is prepared by a process comprising the steps of:
(i) laminating with a resist a substrate having conductor foils formed on both surfaces thereof, followed by patterning the resist to form a resist pattern;
(ii) boring through holes in the resist-formed substrate;
(iii) electroplating the substrate to form electro-plating conductor layers on the regions on which a signal conductor pattern and a land conductor pattern are to be formed and on the inner wall of each through hole;
(iv) plating the electroplating conductor layer--formed substrate with a low melting point metal to form layers of the low melting point metal on at least the electroplating conductor layers formed on the upper and lower land portions of each through hole;
(v) removing the resist from the substrate; and then, (vi) etching the substrate to remove the exposed portions of the conductor foils.

111. A process according to claim 105, wherein said printed substrate is prepared by a process comprising the steps of:
(i) laminating with a resist a substrate having conductor foils formed on both surfaces thereof, followed by patterning the resist to form a resist pattern;
(ii) boring through holes in the resist-formed substrate;
(iii) electroplating the substrate to form electro-plating conductor layers on the regions on which a signal conductor pattern and a land conductor pattern are to be formed and on the inner wall of each through hole;
(iv) removing the resist from the electroplated substrate;
(v) etching the substrate to remove the exposed portions of the conductor foils; and then, (vi) forming layers of a low melting point metal on at least the upper and lower land portions of each through hole.

112. A process according to claim 105, wherein said printed substrate is prepared by a process comprising the steps of:
(i) laminating with a resist a substrate having conductor foils formed on both surfaces thereof, followed by patterning the resist to form a resist pattern;
(ii) boring through holes in the resist-formed substrate;
(iii) electroplating the substrate to form electro-plating conductor layers on the region on which a signal conductor pattern is to be formed and on the inner wall of each through hole;
(iv) plating the electroplating conductor layer--formed substrate with a low melting point metal to form layers of the low melting point metal on at least the electroplating conductor layers formed on the upper and lower end portions of each through hole;
(v) removing the resist from the substrate; and then, (vi) etching the substrate to remove the exposed portions of the conductor foils.

113. A process according to claim 105, wherein said printed substrate is prepared by a process comprising the steps of:
(i) laminating with a resist a substrate having conductor foils formed on both surfaces thereof, followed by patterning the resist to form a resist pattern;
(ii) boring through holes in the resist-formed substrate;
(iii) electroplating the substrate to form electro-plating conductor layers on the region on which a signal conductor pattern is to be formed and on the inner wall of each through hole;
(iv) removing the resist from the electroplated substrate;
(v) etching the substrate to remove the exposed portions of the conductor foils; and then, (vi) forming layers of a low melting point metal on at least the upper and lower end portions of each through hole.

114. A process according to claim 105, wherein said printed substrate is prepared by a process comprising the steps of:

(i) laminating with a resist a substrate having conductor foils formed on both surfaces thereof, followed by patterning the resist to form a resist pattern;
(ii) boring through holes in the resist-formed substrate;

(iii) subjecting the substrate to electroless plating to form an electroless plating conductor layer on the entire surface of the substrate including the inner walls of the through holes;
(iv) removing the uppermost and lowermost portions of the electroless plating conductor layer to expose the uppermost and lowermost portions of the resist;
(v) electroplating the resist-exposed substrate to form electroplating conductor layers on the region on which a signal conductor pattern is to be formed and on the inner wall of each through hole;
(vi) plating the electroplating conductor layer--formed substrate with a low melting point metal to form layers of the low melting point metal on at least the electroplating conductor layers formed on the upper and lower end portions of each through hole;
(vii) removing the resist from the substrate; and then, (viii) etching the substrate to remove the exposed portions of the electroless plating conductor layer.

115. A process according to claim 105, wherein said printed substrate is prepared by a process comprising the steps of:
(i) laminating with a resist a substrate having conductor foils formed on both surfaces thereof, followed by patterning the resist to form a resist pattern;
(ii) boring through holes in the resist-formed substrate;

(iii) subjecting the substrate to electroless plating to form an electroless plating conductor layer on the entire surface of the substrate including the inner walls of the through holes;
(iv) removing the uppermost and lowermost portions of the electroless plating conductor layer to expose the uppermost and lowermost portions of the resist;
(v) electroplating the resist-exposed substrate to form electroplating conductor layers on the region on which a signal conductor pattern is to be formed and on the inner wall of each through hole;
(vi) removing the resist from the electroplated substrate;
(vii) etching the substrate to remove the exposed portions of the electroless plating conductor layer; and then, (viii) forming layers of a low melting point metal on at least the upper and lower end portions of each through hole with a low melting point metal.

116. A process according to claim 105, wherein said printed substrate is prepared by a process comprising the steps of:
(i) laminating a substrate having conductor foils formed on both surfaces thereof, with a first resist onto which a conductor is capable of being deposited by electroless plating and then, with a second resist, onto which a conductor is in capable of being deposited by electroless plating, to form a resist pattern;

(ii) boring through holes in the resist formed substrate;
(iii) subjecting the substrate to electroless plating to form electroless plating conductor layers on the region on which a signal conductor pattern is to be formed and on the inner wall of each through hole;
(iv) electroplating the substrate to form electro-plating conductor layers on the electroless plating conductor layers;
(v) plating the electroplating conductor layer--formed substrate with a low melting point metal to form layers of the low melting point metal on at least the electroplating conductor layers formed on the upper and lower end portions of each through hole;
(vi) removing the resist from the substrate; and then, (vii) etching the substrate to remove the exposed portions of the conductor foils.

117. A process according to claim 105, wherein said printed substrate is prepared by a process comprising the steps of:
(i) laminating a substrate having conductor foils formed on both surfaces thereof, with a first resist, onto which a conductor is capable of being deposited by electroless plating and then, with a second resist, onto which a conductor is incapable of being deposited by electroless plating, to form a resist pattern;
(ii) boring through holes in the resist-formed substrate;
(iii) subjecting the substrate to electroless plating to form electroless plating conductor layers on the region on which a signal conductor pattern is to be formed and on the inner wall of each through hole;
(iv) electroplating the substrate to form electro-plating conductor layers on the electroless plating conductor layers;
(v) removing the resist from the substrate;
(vi) etching the substrate to remove the exposed portions of the conductor foils; and then, (vii) forming layers of a low melting point metal on at least the upper and lower end portions of each through hole.

118. A process according to claims 105, 106 or 107, wherein the substrates having the plated through holes are superposed with an interposed spacer or spacers having plated through holes, which are bored in the land conductor patterns formed on both sides of the or each spacer, so that the plated through holes of the substrates are in line with the plated through holes of the interposed spacer or spacers to form through holes or interstitial via holes; a layer of a low melting point metal being formed at least on the upper and lower end surfaces of each of the plating layers defining the plated through holes.

119. A process according to claims 108, 109 or 110, wherein the substrates having the plated through holes are superposed with an interposed spacer or spacers having plated ]

through holes, which are bored in the land conductor patterns formed on both sides of the or each spacer, so that the plated through holes of the substrates are in line with the plated through holes of the interposed spacer or spacers to form through holes or interstitial via holes; a layer of a low melting point metal being formed at least on the upper and lower end surfaces of each of the plating layers defining the plated through holes.

120. A process according to claims 111, 112 or 113, wherein the substrates having the plated through holes are superposed with an interposed spacer or spacers having plated through holes, which are bored in the land conductor patterns formed on both sides of the or each spacer, so that the plated through holes of the substrates are in line with the plated through holes of the interposed spacer or spacers to form through holes or interstitial via holes; a layer of a low melting point metal being formed at least on the upper and lower end surfaces of each of the plating layers defining the plated through holes.

121. A process according to claims 114, 115 or 116, wherein the substrates having the plated through holes are superposed with an interposed spacer or spacers having plated through holes, which are bored in the land conductor patterns formed on both sides of the or each spacer, so that the plated through holes of the substrates are in line with the plated through holes of the interposed spacer or spacers to form through holes or interstitial via holes; a layer of a low melting point metal being formed at least on the upper and lower end surfaces of each of the plating layers defining the plated through holes.

122. A process according to claim 117, wherein the sub-strates having the plated through holes are superposed with an interposed spacer or spacers having plated through holes, which are bored in the land conductor patterns formed on both sides of the or each spacer, so that the plated through holes of the substrates are in line with the plated through holes of the interposed spacer or spacers to form through holes or interstitial via holes; a layer of a low melting point metal being formed at least on the upper and lower end surfaces of each of the plating layers defining the plated through holes.

123. A process for manufacturing a hollow multilayer printed wiring board which comprises the steps of:

preparing printed substrates made of a thermally resistant organic synthetic resin sheet or an insulation-treated metal sheet, each substrate having a signal conductor pattern on at least one surface thereof and a land conductor pattern on at least one surface thereof, and further having a layer of a low melting point metal formed on said conductor pattern;
superposing the substrates upon another so that the land conductor pattern having the low melting point metal layer of each substrate is in contact with the land conductor pattern or patterns having the low melting point metal layer of the neighboring substrate or substrates, followed by applying a pressure and a heat sufficient for melt-adhering the substrate having the low melting point metal layer to the neighboring substrate or substrates; and then, boring through holes in the melt-adhered land conductor patterns of the superposed substrates, followed by forming plating conductor layers on at least the inner walls of the through holes to complete plated through holes serving as a through connection between the two or more signal conductor patterns of the superposed substrates.

124. A process according to claim 123, wherein said printed substrate is prepared by a process comprising the steps of:
(i) laminating or coating with a resist a substrate having conductor foils formed on both surfaces thereof, followed by patterning the resist to form a resist pattern;
(ii) plating the resist formed substrate with a low melting point metal to form low melting point metal plating layers on the regions on which the signal conductor pattern and the land conductor pattern are to be formed;
(iii) removing the resist from the substrate; and then, (iv) etching the substrate to remove the exposed portions of the conductor foils.

125. A process according to claim 124, wherein the resist-formed substrate obtained by the step (i) is, prior to the step (ii), plated with a conductor to form plating conductor layers on the regions on which the signal conductor pattern and the land conductor pattern are to be formed.

126. A process according to claim 123, wherein said printed substrate is prepared by a process comprising the steps of:
(i) laminating or coating with a resist a substrate having conductor foils formed on both surfaces thereof, followed by patterning the resist to form a resist pattern;
(ii) etching the resist-formed substrate to remove the exposed portions of the conductor foils;
(iii) removing the resist from the substrate; and then, (iv) forming layers of a low melting point metal on at least the so formed land conductor pattern with allow melting point metal.

127. A process according to claim 123, wherein said printed substrate is prepared by a process comprising the steps of:
(i) laminating or coating with a resist a substrate having conductor foils formed on both surfaces thereof, followed by patterning the resist to form a resist pattern;
(ii) electroplating the resist-formed substrate to form electroplating conductor layers on the regions on which the signal conductor pattern and the land conductor pattern are to be formed;
(iii) removing the resist from the substrate;
(iv) etching the substrate to remove the conductor foils; and then, (v) coating at least the so formed land conductor pattern with a low melting point metal,

128. A process according to claims 123, 124 or 125, where-in the substrates having the low melting point metal plating layers on the land conductor patterns are superposed with an interposed spacer or spacers having low melting point metal layers on land conductor patterns formed on both sides of the or each spacer, so that the low melting point metal plating layers of the substrates are in contact with the low melting point metal plating layers of the interposed spacer or spacers.

129. A process according to claims 126 or 127, wherein the substrates having the low melting point metal plating layers on the land conductor patterns are superposed with an inter-posed spacer or spacers having low melting point metal layers on land conductor patterns formed on both sides of the or each spacer, so that the low melting point metal plating layers of the substrates are in contact with the low melting point metal plating layers of the interposed spacer or spacers.

130. A process according to claims 105, 106 or 107, wherein a side wall or walls are formed on the side periphery of the superposed substrates, thereby to seal the spaces between the superposed substrates.

131. A process according to claims 108, 109 or 110, wherein a side wall or walls are formed on the side periphery of the superposed substrates, thereby to seal the spaces between the superposed substrates.

132. A process according to claims 111, 112 or 113, wherein a side wall or walls are formed on the side periphery of the superposed substrates, thereby to seal the spaces between the superposed substrates.

133. A process according to claims 114, 115 or 116, wherein a side wall or walls are formed on the side periphery of the superposed substrates, thereby to seal the spaces between the superposed substrates.

134. A process according to claims 117, 1-23 or 124, wherein a side wall or walls are formed on the side periphery of the superposed substrates, thereby to seal the spaces between the superposed substrates.

135. A process according to claims 125, 126 or 127, wherein a side wall or walls are formed on the side periphery of the superposed substrates, thereby to seal the spaces between the superposed substrates.

136. A process according to claims 105, 106 or 107, wherein an anodically oxidized metal sheet is used as said insulation-treated metal sheet.

137. A process according to claims 108, 109 or 110, wherein an anodically oxidized metal sheet is used as said insulation-treated metal sheet.

138. A process according to claims 111, 112 or 113, wherein an anodically oxidized metal sheet is used as said insulation-treated metal sheet.

139. A process according to claims 114, 115 or 116, wherein an anodically oxidized metal sheet is used as said insulation-treated metal sheet.

140. A process according to claims 117, 123 or 124, wherein an anodically oxidized metal sheet is used as said insulation-treated metal sheet.

141. A process according to claims 125, 126 or 127, wherein an anodically oxidized metal sheet is used as said insulation-treated metal sheet.

142. A process according to claims 105, 106 or 107, wherein a metal sheet having an insulation material layer deposited thereon is used as said insulation-treated metal sheet.

143. A process according to claims 108, 109 or 110, wherein a metal sheet having an insulation material layer deposited thereon is used as said insulation-treated metal sheet.

144. A process according to claims 111, 112 or 113, wherein a metal sheet having an insulation material layer deposited thereon is used as said insulation-treated metal sheet.

145. A process according to claims 114, 115 or 116, wherein a metal sheet having an insulation material layer deposited thereon is used as said insulation-treated metal sheet.

146. A process according to claims 117, 123 or 124, wherein a metal sheet having an insulation material layer deposited thereon is used as said insulation-treated metal sheet.

147. A process according to claims 125, 126 or 127, wherein a metal sheet having an insulation material layer deposited thereon is used as said insulation-treated metal sheet.

148. A process according to claims 105, 106 or 107, wherein, as said insulation-treated metal sheet, a metal sheet is used which is prepared by anodically oxidizing a metal sheet and, then, coating the anodically oxidized metal sheet with an insulative material.

149. A process according to claims 108, 109 or 110, wherein, as said insulation-treated metal sheet, a metal sheet is used which is prepared by anodically oxidizing a metal sheet and, then, coating the anodically oxidized metal sheet with an insulative material.

150. A process according to claims 111, 112 or 113, wherein, as said insulation-treated metal sheet, a metal sheet is used which is prepared by anodically oxidizing a metal sheet and, then, coating the anodically oxidized metal sheet with an insulative material.

151. A process according to claims 114, 115 or 116, wherein, as said insulation-treated metal sheet, a metal sheet is used which is prepared by anodically oxidizing a metal sheet and, then, coating the anodically oxidized metal sheet with an insulative material.

152. A process according to claims 117, 123 or 124, wherein, as said insulation-treated metal sheet, a metal sheet is used which is prepared by anodically oxidizing a metal sheet and, then, coating the anodically oxidized metal sheet with an insulative material.

153. A process according to claims 125, 126 or 127, wherein, as said insulation-treated metal sheet, a metal sheet is used which is prepared by anodically oxidizing a metal sheet and, then, coating the anodically oxidized metal sheet with an insulative material.

154. A process according to claims 105, 106 or 107, wherein a polyimide sheet, an epoxy resin sheet or a triazine resin sheet is used as said organic synthetic resin sheet.

155. A process according to claims 108, 109 or 110, wherein a polyimide sheet, an epoxy resin sheet or a triazine resin sheet is used as said organic synthetic resin sheet.

156. A process according to claims 111, 112 or 113, wherein a polyimide sheet, an epoxy resin sheet or a triazine resin sheet is used as said organic synthetic resin sheet.

157. A process according to claims 114, 115 or 116, wherein a polyimide sheet, an epoxy resin sheet or a triazine resin sheet is used as said organic synthetic resin sheet.

158. A process according to claims 117, 123 or 124, wherein a polyimide sheet, an epoxy resin sheet or a triazine resin sheet is used as said organic synthetic resin sheet.

159. A process according to claims 125, 126 or 127, wherein a polyimide sheet, an epoxy resin sheet or a triazine resin sheet is used as said organic synthetic resin sheet.

160. A process according to claims 105, 106 or 107, where-in a sheet made of an inorganic thermally resistant material is used as at least one of the surface substrates.

161. A process according to claims 108, 109 or 110, where-in a sheet made of an inorganic thermally resistant material is used as at least one of the surface substrates.

162. A process according to claims 111, 112 or 113, where-in a sheet made of an inorganic thermally resistant material is used as at least one of the surface substrates.

163. A process according to claims 114, 115 or 116, where-in a sheet made of an inorganic thermally resistant material is used as at least one of the surface substrates.

164. A process according to claims 117, 123 or 124, wherein a sheet made of an inorganic thermally resistant material is used as at least one of the surface substrates.

165. A process according to claims 125, 126 or 127, wherein a sheet made of an inorganic thermally resistant material is used as at least one of the surface substrates.

166. A process according to claims 105, 106 or 107, wherein a sheet made of an inorganic thermally resistant material is used as at least one of the surface substrates which is a ceramic or an insulation-treated metal.

167. A process according to claims 108, 109 or 110, wherein a sheet made of an inorganic thermally resistant material is used as at least one of the surface substrates which is a ceramic or an insulation-treated metal.

168. A process according to claims 111, 112 or 113, wherein a sheet made of an inorganic thermally resistant material is used as at least one of the surface substrates which is a ceramic or an insulation-treated metal.

169. A process according to claims 114, 115 or 116, wherein a sheet made of an inorganic thermally resistant material is used as at least one of the surface substrates which is a ceramic or an insulation-treated metal.

170. A process according to claims 117, 123 or 124, wherein a sheet made of an inorganic thermally resistant material is used as at least one of the surface substrates which is a ceramic or an insulation-treated metal.

171. A process according to claims 125, 126 or 127, wherein a sheet made of an inorganic thermally resistant material is used as at least one of the surface substrates which is a ceramic or an insulation-treated metal.

172. A process according to claims 105, 106 or 107, wherein a non-hollow multilayer printed wiring board is used as at least one of the substrates.

173. A process according to claims 108, 109 or 110, wherein a non-hollow multilayer printed wiring board is used as at least one of the substrates.

174. A process according to claims 111, 112 or 113, wherein a non-hollow multilayer printed wiring board is used as at least one of the substrates.

175. A process according to claims 114, 115 or 116, wherein a non-hollow multilayer printed wiring board is used as at least one of the substrates.

176. A process according to claims 117, 123 or 124, wherein a non-hollow multilayer printed wiring board is used as at least one of the substrates.

177. A process according to claims 125, 126 or 127, wherein a non-hollow multilayer printed wiring board is used as at least one of the substrates.

178. A process according to claim 105, wherein a ceramic substrate having a signal conductor pattern formed on at least one surface thereof and a land conductor pattern formed on at least one surface thereof is superposed at a predetermined space on a non-hollow multilayer printed wiring board made of a thermally resistant organic synthetic resin material and having a land conductor pattern on at least one surface thereof confronting to the ceramic substrate, said ceramic substrate having through connection pads or plated through holes in the land conductor pattern, each of which through connection pads or plated through holes is in line with a plated through hole in the land conductor pattern of the non-hollow multilayer printed wiring board to form the plated through hole or the interstitial via hole.

179. A process according to claims 105, 106 or 107, wherein a ceramic substrate having a signal conductor pattern formed on at least one surface thereof and a land conductor pattern formed on at least one surface thereof is superposed at a predetermined space on a non-hollow multilayer printed wiring board made of a thermally resistant organic synthetic resin material and having a land conductor pattern on at least one surface thereof confronting to the ceramic substrate, said ceramic substrate having through connection pads or plated through holes in the land conductor pattern, each of which through connection pads or plated through holes is in line with a plated through hole in the land conductor pattern of the non-hollow multilayer printed wiring board to form the plated through hole or the interstitial via hole, and wherein a side wall or walls are formed on the side periphery of the super-posed substrates, thereby to seal the spaces between the superposed substrates.

180. A process according to claims 105, 106 or 107, wherein said signal conductor pattern is covered with a ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed.

181. A process according to claims 108, 109 or 110, wherein said signal conductor pattern is covered with a ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed.

182. A process according to claims 111, 112 or 113, wherein said signal conductor pattern is covered with a ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed.

183. A process according to claims 114, 115 or 116, wherein said signal conductor pattern is covered with a ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed.

184. A process according to claims 117, 123 or 124, wherein said signal conductor pattern is covered with a ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed.

185. A process according to claims 125, 126 or 127, wherein said signal conductor pattern is covered with a ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which the signal conductor pattern is formed.

186. A process according to claims 105, 106 or 107, wherein said signal conductor pattern is sandwiched between conductors of a first ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which said signal conductor pattern is formed, and said signal conductor pattern is covered with second ground conductor pattern electrically isolated from the signal conductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the substrate having the signal conductor pattern, said second conductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern.

187. A process according to claims 108, 109 or 110, wherein said signal conductor pattern is sandwiched between conductors of a first ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which said signal conductor pattern is formed, and said signal conductor pattern is covered with a second ground conductor pattern electrically isolated from the signal conductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the substrate having the signal conductor pattern, said second conductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern.

188. A process according to claims 111, 112 or 113, wherein said signal conductor pattern is sandwiched between conductors of a first ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which said signal conductor pattern is formed, and said signal conductor pattern is covered with a second ground conductor pattern electrically isolated from the signal conductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the substrate having the signal conductor pattern, said second conductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern.

189. A process according to claims 114, 115 or 116, wherein said signal conductor pattern is sandwiched between conductors of a first ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which said signal conductor pattern is formed, and said signal conductor pattern is covered with a second ground conductor pattern electrically isolated from the signal conductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the substrate having the signal conductor pattern, said second conductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern.

190. A process according to claims 117, 123 or 124, wherein said signal conductor pattern is sandwiched between conductors of a first ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which said signal conductor pattern is formed, and said signal conductor pattern is covered with a second ground conductor pattern electrically isolated from the signal conductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the substrate having the signal conductor pattern, said second conductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern.

191. A process according to claims 125, 126 or 127, wherein said signal conductor pattern is sandwiched between conductors of a first ground conductor pattern electrically isolated from the signal conductor pattern and formed on the same surface of the substrate as that on which said signal conductor pattern is formed, and said signal conductor pattern is covered with a second ground conductor pattern electrically isolated from the signal conductor pattern and formed on the confronting surface of the substrate or spacer adjacent to the substrate having the signal conductor pattern, said second conductor pattern having an area sufficient for covering the signal conductor pattern and the conductors of the first ground conductor pattern.