CA1155217A - Filter and system incorporating the filter for processing discrete samples of composit signals - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
A system for processing discrete digitized samples representing composite signals utilizing a filter which eliminates a periodic signal component from the composite signal. The filter receives and stores consecutive digital sample representations of the composite signal and, for each received sample representation, provides a digital average representation of the values of a selected number of the received digital sample represen-tations which define a zero average value of the periodic signal component. In one embodiment of the signal processing system, the filter is arranged in circuit with digital delays and digital signal combining and differencing circuits to form a digital color television signal dropout compensator, which is adaptable for use in NTSC, PAL, PAL-M, or other television standard systems. In a dropout compensator adapted for NTSC
color television signals, the filler receives the digital composite television signal and eliminates the chrominance component therefrom, leaving only the luminance component at its output. A following digital subtractor is coupled to subtract the luminance component provided by the filter from the received digital composite television signal and provide the chrominance component at its output. The separated chrominance component is phase adjusted on consecutive television lines and recombined with the separated luminance component provided by the filter for substitution in the tele-vision signal in place of the dropout affected portion thereof. The dropout compensator also includes a digital delay of one horizontal line period through which the television signal components are passed to provide the delay necessary for substituting television signal information from a prior horizontal line.

Description

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~ The present invention relates ~o a filter ~or -ocessing composite signals and a dxopout coml?ensator u~ zing the ~ er and, more par~ic~larly, to a filter for processing digital represen~ations of composite signals and a digital dropou~ compensator utilizing the filter ~or separa~ing componen~s of a composite signal.

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~l,55 Z~7 ID-2635 In systems for processing composite signals, it i~ often desirable to sepa~ate various signal compo-nents into different signal paths for individual process-ing and then recombine the processed components into a composite -. 5 signal form for further us~O Known devices for separating composite signals composed of different frequency co~ponents are comb filters. Generally, comb filters are known as multiple bandpass filters designed to pass siynals of selected frequency bands and to reject signals outside the se}ected frequency bands. For example/ in processing color television signals, comb filters are widely utili~ed for separating the luminance and chrvminance components. One such comb filter produces the desired separa~ion by processing : discrete digitized samples representing the analog color ~ 15 television signal and providing a weighted average o~ th~ee ;: samples taken ~rom three consecutive horizontal lines o~ the ~ame ~ield ~t v~rtically aligned picture elements o~ the ~ lines. The averaging is repeated or all picture elements.
; While this method is applicable to analog signals, it is 20 particularly ~uitable for digitally encoded signals, since these typically r~present samples of discret~ signal values occurring at a known sampling frequency. ~owever, to obtain samples from the vertically aligned picture elemen~s o~ten requires selection of special sampling rates or special 25 sampling phases and the addition of urther sample processing circui~s, thus complicatlng the apparatus.

, For example, in some standard color television, signal systems, the color subcarrier signal component differs in phase on ad~acent lines of the television field raster. In ~TSC systems, the phase difference is 5 180 degrees; and~ in PAL and PAL-M systems, it is 90 degrees. Some digital signal processing systems ~or such television signals utilize a sampling signal frequency that is an odd multiple of the subcarrier signal frequency. To obtain samples of such television lO 5ignals corresponding to locations of vertically aligned pic~ure elements, the aforementioned further circuits are necessary to provide line-~o-line phase adjustment of the sampling of the ~elevi~ion signal. If samples corresponding to locations of vertically mi~aligned 15 picture elements are comb filtered, picture dlstortion results. Ag an example, a circuit ~or generatiny samples corresponding to vertically aligned picture element loca~ions within a television field raster is described in U. 5. Patent No~ 4,075,656. The above 20 patent ~eveals that sucb circuit contributes to the complexity of the overall system for processing digi-tized color~television signals. A prior ar~ digital co~b filter circuit suitab}e for NTSC systems is described in ~. S. Patent No. 4,143,396. While this 25 type of comb filtering is suitable for NTSC systems, the specific embodiments described in the 4,143,396 paten~ must be provided with further processing circuitry for other color television systems, such as PAL, PAI.-~, e~c., where the differen~ chrominance I~,-2635 i21~

component line-to~line phase characteristics create additional problems in obtaining samples corresponding to locations of vertically aligned picture elements of con~ecutiYe lines.
Color ~elevision signal dropout compensators are examples of television signal processing devices in which the above problems are encountered. Dropout compensators are widely utilized in systems for process-ing color television signals, such as for magnetic r~cording and reproduction, to replace a deficient or missing portion of the color television signal informa-~: tion, commonly called a ~dropou~, due to unpredictable .
. instan.an~ous malfunction of the system or to diminutive defects of the recording medium. When such dropou~s 15 sccur în the teIevision signal, they ~roduce visible di~turbances in the displayed picture. Dropout compensa-t~rs reduce the disturblng e~fect of dropouts seen by the viewer.
Most prior ar~ analog dropout compensators employ an R. ~. envelop~ level detector which monitors the amplitude level of the modulated television si~nal carrier waveform. A switch normally applies the incoming continuous television signal to an output ~erminal of the compensa . or. A delay line ls arranged in the ~elevision signal path, for example, between an input terminal of the compensa~or and an inpu~ terminal of ~he : switch or betwe~n the outp~t terminal of ~he compensator and the input terminal of the swi~ch. When a drop in the R. F. envelope level is detected, the switch is controlled :~ 5 ID--~63S

to apply the delayed signal to ~he output terminal, instead of the incoming television signal. The delayed signal thus replaces the deficient in~ormation~ When the Ro F. envelope level r~turns to normal, ~he switch S is controlled ~o switch its input from the delayed signal back to the incoming television signal, which is then applied to the output terminalO As an example, a prior art analog dropou~ comp~nsator of the above type is described in the U, Sr Patent No. 2,996,576.
There are known analog dropout compensators utilized in color teIevision systems which separate the con~inuous color televi~ion signal into ~he luminance and chrominance components, delay ~he component by one : or two television line period~ and in~ert the chrominance component on consecutive line~ to assure its p~oper pha~e when substituted for a dropout in the color television ~ignal. ~owever, in color ~elevision ~ystems in which the signal is in the form of digitized samples, utilization of digital comb filters for separating the 20 componen~s often requires use of the aforementioned additional comp1ex signal processing circuits to ob~ain samples corresponding to vertically aligned picture elemen~ locations throughout each field of the tele~ ion signal ~
~ . An example of another prior art digital dropou~ compensa~or is d~scribed in the manual ~AVR-2 Video Tape Recorder I Theory of Opera'cion" ~ Catalog ~3O-18009179-01; published by Ampex Corporation, November, D -~635 1977, pages 9-10, 9-14, 9-20 and 9-77 to 9-92. This particular dropou~ compensator replaces individual digital sample~ of data or an entire line of daka with the corresponding data from an earlier occurring line of the 5 same field. The dropout signal to be subs~ituted for the deficient information is stored alternately on a line by-line basis in one of two 256-bit shi~t regis~ers forming a two-line delay circuit. While the da~a for one horizontal line is being written into one of ~he 10 shift registers, the data from two lines earlier is being read out from the same shift register. In this la~ter application, the chrominance and luminance signals are not separated fo~ processing. However, the ; color television æiynal information replacing the 15 dropou~ signal is delayed by two .lines o~ the ~ame field. The interlaciny property oE typical ~elevision signals re~ults in the delayed signal appearing in the display of ~he ~elevision signal at a location four . horizontal line positions away from its real time position.
In some cases, the display of ~he dropout compensated signal is quite disturbing to the eye, especially if sharp ver~lcally-orien~ed patterns are repre~ented on the screen. Such vertically-oriented patterns will be ; horizontally displaced in the dropout compensation lines 25 relative to the adjacent undelayed lines.

It is an object of ~he presen~ inv~n~ion to : provide a system for processing composi~0 signals repr~sented by discrete samples and having recurrent in-tervals oE similar information content to separate the components for further processing and subsequent recombination ko reconstitute an altered composite signal.
It is still a further object of the invention to provide a dropout compensator for color television signals represented by discrete samples, in which compensator the dropout affected luminance information is replaced by luminance information preceding the dropout affected line by one television line ana the dropout affected chrominance information is replaced by chrominance information preceding the dropout affected line by one or two televislon lines.
It is a further object of the invention to provide a simplifled digital dropout compensator suitable for use in color television systems for various television -` signal standards, in which compensator the luminance component is delayed by one horizontal line period and the chrominance ~- component is phase-adjusted to have a known predeterminecl phase with respect to that horizontal line period or which the dropout compensation is provided.
In accordance with the present invention there- is provided a system for providing dropout compensation of a digitally encoded composite signal having recurrent intervals of similar information content and including a periodic signal component of a known frequency equal to a non-integral rational number multiple of the requency of the recurrent intervals, the periodic signal having a known predetermined phase during each consecutive recurrent interval and being ~ ;`
symmetrical with respec~ to a signal crossing axis, the encoded composite siynal comprising consecutive digital representations corresponding to discrete amplitude values thereof provided at a frequency equal to a rational numher multiple of the A~ c s m~ , perioclic signal Erequenc~ and in a fre~uency and phase-locked relationship ~hereto, the rational numb0r multiple ~requency being greater than twice the frequency o~ the highest frequency component of the composite signal, the system comprising in combination; a first means coupled to receive and store the consecutive digital representations and to successively provide an average value output signal by arithmetically combining a given number of consecutive ; digital representations defining a zero average value of the periodic signal componen-t; a second means haviny a Eirst input coupled to receive the consecutive digital representations of the composite signal and a second input coupled to receive the output signal of the irst means to provide a difference signal; a third means coupled to receive the difference signal and adjust it -to have a phase corres-ponding to the known predetermined phase of the periodic signal component during that recurrent interval for which the dropout compensation is provided; a Eourth means having a first input coupled to receive the phase-adjusted di.crence signal and a. second input coupled to receive the output signal of the first means to recombine -the received signals into a composite signal form; a fifth means coupled to provide ; a delay of the composite signal components for a period of time substantially equal to the recurren~ interval of the composite signal; and a sixth means having a first input ` coupled to receive the composite signal and a second input coupled to receive the delayed recombined composite signal, ; the sixth means responsive to a control signal ~o selectively . provide an out~ut composite signal from one of the signals : 30 coupled to its first and second inputs, respectively.
The foregoing and other objects, fea-tures and advantages of the present invention will be apparent :Erom the _ g _ I
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followi.ny detailed description thereo, herein taken wi~h reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
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Fig. 1 is a block diagram of a preferred embodiment of t e filter c rcu ~ of the invention.
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~,' , -~ 2635 Fig. 2 is a block diagram of a preferred embodiment of the filter circuit of the inYentiOn.
Figs. 3a and 3b are graphical representations of the generation of digitized samples processed by the S embodiment o~ the filter circuit of the inven~ion illustrated by Fig. 2.
Fig. 4 is an example of a frequency character-istic of the embodiment of the filter circuit of the invention illustrated by Fig. ~.
Fig. 5 is a graphical representation of the generation of digitized samples process~d by an alterna-. tive embodiment of the ~ilter circuit illustrated by Fig. 2.
Fig. 6 is a block diayram of an alternative embodiment of the filter circuit of the inven~ion~
Fig. 7 is a graphical representation o~ the generation o~ digitized sampl~s processed by the embodi-ment of the filter circuit of the invention illustrated by Fig. 6.
Figs~ 8 ~o 12 are block diagrams of various pr~erred embodiments of ~he dropou~ compen~ator of the inven~ion utilizing he filter circuit of the inven~ion~
~igsO 13a to 13h are consecu~ive parts of ~
detailed circuit diagram of the filter circuit embodiment i 25 illu~trated in the block diagram of Fig. 8.
~ ig5. 1~ ~nd 15 are block diagrams of embodi-ment~ of the dropout compensator vf the invention utilizing ~he filter circuit of the invention and ~;

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arranged for compensating PAL and PAL-M color ~elevisiorl.
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Figs. 16a and 16b are consecutive parts sf a detailed circuit diagram of an alternative memory address qenerator embodiment for use in the dropout compensator illustrated in Figs. 13~ to 13h to adapt the compensator for P~L color television signal appllca'cions.
DESCRIPTION OF THE PREFERRED ~ND ALTERNATIVE EMBODIMENTS
Pre~erred embodiments of ~he filter o~ ~he 10 present invention will be described, followed by the ; description of examples of the utilization of the filter in systems for processin~ digital composite signals.
The filter of the present invention i5 a type of digital comb filter cons~ructed to process a digi~al ::, 15 type composite information signal including two or more . ~requency components. By the ~ilt~r of the present : invention, one or more selected components of the composite information signal axe eliminated by filteringO ~l ~or simplicity o~ description~ the composi~e infonmatîon ~`
signal is referred to herein a~ the composite signal~ The digi~al type signal to be processed may be obtained~ for .' example, by sampling a composite analog siynal utitizing a sampling clock signal which is frequency and phase-locked ~ to the selected frequency component or components, to be ; 25 fIltered, a~ will be described hereinbelow~ Digital represen~ations of he samples are generated by a ~uantizer ~hat receives each sample representing a discre~e amplitude v~lue of the composi~e analog si~nal and converts or encodes i~c into a suitable digi~cal code"
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i~_2635 such as an NRZ code. These digi~al representations of the samples are combined in the fil~er of the present invention in such a manner that one or more selected periodic symmetrical signal componen~s, each having a known nominal frequency, are eliminated from the composite :~ signal. More speciically, the filter of the present invention receives and stores for a selected interval consecutive samples representing the composite signal from which one or more periodic signal components are to be removed by the filter. The filter continuously combines a selected number of the received samples to provide a digi~al average representation of the values of the combined samples which define a zero average value of the selected periodic signal component or 15 Component5-The filter comprises a combination of digital storage devices, such as delays, and arithmetic circuitry arranged and operated to provide at the filter's output for each digitized sample rec~ived at the fill:er ' s input a digital average representation of the values of : a selected number of rec~ived samples. The number o samples averaged is selected to define a ~ime interval which provides a zero average value of ~he portion of the averaged digital sample representations correspond-ing to the signal component to be eliminated from ~he composi~e signal by the filter. The operation of the combination of digi~al storage and arithme~ic means for processing the received digitized samples to ob~ain a I~-2635

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running digital average EepreSentatisn of the values thereof is controlled by a clock signal tha~ has a frequency which is synchronized and e~ual to the frequency ; at which the samples are received by the filter. As will become more apparent from the following description, an important feature of the present invention is the capability of the filter to filter out or eliminate selected signal components from digitized samples of a composite signal transmitted ~o ~he filter at an unpre dictable and randomly varying rate. In such application~
of the presen~ invention, the frequency o~ the filter ' 5 clock signal must vary synchronou~ly with the varying rate of receipt of the digitized samples by the ~ilter.
Of course, a stable frequency clock signal i~ provided 15 to the ~ilter in tho3e applica~ions where the digi~iz~d samples are received by the filter at a ~table rate.
Flg. 1 illus~rates an embodiment of the filter o the invention arranged to filter a selected 3.58 M~z chrominance signal component from a compo~i~e analog 20 NTSC color~ television signal, Typically, the composite color telesTision signal is an analog signal, often containing randomly varying ~:ime base error~
accordance w1th the presen~ invention, the analog signal ~: firs~ is converted to a binary coded digital signal and then is passed through ~he signal delays and arithmetic circuitry to remove the selected frequency component.
More spec,ifically, the analoy composite color television signal received at an input terminal 80 is c~upled to an . ID~2635 i21~7 input of a video signal processor 81. The signal processor 81 is a conventional arrangement of circuitry found in color television signal processing systemsl such as time base correc~ors, that amplifies the received ; 5 signal, provides D. C. restoration and separates the vertical fleld and horizontal line synchroniæing compo-nents (vertical and horizontal sync~ as well as the coIor burst synchronizing component, respectively, from ~` ~he composi e signal. The~ above-indicated respec~iv2 synchronizing components are then fur~her utilized in the following signal processing for synchronization parposes. The analog composite signal ob~ained at the output of the signal processor 81 is coupled to an input o~ an analog-~o-digi~al ~A/~) converter 82 which encodes 15 o~ converts the analog signal to a binary coded signal.
Irl one pref~rred embodiment, an A/D converter S2 i5 employed in which the composite analog NTSC television signal is sampled a~ a rate of three times the subcarrier signal frequency~ that is, 3 x 3.58 M~z or approxima~ely 20 10.7 M~z~ Each sample :i5 digitally quantized into an . .
NRZ digital word composed of 8 parallel bits. In accor-dance wi~h~ the present invention, a 10~7 M~z sampling clock signal that is substantially coherent wi~h the

3.58 M~z chrominance signal component to be filtered 25 from the composite television signal is ~mployed to clock ~he A/D converter 82 ts effec~ the sampling and quantizing of the composite analog t~levision signal~
The 10~7 M~z clock signal is genera~ed by a sampling ~L~L5~

; clock signal generator 83 from the color burst, horizon tal line and vertical field synchroniziny component5 .~ obtained from a te}evision synchronizing signal separator included in the signal processor 81. While small phase ~: 5 variations may be present in the horizontal line of video information followin~ the color burst interval due to velocity errors and the like, particularly, when such signals are obtained from video recorder television signal sources, such varia~ions are so small that they .. 10 can be disregarded and the 10.7 MHz clock signal can be , . .
considered coherent with the 3053 M~z chrominance signal componen~ for purpos~s o~ the invention described herein.
Some tele~ision signal~ contain a continuou-sly available pilot signal. In those cases, the pilot signal may be used to generate a 10.7 M~z clock signal that is truly coherent with the 3.58 MHz chrominance signal componen~.
The A/D conver~er 82 responds to ~he 10.7 M~æ
clock signal provlded at its clock input terminal by the clock signal generator 83 and a clamp control signal ~0 provided at its clamp con~rol input terminal by the signal processor 81 to provide at the output of A/D
converter 82 the NRZ digital words representative of the input analog television signal. The 8 bit NRZ digital words pro~ided by the A/D converter 82 are applied over :
eight parallel lines 84 to the ~ilter ~ircuit 2.
The circui~ details o~ the signal processor 81, A/D converter 82 and clock signal generator 83 are not shown or described herein as they are identical in X~-263S
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their design and operation as those incorporated in the Ampex Corporation TBC-l digital time base csrrector.
More specifically, the schematic diagrams o~ those circuits are shown in the catalog number 1809274-02 5 published by Ampex Corporation in November, 1977. The specific circuitry for the signal processor 81 is shown in schematic drawing No~ 1406103A appearing on page 29/~0; the A/D converter 82 is shown in schematic drawing Nos. 1402409B and 1401312, respectively, 10 appearing on pages 37/38 and 43/44, respectively; and the clock signal generator 83 is shown in schematic drawing No. 1402337 appearing on pages 49/50 and 51/52.
If the digitized televi~ion signal is soupled directly from the A/D converter 82 to the input of the fil~er 2 wi~hout fur~her alteration of the data rate, as in the embodiment illustrated by Figs. 1, 2 or 5 r the 10.7 M~z clock ~ignal generated by the clock signal generator 83 is also coupled to the filter 2 to clock the fil~er's circuit elements or me~ns utilized in the 20 processing of the composite digitized television signal to remove ~he selected periodic signal component.
However, if a reclocking or buffer circuit means ( not ~, shown) is placed in the siynal path between the A/D
converter 82 and ~he filter 2 to alter - ~he data ra~e of 25 the diyitized television signal before coupling it to the filter, for example, as would be necessary to synchronize an uns able digitilzed signal ~o a ~Erequency stable reference, a correspondirlg frequency stable -16~ !

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reference clock signal would be employed to clock the filter's circuit elements. Of course, ~he frequency stable reference clock signal would be generated to have the same frequency and ~ynchronous relationship relative S to the reclocked selected periodic signal component as described hereinabove.
The 8-bit digital word output signal from the ; analog-to-digital converter 82 is applied ~o an input of the filter circuit 2 of;the invention via connecting line 85. :Generally, the~ filter circuit 2 of the invention comprises~a cocperative:combina~ion of circuit elements, which in the preferred embodiment of Fig. 1 are shown as . ~
;~ delay means 84, signal combiner means 86 and signal : divider means 87. As it will be described in more detail hereinbelow, the fllter circui~ 2 receivas consecu~ive digital samples ~rom the above-indicated A/D
converter and delays and combines them to provide a - digital average representation of the value~ of the ~: combined samples by processing a selec~ed number of -; 20 samples representing ~th~e analog color television signal received at the input terminal 80. The number o~
-~ digital samples combined to provide the digital average ; representation is selected ~ith respect to the relation-ship between the clock signal fre~uency and requency of the selected~signal component to be eliminated by the filter in such~a manner that the di~ital average repre~
sentation at the output o~ the filter represents an average signal value of the composite signal and~ at the ~2635 same time, a zero average value of the selected frequency component.
Now, the operation of the filter circuit 2 of Fig. 1 will be described in general, ~ollowed by the description of the specific preferred embodiments shown in FigsO 2 and 5~ respectively.
The delay means 85 receiYes the consecutive digitized samples from the A/D converter 82, and it delays or stores each sample for a predetermined number of 10 sample intervals so that a selected number of received samples are simultaneously accessable for arithmetic combinatlon. In the preferred embodiments of the filter circuit ~, ~he delay means inaludes a plurality of parallel slgnal transmission pa~hs having signal delay elements that provide di~erent transmlssion times between the input and output 4f the delay means ~or each received sample so tha~
the selected number of different received samples are simultaneously provided to the ~ignal combiner 20 means 860 The selected number of delayed samples transmitted through the delay means 85 are applied via respective connecting lines 89 to associated inputs of the signal combiner means 86~ The signal oombiner means ari~hmetically combines selected 25 samples and p~ovides at it~ output a digital : representation of the value of the combined samples.
The digital representation is applied to an input of the signal divider me~ns 87 via oonn~cting ~ 635 ~ 52~7 .~
, line 90. The signal divider means 87 divides the combsned sample value to provide at its output 91 a digital average representation of the values of the - combined samples. The number of samples combined, 5 ~he arithmetic comblnational fac~or and the divisor are selected so ~hat the s~gnal provided a~ ~he ~ output 91 of the filter ci~cuit 2 is a digital : average representation of the values of the combined samples that defines a zero average value of ~he 10 selected frequency component. In thls manner, the selected frequency componen~ is eliminated from the ~ compssi~e slgnal by the filte~ circuit 2. Now~
:. pre~erred embodiments of the filter circuit 2 shown I in Figs. 2 and 5 will be described.
The ilter circuit o Fig. 2 provides a ! diyital average representation of the values~4f thr~e ~, consecutive dlgital sample representatlons, ~1~ S2~
S3, received in succe sion ~rom~ for e~amplel an A/D
convertert such as shown in Pig. lo The f11~er circuit ~i ~ 20 of Fig. 2 utillzes a cascade combination of digi~al devices, including registeFs~ binary adders and a divider, arranged to form ~hree parallel transmission paths of different transm~ssion times for each of the received samples. Each consecu~ive sample ~enerated by : 25 the A/D conve ter:82 shown in Fig. 1 is coupled by the ~' eight parallel conn~cting lines 84 to an input o~ a clocked register 49, which serve~ as a timing buffer between the A/D converter 82 and the filter circuit 2 -19~

~ 635 l~s"S217 The propagation of the 8-bi~ digital word sa~ples through ~he register 49, as well as ~hrough other clocked devices o~ the filter circuit 2, is con~crolled by the 10.7 M~z clock signal generated by the clock signal generator 83 ( Fig . 1 ) and provided over connect~ng l~ne 88. The output of ~he register 49 ~5 coupled by lines I to an inpu~ of a clocked register 50 and a first input of an adder 51. Register 50 is clocked by the 10O7 M~z clock signal to receive the consecutive samples 1~ Sl, S2, S3, etc., coupled to its input by the clocked register 49 and delays each received sample by : one clock cycle relative to the time the sample appears on lines I coupling the output of the register 49 to the input of r~gister 50. The ou~put o~ regis~er 50 i8 15 coupled by connecting lines II to a second irlput o~ ~he ~dder 51. Adder 51 ~ an ari~hmetic dev~ce of the type that provides at its output coupled to connecting lines III the sum o~ i~s inputs received over lines I and II.
Therefore, adder 51 add~ each one clock cycle delayed : 20 sample received from the register 50 ~o the nex~ consecu-tive sample received from register 49 to provide a running sum of two cons~cutive samples output by the A/D
converter 82. ~nother clocked reglster 52 has i~ inpu coupled to the output of the adder 51 by th~ connec~ing 25 lines III and is clocked by the 10~7 M~z clock signal present on line 88 ~o receive ~he sum af ~wo consecutive samples provided by the adder 51~ Like regis~ers 49 and 50, the regi~ter 52 provides a delay of one clsck cycle 1., -2 63~
~S~ 7 for each sample sum received rom ~:he adder 51. The output of the register 52 is coupled by connecting lines IV to a second input of an adder 53, which adder has its first input coupled by lines I to receive ~he consecutive samples fro~ register 49~ ~dder 53 provides on connect-ing lines V coupled to its ou~put the sum of its inputs received over connecting lines I and IVo Therefore, a running sum of three consecutive samples provided by the A/D converter 82 through register 49 is presen~c at the ~ . 10 lines V coupled to the output of the adder 53O A
`~ clocked divider 57 has its input coupled to the output V
of adder 43 via a preceding register 54 and it provides a division by three of the received sum of thre~ consecu-tive samples~ The register 54 immediately precedlng the :,15 divider 57 (or register 56 in the f~lter circuit embodi-ment ar~anged to average four consecu~ive samples) is utilized ~o reclock the bits forming each averaged û bi~
digital word and, thereby, remove any bit skewing or transients that may be present in the averaged 8-bit 20 digital word. Bit skewing is caused by small differences in the propagat:ion delays experienced by the individual :bits of each 8-bit digital word as ~hey are processed in parallel ~hrough tbe filte~r circuit. Transients are generated by active circuit elements ~hat Lmmedia~ely transmit to their outputs withou~ clocking the results of signal stat~ chanyes at their input~. The adders employed in the preferred embodlmen~ of the filter circui~ 2 are examples of such circuit elements in that ~-21-I~-2635 ~iiS21~

they are the kind in which changes in the logic level of the signals at their inputs are immediately transmitked to their output~ The registers 49, 50 and 52 also perform a reclocking function. Should the bit skewing and transients be tolerable or absentt ~he reclocking reglster immediately preceding the divider 57 can be eliminated from the filter circuit 2.
Each of the registers and the divider of the filter circuit delays the data received at its input by one clock cycle. This delay results from the clocking : of the registers and divid~rs because the digital sample representations present at their inputs do not appear at their outputs until after the d~vic~s have been clocked by the 10 ,. 7 MHz clock signal . AS a resul~ o such 15 clocking, each sampl~ proceeds along the serie~ circui~
path~ deined by ~he reglster and d~vider devices only ; in steps o~ one device per clock cycle.
In the fil~er circuit 2, the connecting lines I at its inpu~ branch into thr~e different signal 20 tran~mission paths to the outpu~ 91 of ~he filter circuit., The signal transmission times through th~
three paths differ by integral multiples of ~he period of the 10 9 7 MElz clock signal, with the transmission time ~hrough the long~st sign~l transmission path b~ing two clock signal p~riods longer than the transmission ~ime : through the shortest signal transmission path and the transmiss~on time through the signal transmission path of intermediate length being one clock signal period ~Z2--, ~263~
1~i5Z1~7 longer than the transmission time through the shortest signal transmission path. The shor~est signal t~ans-mission path between the connecting lines I and the output 91 of the filter circuit 2 includes the binary S adder 53 followed by the register 54 and the divider 57. The register 54 and the divider 57, respectively, introduce a propagation delay of one clock signal cycle each in the signal transmission pathO Consequently, the shortest signal transmission pa~h has an overall signal transmission delay of two clock signal cycles. Adder 53, register 54 and divider 57 are common to the three signal transmission paths. Therefore, the aforementioned differences in the tran~mission times ~hrough ~he ~hree paths must be es~ablished before~the adder 53.
The portion o~ the sîgnal transmission path of interMediate length between connecting l~nes I and the adder 53 includes anothe~ binary adder 51 followed by the register 52. As described hereinabove, the regist~r 52 introduces a propagation delay of one clock signal cycle in the signaL transmission path~ Consequently, the signal ~ran~mission path of in~ermediate length provides a signal transmission delay between lines I and the connecting lines IV coupled to the second input of the adder 53 of one clock signal cycle, which is one ~5 cycle longer than the delay through the portion of the shor~est signal transmission path between the lines I
and the input to the adder 53. Thus, at the same kime tha~ register 52 provides data a~ the second input of ;Z17 the adder 53, a sample that was generated one sample in~erval or clock period earlier by the A/D converter 82 of Fig. 1 is provided at the firs~ input of ~he adder 53 over connecting lines Ic The longes~ signal transmission path i~ formed in part by the signal transmission pa~h of intermediate length, i.e.~ the path from adder 51 ~o divider 57 and in part by register 50. Since the register 50 introduces a propagation delay of one clock signal cycle in the transmiss~on path, the signal transmission delay between the lines I and the connecting lines II coupled to the second input of the adder 51 is one clock signal cycle, which is one cycle longer than the signal transmission delay through the transmlssion path of intermediate length. Thus, a~ the same time that a sample is coupled by lines I ~o the first input of the adder 51, a sample generated one sample int~rval or clock signaI periods earlier by the A/D converter 82 of Fig. 1 is provided a~
the second input of the adder by the regis~er 50~
Therefore, the longest ~ignal transmission pa~h provides a signal transmission delay between lines I and ~he outpu~ of the filter circuit 2 that is two clock signal cycles longer than thak provided by the shortes~ signal transmission path The filter circuit illustrated by ~ig. 2 provides an average of three consecutive samplesO If it is desired to provide, for example, an average of four consecutive samples, an additional adder 55 and clocked regis~er 56 -2~

; 2635 S21~7 are added to the filter circuit 2~ coupled in cascade between register 54 and divider 57, as shown by dashed lines. ID this modified filter circuit, the divider 57 . is a divide~by-four dividerO For each additional sample averaged, an additional adder and reglster are coupled in : the fil~er circuit of Fig. 2, preceding the divider 57 in the above-descri~ed mann r, and the di~ider is implemented accordingly. All the above digital devices are commercially available conventional devices, as will :10 be appreciated upon consideration of the detailed circuit diagram of Figs. 13a to 13ho The operation of the filter circuit o~ Fig. 2 will be described now with respect to particular circuit locations indicated I, II, III, etc., and as indicated in TAB. l below.
TAB. 1 Location Clock Time I II III IV V VI VII
_~ __~ ...___ _ _ . _ . I

2 S2 Sl Sl+S2 3 s3 S~ S2+S3 Sl+S2 Sl+S~S3 :~ 4 S4 S3 S3+S4 52+S3 S2+S3+S~ Sl+S2+S3 .
~ , 5 S5 S4 54+sS ~3+54 s3+s4+s5 2 3 4 3~Sl+52~S3) .~ .
.:

-~5-1~ 2 635 As shown in TAB . 1, each consecutive sample clocked to the outpu~ of the register 49 is received simultaneously over lines I at respPctive inputs of register SO, firs~ adder 51 and second adder 53, a~ well 5 as any further adder, such as 55, present ~n the circuit~.
At a first clock time 1~ register 49 is clocked to place sample Sl at its output, which is coupled by lines I
: to the input of the register 50 and first input of each of the adders 51, 53. Because of the clock~ng of :~ 10 register 49, sample Sl does not appear at its output ~ on lines I, hence, at the inPuts o~ the adders 51, 53 :: and r~gister 50, until a~ter ~he clocking of the registers ~
and dividers. Consequen~ly, sample Sl is not clocked at this ~ime through ~egister 50 to the connecting l~nes 15 II extending l:o ~he second input of the adder 51c Each : adder 51, $3, however/ i~mediately responds to th~
receipt o~ a new digital sample representation a~ its I input~ ~uch as the appearance of sampl0 Sl on lines I~
~ ~o couple to its outpu~ the sum of the new digital ; 20 sample repres2ntations at its inputs. Wh~le the ~ample Sl i5 present in the summed outpu~s of adders 51 and 53, such presence occurs after the clocking of t.he following registers 52 and 54; and, th~refore, khe sample S:L is not clocked through the registers 52 and 54 25 during clock time lo At tha next clock time ~, sample S~ is presen~ ~ the input of register 49. Each of the regi~kers 49~ 50, 52, 54 and divider 57 is clocked to ~ 635 ~S~

effect the ~ransmission to their respective outputs ofthe data then present at their respective inputst which occurs an interv~l after the onset of the clock7.ng. As a result of the clocking, sample S2 appears at the 5 ou~pu~ of register 49, hence~ on lines I extending to the inpu~s of th~ adders 51, 53 and register 50, register 50 transmits the previous sample Sl from its input to its output, hence, connecting lines II extending to the second input of the adder 51; the summed samples appear-: 10 ing on connecting lines III coupled to the input of register 52 are transmitted to the output of the register and placed on connecting lines IV extending to a se~ond input of the adder 53; the summed sample~ appearing or connecting lines V coupled to the input o~ regis~er 54 lS are tra~smitted to th~ output of the register and placedon connecting lines VI extending to the input of the d~vider 57; and the summed samples appearing on conllect-ing lines VI coupled to ~he inpu~ of the divider 57 are divided by three and the divided output is ~ransmitted 20 to the divider ' s output and placed on connec~ing line~
VII~ Following the af?redescribed clocking of the registers and divider, botb adders 51 and 53 provide the new sample sum on lines III and V respec~ively coupled to the outputs of adders~
"5 At the next clock 'cime 3, sample S3 is present at th~ inpu of the register 49 and the regis~ers and divider are clocked to transmit the sample sum then present at their respective inputs~. Ps a result, adder 51 I~-2635 ~5~ 7 receives sample S~ from the clocked regis~er 50 and sample S3 over lines I from the clocked register 49 and responsively provt dPS the sample sum S2 + S3 on lines III connected to its output. Adder 53 receives the sample sum Sl + Sz over lines I~ from the clocked register 52 and the sample S3 over lines I
from the clocked register 49 and responsively provides : the sample sum Sl + S2 + S3 on lines V connected to its output. Clocked register 54 ~ransmits the sample ~: 10 sum previously provided at ~he outpu~ of ~he adder 53 to lines VI connected to its outpu~ and the clocked divider transmits the divided sample ~um to llnes VII connec~ed to its outpu~.
At the nex~ clock time 4, sample S~ is 15 present at the inpu~ of ~he register 49 and the registers and divider are agaln clocked to transm~ the sample sum then present at their respective inputs. As a result of ~h~s clockiny, adder 51 receives sample S3 over lines II from the clocked register 50 and sample S4 over 20 lines I from the clocked register 49 and responsively provides ~he sample sum S3+ S4 on ].ines III connec~ed to its ou~put. Adder 53 receives the sample sum S2 ~ S3 over lines IY from the clocked register 52 and the sample S4 over lines I from the clocked register 49 25 and responsively provides ~he sample sum S2 ~ S3 ~ S4 on lines V connected to its output. Clocked regis~er 49 transmits the sample sum Sl + S2 + S3 on lines VI
connec~ed to its output and ~he clocked divider ~ransmits .~ .

. , .

I~ ~635 iS~

the divided sample sum previously provided by theregister 54 to l;nes VII connected to its output.
At the next clock time 5, sample S5 is present at the input of ~he regis~er 49 and the registers and divider are again clocked to transmit the sample sum then present at their respective inputs. In the manner described hereinbefore with respect to previously received samples, adder 51 places the sample sum S4 + S5 on the lines III coupled to its output, add~r 53 : lO places the sample sum S3 + S4 + S5 on lines ~
coupled to i~s outpu~, regi~ter 54 transmits the sample sum S2 + S3 + 54 to the lines VI coupled to its output and d~vider 57 transmits ~he divided ~ample sum 3l(Sl t S2 + S3) to the lines VII coupl~d to lts output, the digital representation of the aver~ge values of three consecutive sampl2s. For each subsequenk 8-bit digltal word sample received over line 84 from the A/D converter 82, the adders, registers and divider : i, cooperate to provide on lines VII, connected to the ou~put of the divlder 57, the digl~al averag~ representa-tion of the values of each next three consecutive samples, whereby a running d~g~al average r~presenta-tton of ~he values of three consecu~ive samp1es of the signal received at the input of filter circuit 2 Ls provided a~ ~he outpu~ 91 o the filter c~rcuit.
To illustra~ the manner in which the foregolng opetation of the filter circuit shown in Fig. 2 eliminates a selected periodic Erequency component of the composi~e ID--2635s~
~ O

analog signal, reference is direc~ed to Fig. 3a. The periodic ~requency component to be eliminated, represented as sine wave of amplitude v at frequency f, is sampled at a fre~uency 3f by a clock signal that is in phase with the periodic signal component~ According to the well-known Nyquist sampling theorem, the sampling frequency should be higher than twice the highest frequency of the sampled composite signal bandwidth~ The sampling points on wave v are designated Vl; V2, V3, V4, etc~ 9 and are 120 degrees apart. Each sampling poin~ Vn represents a particular amplitude value of the sine wave.
In this example, a running average vol~age value Ln is obtained for each consecu~ive sample received by the filter by averaging the combin~d amplitudes o~ three consecutive samples. For filter embodiments that are constructed and operate to provide an average valu~
output for each received sample by averaging ea~h sample with a given number of its immediately preceding and sucoeeding samples, the averag~ value, L, of each sample, 20 Vt is given by ~he equation: :
Ln ~ n (Vl+V2'--+Vn) (1) where n is a known integral number of ~he samples averaged. Specifically~ when averaging ~hree consecutive samples:
L3 = 3(Vl+V2+V3) (2) . -3~

ID-263$
3~31L~5Zl~

Because o~ ~he symmetrical properties of sin~
wave signals with respect to a signal crossing D. CO
axis, any average value Ln obtained by averaging n consecutive samples which define an integral number of signal cycles as described above with respect to equation (1) will be zero. This is true for any integral number of averaged samples, greater than two per sine wa~e period ~nd regardless of the phase points at which ~he sine wave is sampled, i.e., phase relat.ionship between the sine wave and sampling clock signal.
Furthermore, because the sampling signal or clock signal employed to control the arithmetic operations performed by the filter is, a~: the inpu~ to the filter, frequency and phase-~ocked to the periodic ~ignal componen~ to be separated or ellm~nated by the filter o~
the p~esent inventiont ~he filter may be u~llized r ~r example, to separate or eliminate s~gnal components ~rom a compos~te signal having time base errors ~ such as resulting from a magnetic recording and reproduciny process.
An example of sampling a sine wave w of frequency f util~zins a samplin~ clock siynal having an arbitrary phase relat~onship thereto, is shown in FigO
3b. Equispaced sampIing points 1, 2, 3 and 4 of frequency 25 ~f are ~hown dlsplaced by 3- = 12~ degrees wi~h respect to the sine wave period T = 360 degrees~ There is an arbItrary phase d~fference between the wave, w, ~31-l~S5~21 7 ID-2635 and ~he sampling clock signal, represented by sampled points 1, 2, 3, 4, etc. The sine wave w may be generally defined as:
w(t) z A sin (B - C) (3) 5 where C is the arbitrary phase difference between the sine wave w and the sampling signal, and A is the ampl i tude .
Equation ~ 3 ) may be fur ther def ined as:
A sin ( B - C ) - Alcos B ~ A2 sin B ( 4 ) Al = - sin C ~ 5 ) A~ = cos C (6 ) When ~ubstituting particular amplitude and phase angle values for Al, A2, and cos C and sin Cy respectively, into the above equa~ions ( 3 ) to ~ 6 ) ~ the 15 sum of any three consecutive samples equals zero, and, thus, any average sample val,ue Ln as indicated ~n (l) also will be zero. The zero average value~ are plot~ed :, as Ll ~ L2 ~ L3, etc ., in Fig . 3a and as l ', ~ ' I 3 1, etc., in ~ig. 3b.. I~ is seen from both Figs~ 3a and 3b 1, 20 that a full cycle o~ the selected signal component of the kind defined by equations ( 2 ) and ( 3 ) has equal and identical portions extending above and bPlow a signal crossing D. C., axis. Consequently, ~he average D~, C. value of tha~ signal component is zero. An integral number, n, 25 of samples which define a time interval eqllal to an integral number, N, of orle or more cycles of the sel~cted periodic signal component to be eliminated by the filter circuit 2 comprlse an equal number of "positive" and . --32--' negative" value samples whose average value, Ln ~
equals zero, that is, the summation of the values of samples from above the Do C. axis is cancelled by the summation of the values of the samples from below the D. Cz S axis. In other words, an integral number of samples defining one or more integral cycles of the selec~ed signal component have complementary amplitude levels above and below a signal crossing axis r whicb yield a zero averag~ value. This is true regardlecs of the phase 10 poin~s a~ which the signal component waveform is sampled as it follows from the foregoing description.
The filter of the present invention is a type of comb filter which eliminates signals having frequen~ies coinciding with the no~ch frequencies de~ined b~ ~he 15 filter's response characteristic~ such a3 illustrated ln Fig. 4. The fil~er can be constructed and operated to remove any one or more ha~monically ~elated signal component~ included in the digitized composite signal coupled to its input, with the number of harmonically 20 related signal components removed depend~ng upon the frequency of digitized samples at the input of the filter and the number of samples averaged by the filter ~o genera~e the running average value ou~put. The lowest order signal component remsved by the filter o 25 ~he present invencion is defined as having a frequency fmin n (7 , ID~2635 where fsampl is the sampling clock frequency defined in equation (l); and n is the number of samples ~aken for averaging as defined in e~uation (1)~ The diagram shown in Fig. 4 depict ~he frequency compon~nts eliminated by ~ 5 the filter of the present invention. As it is seen, the ;~ filter of the invention has a first notch at a frequency fmin defined by equation ~? j and it has further notches at higher in egral multiple frequencies of . fmin. Consequen~ly, the highest order signal component ;~ 10 removed by ~he filter is one having frequency equal to i an integral multiple of the lowest removed component ' fmin and which is contained within ~he frequency band .l of the filtered composite signal. However, in applica- .
~, tions where i~ is desirable ~ remove only a speciic 15 selected frequency component ~rom a wideband composite s~gnal, khe sampling ~re~Uen~Y fsampl (~ filter s clock signal fre~uency) is selected such that the frequency of any other component included in the composite signal does not coincide w~h the notch frequencies of the fil~er.
In the embodlment of ~he fîlter circult 2 .
illustrated in Fig~ 2, the sampling clock frequency and filter ' s clock frequency have been chosen as an in~egral multiple of the selec~ed frequerlcy component to be 25 removed. However, the filter circuit 2 can be modified to process digital sample represen~a~ions prov~ded at a sampling frequency which is a rational fractional multiple of the selected frequency component to be eliminated ~5;~7 ID-2635 from the composite signal; a sampling frequency equal to 2.5 ~imes ~he selected signal component frequency being selected as an illustration of this embodimentO With such a sampling frequency, two and one-half samples are obtained for each cycle of the selec~ed periodic signal component and five samples are obtained over two full signal component cycles, as shown in Fig. 5. To obtain an average sample value defining a zero value for the selected periodic signal component, a running average sample represen ation is generated of the values of n=5 consecutive samples.
~, .
To proYide a running digital average represen-tation of khe valu~s of five consecutive samples generat-ed at a rate of 2.5 times the s~lected frequency compo-nent ~o be elimina~ed from ~he composite signal, the . filter cLrcuit 2 of Fig~ 2 is modlfied to include two addltional parallel slgnal tran~mi~s~on pa hs between j the connec~ing lines I and the input of the divider 57.
The first of the additional paths includ~s ~he connecting lines I, the adder 55 and the clocked regis~er 56 . ~
illustratd by dot ed lines in Fig. 2. The second of the additional path~s~is formed by an addi~ional parallel path extension of the connecting lines I and another cascaded combination of an adder and clocked register (none of~wh~ch are shown in Fig. 2)e The addi~ional ,: add~r has one input coupled to receive ~he ~ummed samples from the register 56 and a second input coupled to receive con~ecutive samples from the parallel ex~en-.

sion of the connecting lines I. The additional register ls coupled between the output of the additional ad~er and ; the input of the divider 57 and performs the above described reclocking func~ion. With the two additional parallel signal transmission pa~hs, the modified filter ; circuit 2 has five parallel signal transmission paths between the connecting line I and the input of the divider 57, respectively providing signal transmission times differing by 1 through 5 clock si~nal periods whereby five consecutive samples can be arithmetically combined for averaging.
:
Besides adding the two additional parallel : signal transmiss~ion paths to the ilter circuitl the divider 57 is modifled:to divide the combin~d samples by a ~actor of ~ve~ Also, all clocked reg~sters and d~vide~s are adapted to be clocked by a clock signal ooupled by llne 88 to the~r respective clock inputs having a frequency of 2.5 times the selected frequency component to be eliminated from the componen~ signal.
~Summing five consecutive samples and dividing ~: the obtained value by S provides an average representa-`~ tion of the values of the fiYe consecu~ive samples which defines a zero value of ~he selected periodic signal : component. ~owever, in this modified embodiment of the 25 filter circ~uit 2, a fr~quency component equal to one~-hal~
of the frequency component of the composi~e signal also ~ will be eliminated. For example~ for a selected siynal : component of frequenc~ fsig ~ 3~58 MH~, such as the ~ -36-, 55 21 ~ ID-2635 standard chrominance subcarrier signal component included in the NTSC color ~elevision signal, and for the sampling frequency fsampl equal to ~wo and one~
half times ~he subcarrier signal frequency, i.e~, fsampl ~ 2.5 x 3.$8 - 809S MH2u The lowest frequency component removed by the modified fil~er circuit, as 8.95 ~Iz given by equation (7) is fmin = 5 - 1.79 MHz.
If it is undesirable to remove the 1.79 ~Hz component in addition to the 3.58 M~z chrominance component from the .

color television signal, a different sampling frequency should be seIected, such as the previously described f 1 = 3 fsig. Removal of the 1.79 M~z component of a color television signal may undesirably degrade the `, signal. In ~he previously described unmodified embodimen~
of ~he ~llter circuit 2 illustrated by Fig. 2~ ~m~n equals 3.58 MH2, whlch is the lowest .requency compon~nt removed by the ~ilter. As it has been ~xpla.ined above, and illustrated in FigO 4, integral multiples of the : lowest frequency component removed by the ~ilter cor~es-ponding to higher order ùarmonlcs also will be removed by the filter.
The filter of th~ invention can be construc~ed and operated to average either an even number or an odd number o inpu~ samples ~o generate at its outpu ~he 25 digital average representation for each rece~ved inpu~
~: sample~ ~owever, averagin~ an odd number of i~put samplés ~acilitates ~he avoidance of the introduction of 1~ ~S217 ID-2635 undesirable phase shifts to the digital average repr~sen-tation provided by the filterO Averaging an odd number of the input samples permi~s substituting in place o~
each input sample value a representation in the form of a digital representa~ion of the average of the value of the input sample plus the values of equal numbers of input samples occurring before-and after the input sample. Averaging an even number of inpu samples to generate the digital average representation does not permit generating the representation from equal numbers of input samples occurring before and after the input sample to be substi~uted by the representation. As a result, some phase displacement occurs when averaging an even number of input samples. The phase displacement can lS b~ limited to one-half of the interval between consecutive samplesl or sampl~ng period~ 1 the dig.ital average representation generated ~rom a sequence of an even number of lnput samples is substituted for an input sample occurring nearest the middle of the sequence~ Since i, 20 such phase displacement is constant for all substi~uted sample values, no ob~ectionable phase distortion results.
E~ow~ver, in some signal processing appli ations, such as color television signal dropout compensators, such fractional phase displacements are undesirable be~ause 25 they complicate the processing o the sign~1 for use in alleviatlng dropouts tha~ often occur in television signals reproduced from a magne~ic recordingO

-3~-~ SZ~ 7 ID-2635 When u~ilizing ~he filter of the above-described invention as a low-pass filter, it is preferable to have :; a relatively low integral number of samples per cycle of the selected periodic signal to avoid high sampling 5 signal frequencies while main~aining the shortest possible signal period for averaging. A sampling rate of three times ~he frequency of the selected periodic signal ~o be el~minated by the filter satisfies these preferred conditions.. Such sampling rate has the 10 further advantage of facilitating the avoidance of the : introduction of ~he aforementioned undesirable phase shifts because an odd number o~ inpu~ samples can be conveniently averaged ~o generate the digital average representation for each input sample.
lS A filter constructed in accordance with the embodiment illustrated ~n Flg~ 2 and opera~ed to p~ovide a running average sample value repres~ntation of a composite signal sampled at a frequency equal to an even number mul~iple of the signal component to be elimlnated 20 by ~he filter will introduce the aforedescribed phase displacement. ~owever, ~he embodimen~ of the present inYen~iOn shswn in Fig. 6 avoids introducing a phase displacement in ~he running average sample value represen-: tation of a composite signal sampled a~ such even number ; 25 multiple frequencyO :Generally, the filter embodimen of Fig. 6 avoids the introduc~ion of a phase displacement by genera~ing an average sample Yalue representation of each sample from selected ones of a sequence o~ input ~ 5217 ID-2635 samples which are weighted for avera~ing. That f~lter embodiment and the manner in which it operates to generatP
the desired average sample value representation are described i~ detail hereinbelow9 To obtain a zero average value of a selected periodic signal, a weight~d average value signal may be pro~ided, for example r by assigning selected respective weishting coefficients to respective inputs of the various circuit elements utilized in the fil~er of the present inven~ion. The foregoing may be lmplemented by coupling digital multipliers 70 to 75, indicated by dashed lines in Fig. 2O to ~he respective inputs of adders 51, 53, 55. For example~ dig~tal multipliers TDC
10085 manu~actured by T~R.W~ Corpora~ion may be utiliz~d~
Alternatively, i~ the samples being summed are weighted by coe~icients of powers o~ 2, ice~, 1/4, 1/2, 1, 2, 4, etc., to obtain the averaged sample value representation, the weighting of the samples can be accomplished conven-iently by~ bit shifting ~he 8-bit digital word sample at 20 th~ inputs of the adders the appropriate number of bit posi~ions and in the appropriate direction corresponding to the weighting coefficien~. Such bit shi~ting is effected in the well known manner of coupling the input bi~ lines to lower or higher order binary bil: posi~ion 25 inputs o the adders. For exampl~, to multiply the sample by 4, each inpu~ bit line is coupled to a bi~
position input of the adder whlch is two bl~ position orders higher than the bit position order of the input - \

- ~ ~ r~ ID-2 63 5 ~;2 7 bit line. To multiply the sample by 1/4 (or dlvide by

4), each input bi~ line is coupled ~o a bit position input of the adder which is two bit position orders lower than tne bit position order of the input bit line.
The forego-ng will be explained with reference to Figs. 6 and 7 ~espectively depicting the block diagram of an alternative embodiment of the digl tal filter of the presen~ invention and the opera~ion thereof.
Fig~ 7 shows a sine wave of amplitude Z at frequency f 10 sampled at a frequency 4f. q~he sampling points on wav~form Z are designated Zl~ ~2~ Z3, etc.~ and are 90 degrees apart. ~n average sample value of ~he sine wave Z ~g obtain~d by generatlng a weighted average sample value o~ ive consecutive samples in acco~dance 15 with ~he ~ollowing equation:
Mn ~ Zrl ~ ( Zn-2 ~ Znt2~ ~ (gn-l ~ Zn~l~ (8) For ~xample, an average sample value M4 sub~tituted for sample Z4 is:
M a 12 Z4 ~ 14 ( Z2 t Z6 ) t- O t Z
To generate the weighted average ~alue of the five consecutive samples in accordance with equation (8), digital weighting means a~e arranged in circuit wi~ch digi~cal time delay and dig~al arithmetic devices to weight the five consecu~ive samples by weighting 25 coefficients as follow~: Zn is weighted by "1/2n;
both Zn 2 and Zn-~ 2 are weighted by ~1/4"; and both Zn 1 and Zn~ l are weighted by HOn. As illustrated by Fig. 7 and the above equations 8 and 9, appropria~ely -~ 1 ~S21~

selec~ed weighting of consecutive samples enables a selected periodic signal component Z to be eliminated from a composite signal sampled at a frequency equal to an even number multiple of the frequency of th~ selected periodic signal without introducing a phase displacement to he resulting co~posite signal. Introduction of a phase displacement is avoided because each generated average sample value is substituted for a sample that occurs in the middle of the sequence of consecutive samples tha~ are averaged.
: A block diagram in Fig. 6 shows an embodiment of the filter circuit 2' of the present invention as arranged to generate and substitute an average sample value for each inpu~ s~mple in accordance with equation ~8)~ To facilita~e the descrip~lon, the operation o the circuit o~ Fig. 6 is indicated in TAB. 2 ~elow, depic~ing the propagation o~ con~ecutively received sample~
Z~' Z2' Z3~ etc., at clock signal ~lmes 1, 2, 3, Ptc., with respect to particuIar locations A, B, C, e~c.
in the block diagram of Fig. 6.

11~52i~ ID-2635 TAB. 2 .. _ _ _ . , _ . ... _ _ _ ., .. . . _ .. ~ . . _ _ ... . . . . . .. . _ . . . . . ... . _ . .. .
Location Clock A B C D E F G H
~ r~
3 Z3 Z2 Zl Z +~ Z _~

4 z4 z3 22 Z4+ 2 Z3+2l

5 ~5 Z4 Z3 Z5+23 Z+~ Z+~ 25+Z3+~ .
_. _ _ . ~_

6 Z6 z5 z4 Z6+~ Z5+~ æ4+æ~2 ~$Z~2- ~Z3~z )

7 Z7 26 Z5 ~ B6+~. Z5+~ ~- Z3 ~ ~ 4+~
_ _ _ _ _ ~ . . __ ~_ _ d Z B Z 7 6 Z 8 ~ Z 7 2 Z 6 2 ~Z 6 ~ 1 ~ ~ ~ 5t ~ 3 ~ _ i :~ . . . . ..... .. ... . ......... . . ....... ..

--~3--Zi~7 The filter circuit 2' illustrated in Fig. 6 comprises a combination of commercially available binary adders, regis~ers and dividers of the kind described hereinabove as being employed in the filter clrcuit 5 embodiment of Fig. 2. Each 8-bit digital word sample generated by the A/D converter 82 of Fig. 1 is coupled by the connecting lines 84 to the input of the timing buffer register 4~0 Upon the occurrence of each clock signal of the 10.7 M~z sampling signal at the clock input 88 of the register 49, an 8-bit digital word sample is transmitted from the input of the register 49 to its ou put coupled to the eight parall~l connecting llnes A. The connec~ing lines A branch into three different signal tran~mission paths to the ou~pu~ 91 o lS the fllter ci~cu~t 2'. The transmission p2ths include signal d~lay elements or mean~ that provide di~e~ent transmlssion times ~or each sample through the diferent signal transmlssion paths. In ~he embodiment of the filter circuit 2' illus~rated by Fig~ 6, the transmlssion 20 times differ by even mul~ples of ~he period of ~he 14 ~ 32 ~Hz sampling signal, wi~h the transmission time through the longest signal transmission path being four sampling signal periods longer than the transmission time through the shor est signal t~ansmis~io~ path and 25 the transmission time through the signal transmission path of in~ermedia~e length being two sampling signal per iods longer than the transmission tim~ ~hrouyh the shortes'c ~ignal transmission pathO As will become more -4~

~1~3~0 apparent upon consideration of ~he more detailed descrip-tion of the filter circuit 2' herelnbelow, the even mul~iple sampling signal period rela~ion hip of the transmission times of the tbree transmission paths S creates the "O" weighting coefficients specified in equation (8~ be~ause only every other sample of each sequence of five consecutive samples are combined to fo~m the weighted average sample value representation a~ the output 91 of ~he filter circuit 21.
The shortest signal transmission pa~h between connecting lines A and the output 91 of the filter circuit 2' includes a binary adder 65-coupled at its first input to the line A extending from the buffer register ~9 and followed by a binary divlder 66. The divider is responsive to ~he 10. 7 MHz sampling s~gnal coupled by,line~ 88 to it5 clock input to div~de the binary signal at its input by a factor o~ two. As descrlbed hereinbefore wi~h refer~nce to the embodiment of the filter circuit illustrated in Fig~ 2, such 20 dividers introduce a propagation delay of one sampling signal cycle in the signal transmission path. Conse-quently, the shortes~ signal transmission path has an overall signal transmission delay of one sampling signal cycle r with the delay located in the transmission path 25 so that a sample appearing on the cormecting li~es A
coupled to output of the register 49 appears at the firs~ input of the adder 65 without delay and a sample sum appearing on connecting lines G coupling the output 1~5~17 ID 2635 of the adder 65 to the input of the divider 66 is delayed one sampling slgnal time before it appears on the connecting lines H extending to the outpu~ 91 of the filter circuit 2 ' o The shortes~ signal transmission path generates the weighted average value 1/4 Zn+2 specified in equation ~8). The divider 66 provides a weighting coefficient of 1/2. The remaining 1/2 of the weighting o~ the average value is accomplished at the first input of the adder 65 by coupling each of the inpu~
bit lines ~ to a bit posi~ion input of the adder which is one bit position order lower than the bit position order of the input bit line.
Adder 65 and divider 66 are common to the three signal transmission path~. Therefore, the a~ore-lS mentioned di~ferences in th~ transmi~sion times throughthe three paths must be establlshed before the add~ 65.
The pos~tlon of the signal transmiss~on path of intermediate length be~ween connecting lines A and a second input of the adder 65 includes another binary adder 62 followed by two cascaded binary registers 63 and 64~ ~s described hereinbefor~ with ref~rence to the embodimen of the filter clrcuit illustrated in Fig.
2, each of the registers t ansmit~ data fro~ its input ~o its output in ~e~ponse to the sampling signal coupled to its clock input by line 88 and introduces ~ propagation delay of one sampllng slgnal cycle in the signal trans mission path. Consequ~ntly, the signal transmiss~on path of intermediate length provides a signal tran~mission delay be~ween lines A and the connecting lines F coupled 1, to a second input of the adder 65 of ~wo sampling signal cycles, which is two cycles }onger than the delay 'chrough the corresponding shortes1: signal transmission path. Therefore, a sample appearing on lines A coupled 5 to the first input of adder 6Z essentially will appear simul~aneously on connecting lines D ooupllng the output of the adder to the input of the register 63q Upon the occurrence of the nex~ sampling signal, the sample will be ~ransmitted by the register 63 to the connec~ing lines 10 E coupling the output of ~he register 63 to the input of the following register 64. Upon the occurrence of ~he second following sampling signal, the sample will be transmitted by ~he register 64 to the connec~ing lines F
coupling the output o~ the r gis~e~ 64 to the second lS input of tbe adder 65. Thus, at the same time that register 4g provides a sample at the firsk input o the adder 65, a sample tha~ was generated ~wo sample periods earlier by the A/D converter 82 o~ Fig~ 1 and transmltted through the transmission path of intermediate length is 20 provided a~ the second inpu~ of the adder 65 by the register 64. The signal transmission path o in~ermediate leng~h is comple~ed through adder 65 and dividez 66 to generate the weighted average valu~ 1/2 Zn ~pecified in equation (8).
The longest signal ransmission path is formed in part by ~he 9ignal transmission path o intermediate length, i.e~, the path from adder 62 ~o di~ider 66 and in part by register~ 60 and 61 preceding the adder 62J

ID ~635 E~ch of the registers 60 and 61 introduces a propagation delay of one sampling signal cycle in the s~gnal trans-mission path whereby the signal transmission delay between lines A and ~he connec~ing lines C coupled to a 5 second inpu~ o~ the adder 62 is two sampling signal cycles. The value of each sample received at ~he second input of the adder 6~ is wei~hted by a factor of 1/2 by coupling each of the input lines C to a bit position input of the adder which is one bit position order lower than the bit position order of the input bit lin~. At ~he same time that the register 61 provides a sample a the second input of the adder 62, a sample that is generated two sample periods later by the A/D converter 82 of Fig. 1 is pro~ided at the other first input of the adder 62 by the regi~ter 49. Therefore, the longe~t signal tran~m~ssion path provides a signal transmission delay be~ween lines A and the output 91 o~ the ~ilter circuit 2' that is four s~mpling signal cycles longer than that provided by the shortest ~ignal transmisson path 20 and generates the weighted average value 1/4 2n 2 ' specified in e~uation (8).
The operation of ~he ~ilter circui~ embodiment of Fig. 6 will be described now wi~h reerence to TAB. 2 tha~ depicts the propagation and processing of consecu~iv2 samples through ~he filter circuit 2'. Consecu~ive : samples Zl~ Z2~ Z3~ etc.~ are received in successlon at the input of the register 49 from the A/D converter 82 via connecting lines 84 at a rate of four times ~he ~D-2635 1~5Z1~7 frequenzy of the selected component to be eliminated from the composite signal sampled by the A/D converter~
At each clock time, th~ register and dlvider devices included in the fi:lter circui~ 2 ' are clocked by the 5 sampling signal applied to their respect~Ye clock inputs by line 88 to initiate processLng of the digital ~ignals present at their respective data inputs. For example, at the first clock time 1, register 49 is clocked to transfer sample Zl present on lines 84 to its outpu~, 10 which is coupled to lines A that ea~tend to the inputs o register 60, adder 62 and adder 65. Immediately upon the occurrence of the sample Zl on lines A extending ~o the first input of the adder 62, the adder responds by : transferring to tts output the sum of the samples recelved 15 at its two inpu~s. ~rhis sample sum, which includes sample Zl ~ is coupled by lines D to the lnput of th~
~egister 63, In addition, th~ adder 65 respcnds by trans~err~ng to its outpu1: the sum of the samples received at its two inputs, which includes the sample 20 Zl presen~ on l~nes A as weighted by a fact~r of 1/2 at ~he first input of the adder 65. This sample sum is coupled by lines G to the lnpu of the divider 66~
Upor~ the occurrence of the nex~ clock time 2, sample Z2 is placed on lines A and D and the weighted 25 sample 1/2 Z2 is placed on lines G at the outpu~ of the adder 65 in th~ manner describ~d hereinaboqe with respect to sample Zl at ~he clock t.ime 1. In addi~ion, registers 60, 61, 63 and 64 and divider 66 are clocked ~5217 ID-2635 to process and transfer to their respective outputs the sample values present at their respective inputs. As a resul~, sample Zl is placed on lines B extending fro~
the output of register 60 to the input of re~ister 61, and on lines E extending rom the output o~ register 63 to the input of register 64. Also, divider 66 weights the value of the sample sum then present on lines G by 1/2 and places the weigh~ed sample sum on lines H extending to the output lines ~1. This weighted sample sum includes the weighted sample 1j4 Zl-During the next clock time 3, sample Z3 isplaced on lines ~ and D, sample Z~ is placed on lines B and ~ and ~he weighted ~ample 1/2 Z3 is placed on lines G in ~he manner described hereinabove with re~pect lS to samples Zl and Z2 at clock tlmes 1 and 2~ In add~tion reglster ~4 and d.ivider 66 are clocked to process and transfer to their respective outputs the ~ample values then present a~ ~helr respectlve inputs.
This places sample Zl on lines F coupling the output o register 64 o the second input of the adder 65.
Consequently, the adder 65 places a sample sum on lines G that includes sample Zl plus the weighted sample 1~2 Z3. Register 61 place~ the sample Zl on lines C
e~tending to ~he se~ond inpu~ of the adder 62, at which point it is weighted by a factor of 1~2 and placed on ~he lines D. ~ence, before lock ~ime 4, the combined ~ample value 1/2 Zl ~ Z3 1~ ~rans~erred to the output of the adder 62 and is p~aced on lines D extend-~SO---SZ~7 ing to the input of register 630 Divider 66 weights the-sample sum present on lines G by a factor of 1/2 and places the weighted sample sum on lines H extending to the outpu~ 91 of the filter circuit 2'. This weighted sample su~ inclu~es the weighted sample 1/4 Z2 During the next three clock times 4, 5 and 6, samples Z4, Z5 and Z6 are successively placed on lines A by the timin~ buffer register 49 and are process-ed in the manner described hereinabove with respect to samples Zl~ Z2~ and Z3 at previous clock times 1, 2, and 3. P. more deta~led understanding of the process-ing and propagation of samples Z4, Z~; and Z6 through the fil er circuit 2' ln response to sampling signals at clock times 4, 5 and 6 can be had by reference 15 to T~B. 2, above. Clock~ng the regis~e~ and dlvide~
devices o the ~ilter circui~ 2 ' dur lng the clock t~me~ 4 and 5 cause~ reglsters 63 and 64 ~o trans~er the comb~n~d sample value 1/2 Zl ~ Z3 from the input of the register 63 to lines ~F extending from the output of ~he 20 regi~ter 64 to the second input of the adder 65 and causes the register 49 to place the sample value Z5 on lines P. extending ~o the firæt weigh~ing input of the adder 65. Hence, at the end of the clock time 5 ~ adder 65 provides a combined sample value 1/2 Zl + Z2 ~
25 1/2 Z5 on its ou~put coupled ~o lines G extending to the input o divider 66~
Upon th~ occurrence o~ ~he clock time 6, the combined sample value 1/2 Zl + Z3 1 1/2 Z5 present ~5~it7 at the inpu~ of the divider 66 is weighted by a fac~or of 1/2 and transferred ts i~s output coupled to lines H
extending to the filter circuit' s output 91. The weighted output of the filter circuit, i.e., 1/4 Z
1/2 Z3 ~ 1/4 Z5 and following weighted sample value representations is in accordance with equation ( 8 ~ and has the selected component whose frequen~y corresponds to one-fourth the frequency of the clocking signal eliminated because the weighted sample value representation of the selected component is zero, as can be seen upon consider-aton of equation ~ 8 ) and ~ig. 7.
It will be understood from ~he foregoing description that other combinations and arrangemen~s of regis~ers and arithmetic devices could b~ provided in a similar manner to obtain ~or a given number of averaged s~mple~ a zero welghked average sample value o a selected p~riodic signal., To simpllfy the description, the frequency and phase of the sampling sign~l is selected so ~hat the 20 sampled points Zl to Z7 shown in Fig. 7 coincide with zero and maximum values of sine wave Z. It will become apparen~ with respec~ to the ~oregong de~cription that the embodiment of Pig. 6 also will provide a desired zero average value of sine wave Z if here is a constant 25 phase difference hetween the sampling signal and the sine wave or selected signal componen~ to be flltered~
The filter circuiS embodiment of the presen~
invention illustrated in Fign 6 is particularly advanta-geous for filter circuits ut lized in applications where ~he sampling signal frequency is an even number multiple of the freyuency of the periodic signal component to be el~minated from ~ composite signal. The embodiment o~
5 Fig. 6 provides a desired zero weighted average value of the per iod signal component from a given odd number of samples. Consequently, ~he aforementioned potentially undesirable phase shift of one-halî of the sampling signal period which would result from averaging an even 10 number of samples is avoided by the circuit o~ Fig~ 6.
Wi~h reference to the foregoing description, lt is to be unde~stood that the filte~ of the present invention is not limited to the above-described embodi~
ments ~llustrated by Figs. 2 and 6. It will become 15 apparent ts ~hose skilled in the art that the filter may comprise ~arious arrangements o~ digltal signal p~oce~-~ng mean~ that cooperate to provide a zero average ~alue or a weighted zero average value of the si~nal component to be eliminated from a composite signal in accordanGe 20 with the described method of the invention. Por example, the filter circuit may utilize circuit elements for dividiny or part~ally dividing the samples followed by clrcuit elements for add~ng the divided samples ins~ead ` of bi~ shifting the samples at:the inputs of th. adders : 25 as described above with reference to the embodiment of Fig~ 60 ~urthermor~, the filter of the invention can be arranged to operate with variou~ re~ationships of sampling signal frequency and frequency o~ signal l~SZ~7 ID-2635 component to be eliminated or filtered from a composi~e signal. As described here.inbefore, the sampling signal frequency can be an odd or even integral multiple of the selected periodic component frequency to be eliminated.
Also, the sampling frequency can be a non-integral rational mul~iple of the selected periodic signal frequency. With respect to the embodiment illustrated by Fig. 6, an average of three weighted samples is obtained by weighting the first and last sample of five consecutive samples by one-half and not weighting the third o the five consecutive samples and dividing the sum of the three samples by a f ctor of two/ i.e., weighting the sum by a factor of 1/2. ~owever, if the three sample~ are weighted by lower actor, such as one-eighth for ~he first and last sample of the five consecutive samples and one-fourth for the ~hird sample, tha weighted ~um would ha~ to be multiplied by a factor of two, l.e., weighted by a factor of 2, to obtain the desired average sample represen~ation.
The filter of the present invention provides special advantages as a luminance-chrominance separator in color television signal processors, such as, for example, dropout compensators~ Fig. 8 illustrates one ~mbodiment of the dropout compensator of the present invention in which a digi~al color television signal i~
received at an input terminal 10 coupled to a firs~
input 11 of a two-way switch 1. A control signal indicating pr~3sence of a dropout is received by a control terminal 12~ for example, from a conventional .... ..

~l~S2~ 7 ID-2635 dropout detector (no~ shown), such as included in commercially available video tape recorders. A suitable dropout detector may be of a conventional carrier monitor type which provides a control signal when the R. F.
envelope of the modulated television signal drops below a predeter~ined level, such as used, for example, in the Amepx Corporation manufactured VPR-l ~ideo Production Recorder, and shown in the manual for that recorder~ Catalog No. 1809276-02, published by Ampex 0 Corporation in December, 1977, schematic drawing 1378633C, pages 8-41/42 and 8-43/440 The control terminal 12 is -54a-t~ ID-2635 coupled to a control input 13 of swltch 1. Outpu~ 14 of switch 1 is coupled to an output ~erminal 15 of the dropou~ compensa~or. The output 14 of switch 1 is also coupled to an input 18 of a digital filter 2 correspond-ing to the filter of the present invention, such as theabove-described embodiments illustrated by Fig. 2 or Fig.
6, respectively, The output 14 of swi~ch 1 is further coupled to first input 16 of a digital differencing circuit 3 via a digital delay circuit 7. A second input 1~ 17 of the differencing circui~ 3 is coupled to an output 19 of the digital filter 2. An output 20 o~ the differ-encing circuit 3 is coupled to a first input 21 of a digital adding circu~t 5 via a fixed digital delay line 4. The second input 22 of addlng circuit 5 is coupled to the ou~pu~ 19 o~ the digital il~er 2~ An outpuk 23 o ~he a~ding circuit 5 is cou~led to a ~econd input 24 o swi~ch 1 vla another ~l~ed digital delay line 6. The delay circu~t 7, coupled be~ween the output 14 of switch 1 and inpu~ 16 of differencing circuit 3 is u~iliz~d to compensa e for circuit delays in filter 2, as it w~ll follow from the further description. The dropout compensator is controlled to process the digi~l tele-vi~ion signal by a clock signal provided a~ inpu~
terminal 260 The provided clock signal is ~he signal related clock signal prevlou~ly described as being generated for use by the filter circuit of the presen~
inverltion and is d~termined by the particular fil~er embodiment used in the d~opout compensator" If ~he 1'7 filter circuit illustrated in Fig. 2 is used in ~h~
dropout compensator; the clock signal is obtained from the signal clock generai:or 83 of ~ig. 1.
Now the operation of one pre~erred embodiment 5 of the dropout compensator of the present inven~ion will bP desoribed with reference to Fig. 8. ~ digi~al NTSC
color television signal in the form of discrete 8 bit digital data words representing samples of the television signal, such as provided by the A/D converter 82 of ~ig.
10 1, is received at input terminal 10 and fed to first input 11 of switch 10 When the telev sion signal system is in normal operation, that is, no dropouts in the incoming ~ignal are d~tected by the dropout detector, switch 1 is in its irst position re~eiving the input 15 signal a~ input 11 and applying i~ to output 14. When a dropout is detected in the color televi~ion ~ignal, ~or example, by the aforemen~ioned conventional dropout de~ector, the control signal received at terminal 12 i5 applied to control input 13 of the two-way switc~
~ The control signal received by ~he two-way switch 1 causes it to disconnect the ~irst input 11 from ~he ou~put 14 and to connect i s second inpu~ 24 ~o the output. Consequently, th~ s~gnal representing- a delayed portion of he dlgltal color television slgn~l rece'ved 25 at second inpu~ 24 is now applied to outpu~ termlnal 157 That delayed slgnal represents a dropout compensat on si~nal utilized to replace the dropout por~ion of ~he ~elevision information signal, ~hus preven~ing any ~-2635 21~

disturbances in the displayed television picture which would be caused by ~he presence of a dropout., The above indicated dropout compensation may be provided for one or more television line perlods or any fraction 5 thereof.
The portion 25 of the dropout compensator circuit clrcumscribed by dashed lines, which provides the desired signal delay for dropout compensation, will be described now in accordance with the preferred 10 embodiment of the invention shown in Fig. 8. Filter 2, which i~ designed, for example, as shown in Pig. 2, receives the digital composite color tPlevis.ion signal from outp~t 14 of switch 1 i~ the form of consecutive samples at a selected clock signal frequency, ~or exampl~, equal ~o ~hree t~mes ~he nomin~l fre~uency oE
the NTSC chrominance ~ubcarr~e~ component~ tha~ is~
f5amp1 =3 x 3.58 MHz 3 10.74 MHz~ The sampling signal is phase locked ~o the chrominance subcarr~er signal, as it i~ well known in the ar~, ~or example by phase-locking to ~he color burst component, as described in ~he previously mentioned AVR-2 Video Tape Recorder Catalog, pages 9-28 to 9-39O It follows from the foregoing descrip~ion of the opera~ion of the filter with respect to Fig. 1 khat three samples define a time interval 25 equal to one cycle of the chro~llinance subcarr ier componeritO
~t also follows from ~he fore~oing descrip ion ~ha~ th~
lowest frequency component whlch is removed by fil~er ~
from the composite signal is 3.5~ M~z~ The nex~ higher ~ ~5~17 ID-2635 frequency component also removed by the filter is 2 x 3.58 MHz = 7.16 M~z. ~his la~ter frequency, howeverr is ou~side the frequency band of an NTSC signal whose ~otal bandwidth is 4 . 2 M~lz. Generally, in other conventional color television signal systems, such as PAL, PAL-M, etc., ~he total bandwidth is also below twi~e the color subcarrier signal frequency and, consequently, no signal d~gradation results.
As de~cribed hereinbsfore with reference to 10 Flg. 2, filter Z provides an average of the ampli~ude values of three consecutive samples received at its input 18. It follows from equation (2) that Pach such average value o ~he chrominance subcarrier signal component is equal to zero~ Consequently, ~he 15 signal at the output 19 of fllter 2 r~presents the composite color television signal from whlch the chromi-nance subcarri~r component having a nomlnal ~requency of 3.58 M~z is eliminated. Thus, ~he resulting signal at the ou~put 19 of ~lter 2 is a chrominance-lesq colo.
20 televislon signal, which will be considered fur~her as representing the luminance component. It follows from ~he foregoing descr~p on, tha~ the resulting signal at ~he output 19 of the filter 2 is represented by average sample values obtained by successively averaging three 25 consecu ive samples. Each ob~ained average sample value is substituted for ~he sample in the middle of each three consecutive samples taken :Eor averaging~ It is noted that the obtained averaged samples do not exhibit -5~-i217 ID-2635 a phase-shift with respect to the originally received samples, since an odd number of consecutive samples is being averaged.
With further reerence to Fig. 8, the signal from output 19 of digital fil~er 2 representing the separated luminance component is applied to the second input 17 of differencing circuit 3. The color television signal V ~rom output 14 of switch 1 is applied via delay circuit 7 ~o ~he first input 16 of circuit 3. Differenc-ing circui~ 3 provides at its output 20 a differenc2signal of the two signals received a~ its first and second inputs. The resulting difference signal represents the separated chrominance component of ~he color tele-vision signal. It is seen from the foregoing description that by utilizing the dlgi~al filter 2 of the present invention in comblnation wi~h the differenc~ng circuit 3, as above disclosed, separation o the luminance and chrominance componen~s of the color television signal is provided. The separated chrominance component at ou~put 20 is delayed in the first delay line 4 by a time subs~antially corresponding to one horizontal line period of the televi~ion signal~ The separated and delayed chrominance component and separated luminance component are respectively fed to inputs 21 and 22 of 25 adding circuit 5~ These two signal components are recombined in circui~ 5 to form a composite color television signal at outpu~ 23 thereof. The latter signal ~s fed from outpu~ 23 of circuit 5 to input 24 of ~ ~ ~ 5 ~ ~ XD-2635 swi~ch l through a second delay line 6, and i~ is delayed thereby by a ~ime subs~an~ially corresponding to one horizontal line period of the television signal.
The delayed signal represents the dropout compensation 5 signal by which one or more co~secutive lines, or fractions of lines, of missing ~elevision information may be replaced by the dropout compensator when a control s1gnal at terminal 12 is applied, as it has been described previously. If it is necessary to replace lO more ~han one television line by the dropou~ compensator, the output signal from circuit 25, representing the dropout compensation signal, will circulate from ou~put 14 of switch 1 to its second lnput 24 via circuit 25 and o~t through output t~rminal lS un~il the con~rol signal a~ 1~ is removed.
It is to be realized that the above-d~scr~bed preferred embodiment of Fig. 8 represents a dîgital dropout compensator in accordance with the present invention in which high speed dlgital da~a is processed.
Consequently, the various elem nts shown in the simpli fied block diagram of Fig. 8 may be designed a~ conven-~ional digital circu~ts in which the high speed da~a is precisely clocked a~ three timés the color subcarrier signal frequency, that is, at approximately lOu74 M~z, 25 while ~he clock signal i5 frequency a~d phase-locked to the chrominance subcarr~er component of ~he sampled color television signal, as described before. For simplicity of representatio~, ~he clock signal path is ~60-r S~ 2 6 3 5 not shown in the block diagram, however, it is shown in a detailed circuit diagram of Figs. 13a t~ 13h co~respond-ing to the block diagram of Fig., 8, which circult will be describPd later.
Delay circuit 7, shown in Fi~. 8 as ooupled between input 18 of digital filter 2 and input 16 of diffeEencing circuit 3 ln the composite color television signal path, serves to provide additional fixed delay to compensate for ~he propagation delay of ~he signal lû through the digital filter circuit 2. For proper opera~ion of the digital dropout compensator, it is important to separa~e and combine corresponding data by the subtraction circuit 3 and addition circuit 5, respectively~ in a precisely synchronized man~er to preYent undesirable phase shi~ts between the ~eparaked ch~ominance and luminance compone~t. Such phase ~hi~ts would introduce unacceptable time base errors and distort ~he resulting television pictureJ Therefore, it i5 necessary to determine the exact amount of fixed delay provided by the respective delay line~ 4, 6 and 7 in such a way that the ~otal delay of the chrominance signal component from output 14 of sw~tch 1 to its input 24, that is, when passing through circuit branch 25, is exactly equal to two horizontal line periods of the 25 color televisiqn signal re::eived at terminal ~2, wh~reas the total delay of the luminance signal component effected by its passage through ~he circuit branch 25 is exactly equal to one horizontal line periodg For ~.~.55~17 determining the exact amount of delay to be provided by-each o the fixed delay lines 4, 6 and 7~ respectively, the total amount of delay provided by the respective circuit elements in the luminance and chrominance signal paths should be considered. The ac~ual amount of delay provided by delay lines 4, 6 and 7 should be adjusted accordingly. Consequently, in the preferred embodiment of Fig. 8, the delay provided by delay line 4 is equal to one horizontal line period less the delay provided by dif~erencing circuit 3. Similarly, ~he actual amount of delay provided by delay line 6 is equal to one horizontal line period less ~he comb~ned delays provided by filter 2 and adding circuit 5, respectively.
With respect to the well known relationship of the color subcarrier component frequency and horizontal lin~ frequency of NTSC signals fSC=227.5fH, in this part~cular embodim~n~ of ~he invention a non-in~egral number of samples equal to 3 x 227.5~682.5 clock cycles is obtained within one horizontal line period4 To compensate for the non-integral relationship, delay line 6 may be de~igned to provide an alternative delay of, ~or example, 682 and Ç83 clock cycles on alternative consecutive linesr corresponding ~o the closest h~gher and lower integral number of clock cycles~ Thus, ~he average delay provided by delay line 6 over any two consecutive lines will be 6B2.5 clock cycles. To compensate for ~he above deviation of one clock cycle on consecu~ive lines, delay line 4 may be designed to ~ 5 21 7 ID-2635 provide comp~ementary delays in the chrominance signal path of, for example, 683 and 682 clock cycles, respec-tively, on ~lternative consecutive lines. Thus~ a desired two line delay of exactly 2 x 6~2~5 cycles is provided by combined delay lines 4 and 6 in the chrominance signal path. However, it is noted with . respect to the previous disclosure that, the actual delays provided by delay lines 6 and 4 will be reduced by the above mentioned respective circuit delays in the luminance and chrominance s:ignal paths.
It will become evident that if an integral number of~clock signals is provided within one hori~ontal line period, such as by selec~ing a sampling frequency equal to an even number-mult~ple of the color subcarrler 15 fre~uency, for example four times the color subcarrier frequency~ the delay provided by delay line 4 doe~ no~
have to be changed on al~erna~e lines.
With respect to the above-described operation of the digital dropou~ compensator of Fig. 8, providing I
~0 a one-line delay of the luminance componen~ and a two line delay of the chrominance componen~ offer~
several advantages. First of all, ~he one-line delay of the wideband luminance component is an improvement over known digital dropout oompensators, which provide a 25 two-line delay of the luminance component. Seeondly7 the circuit of the pre~ent invention is an Lmprovement over the prior art analog dropout compensators which provide one-line delay of both the luminance and chromi-~s~ ID-2635 nance componen~ and require line-to-line inversion of the chrominance component to ob~ain a proper phase relationship thereof. As it has been pointed out above, ~hese latter dropout compensa~ors are not directly applicable for digital PAL or PAL~M systemsu Similarly, they are not direc~ly applicable for digital NTSC
systems utilizing a sampling signal frequency equal to an odd in~egral multiple or rational number multiple of the NTSC subcarrier frequency. In case the above-10 indicated type of analog dropout compensator would beadapted for digital color television systems utilizing known com~ filter ci~cui~s, it would be necessary to provide vertical alignment of samples. ~n advantage of the digital dropou~ compensa~or of the invention is that it does not require vertical alignment of sample~ thus elimlrlating the need ~or line-to-l~ne adjustment o~
~amples .
It ~ to be noted tha~ in the digital dropou~
compensator of the present invention the separated chrominance component notched out by the fil~er ha a bandwid~h restricted to a sin~le nominal frequency, such as 3.58 MH2 fo~ NTSC, or 4.43 MHæ for PALo This restrict-ed bandwidth is ve y narrow in comparison to the lumi-nance componen~ bandwidth~ which is, for example, D. C., ~o 25 4.2 MElz in NTSC systems. Consequently, ~he two line delayed chrominance component combined with the one line delayed luminance component does not represent objection-able distortion o~ the displayed television signal.

\

,~f~ O

When comparing the above-described dropout compensator of ~he invention to prior art analog compensators utilizing, for example, band pass filters for separation of the chrominance and luminance components, a d~opout 5 compensa~ion signal compr ising a luminance component delayed one line and a chromirlance component delayed two lines would ~ntroduce a visible luminance to chrominance interference in the television picture. This is largely due to a relatively wide nominal bandwidth of the separated analog chrominance component resulting from the well known frequency characteris~ics o~ analog filtersc Furthermore, when recombining the separately processed components into a composite signal by the dropout compensator of ~he present inven~ion, the fu17 or~ginal fre~uency bandwidth of the ~levision signal i5 restored, thus pract1cally no frequency losses occur~
As opposed there~o, losses in ~he composite signal bandwidth are effected when analog filters are u~ zed for signal processiny~
There is a further advantage of the dropout compensator of the present invention when comparing to known analog compensators. In the dropout compensator of the present i~vention, no relakive delay between the luminance and chrominance component other than the desired one horlzontal line delay occurs in ~he composite signal processed by the compensator, since these signal components are maintained synchronous throughou~ the processing by precisely clocking the digital signals, "

~ S217 ID~2635 and the respective delays provided by various circuitelements are known and compens~ted for by fix`ed delay lines.
Since the filtering pro ess of the present 5 invention is restric~ed ~o averaging a few consecutive samples wl~hin the same television line, any unwanted short tlme disturbances, such as noi~e spikes in~roduced into the television signal, are limited in tim~ ~o the occurrence of ~he particular samples and to the relative-ly short time in which they are averaged~ As opposedthereto, known digital comb filters providing sample values taken from samples of different television linPs or; analog filters whose time response effects v~slble transients in form o~ streaks in the displayed kelev~slon lS signal caused by noise spike~, provide a more extenqive sig nal distor tion .
Still ~ the~e is a further advantage o~ the digital dropout compensation circuit of the present inven~ion in that all signal processing is provlded in 20 real time utilizing standard TTL ( transistor-to-transistor logic) circuitry, as it will be seen from a detailed cir'cuit diagram of a preferred embodimen~ of the present inven~ion shown in Figs. 13a to 13h, the descrip~ion of whic:h :Eollows. The circuit of the above-indicated 25 figures is sui~able for dropou~ compensation in a color television signal recording and reproduc~ng system where an NTSC, PAL, PAI,-M, etc., color television signal is encoded in digital fs: rm by sampling at a requency --~6--~ S217 ID~263S

equal tc three tim~s the color subcarrier frequency of the television signal . First, an embodiment suitable for use in NTSC systems will be descr ibed I in which the sampling signal frequency fsampl = 3 x 3.58 M~z - 1û.74 M~z., 5 ~he sampling signal is phase locked to the color burst componen~ of ~he subcarrier signal as well known in the artO The sampling frequency is equal to the clock frequency as previously mentioned with respect to the description of Fig. 8; consequently, in the fur~her description we will refer interchangeably ~o ~he sampling frequency and clock frequency.
Generally, for opera~ion of the dropout compensator of the invention, the sampling requency ueilized to encode the composite analog signal, for 15 example, ~he color television signal, does not have to be ~he same as ~he clock signal ~requency utllized ~o synchroni~e the var ious elements of the dropout compensa-tion circuit. In the latter case the samples may be received and stored in a buffer circuitt for example, at 20 the sampling ~requency, and subsequently recovered at a different clock freque~cy, while the latter frequency : is utilized for synchronization of ~he circuit.
U ternative dropout compen~ator embodimenSs are shown in Figs. 9 to ll and will be descr~bed briefly.
25 To fac~litate comparison with the previously described embodiment of Flg. 8, similar circuit elemen~s in ~he following alternative embodimen'cs are designated by like reference numerals. The circuit of Fig. 9 is simila~ to that o~ Fig. 8 with the exception that the input of the circuit branch 25, that is, input 18 of filter 2 and input 27 of delay circuit 7, respectively are coupled to input 11 of switch 1, instead of to its 5 output 14, as i~ is in ~ig. 8. This particular circuit arrangement is useful when only one line of the television information is to be replaced by a dropout compensation signal since no means is provided for recir~ulating the delayed information from the output of the switch back 10 to its input a~ in the circuit of Fig~ 8. ~f it is necessary ~o compensate for more than one television line, additional memory means, such as a known circulat-ing memory, could be utilized a~ ~he ~utput of switch 1 Figs~ 10 and 11 depict further alternative lS embodiments of the dropout compensator of the present inverltion. These lat~er embodim~nts di~er ~rom ~he previously described embodiments of Figs. 8 and 9 by the implementation of the circuit branch 25~ as followsO In the embodiment of Fig. 10, the delay line 6 of the 20 embodiment of Fig. 8 is replaced by delay line 30 coupled in the composite television signal path between the ou~pu~ 14 of swltch 1 and input 18 of fil~er 2.
Delay line 30 p~ovid~es delay for both the chrominance and luminance component o~ a period of one horixontal line 25 less the combined delays in filter 2 and adder S,. It is seen that the resulting respective delays of the chromi-nance and luminance component are the same as in the ll~S21~ ID~2635 previously described circui~ of Fig. 8.
In the circuit branch 25 of the embodiment of Fig. 11, ~he delay line 6 in the correspond~ng circu~t branch 25 of the embodiment of FigO 8 is replaced by 5 a delay line 31 coupled in the separated luminance signal path between the output 19 of filter 2 and input 22 of summing circuit 5, by an additional delay line in the separated chrominance signal path, as it is explained belowc Filter 31 provides a one horizontal line delay 10 less the combined delays provided by filter 2 and adder 5. Delay line 4 o~ Fig. 8 is replaced in the embodi~ent of F~g. 11 by a delay line 32 coupled in the separated chrominance signal path between the output 20 of the dif~erencing circuit 3 and input 21 o~ adder 5c Delay 15 line 32 provides a two horl~ontal line delay lesq the combined delays in circuit~ 7, 3, and 5O Consequently, the deslred one line delay of the luminance component and two line delay of ~he chrominance component are provided each in the respective separated signal pa~hs 20 Of these components in the circuit of Fig. 11~
It will become apparent from the above descrip-tion that the dropout compensa~or of ~he present invention may be implemen~ed by a variety of combina~io~s of delay means coupled in the composite siynal path as well as in 25 ~he sepa~a~ed chrominance and luminance signal pa~hs to achieve ~he desired one-line luminance and ~wo-line chrominance component delay, respectively. It will become further apparent tha~ various alterna~ive embodi--69~

~ 5Zi~ ID-2635 ments o circuit branch 25 of the dropout compensator may receive an input signal directly, as shown in Fig~ 9 or via switch, as shown in Figs. 8, 10 and 11. It will also become apparent that in the embodiments of Figs. 8 to 11 filter 2 may be implemen~ed to plovide an average value output signal or a weighted average value signal in accordance with the forego7ng disclosure with respect to Figs. 2 and 5.
An example of a preferred embodiment of the 10 dropout compensator of the present invention arranged ~o process a digital NTSC color television signal formed by sampling the signal at a sampling fre~uency that is an even number multiple of the color subcarrier signal frequeney is illustrated ~n F~g. 12. In that embodimentr 15 a s mpling frequency of four tlmes th color subcarrler frequency ls used. ~s is well known .in ~he art, samQling an NTSC color ~elevision signal a~ a fre~uency equal to an even number multiple of the color subcarrler signal frequency results in obtaining samples corresponding to 20 loca~ions of vertically aligned picture elements~
~owever, an NTSC color subcarrier signal has an opposite phase on consecutive horizon~al lines and an lden~ical phase on ~very other line. Consequen~ly, to ach eve a properly phased dropout compensation signalf a separated 25 NTSC chrominance component may be slmply inverted on consecutive line~, a~ it is known in the art~ ~o facili~a~e a comp~rison with the previously described embodiments of Figs~ 8 to 11 7 corre~ponding circuit 1~ 2i~ 635 . . ~d~ , elements in the embodiment of Fig. 12 are designatedby corresponding reference numeral~. To avoid undue repetition, only those portions of Fig. 12 will be described which are different from the previously 5 described circuits of Figs., 8 to 11.. As menJciond above, the embodiment o Fig. 12 uses a sampling frequency fsampl 1:hat is an even multiple of the subcarrier frequency f5ubc~ a clock signal frequency equal to 4 x 3.58 M~z = 14.32 M~z. In the embodiment of Fig~
filter 2 may be designed in accordance with the embodi-ments of Figs. 2 o~ 5, as previously described.
In the embodiment of Flg~ 12, an NT5C color television signa~ is separated lnto its luminance and chrominance component at the output of filt~r 2 such as previously described wl~h respect ~o Fig. 8. When comparing the circuit o~ FigJ 12 to the circuit of Fig.

8, it ~s s~en that delay line 4 in the separated ch~om~-nance componen~ path is replaced by phase ~nverter 40.
: To compensa~e for the clrcui~ delay of the inver~er, an additional delay circuit 41 is coupled in the separated luminance sign~l pa~h. Delay circuit 41 provides a delay equal to that provided by ~nver~er 40. Thus, the same amount of d~lay ~n both the separated luminance and chrominance signal paths is provided in preparation for subsequent combination of the separa~ed siynals in adding circalt 5O Consequently, the one-line delay 6 provides a delay ~qual to one horizontal line in~erval less the co=bined circuit delays of ~ er 2, delay iZl~

circuit 41, and ad~ing circuit 5~ It follows from the foregoing description that both the luminance and chrominance components of the dropout compensator in Fig. 12 are ~elayed by one hori~ontal line interval.
One preferred embodiment of specific circuitry for implementing the dropout compensator embodiment of the present invent-on shown in Fig. 8 is illustrated in consecu~ive Figs. 13a to 13h. To facilitate comparison between Figs~ 8 and 13, individual circuits in the 10 specific circuitry of Figs. 13 corresponding to elements of the block diagram of Fig. 8 are circumscribed by dashed lines and designa~ed by like reference numerals~
Similarly, connecting lines between the individual circuits of the speci~ic circuitry a~e designated by 15 reference numerals corresponding to input!outpu~ deslgna-~ion5 of corr~sponding block~ of Fig. 8. For the purpose o~ complete disclosure, the integrated circuit componen~s shown in Figs. 13a to 13h are designated by respective part numbers commonly used by manufacturersO
In Fig. 13a, consecutive 8-bit parallel digital word samples Sl, 52~ S3, etc., of ~he dig~tal color television signal are received at lnput 10 of the dropout compensator by two da~a selector/multi-plexers U42 and U51 of swi~ch 1. These multiplexers 25 also receive data at input 24 from delay line 6, shown in Pigs. 13g and 13h. A control signal is r~ceived at input 1~ by the multiplexers from a oonventional R. F.
envelope level dropou~ detector circult (not shown~, as -72~

~ ~Lr~ 7 ID-2635 ~ , entioned be~ore. In normal operatio~lt the mul~iplexers apply the input data from 10 to output 14. When the control signal at 12 is ~eceived, ~he mul~iplexers switch from input 10 to inpu~ 24. The data from 14 is 5 fed to output 15 of the dropou~ compensator, and it is also supplied to the inpu~s 18 of the ~hree transmission paths through the filter circuit 2 located in Figs. 13a, 13b and 13c. A f ilter circuit embodiment of the kind shown in Fig. 2 is utilized. ~he data from 14 is applied to 10 the first register 50 of the fllter circuit formed of flip-flops U66 and U9, which delays th~ first sampIe Sl by one clock signal period to assure its proper 1 imin~ for addi tion with the second sample S2 ~eceived one clock signal late~ . Samples Sl and S2 are 15 coupled for adding in adder 51 formed of two 4-bi~
b~nary adders U75 and U83 shown ln F~g,. 13b ~nd the sum Slt~S2 i5 coupl(3d to ~egiser 52 ormed by 1ip-flops U57 and U50, which provides the one clock signal delay in preparakion for add~ on with he subsequently 20 recei~d sample S3. The latter summation is performed 1, : by the adder 53 formed by two 4-bit binary adders U58, U67, and an output signal therefrom represent~ the swn S-Sl~S2+S3O The summed signal S i5 coupled to register 54 formed by flip-flops U49, U50 to assure 25 proper timing for further processing. In this partLcular embodiment of the invention an avPrage sample value is obt~lned by dividing signal S by 3. The division by 3 is performed with a û;,1396 accuracy by an approximal:ion -~1 ~S Zl ~ ID-2635 algorithm:
3 4 16 64 256 (lO) For the particular application of averaging the samples ln the p~esently described preferred embodimen~, the approximation algorlthm of equation is implemented in two s~eps as follows:
PS - S4 + S16 (11) 3 = PS + PlS (12) Steps tll) and (12) are performed by the divider 57 of filter 2 shown in Figl 13c as described below.
4-bit binary adders U39, U48 of Fig. 13c receive the signal S at ~wo sets of inputs. At one of the inputs, the lines are coupled to ~he adder in a conventional manner to bit shi~t the signal S two bit 15 positions to become 4~ The adder provides a sum o ( S ~ ,S,, ) ~ ~t the output of the adder, the summed ~ignal is shlfted conventionally another bit postion to obta~n an output s~gnal corresponding ~o (S + S~)/20 The lat~er output signal represents twice 20 the partial sum PS deined in equa~ion ( 11 ) ,, The signal 2PS ~s applied to flip-flops U4û, U14, which are clo~ked to supply sigllal 2PS to two sets of inputs sf ~he 4-bit binary adders U~2 and U33. At one of ~he inputs, the lines are coupled conventionally to the adders to blt shift the signal 2PS four b~t posi~ions to obtain 2P6S. At khe output o~ the adders, the ~ummed signal is conven~ionally shifted ano~her bit po~ition to provide an output signal correspond~ng ~o 1 ~ ~ 5 ~1 ~ ID-2635 (2PS + ~- )/2. This outpu~ signal represents S3 of the approximation algori~hm ~ndicated by equation (12). The obtained signal 53 corresponds to the previously described average value outpu~ signal 5 of the filter of Fig. 2 at the output VI~ of divider 57.
For bet~er comparison with ~lg. 2, corresponding registers and adders in Figs. 13a and 13b and the divider in Fig. 13c of the filter circuit 2 are respectively designated by like reference numerals. The output signal of the 10 divider 57 in Fig~ 13c thus represents the chrominance-le5s color television signal, tha~ is, ~he separated luminance componen~, as ha~ been described above with reference to Fig. 8. Signal 3 is appli~d ~o flip-flops U31 and U22 which provide both an ou~put 15 slgnal S3 applied ~o input 22 of adder 5 shown ~n Fig. 13f and an inverted output ~ignal _S
applied to input 17 of dl~ferenc~ng circuit 3 shown in Fig. 13d.
The dif~erencing circui~ 3 includes 4-bit 20 binary adders U30, U21 that receive the signal -at one ~et~of inputs 17~ ~s it is shown ~n Eig~ 13a, the color television data received by switch 1 iS
~pplied to the delay line 7 comprising flip-flops designa~ed~U8, U65~ U56~and U47, which are clocked by the clock signal on l~ne 26 to provide a fixed predPter-mined delay of the re ::~ived signal to comperlsa~:e :Eor a known amount of delay provided ~y the ~ lter circuit ~
illu~rated in Figs. 13a through 13c. The output data, ~ 75--1~ ~S~17 ID-2635 indicated V, of delay line 7 is applied to a second set of inputs 16 o:E adders U30, U21, of the differencing circuit 3 shown in Fig. 13d. The above adders provide an output signal (V - 3) which represents ~he separated chrominance component of the colsr tele-~ision signai, as described above with reference to the embodiment of Fig. 8. The obtained chrominance component is fed via clocked flip-flops U29, ~3 and output 20 of circuit 3 ~o ~he delay l1ne 4 shown in Fig. 13eO
Delay line 4 comprises eight identical 4 x 256 bit random access memories of which six memories designat-ed U26, U17, Ul, U27, U18 and U2 are shown. Two groups of four memories each are utilized for xeceiving higher and lower order bi~s, ~espectively. The delay line 4 provides a fixed amount o~ delay of the separated chrominance component, equal ~o one horizon~al lin~
period of the colo.r televi~on signal l~ss ~he delay in diferencin~ circuit 3 coupled in the chrominance signal path. The wrtting of data into and reading of data from the memories of the delay line 4 ~s controlled by control signals ~ through ~ These signals ar~
obtain~d from the memory address genera~or 9 shown in Fig. 13d, which will be described in urther detail hereinbelow. Cascaded clocked flip-flops Ull, U3 and 25 U12 ~ U3 r and multiplexer~ U20, U4 are utilized to assure proper timing of output data a~ output 28 from de~ay line 4 to achieve the forego~ng delay.

To effect ~he aforedescr~bed alteration of thede~ay provided by the delay line 4 so that th~ overall delay in the chrominance sign~l path 1s changed between 6~2 and 683 clock cyclesl a cont~ol signàl, W~0, ~s 5 applied to ~he mul~iplexers U20, U4 to swi~ch the output of the multlplexers between its two inputs ~espectively supplied by the flip-flops Ull, U3 and U12, U3~ The control signal, WA0, is a signal that alternates between a high and low logic level at a frequency equal to 10 one-half the horizontal line ra~e and is genera~ed to be synchronous with the 10.7 M~z clock sig~al and the hori~ontal synch~onizing signal of the video signal belng processed by the dropout compensator. During each cycle of the cantrol signal, WA0, i~ i~ at one o~ its logic levels for an interval equal to 682 clock cycles and at the other for an lnterval of 683 clock cycles~
5witching the ou~put of the mul~1plexers between the ~nputs ~upplied by the two clocked cascaded ~lip-flops ha~ the effect of inser~ing (or removing) one clock cycle of delay~into the d~lay 40 W~th the output o the mul~iplexers coupled to the input supplied by the flip-10p U12, U3, the delay provided by delay devlce 4 ~s one clock cycle longer than when the mul~iplexer's output is coupled to recelva data ~upplled by ~he flip-flop U11, U3~ This additional one clock cycl~ of delay is tbe time requ1red to transer data from the output of flip-flop Ull, U3 ~o the outpu~ of flip-flop U1~, U3.

ID-~635 ~ I ~11 ~L~
Ll~ 4 The delayed chrominance component provided at the ou~pu~ 28 of delay 4 is applied to input 21 of adder 5 shown in Fig. 13f. As shown in Fig. 13f, the data from inpu~ 21 's applied to a first set of inputs of 4-bi binary adders U37, U13. The da~a S3 from inpu~ 22, representing ~he separated luminance componen~, ~s applied to a second set of the inputs of the adders via clocked flip-flops U38, U14 to assure proper timing for addition. The output da~a from the latter adders represents a composite color ~elev~sion sIgnal in which the chrominance component is delayed about one horizontal line period of the television signal while the luminance componen~ is essentially undelayed, with the except~on of the respective circuit delays as lndlcated before.
To prevan~ ~oldback ln the output siynal ~rom adde~s U37, U13, an overflow and ~nderflow ind~cating circult i~ utilized ~n the c~rcuit o~ Fig. 13~ as ollows. The most s~gnifican~ bi~ Cl a~ ~he inpu~ of adder U37 is applied via inver~er Il to the ~npu~ of ~ AND gate Al~ The o~her input f ~1 is formed by the ncarry" output a~ p1n 9 of adder U37. The outpu~ of Al is applied to one ~nput of OR gates l 8' respectively. The other inputs of the OR gates receive the ou~put~slgnal from adders U37, Ul30 Th~ ou~put signal from the OR gates l to 8 i5 applled to multiplexers U39, U4~. Whenever an vverflow occurs, ~he ~ND gate Al act~vates the OR gates to force the multiplexers U39, U46 to place a h~gh loyic level ~lgnal ;Zi7 on all its output lines 23 when clocked by the clock signal. For underflows, the "carry" ou~put of pin 9 of adder U37 is also appl~ed via inverter I2 to one input of NAND gate Nl, which also receives at its other input the most s~gnificant bit Cl applied at the input o~ adder U370 The output of Nl is applied to a control inpu~ of the multiplexers U39 J U46. Whenever an underflow condition occur~, which is represen~ed by a simultaneity of conditions at pins 9 and 11 of the adder U37, the output of the NAND gate Nl goes to a low lo~ic level and forces the mul~iplexer U39, U46 to place a low logic level signal on all of its output lines 23.
As it is known ~n the artt the NTSC chrominance subcarrier componen~ has an opposlte phase at the 15 b~ginning o~ each consecuti~e television line, and consequently, lt ha~ th~ same phase at the beginn~ng of every other line. It is also known in the ar~ that for ob~aining a dropou~ co~pensation signal it ls necessary to delay both the luminance and chrominance component by one horizontal line pe~'od. Howeve~, to achieve a proper lin~-to~line phase relationship of the chrominance component in the embodiment of ~igs. 13a ~o 13h~ ~he latter component is delayed by two horiæon~al line periods as will become apparent from the following description~
The signal at the ou~put 23 of multiplexers ~39~ U46 in Fig~ 13~ represen~ an NTSC color ~elevlsion signal having the chrominance componen~ delayed substan-~L rj~ ID- 2 6 3 5 tially by one horizontal l~ne per ' od and having the luminance component subs~antially undelayed. The combined composlte ~elev~si.on signal from the output 23 ~s applied to th second delay line 6 shown in Figs. 13g 5 and 13h. Delay line 6 comprises eigh~ ldentical 4 x 256 bit xandom access memories of which six memories designat ed U79, U70 r U52, U80, U71 and U53 are shown. Two groups of four memories each are utilized to receive highex and lower order bits, respec~ively. The delay lO line 6 delays the composite color television sig~al for a~
interval ~ha~ is adjusted on alternate horizontal lines by one clock signal cycle so that a delay of 682 or 683 clock signal cycles less th~ respective circu~t delays in the luminance signal path provided by the ~lter 2 15 and addex 5 is provlded.
Alteration of the length of ~he delay prov~ded by delay ltne 6 is effec~ed by ~he multiple~er~ U82 ~ U73 and clocked fl~p-flops U81~ U74 shown in Fig. 13ho These mul iplexers and flip-flops cooperate ln the same 20 manner as ~he corresponding de~ices described hereinbefore wi~h reference to the delay line 4 illustra~ed in Fig.
13f to alternately inser~ and remove ~he flip-flops from the signal path of the delay line 6. As in the case of the delay line 4, the outpu~ of the mul~iplexers U82, U73 is al~ernately switched between its inputs by the previously described control signal WA0~ Delay lines 4 ~nd 6 are synchronously clocked so that each prov~des the same leng~h of delay at the same timeO Consequentlyg ~8~

~i52~

the separated chrominance componen~ will pass through the delay line 4 wh~le the delay lines 4 and 6 each provide a first delay that corresponds to an overall delay of t for example, 682 clock signal cyclesO However, 5 the same chrominance component (now combined with the : - luminance componen~) passes through ~he.following delay line 6 a~ter the multiplexers of the delay lines have been switched so that a delay corresponding ~o an overall delay of 683 clock signal cycles is provided 10 Thus, the chxominance componen~ experiences a two line overall delay and an average delay of 682 . 5 clock ~ignal cycles rela ive to ~he luminance componen~. The luminance componen~ experiences essentially a one line overall .. . .
delay. The alteration of ~he delay provided by delay 15 line 6 by one clock cycle of ~he 10.7 M~z clock signal doe~ not introduce signlfican~ lumlnance dis~urbances in the displayed picture con~ain~ng a subst~uted, dropout compensating portion.
: As it is seen from the above descrip~ion~
the combined delays provided respectively by ilter 2, adder 5 and delay line 6 effec~ a luminance signal delay co~responding to abou~ one horizon~al line period.
Similarly, the com~ined delay~ proYlded respectively by delay line 7~ differencing circuit 3, delay lines 4 and 6 and adder 5 effec a chrominance signal delay correspond-ing to two horizontal line periods. As shown in Fig~
13h, ~he outpu~ da a from delay line 6 is applied ~o inpu~ 24 of swi~ch 1 shown in Fig. 13a. As i~ has been rj5i2l7 described previously in the specification wi~h respec~
o Fig. 8, he la~ter data represents a color tel~vision dropout compensation signal in which ~he luminance componen~ is delayed by a period of one horizon~al line and the chrominance component by ~wo horizon al line periods.
Figs. 13f and 13d show respec~ive circuit diagrams of memory address generators 8 and 9 providing address signals on memory address lines Ao to A7 and 10 A'~ ~o A'7, respectively, and wri~e and read enable con~rol signals on memory write/read lines OEl ~o 0~4 and WEl to WE4, whlch are coupled to control ~he da~a flo~ ~hrough ~he respec~ive delay lines 6 and 4. In Fig. 13d, coun~ers Ul9, U~8 and U36 are coupled to count clock cycles corresponding ~o the ac~ual delay provided by ~he delay line 4 coupled in ~he chrominance signal path, as previou~ly described wi~h respec~ to Figs. 8 and 13a to 13h. The binary outpu~ of counter U36 is coupled ~o a two bit binary decoder U44, which 20 decodes ~he two bi~ binary inpu~ signal in~o a correspond-ing four line ou~put signal. ~he four bit signal is applied to a D-type flip-10p U35 which, in turn, provides a four b~t con~rol signal on line~ OEl to OE4. Each bi~ of the latter signal is util~zed as a : 25 memory write and memory read signal ~o control ~he respective read and wri~e cycles of ~he prev~ously mentioned random access memories U26, U17, Ul, V27, U13 and U2 of ~he delay line 4 in ~ig. 13e.

I~-2 63 5 i2~L7 The memory write contxol signals are coupled to pin 20 and memory read signals to pin 1~ of each memory.
In Fig. 13f the coun~ers U72, U63 and U54 are coupl ed to co unt cl oc: k cycl es cor r e spond ing to ~he actual delay provided by delay line 5 coupled in the combined dropout compensa~lon signal path, as previously described with reference to the above-indica~ed figures.
The circuit design of the memory address genera~or 8 of Fig. 13f is similar to that of memory address genera~cor

9 of Fig. 13d. Consequently, ~he four bi~ memory write and read control signal on lines ~gl to WE4 at the ou~put of D-type flip-flop U43 in Fig. 13f is analogous to ~he above-described control si~nal OEl to ~2 f Fig. 13d and it iS u~iliæed ~o control ~he ~1rite and read cycles of random access memor i es U79, U70, U52 U80, U71 ut~lized in delay line 6 o~ Flg. 13g. The dla~rams o~ Figs. 13f and 13d reveal the memory address generators 8 and 9 in sufficient detail; consequently, no further disclosure ~hereof is ~ecessary.
As it will become apparent to ~hose skilled in the art, al~ernative embodiments similar ~o ~he disclosed de~ailed ci~cuit diagrams of FigsO 13a to 13h, as well as alterna~ive circuit elemen~s in ~hese embodlmen~s, may be ut~lized to ob~ain the disclosed operation of the dropout compensator in accordance with ~he method o the present invention. Thus, the differenc~ng circui~ 3 may be implemen~ed as a subtrac~ing circ~lt ~o which respec-~ive signals of the same polarity are appl~ed, as it is 1~ s~SZ1~7 ID-2635 known in the art. Similarly, known al~erna~ive circuit elements in the summing circuit 5 may be utilized to obtain ~he combination of ~he chromlnance and lumlnance components. As an alternative, differen~ means of ob~aining the delay in the delay lines 4 and 6 may be u~ilized, such as shift regis~ers, ins~ead of the random - access memories D Likewise, ~o ob~ain division by 3 of the samples in filter- circui~ 2, read only memories may be u~ilized instead of the disclosed circuit elements implementing ~he approximation algori~hm of equation

(10) .
Hereinbefore, examples of preferred embodimen~s of dropout compensators have been de~cribed for compensa~-ing NTSC color ~elevision siynals. As i~ wlll becom ~5 apparent to those skilled in the art, the yartOUS
embodim~n~s could be adap~ed for dropou compensation o~
o~her color ~elevision systemst such as PAL, P~L ~, etc.
For example, ~he detailed circuit diagram as shown in Figs. 13a to 13h may be utilized for PAL sys~ems with 20 the exceptlon of the respec~ive memory address genera~or circu~ts 9 and 8 for con~rolling the respec~ive delay lines 4 and 6.. The la~ter difference in ~he circuit diagrams is necessi~ated because of the dif~erence in he relationship of the chrominance subcarrier signal 25 frequency to ~he hori20n~al line frequency in NTSC and PAL sys~ems. For P~L color ~elevision signals, a three ~imes chrominance subcarr~er clock signal frequency o~
13 . 29 ~z is required in contras~ to 10 ., 7 M~z for ~TSC

~ ~ ~ S 2~7 signals. Since the horizontal line fre~uency of PAL and NTSC signals differ by less than 1 percent, the h~gher sampling fre~uency in PAL results in a higher number of clock cycles per one horizon al line pe~iod~ Consequent-ly, for PAL signals, the above-mentioned circuits 4, 6, 8 and 9 of Figs. 13a ~o 13h have to be adap~ed ts process the higher number of clock cycles per line to provide substantially ~he same amount of fixed delay as provided or NTSC signals. Fur~hermore, the clock signals indicated 10 . 7 MHz and 10.7 NHz in Figs~ 13a to 13h will be replaced by 13.3 M~z and 13.3 MHæ, respective-ly. Similar changes would have to he made in circui~
elemen~s of ~he respec~ive embodimen~s of Figs. 9 ~o 12 if ~hey are ~o ~e arranged to process P~L or o~her 15 television signal~. In addition, a samplin~ frequency tha~ is an even mul~iple of the PAL ~ o~ other ~elevision signal) color subcarrier frequency may be employed.
Figs. 14 and 15 illus~rate block diagrams of a PAL
dropout compensator in which the PAh television signal 20 is sampled at a frequency equal to four times the PAL
color subcarrier frequency, i.e., 17.72 M~z) and a fil~er circui~ 2 is used that is adapted to process such samples, such as a fll~er circui~ of tne type shown in Fig~ 6~ Since the embodimen~s of Figs. 14 and 15 are similar ~o ~hose illus~ra ed in Figs. 8 to 12, correspond-ing circui~ element in the various embodiments are iden~i~ied by corresponding reference numeral~ and only those portions of Figs~ 14 and 15 will be described _~

r'.~;;21~

which are different from the previously described embodiments.
The embodiment of Fig. 14 is useful for compen-sating both PAL and PAL-M color television s~gnals. The 5 separated chrominance component is delayed on consecutive lines by a one-line delay circuit 4 and inverted by phase inverter 40, both latter elements be7ng collpled in the separated chrominance signàl path. The delay provided by delay line 4 is equal to one horizontal line 10 period less the combined circuit delays in differencing circuit 3 and phase inverter 40. The one-line delay means 6 provides a delay equal to one horizontal line period less the combined circui~ delays provided by filter 2 and adding circuit 5. Thus, in the embodiment 15 of Fig. 14, the luminance component is delayed by es~entially one horizontal llne period and the chromi~
nance component by two horizontal lin~ periods.
In the embodiment o~ Fig~ 15, a dropout compensator circuit in accordance with the present invention ~s shown, suitable or P~L and PAL-M system applications~ The separated chrominance componen~ at the outpu~ of the differencing clrcui~ 3 is color decoded by decoder 42 into i~s u and v color components as it is known in the art. For example, if the sampling of ~he color television signal ls done precisely along the color subcarrier component axis, al~:erna~ive consecu-tive samples will represent the respactive u and v components. The latter follows from the well known i5Z17 feature of PAL and PAL~M signals, ~hat the u and v components are quadrature-modulated onto the subcarrier thus having a phase difference of exactly 90~ at all times. Conse~uently, when the sampling frequency is 5 equal to four times the color subcarr~er signal frequency and the sampling signal is in phase with the color subcarrier signal, the decoder 42 may be implemented by a simple gate for separa~ing alternative consecutive samples pertain~ng to ~he u and v componen~s, respec~ively.
10 The above-indicated decoding technique is well known in the PAh or PAL-M systems. The separated v component is then inverted by a phase inverter 44. The separated u component and inverted v componen~ are combined in adder 45, for example, by simply adding the two compon~nts u 15 and ~-v). To compensate ~or the circuit delay o~
inverter 44, a delay clrcuit ~3 is utlllzed ln the separated u signal path, coupled between the ou~put o~
decoder 42 and adder 45, to obtain the same amoun~ of delay of the u and v components in preparat~on for ~he 20 subsequent addition in adder 45. Similarly, delay circuit 41 coupled in the separa~ed luminance signal path between the output of filter 2 and input of adder 5 has a delay equal to the combined oircuit delays of elements 3, 42, 43 and 45, ~n the separated chrominance 25 signal pa~h to provide exactly the same amount of delay in the separated chrom~nance and luminance signal paths, respec~ively, in preparation for ~ubse~uent addi~ion of these components in adder 5 It follows from the foregoing ~escription that both the chrominance and luminance signal components are delayed in ~he circuit of Figc 15 b~ one horizontal line period.
The line-by-line one-quarter cycle offse~
resulting from the 90 degree phase shift occuring in the PAL subcarrier component during consecutive ~elevision lines is selectively adjusted in the PAL-type dropout compensators of the present invention when a prev~ous lO line of ~he television signal is substituted for a subsequent defective line of the television signalO
This is achieved by applying an appropriate number of clock signals to the respective delay lines 4 and 6 o~
the various embodiments, and shiftlng the b~ginning 15 of ~ach consecu~ve llne accordingly to compensate for ~he o~se-k.
To illustrat~ this, Figs. 16a and 16b re~real detailed circuit diagrams o~ respective memory address generators for utilization in the dropout compensa~or circuit of Figs. 13a o 13h as adap~ed for PAL color television signals. More pa~icularlyJ the P~L memory address generator c~rcuit lO9 shown in Fig~ 16a replaces the NTSC memory address generator g of Fig0 13d, and the : P~L circuit 108 shown in Fig. 16b replaces the NTSC
addres~ generator 8 of Fig. 13fo In Fig. 16ay a first signal Cl of frequency f~/4~ that is, one-quarter of the 15.625 k~æ P~L

horizontal sync frequencyr is received by a flip-flop ~L:~Ll$5;~ 7 ID-2635 U221. A second signal C2 o frequency fH/2, that is, one-half of ~he PAL horizontal sync frequency, is received by flip-flop U223. Bo~h signals Cl and C2 are frequency and ph~se locked to the standard PAh our 5 horizon~al llne sequence ~elevision signal received at 'cerminal 10 in Fig. 13a and they may be obtained from a conventional PAL synC processing circuit ( not shown).
The se s i gn al s ar e c l oc ked by the f l ip~ f 1 ops U 221 and U223 for noise immuni~y. The fH~4 outpu~ signal from lO flip-flop U221 i5 fed vla inverter U222 to both flip-flops U224 and U225. The la~ter flip-flops each xeceive an fE~/4 signal from flip-flop U223, which in turn, i5 clocked by a 13.3 M~z clock signal. The frequerlcy of the clock signal corresponds to three times the PAL color 15 subcarrier signal requency 4r43 ~Hz. Flip-flop~ U224 and U225 bo~,h divide th~ frequency o~ the~ signals at thelr r~spectiYe lnpu~ signals by two. Thu~, the respec~ive ou~pu~ signals of flip~flops U224 and U225 have a frequency fH~ ~, and are phase locked to each 20 o~her by the above-de5cribed operatiorl of circui'c elements .
An H-ra~e write pulse, fH, is received by a one-shot multivibra~or U226 which opera~es as a pulse s~retcher. The write pulse is modula~ed by ~he well-known 25 PAL ~/4 horizon al line sequence and ls generated by the aforemen~cioned conYen~ional PAL sync processor circuit to be f~e~uency and phase locked to signals C
and C2. The s'cretched wri~e pulse is 8~-ID~2635 received by a counter U227, which also receives the~/4 signal from flip-flop U224 and ~he 13.3 MHz clock signal. The s~retched write pulse indicated ~counter reset" is u~ilized to reset ~he counter U227 a~ the beginning of each horizontal line.
Memory address counters U229, U~30, U231 and U235 are coupled to coun~ 0 ~0 768 clock cycles a~ ~he 13.3 MHz clock signal ra~e in a well known manner to effect the generation of memory address signals A~o to 10 A17 and write and read enable signals ~1 to OE4 for use in the con~rol of random access memories of the delay line 4 shown in Fig~ 13e. A ~wo-by-four decoder U236 -~nd following clocked latches U~37~ U238 respond ~o the counters ~o provide ~he address signals and wri~e and read enable signals in the manner described hereinbe-fore for ~he comparable device~ lncluded in ~he memory addrefss generator 9 illfustra~ed in Fig~ 13d. The aforemen~oned one-quar~r subcarrier cycle llne-by-line adjus~ment is effected by coun~er U227~ The ou~pu~
signal of counter U227 is coupled via inverter U228 ~o ; : counters U229, U230 and U231 and via an additional flip-flop U233 to counter U235. The output signal of counter U227 is utilized to star ~he memory address i coun~ers a~ he beginning of each hori20ntal line.
25 Modulation of the ou~put signal of counter U227 by the fE~ signal from flip~flop U224, effects shifting of the begi~ning of each consecutlve horizon~al line to obtain the desired offse~ by one quar~er of the subcarrier , . -9.0 ~1 ~521 7 ID-2635 cycle on consecu~ive horizontal l~nes. The above-mentioned 768 clock cycles correspond to the one-line delay provided by the delay line 4 in the chrominance signal path as it has been described in detail with 5 respect ~o the block diagram of Pig. 8 and de~ailed diagram of Figs. 13a to l~h.
As it is revealed by the drawings, the memory address generator circuît 108 of Fig. 16b is similar to the above-described circuit 109 of Fig~ 16a. Both 10 pulses, the f~/4 output pulse ~rom flip-flop U225 and the counter reset pulse from U226, are applied ~
counter U227a of circuit 108. As it will become apparent from compar~ng the circuits o~ FigsO 16a and 16b, the operation of counter U227a of Fig. 16b is similar to the 15 previously descr~bed operation of counter U227 of Fig.
16a~ Consequently, c.ircuit ~08 operates in a similar manner as the previously described circuit 109. ~owever, the actual count provided by the memory address counters of Fig. 16b transferred via memory address lines Ao ~o 20 A7 to random acc~ss memories of delay line 6 shown in Fig. 13g, is different from the count provided by circuit 109. The latter difference is effected with respect to the diffeent lensth of the one-line delay 6 in the recomb~ined luminance and chrominance signal path, 25 as it has been previou~ly disclosed wîth respect to PigsO 8 and 13a to 13h. Thu~, the minor differences between the respective clrcuit diagtams of Figs. 16a and 16b reflect the above-indicated variationsD

~ zl~ ID-2635 A PAL or PAL-M chrominance subcarrier signal has an incremen~al 90 degree phase shift on consecutive lines and has an opposi~e phase on every other line~
Consequently, a PAL or PAL M siynal has an identical S phase on every four~h line. To achseve a proper phase of the dropou~ compensation signal for PAL o~ PAL-M
signalsr the separated chrominance component may be delayed by one horizontal line period and inverted on consecutive lines or, instead, ~he separated chrominance component may be decoded into u and v components and the v component subsequen~ly inverted on consecutive lines to achieve vert~cal alignment of samples of ~he dropou~
compensa~lon signal.
With re~pect to variations of ~he variou~
embodimen~s o~ ~h~ presen~ invention, it should be apparen~ ~ha~ instPad of coupling the input of the dropou~ compensator circuit 25 ~o output 14 o ~witch l, as shown in F~gs~ 12, 14 and 15 it may be coupled ~o input 11, of swltch l, similarly as shown in Fig~ 9.
Furthermo~e~ in ~he embodimen~s of ~he invention shown in Figs. 12, 14 and 15 a~ sampling frequency equal to : four times the color subcarrier frequenGy is used.
Therefore, it is advantageous ~o u~ilize ~he embodimen~
of fil~er 2 shown in F~igO 2. This advantage follow~
from the fac~ tha~ ~he filter of Fig. 2 provides a weigh~ed average sample value of ~he color ~elevlsion signal ~aken from an o~d number of samples thus elimina~ing phase displacem~nt of ~he average samples by one-half ~ 5 217 ID-2635 sampling period wi~h respec~ to the originally received samples, as it has been disclosed previously in detail.
However, the embodimen~ of fil~er 2 shown in Fig. 6, providing an average sample value taken from an even s number of consecu ive samples could be used as well.
While the invention has been shown and described with particular reference to preferred and alterna~ive embodiments thereof, it will be unders~ood tha~ vaxiations and modifications in form and details may be made 10 therein withou~ depar~ing from ~he spirit and scope of the inven~ion as defined in ~he appended cla~ms~

Claims (30)

I claim:

1. A system for providing dropout compensation of a digitally encoded composite signal having recurrent intervals of similar information content and including a periodic signal component of a known frequency equal to a non-integral rational number multiple of the frequency of said recurrent intervals, said periodic signal having a known predetermined phase during each consecutive recurrent interval and being symmetrical with respect to a signal crossing axis, the encoded composite signal comprising consecutive digital representations corresponding to discrete amplitude values thereof provided at a frequency equal to a rational number multiple of said periodic signal frequency and in a frequency and phase-locked relationship thereto, said rational number multiple frequency being greater than twice the frequency of the highest frequency component of the composite signal, said system comprising in combination:
a first means coupled to receive and store said consecutive digital representations and to successively provide an average value output signal by arithmetically combining a given number of consecutive digital representa-tions defining a zero average value of said periodic signal component;
a second means having a first input coupled to receive said consecutive digital representations of said composite signal and a second input coupled to receive said output signal of said first means to provide a difference.
signal;
1. Claim 1 (continued) a third means coupled to receive said difference signal and adjust it to have a phase corresponding to said known predetermined phase of said periodic signal component during that recurrent interval for which the dropout compensation is provided;
   a fourth means having a first input coupled to receive said phase-adjusted difference signal and a second input coupled to receive the output signal of said first means to recombine said received signals into a composite signal form;
   a fifth means coupled to provide a delay of the composite signal components for a period of time substantially equal to said recurrent interval of said composite signal and a sixth means having a first input coupled to receive said composite signal and a second input coupled to receive said delayed recombined composite signal, said sixth means responsive to a control signal to selectively provide an output composite signal from one of the signals coupled to its first and second inputs, respectively.
2. 2. The system of Claim 1 wherein said first means is coupled to arithmetically combine an integral number of consecutive digital representations defining a time interval equal to an integral number of cycles of said periodic signal component.
3. 3. The system of Claim 1 wherein said first means comprises means for weighting said consecutive digital representations in accordance with selected weighting coefficients and means for providing a weighted average value output signal by arithmetically combining a given number of said weighted consecutive digital representations defining said zero average value.
   
   4. The system of Claim 1 wherein said composite signal is a color television signal comprising a luminance and a chrominance signal component, said recurrent intervals are horizontal line intervals, said periodic signal is a color subcarrier signal representative of said chrominance signal component, said color television signal being encoded into consecutive data obtained by sampling at a clock signal frequency equal to a rational number multiple of said subcarrier signal frequency utilizing a sampling signal which is frequency and phase-locked to the subcarrier signal, and wherein:
   said first means is coupled to receive and store said consecutive data at said clock signal frequency, said average value output signal of said first means is representative of a separated luminance component, said first means providing a circuit delay equal to a known fixed number of clock signal cycles;
   said difference signal provided by said second means is representative of a separated chrominance component;
   a compensating delay means is coupled between an input of said first means and said first input of said second means to provide a delay equal to that provided by said first means;
   said third means is coupled to delay said separated chrominance component by a number of clock cycles defining substantially one horizontal line period of said color television signal;
4. Claim 4 (continued) said fourth means is coupled to receive at its first input the delayed chrominance component and at its second input the separated luminance component to recombine said received components into a composite signal form;
   said fifth means comprises additional delay means coupled to delay both said luminance and chrominance signal components of said color television signal by a number of clock cycles defining one horizontal line period of the color television signal, less a circuit delay provided by said first means; and said sixth means is coupled to receive at its first input said color television signal and at its second input said recombined color television signal having its luminance component delayed by one horizontal line period and its chrominance component delayed by two horizontal line periods relative to said received encoded color television signal.
5. 5. The system of Claim 4 wherein at least one of said second and said fourth means provides a circuit delay equal to a known fixed number of clock cycles, respectively, said third means providing a one horizontal line delay less said circuit delay provided by said second means and said fifth means provides a one horizontal line delay less combined circuit delays provided by said first and fourth means, respectively.
   
   6. A system for compensation of dropouts in a digitally encoded composite color television signal comprising a luminance component and a chrominance component, said chrominance component including a color subcarrier signal of a known frequency, the encoded color television signal comprising consecutive data corresponding to distinct amplitude values thereof, said distinct amplitude values being provided at a clock signal frequency equal to a rational number multiple of said sub carrier signal frequency, said rational number multiple frequency being greater than twice the frequency of the highest frequency component of the composite signal, and said clock signal being frequency and phase-locked to said subcarrier signal, comprising in combination:
   a signal averaging means coupled to receive said consecutive data at said clock signal frequency, to store said data for a predetermined number of clock signal cycles, and to successively provide an average value output signal by arithmetically combining a given number of consecutive data defining a zero average value of said subcarrier signal component, said average value output signal being representative of a separated luminance component;
   a signal differencing means having a first input coupled to receive said consecutive data and a second input coupled to receive said output signal of said signal averaging means for providing a difference signal representative of a separated chrominance component;
6. Claim 6 (continued) a first delay means coupled to receive said difference signal provided by said differencing means for providing a delay substantially equal to one horizontal line period of the color television signal?
   a signal recombining means having a first input coupled to receive an output signal of said first delay means and a second input coupled to receive an output signal of said signal averaging means, for combining said respectively received signals into a composite color television signal;
   a second delay means for providing a substantially one horizontal line delay of both said luminance and chrominance signal components of the color television signal; and a switching means having a first input coupled to receive said color television signal and a second input coupled to receive said recombined and delayed color television signal, said switching means responsive to a control signal to selectively provide an output color television signal from one of the signals coupled to its first and second inputs, respectively.
7. 7. The system of Claim 6, wherein said signal averaging means provides a time delay equal to a known fixed number of clock cycles, said system further comprising a third fixed compensating delay means coupled between an input of said signal averaging means and said first input of said differencing means to provide a delay equal to that provided by the signal averaging means.
8. 8. The system of Claim 6 or 7 wherein said differencing means provides a circuit delay equal to a known fixed number of clock cycles, said first delay means providing a delay equal to a number of clock cycles defining one horizontal line period less said circuit delay provided by said differencing means.
9. 9. The system of Claim 7 wherein said signal combining means provides a circuit delay equal to a known fixed number of clock cycles, said second delay means providing a delay equal to a number of clock cycles defining one horizontal line period less combined circuit delays provided by said signal averaging means and signal combining means, respectively.
10. 10. The system of Claim 6 for NTSC color television signal dropout compensation, wherein one horizontal line period is defined by a non-integral rational number of clock cycles, and wherein:
    said first and second delay means are respectively coupled to provide during consecutive horizontal line periods predetermined alternative complementary delays, each delay corresponding respectively to a higher and lower integral number of clock cycles closest to said non-integral rational number of clock cycles, said complementary delays corresponding to a total amount of delay equal to two horizontal line periods, each of said delay means providing within a given number of consecutive lines an average amount of delay equal to said non-integral number of clock cycles defining one horizontal line period.
11. 11. The system of Claim 6 for PAL or PAL-M
    color television signal dropout compensation, wherein one horizontal line period is defined by a non-integral rational number of clock cycles and the phase of said color subcarrier signal sequentially changes by equal 90 degree increments with respect to the beginning of each consecutive horizontal line interval, and wherein:
    said first and second delay means are coupled to provide respective delays each equal to a predetermined fixed integral number of clock cycles during consecutive horizontal line periods, and to provide during each horizontal line period a total delay equal to two horizontal line periods;
    wherein means are provided for repositioning in time the beginning of the delay provided during each consecutive horizontal line period by a number of clock cycles corresponding to the 90 degree phase increment of said color subcarrier signal; and wherein each of said delay means provides within a given number of consecutive lines an average amount of delay equal to said non-integral number of clock cycles defining one horizontal line period.
12. 12. The system of Claim 10 wherein: said signal averaging means provides a circuit delay equal to a known fixed number of clock cycles;
    a compensating delay means is coupled between an input of the signal averaging means and said first input of said signal differencing means to provide a delay equal to that provided by said signal averaging means; and said second delay means provides said delay diminished by the circuit delay of said signal averaging means.
13. 13. The system of Claim 11 wherein: said signal averaging means provides a circuit delay equal to a known fixed number of clock cycles;
    a compensating delay means is coupled between an input of the signal averaging means and said first input of said signal differencing means to provide a delay equal to that provided by said signal averaging means; and said second delay means provides said delay diminished by the circuit delay of said signal averaging means.
14. 14. The system of Claim 12 or 13 wherein:
    at least one of said signal differencing means and signal recombining means provides a circuit delay equal to a known fixed number of clock cycles, respectively;
    the first delay means provides said delay diminished by the circuit delay of the signal differencing means; and the second delay means provides said delay diminished by the combined circuit delays of said signal averaging means and said signal recombining means, respectively.
15. 15. The system of Claim 6 wherein said signal averaging means is coupled to arithmetically combine an integral number of consecutive digital data defining a time interval equal to an integral number of cycles of said subcarrier component.
16. 16. The system of Claim 6 wherein said averaging means comprises means for weighting said received digital data in accordance with selected weighting coefficients and means for providing a weighted average value output signal by arithmetically combining a given number of said weighted consecutive digital representations defining said zero average value.
17. 17. The system of Claim 6 wherein said input said signal averaging means is coupled to an output of said switching means.
18. 18. The system of Claim 6 wherein said input of said signal averaging means is coupled to the first input of said switching means.
19. 19. The system of Claim 17 or 18 wherein said second delay means is coupled in the color television signal path between an output of said signal recombining means and said second input of said switching means.
20. 20. The system of Claim 17 or 18 wherein said second delay means is coupled in the color television signal path connecting said switching means to said input of said signal averaging means.
21. 21. The system of Claim 17 or 18 wherein one said second delay means is coupled in the separated luminance signal path between an output of said averaging means and said second input of said signal recombining means, and another second delay means is coupled in the separated chrominance signal path between an output of said signal differencing means and said first input of said signal recombining means.
22. 22. In a system for providing dropout compensation for a digitally encoded composite color television signal comprising a luminance component and a chrominance component, said chrominance component including a color subcarrier signal of a frequency equal to a non-integral rational number multiple of the horizontal line frequency, said subcarrier signal having a known predetermined phase during each consecutive horizontal line interval of said color television signal, said color television signal being encoded into consecutive digital data by sampling at a frequency equal to an even integral multiple of the subcarrier component frequency, said even integral multiple frequency being greater than twice the frequency of the highest frequency component of the composite signal, the combination comprising:
    a signal averaging means coupled to receive said consecutive digital data and to store said data for a predetermined number of clock cycles to successively provide an average value output signal by arithmetically combining a given number selected ones of consecutive data defining a zero average value of said subcarrier component, said average value output signal being representative of a separated luminance component;
    a signal differencing means having a first input coupled to receive said consecutive data and a second input coupled to receive said output signal of said signal averaging means for providing a difference signal representative of a separated chrominance component;
    
    a phase adjusting means coupled to receive said difference signal to adjust its phase to correspond to said known predetermined subcarrier signal phase during the consecutive horizontal line intervals during which the dropout compensation is provided;
    a signal recombining means having a first input coupled to receive said phase-adjusted difference signal and a second input coupled to receive the output signal of said signal averaging means for recombining said respectively received signals into a composite color television signal;
    a delay means coupled to provide a substantially one horizontal line delay of both said luminance and chrominance signal components of said color television signal; and a switching means having a first input coupled to receive said color television signal and a second input coupled to receive said recombined and delayed color television signal, said switching means responsive to a control signal to selectively provide an output signal corresponding to one of the signals coupled to its first and second inputs, respectively.
23. 23. The system of Claim 22 wherein said signal averaging means comprises means for weighting said consecutive data in accordance with selected weighting coefficients and means for providing a weighted average value output signal by arithmetically combining a given odd integral number of selected ones of the weighted consecutive data defining said zero average value, each said weighted average value output signal provided by said signal averaging means corresponding to a data occurring in the middle of each said selected ones of consecutive data taken for averaging.
24. 24. The system of Claim 22 wherein said input of said averaging means is coupled to an output of said switching means.
25. 25. A digital color television signal dropout compensator suitable for use in NTSC, PAL or PAL-M systems, said signal represented by consecutive data obtained by sampling at a clock signal frequency equal to an integral multiple of the color subcarrier signal frequency, said integral multiple frequency being greater than twice the frequency of the highest frequency component of the color television signal comprising in combination:
    a register means for receiving and storing said consecutive data in synchronism with said clock signal frequency;
    a signal averaging means coupled to said register means for successively providing an average data value by arithmetically combining an integral number of consecutive data defining an integral number of subcarrier cycles to obtain an output signal representative of a separated luminance component, said averaging means providing a circuit delay equal to a known number of clock cycles;
    a signal differencing means having a first input coupled to receive said consecutive data and a second input coupled to receive the output signal of said averaging means to provide a difference signal representative of a separated chrominance component, said differencing means providing a circuit delay equal to a known number of clock cycles;
    a first delay means coupled between an input of said signal averaging means and said first input of the differencing means to provide a delay equal to that provided by the signal averaging means;
    
    a second delay means coupled to receive said difference signal for providing a delay equal to a number of clock cycles defining one horizontal line period of the color television signal less the circuit delay provided by said differencing means;
    a signal combining means having a first input coupled to receive an output signal of said second delay means and a second input coupled to receive an output signal of said signal averaging means, for recombining said respectively received signals into a composite color television signal, said combining means providing a circuit delay equal to a known number of clock cycles;
    a third delay means coupled to provide a delay of both said luminance and chrominance component of said color television signal, said delay corresponding to a number of clock cycles defining one horizontal line period less combined circuit delays provided by said averaging and combining means, respectively; and a switching means having a first input coupled to receive said color television signal and a second input coupled to receive said recombined and delayed color television signal, said switching means responsive to a control signal to selectively provide an output color television signal from one of the signals coupled to its first and second inputs, respectively.
26. 26. A digital color television signal dropout compensator circuit suitable for use in NTSC, PAL, or PAL-M, systems, where the television signal is encoded into consecutive digital data by sampling at a frequency equal to three times the color subcarrier signal frequency, comprising:
    means coupled to receive said consecutive data and to provide an average value output signal by continuously combining three consecutive data defining one subcarrier signal cycle, said average output signal corresponding to a separated luminance component;
    means coupled to provide a difference signal of said color television signal and said average value output signal, said difference signal corresponding to a separated chrominance component;
    means coupled to delay said difference signal by substantially one horizontal line period of the color television signal to provide a one line delayed chrominance component;
    means coupled to combine said average value output signal and said delayed difference signal into a composite color television signal form;
    
    means coupled to delay both the chrominance and luminance component of the color television signal processed by said circuit by substantially one horizontal line period to provide a dropout compensation signal having its luminance component delayed by one horizontal line period and its chrominance component by two horizontal line periods; and means having separate respective inputs coupled to receive said color television signal and said dropout compensation signal respectively, said means being responsive to a control signal to selectively provide an output signal corresponding to one of its input signals.
27. 27. A digital color television dropout compensation circuit suitable for use in NTSC, PAL or PAL-M systems, wherein the television signal comprises a color subcarrier component having a known predetermined phase with respect to the beginning of each consecutive horizontal line interval and wherein the television signal is encoded into consecutive digital data by sampling at a frequency equal to four times the color subcarrier signal frequency, comprising:
    means coupled to receive said consecutive data and to provide a weighted average value output signal by continuously combining three alternate ones of five consecutive data with the first and fifth data weighted by a factor of one-half and the third data unweighted, respectively, said weighted average value output signal corresponding to a separated luminance component;
    means coupled to provide a difference signal of said color television signal and said weighted average value output signal, said difference signal corresponding to a separated chrominance component;
    
    means coupled to adjust said difference signal to have its phase corresponding to said known predetermined subcarrier signal phase with respect to the beginning of that horizontal line interval for which the dropout compensation is provided, to provide a phase-adjusted chrominance component;
    means coupled to combine said phase-adjusted difference signal and said weighted average value output signal into a composite color television signal form;
    means coupled to delay both the chrominance and luminance component of the color television signal processed by said circuit by substantially one horizontal line period to provide a dropout compensation signal;
    and means having separated respective inputs coupled to receive said color television signal and said dropout compensation signal, respectively, said means being responsive to a control signal to selectively provide an output signal corresponding to one of its input signals.
28. 28. A system for processing a digital signal representing a composite signal having recurrent intervals of similar information to replace deficient portions of the composite signal with similar information from different recurrent intervals, said composite signal including a signal component of a known frequency equal to a non-integral rational number multiple of the frequency of said recurrent intervals and having a known nominal phase during each recurrent interval, the digital signal comprising consecutive digital value representations at a frequency equal to a rational number multiple of said known frequency and in a frequency and phase locked relationship to said signal component, said rational number multiple frequency being greater than two times said known frequency, comprising:
    first means responsive to a clock signal in synchronism with said rational number multiple frequency for receiving at an input each of said consecutive digital value representations and arithmetically combining said each digital value representation with a selected number of other selected ones of said received digital value representations to generate in place of said each received digital value representation a further digital value representation of the average of the values of said arithmetically combined digital value representations that is productive of a zero average of a portion of said arithmetically combined digital value representation corresponding to said signal component of a known frequency;
    
    second means coupled to receive said consecutive digital value representations of said composite signal and said further digital value representation generated by said first means to provide a digital difference value representation of the difference between each received digital value representation and each further digital value representation generated in place of said each received digital value representation;
    third means coupled to receive said digital difference value representation for adjusting its phase to correspond to the nominal phase of the signal component during the recurrent interval to be replaced by a dropout compensation composite signal including said digital difference value representation;
    fourth means coupled to receive each phase-adjusted digital difference value representation and each further digital value representation to combine the received representations to form the dropout compensation composite signal at an output;
    fifth means coupled in circuit with said first, second, third and fourth means between said input and output for delaying the representations forming said dropout compensation composite signal for an interval substantially equal to the recurrent interval of said composite signal;
    and sixth means coupled to receive said digital signal and the delayed dropout compensation composite signal and responsive to a control signal indicative of the occurrence of deficient portions in the composite signal to selectively provide at an output one of said received signals, said sixth means responsive to said control signal to provide the delayed dropout compensation composite signal at said output when said control signal is indicative of the occurrence of a deficient portion and to provide said digital signal at said output in the absence of said control signal being indicative of the occurrence of a deficient portion.
29. 29. The system according to Claim 28 wherein the fifth means for delaying the representations forming the dropout compensation composite signal is coupled to receive and delay the dropout compensation composite signal provided by the fourth means.
30. 30. The system according to Claim 28 wherein the composite signal is a color television signal and the signal component of known frequency is a color subcarrier component including a color burst synchronizing portion occurring at the beginning of each recurrent interval at the nominal phase, the third means for adjusting the phase of the digital difference value representation is a first adjustable delay means for delaying the digital difference value representation for an interval substantially equal to one recurrent interval of the color television signal relative to the occurrence at the input of the first means of the portion of the color television signal from which the delayed digital difference value representation was obtained, the fifth means for delaying the representations forming the dropout composite signal is a second adjustable delay means, and said first and second adjustable delay means responsive to said clock signal in synchronism with said rational multiple frequency for synchronously adjusting the delay provided by each of the delay means during alternate recurrent intervals by an interval equal to one clock signal cycle.