CA1155569A - High speed modem suitable for operating with a switched network - Google Patents

Abstract

Abstract:

A high speed modem suitable for operating with a switched network and capable of achieving essentially 9600 bit per second information transfer rate through the switched tele-phone network. The high bit rate is achieved notwithstanding the variations in the characteristics of the switched tele-phone network by phase and amplitude modulating a plurality of sub-carriers at a relatively low baud rate. Correlation detection is employed at the receiver to extract or demodulate the information contained in the various sub-carriers. To allow correlation detection with orthogonal signals, each of the sub-carriers is harmonically related to a fundamental which fundamental is, however, slightly higher than the baud rate. This allows the receiver to delay correlation for a "gap" time, which reduces the effect of transients produced by modulation and also provides greater tolerance to inter-symbol distortion. Since the fundamental of all the sub-carriers is higher than the baud rate, the receiver "sees"
orthogonal signals during the integration or correlation time which is maintained as the period of the fundamental.
In addition to the information sub-carriers, a pair of un-modulated sub-carriers are also transmitted to enable the receiver to maintain the correlation interval in proper syn-chronization with the transmitter, and to correct for phase distortion and frequency offset.

Description

High speed modem suitable for This invention relates to information transmission over a switched network such as the telephone network. The conjunction of relatively high bit rate and relatively 1QW
baud rate, resulting in improved noise burst tolerance, makes use of the invention advantageous on non-switched networks as well.
Increasing demand for information transfer has made it desirable to employ the e~isting telephone network for this purpose. The telephone network makes available a variety of grades of services, and it is obviously desirable to employ the lowest graae, and therefore, the most inex-pensive, service, as is consistent with acceptable bit error rates.

The typical commun~ication medium made available by the telephone network is an analog channel; accordingly, the need to transfer information which is digital in form has led to the development of devices to convert digital data into a signal that will propagate on an analog channel, and to correctly convert this signal back into digital form.
, .
Devices of this sort have been available for some time, and are characterized as "modems", shorthand for modulator-demodulator. Stated in the simplest terms, the goal of the modem is to adapt the digital signals to the charac-~' ~.

1 ~5~9-- 2 --teristics of the available transmission medium, i.e., the phone channel. Phone channels come in at least two dif-ferent types, i.e., leased and switched. The leased channels have characteristics which are maintained -to within speci-fied limits. The switched channel, on the other hand, has properties which vary rom channel to channel, and are usually characterized by their mean and standard deviation.

The most popular prior art modems can be characterized as high baud rate modems. Generally, these modems require rather precise time equalization to compensate for the telephone channels envelope delay distortion. This par-ticular type of distortion, which comes about because the phase delay encountered by signals of different frequencies is dif~erent, is extremely troublesome. $his is particu-larly so since the envelope delay distortion will ~ary for different lines in the switched network, and thus, the various parameters of the equa}ization networ~s cannDt be standardized. Rather, these networks must adapt or "learn" proper parameters through actual use. Since most adaptive equalizers require special training signals, the learning process cannot take place during the transmission o real data. Accordingly, the duration of the training period reduces the time available for transmission of ac-tual data. Since the physical channel actually used from call to call will be di~ferent in a switched network, the equalization may require adjustment on each different con-nection. See, for example~ "Modems" by Davey, in Proc.
IEEEj November 1972, pages 1284 92.

There have been suggestions in the prior art to implement modems which transmit a plurality of bits per signalling element or baud. With multi-bit bauds, the baud rate, which is the rate at which different bauds are transmitted, can be reduced, resulting in a lower baud rate than bit rate. Some examples are Ito, U.S. Patent 3,349,182;
Walker, U.S~ Patent 3,456,194; Haubex, U.S. Patent 3,579,110;
Low, U.S. Patent 3,659,053i Walker, U.S. Patent 3,431,143.

1 ~l555~9 While these systems can reduce the baud rate for a given bit rate, they are not directed at using the switched tele-phone networ~ as a communication channel, and therefore, do not address the problems caused by envelope delay dis-tortion.

Several of the suggestions referred to above employ a plurality of sub-carriers, modulating each sub-carrier to increase the bit rate without increasing the baud rate.
The suggestions also employ correlation detection, that is, each diferent sub-carrier is separately detected by use of a locally genera~ed noise free replica of the sub-carrier.

In more detail, Whang (U.S. Patent 3,524,023) indicates that a significant problem with respect to data transmission over the switched telephone net~ork is the variation in line characteristics that are expected. One solution to the problem was equalization, i.e., an ef~ort to ~Ismooth~
the line characteristics by compensating for distortions in the time domain~ Unfortunately, the best equalizers take a significant amount o time to determine the proper equalization for each line. Since equalization is required on each different connection, the time required far equali-zation is a substantial disadvantage and efforts are going forward to reduce this timej see IEEE Transactions on Communications, Vol. COM-26 #5 (May 1978).

Whang, in U.S. Patent 3,524,023, taught a different technique, i.e., instead of attempting to employ as much of the avail-able bandwidth as possible, and running into severe equali-zation requirements, he suggested employing a relatively small portion of the available bandwidth, e.g., about 1/3.
With thls technique, variable equalization was not required since, in the chosen third of the bandwidth, all the tele-phone lines appear substantially similar. The disadvan-tage to the ~hang approach is, of course, the two-thirds of the available bandwidth that are discarded. Accordingly, Whang claimed the capability of transmitting at a rate of 2400 bits per second thxough the switched telephone network, which at the time, was considered a radical advance.

Walker, in U.S. Patent 3,456,194, took a different approach to data transmission although not related to switched networks as a communication media. Instead of discarding two-thirds of the avallable bandwidth, he attempted to em-ploy as much of the available bandwidth as possible, and instead employed a gap or guard space in his regime.
More particularly, to provide a large bit/baud ratio, a plurality of sub-carriers are each modulated. To allow coherent demodulation, the sub-carriers are harmonically related. The modulated sub-carriers are transmitted for a time termed the symbol time and modulation is effected at a rate corresponding to the symbol timeO Walker proposed coherent demodulation, and used a guard space, or gap to reduce intersymbol distortion. In effect, the demodula-tion process operated for less than the entire symbol time, the difference being the gap or guard space. ~owever, since Walker chose the fundamental as the symbol rate, i.e., the symbol interval was equal to the period of the funda-mental, the demodulation took place for an interval which was less than the period of the fundamental. Accordingly, Walker's demodulation took place with non-orthogonal si~-nals, i.e., he could and did expect distortion caused by a contribution in one channel or sub-carrier, from other chan-nels or sub-carriers. To attempt to overcome this diffi-culty, he attempted to precalculate the contribution in each channel, from all other channels, and Ucompensate" for this contribution by using a weighting network. The diffi-culty with this technique is that the precalculations neces-sary to determine the weightings require knowledge of the characteristics of the transmission medium. Since Walker is disclosed in the context of a radiated transmission, the approach may be workable. However, employing the Walker technique in the switched telephone network does not appear advantageous since it is the very variations in the charac-teristics of the communication medium which made use of the switched telephone network difficult in the first place.
Therefore, it would appear that applying the Walker tech-nique to data transmission over the switched network would not be appropriate since the weightings will properly apply to only nominal lines which, in the context of the switched network, are usually not available.

However, Walker appears to have an advantage over ~hang in that Walker merely discards a portion of the available time bandwidth product e~ual to the ratio of the gap time or guard space to the symbol time whereas ~hang employs only about one-third of the available time banclwidth product.

In accordance with the teachings of the present invention, the disadvantages inherent in Walker are obviated while at the same time, retaining the advantage of employing much more of the time bandwidth product than used by Whang.

It is therefoxe one object o the invention to provide a transmission system capable of reliably transmitting 9600 bits per second over an unconditioned line in the switched telephone network It is another object of the invention to perform the foregoing without requiring automatic or variable time equalization as in many prior art modems.
It is another object o~ the invention to achieve the fore-going data transmission rates with acceptable bit error rates and with equipment of reasonable cost, size, etc.
It is yet another object of the invention to achieve the foregoing and other objects by using a modem which is readily interfaced with conventional data terminal equipment.

The present invention overcomes the disadvantages mentioned above by employing several novel techniques providing a high bit rate, low baud rate modem, capable of transmitting 9600 bits per second over the switched telephone network with acceptable bit error rates.

The modem of the invention provides for plural frequency division multiplexed communlcation channels. Each channel comprising a different sub-carrier, is modulated at a common rate for the transmission of a multi-bit baud per signal-1 1 55~69 6 --ling interval or baud time. Demodulation employs correla-tion detection in which the received signal is separately correlated with a noise-free replica of each of the sub-carriers. Based on the results of the correlation process, the demodulator detec~s the modulating intelligence and provides corresponding outputs. Each sub-carrier is a har-monic of a fundamental. To reduce errors caused hy noise bursts, the baud time is made relatively long to the extent that typical noise bursts are a small fraction of the baud time, for example, the baud time may correspond to a sig-nalling or baud rate of about 60/sec., as compared to typical prior art baud rates of 1600 or 2400/sec. This allows the fundamental to be on the order ot 60 Hz. How-ever, the passband characteristics of the telephone net-work preclude use of the fundamental or the very low har-monics as sub-carriers.

To minimize the effects of intersymbol distortion, the de-modulator is arranged ~o ignore the received signal for a port-on of the baud time near the beginning, thus creating a yap or guard time in the time sequence of demodulator operation. To maintain the orthogonality of the signals being correlated, the time duriny which correlation takes place, (i.e., the correlation timej is selected as the period of the fundamental. Thus, hy selection, each sub-carrier has an integral number of cycles in the correlation time. To account for the gap or guard time, the baud time is increased beyond the correlation time by the amount of the gap or guard time.

To increase the bit rate, for given baud rate and number of channels, we prefer to modulate each sub-carrier with the equivalent of a multi-bit quantity. To do this, we use a combination of amplitude and phase modulation, although it is within the scope of the inve.ntion to use amplitude and phase modulation combinations different from those disclosed herein or to use amplitude or phase modulation to the ex-clusion of phase or amplitude modulation.

1 ~55~9 Thus, in accordance with the invention, an information trans-mission system includes means for synchronously generating a plurality of information sub-carriers, each of the infor-mation sub-carriers harmonicall~ related to a fundamental fO, means are provided for assembling the information for trans-mission into a plurality of separate information groups, equal in number to the number of information sub-carriers, means are provided for modulating each information sub-caxrier with a different one of the information gxoups, and means are provided for transmitting the modu}ated information sub-carriers for a period Tb, i.e., the signalling interval, wherein the signalling interval is greater than the period To of the fundamental fO.

Preferred embodLments of the invention employ digital techniques for the generation of the sub-carriers, modula-tion, transmission, and demodulation thereof.

At the modulator, a pair of shift registers are employed, one with a stage for maintaining phase representation for each of the sub-carriers, the other with an equal number of stages for storing an amplitude representatio~ for each of the sub-carriers. Generation of the sub-carriers is digi-tally simulated by updating the phase of each sub-carrier as a function of time and generating a sample of each sub-carrier at the time its phase is updated. Modulation is effected once per baud time for all sub-carriers by changing the stored amplitude and phase for each sub-carrier in ac-cordance with the modulating intelligence. Thus, during each baud time, plural samples of each of the sub-carriers are generated. A single sample for each sub-carrier is coupled to an accumulator once in each sampling interval, and the sum of samples from each sub-carrier is transmitted.
In each baud time, there are a number of sampling intervals and during each the modulator transmits the sum of a sample from each of the sub-carriers.

L 1 5 ~ ~9 The descrihed shift register implementation wh ch leads to sequential updating of all sub-carrier phases in the order of the sampling intervals is not essential to the invention.
If there are m sampling intervals and n sub-carriers, and we denote 0xy as a sub-carrier phase, where x represents sample interval and y represents sub-carrier, then the shift register implementation produces ~ 012~ 013~ 01n' ~21' 022' 02n' 0ml' 0m2' 0mn' in time sequence. This implementation reduces the required storage for it only requires n storage locations, one for the up-dated phase of each of n sub-carriers. On the other hand, with increased s~orage, all the samples for all sub-carriers can be generated and stored in any desirable order. One desirable order of generating sub-carrier phases is to genexate 011' 021' 031' ~ml' 012' 022' 0m2 t and so on, i.e., generate all samples for a given sub-carrier and then proceed to the next sub-carrier and so on. Once all samples of all sub-carriers are available, they can be read out in the desired order, i.e., 11~ 01~ 013~ . .
01~/ 021~ 02n'' ~ml~ mn- ~ readout, the trigonometric function Aysin(wyt ~ 0y)1y~l is derived and in each sampling interval the sum of all trigonometric functions y~n ~ysin(wyt ~ 0y) is produced and transmitted.
y=l As should be apparent, the sequence and technique used for generating sub-carrier samples are numerous. One technique, not yet mentioned, which has the advantage of reducing com-putational load in generating su~-carrier samples is the FFT.
At the demodulator, the phase and amplitude of each of the subcarriers must be detected in order to determine the trans-mitted intelligence. In addition, the frequency and phase of each of the locally generated sub-carriers must be main-tained coherent (of like frequency and phase) with those generated at the modulator. To do this, compensation must be provided for phase distortion, frequency offset and am-plitude distortion all of which are functions of both time and frequency. To minimize inter-channel and inter-baud distortion, the correlation interval must be maintained with 1 ~555~9 g ~he proper relation to the baud time boundaries. To assist in these functions, the modulator transmits a pair of un-modulated sub-carriers, also called timing channels, the relation between which, as detected at the demodulator, is employed to provide for some o the compensation. In addi-tion, the relation between timing channel phase in adjacent baud times is employed to correct for frequency offset.

In more detaill demodulation of each of the information sub-carriers is made up of an AGC function, a correlation func-tion and a decision function. the AGC function is used to insure that the amplitude range of the received signal is within proper limits to effectively convert the received signal to a digital representation regardless of gain changes in the transmission medium~ A further benefit of AGC is to malntain digital sample word size within proper limits to preclude overflow in later processing such as in the later to be mentioned multiplier.

The correlation process is implemented by generating a corresponding sub-carrier for each of the information sub-carriers (as well as for each timing channel). For the present, we will assume that phase and frequency compensa-tion for telephone line distortion has been achieved, the manner in which this is achieved is explained later.

At the beginning of the correlation time, a process of sampling and digitizing the received signal is begun.
Samples are taken and digitizad on a periodic basis under control of a system clock. Simultaneously, each of the plurality of locally generated sub-carriers are sampled, once per received signal sample. Each received sample is multiplied by each sub-carrier sample. A memory is provided to store the product. On the next sample of the received signal, the process is repeated except that the product of each multiplication is added to the product of the prior multiplication for the same sub-carrier. The process con-tinues until each received signal sample is muLtiplied and a sum of products is produced for each sub-carrier.

~ 1~55~9 Actually, each sub-carrier is used to generate quadrature representations of the sub-carrier and both are correlated with the received signal. Accordingly, pairs of summed products are produced for each sub-carrier. Each pair rep-resents a vector, from the direction and amplitude of the vector the modulating intelligence can be recoveredO

The decision process employs the vector representating signals to produce the transmitted data. The decision process also determines the relationship between each vec-tor with the ideal or expected vector. Variations are treated as amplitude and phase distortions and compensation for the distortion in each channel is effected separately. This compensation has an effect similar to equali~ation. A
prime advantage of the invention is that this "equalization"
is driven by real data - and not be training or test signals.

The correlation process also produces vector representation or the timing channels as weI10 These are employed in the decision process to maintain the proper phase and frequency relation between the locall~ generated sub-carriers and those generated at the modulator.

In a preferred embodiment of the invention, adjacent harmonics are used as timing channels and preferably, the timing chan-nels are located at or near the center of the frequency spectrum used. The beginning of the correlation interval is marked by appropriately adjusting the phases of the timing channels to have a predetermined relationship. For example, the one timing channel is produced with a predetermined phase and the other timing channel is maintained to have identical phase. Accordingly, at the demodulator, a proper correlation interval is one in which the vectors produced by the correlation process on the timing channels have iden-tical phase. To the extent that the vectors do not have identical phase, the correlation interval must be "moved"
and the direction of the necessary movement is determined by the vector phase difference.

5 ~ 9 The telephone line also may subject the transmitted signals to frequency offsets, which is common throughout the sub-carriers. _Freqeuncy offset is detected by comparing vec-tors of one of the timiny channels in adjacent baud times.
Changing phase represents frequency offset, the airection of phase change indicates the sign of the offset and the mag-nitude of the phase change represents the magnitude of the offset. Detection of frequency offset produces a compensa-tion at the demodulator by controlling the rate at which the sub-carrier phase is advanced for all sub--carriers. Al-ternatively, a measure of the detected frequency offset or incremental offset can be fed back to the modulator for compensation at the modulator.

The present invention can be used as a direct or differential phase modulator. For direct phase modulation, the trans-mitted phase differs from a reference or absolute phase by the modulating signal. Thus, a reference phase is required.
The timing channel can be used as such a reference, but since the baud time is not the fundamental period, sub-carrier phase at the modulator must be continually adjusted to the reference phase. Differential phase modulation relies on the previous phase as the reference and so no ad~ustments of modulator phase are required. At the demodulator, however, the sub-carriers' phase must continually track the modulators.
Accordingly, at the conclusion of each correlation interval, each sub-carrier phase is advanced to ensure demodulator phase tracks modulator phase.

The present invention will now be described in further detaiL
when taken in conjunction with the attached drawings in which:

Figure lA is a functional diagram of the modem processes;

Figure lB is a frequency spectrum of the umodulated sub-carriers, each corresponding to a channel;

Figure lC is a timing diagram correlating modulator symbol interval with the gap or guard time and correlation interval ~ 1~5~9 at the demodulator;

Figure 2 illustrates the data encoding;

Figure 3A is a block diagram of components of the modulator;

Figure 3B is a detailed timing diagram of a typical baud time;

Figure 3C illustrates the modulator clock;

Figure 3D iLlustrates the synchronization technique used to mark the correlation interval at the modulator;

Figure 3E illustrates phase changes effected at the modulator;

Figure 4 is a demodulator block diagram;

Figure 5 is a detailed block diagram of the demodulatox sub-carrier generator;

Figur~ 6 is a detailed block diagram of the correlator;

Figure 7 .is a detailed block diagram of the decision unit;

Figure 8 illustrates the decision regions implemented at the decision unit;
-Figure 9 illustrates the frequency offset detection technique;

Figure 10 is a block diagram of the demodulator clock; and Figure 11 illustrates the correction logic of Figure 7.

Before describing the apparatus, it is worthwhile to under-stand the ~unctions performed. Reference i5 made to Figures lA through lC, wherein Figure lA represents the functions performed, Figure lB is a frequency spectrum illustrating the relation between the suitable sub-carriers, and Figure lC is l ~ ~?5~

a timing diagrc~m correlating the baud time of the modulator with the correlation interval established at the demodulator.

.
More particularly, as sho~n in Figure lA, the data to be transmitted is first assembled at function 30. The data is in digital form and can be accepted in serial form. Simul-taneously, a plurality of suitable sub-carriers are genera-tPd at function 31. Figure lB illustrates the relation be-tween the sub-carriers where sub-carriers at frequencies f to fn corresponding to n channels are illustrated. The frequency difference between adjacent sub-carriers is the fun-damental fO ~shown dotted~; constraints imposed by the band-pass of the telephone network dictate the absolute frequencies employed~ The ~undamental f~ is shown dotted since it is not a sub carrier. The distance between fO and fl, the lowest sub-carrier, is representative of the fact that the lowest harmonics are also not used as sub-carriers. Typical sub-carriers are in the range of 500 Hz to about 2.5 k~z. for use with the telephone network. ~ub-carriers of different fre-quency ranges could be used with othex networks depending on the available pass band.

Actually, the generation of the sub-carriers is, in the preferred embodiment, accomplished digitally. Accordingly, only samples of the sub-carriers are produced. Nevertheless, it ls within the scope of the invention to generate continuous sub-carriers and modulate them as explained below.

Figure lC illustrates the baud time, i.e., Tb. The baud rate is fB ~ l/Tb. At the demodulator, the correlation time, i.e., the time during which the received signal is operated on to detect the modulation impressed by the ~rans-mitter, is the interval To which is the period of the funda-mental fO. The difference between the baud time and the cor-relation interval is the gap time Tg. During the gap time, the demodulator ignores the received signal, accordingly switching transients and inter-symbol distortion is reduced.
For reasonable distances between modulator and demodulator, a gap time of l ms is sufficient. However, this may be 1 1~5~9 increased or decreased by changing baud ~ime or fundamental frequency. ~ith a 1 ms gap time and a baud rate of 60/sec.
the fundamental is about 64 Hz.

Returning now to Figure lA, the serial data assembled at the function 30 is coupled to the modulator on a timed basis, i.e., once per baud time, as shown diagrammatically by the AND gate and enabling waveform. Thus, once per baud time, the data modulates the associated sub-carriers, function 39.
Once the modulation has been effected, i.e., the phase and/or amplitude has been selected~ the sub-carriers are generated for the remaining portion of the baud time.

The baud time is broken down into a plurality of sampling intervals. Once per sampling interval each sub-carrier is sampled and the sample passed to an adder. When all sub-carriers have been sampled and accumulated, function 32, the sum is placed on the switched network. A new sampling in-terval is begun and the process is repeated. For n sub-carriers, each is represented by a phase 0~y where x repre-sents sub-carrier (from 1 to n~, y represents sample number tfrom 1 to m). In each sampling interval 01 to ~n is de-termined and trigonometric function Axsin(w~t ~ ~x) is pro-duced for each sub-carrier (1 ~ x ~ n) and x ~ n ~xsin(wxt ~ 0x) is determined. The process is repeated or each sampling interval throughout the baud time.

At the receiver, automatic gain control is provided at func-tion 33. ~ switch 34 is symbolically shown coupling the out-put of the gain controlled received signal to the correla-tor which is representated at function 35. The switch is referred to as symbolic for reasons which will now be ex-plained.

~s explained in connection with Figure lC, the correlation interval To is less than the baud time, and it is the opera-tion of symbolic switch 34 which establishes this difference.
The correlation function 35 correlates samples of the received 1 ~5~9 slgnal with the locally generated sub-carriers generated in function 36~ Each sub-carrier has a corresponding locally generated sub-carrier at the demodulator. The correlation of the unmodulated timing channels with the corresponding sub-carriers is monitored by the timing function 37 which adjusts the corresponding sub-carrier generator to maintain a desired correlation interval. Finally, the correlation of the modulated sub-carriers and their corresponding sub carriers are monitored by ~he decision unit a~ function 38 which produces the data output.

Function 36 may generate sub-carriers in any suitable manner, i.e., in analog or digital fashion. The received signal may be A~D converted and provided to the correlator as a sequence of samples, i.e., Ry¦yY_ml where y identifies the sample.
Samples of each sub-carrier are required for each sample of the received signal. Digital generation of the required sub-carrier samples can be effected by storing a phase represen-tation for each sub-carrier and updating the representation for each sub-carrier at the proper ratè. In this fashion, a series o phase representations 0xy is generated (where x represents sub-carrier index from 1 to n and y represents sample number from l to m). Since the signal is received and sampled in real time, the phase representations 0xy can also be generated in real time using a similar shift register technique to that which may be used at the modulator. Name-ly, ~ 021~ ~31 through 0nl is produced within one sampling interval. For each phase representation, the trigonometric function sin ~ and cos 0 is produced. Each of the trigono-metric representations is multiplied by the sample of the received signal generating a series of products Rl sin 0xl and Rl cos 0xl as x goes from l to n. In the next sampling interval, a similar series of products R2 sin 02x~ R2 cos 02x is generated as x goes from 1 to n.

Corresponding products are added, giving a pair of sums y=2 y-2 ~ Ry sin 0y and ~ ~y cos 0y for each sub-carrier. This 1 ;~55$~9 process repeats for each sampling interval so at the con-clusion a pair of sums y=m y=m ~ Ry sin 0y and y~l Y Y
are produced for each sub carrier. The pair of sumsy=m y=m ~ Ry sin 0y and ~ Ry cos 0y for each sub-carrier represents a vector rom which the modulating intelligence can be recovered~ The decision process 38 operates on each vector and, from its amplitude and phase determines the modu-lating intelligence. The decision process also operates on the correlation result of the timing channels to determine the phase relationship of the timing channels and the phase relationship between one of the timing channel phases in adjacent baud times.

From the preceding brief description of the invention, those skilled in the art will readily appreciate that the invention can be implemented with discrete circuits or can be imple-mented almost wholly within a microprocessor or similar de-vice having the capability of responding to a stored program.
Typically, the units will be packaged so that each location has a modulator and demodulator. The remaining portion of the description will disclose a preferred embodiment of the invention in which the modulator comprises a discrete circuit embodiment and demodulator in which the correlator lS
pro~ided by discrete logic and the decision function is implemented by a special purpose stored program processor.

The modulator is shown in Figure 3A and accepts data in the form of 160 bit groups for each baud time. The 160 bits represent 32 in~ormation groups or characters, each consis-tins of 5 bits. Each character modulates in terms of ampli-tude and phase change, one of the information sub-carriers.
Since there are 32 characters per baud time, 32 inormation sub-carriers are provided. It will be understood that the number of sub-carriers, and the number of bits used to modu-late each, may be varied from the quantities mentioned herein.

1 155~9 The 5 bit character is represented by 1 of 32 possible amplitude and phase change combinations; the selected am-plitude and phase change, corresponding to any character, is derived from a read only memory which stores a table of all possible characters and the corresponding amplitude and phase changes. When digital values corresponding to the desixed phase change and amplitude are read out of the read only memory storing them, the data is applied to ~he corres-ponding sub-carxier generator.

Figure 2 illustrates the 32 characters (each represented by a pentagon~ wherein the coordinates of the character (x, y) satisfy the relation x = A cos (~) and y = A sin (~, where A and ~ correspond to the modulation.

As shown in Figure 2, the character coordinates are symmet-rically located with 8 characters in each quadrant. For example, the 8 characters in the first quadrant are located at (1, 1~, (3, 1), (5, 1), (1, 3), (3, 3), (5, 3), (1, 5) and (3, 5~. It will be appreciated that this character en-coding is regular in form. This simplifies the decision unit which detects the characters~ However, it should be under-stood that the par~icular character encoding shown in Figure

2 and the regular order thereof, are not essential to the invention. It should also be noted that the amplitudes shown in Figure 2 are normalized, i.e., they are relative~

One advantage of the character arrangement shown in Figure 2 is that there are only 5 different amplitudes employed, i.e., , ~ and ~ ~ . The number of different ampli-tudes that must be generated can be reduced to four by noting that ~ is 3 ~ . Accordingly, as will become clear below, the modulator is arranged to generate four different ampli-tudes and the fifth is generated by adding a selected ampli-tude to twice the selected ampLitude to obtain three times the selected amplitude.

In order to generate the 32 information sub-carriers, and the two timing channel sub-carriers, effectively 34 oscillators ~35 are required. The 34 oscillators are implemented in digital fashion, a 34-stage shift register stores a phase represen-tation for each sub-carrier. A second 34-stage shift regis-ter stores an amplitude representation for the sub-carriers.
Each phase representation must be periodically updated to correspond to phase change as a function of time. By properly choosing the phase representation of 2~ and the sampling period the updating function is reduced to periodically incremen~ing each phase representation by a quantity corres-ponding to the harmonic index k, where each sub-carrier fre-quency is Kfo, where K represents the harmonic index. Since phase varies modulo 2~, phase arithmetic must be modulo 2~.
In balancing ~uantization error caused by limited precision and equipment necessary to increase precision we have used a nine bit phase representation, i.e., 2~ is represented by 512. Thus, the adder which is used to update phase performs modulo 512 arithmeti~. We sample at intervals of ht = 2~
5 }2wo or 1 . Change in phase 0 for any sub-carrier over a samp-512~
ling interval ~t is ~0 = fx ~t, since f = k fO then ~ =
x -~, x x x 2 Kx O which is 2 kx but since 512 = 2~, then ~x = kx for our selected sampling interval. Accordingly, updating 0x for each sampling interval merely requires adding kx to each phase representation.
.
Figures 3A and 3B comprise a block diagram of the modulator and a timing diagram illustrating its operation.

More particularly, Figure 3A illustrates a serial data input stream as provided to a serial to parallel converter 50.
The converter 50 presents 5 bit parallel data to a shift register 51 which is clocked by a system clock 52 which, in turn, is driven by oscillator 53. As the 5 bit words rep-resenting a chaxacter are shifted through the shift register 51, they are made available to a read only memory 54. The data input operation occurs only during the modulation time which is one sampling interval of the baud time as controlled S ~ fi g by signals produced by the system clock 52, illustrated in Figure 3C. Although Figure 3A is illustrated in conjunction with a serial data stream, those skilled in the art will realiæe that conventional e~uipment can be employed to generate a serial data stream from any type of data storage arrangement. Figure 3B shows the baud time TB as including a plurality of sampling intervals. As shown in Figure 3B, the modulation function occupies only one sampling interval.
In the typical sampling interval, the clock cycles a phase representation shift register 57 and an amplitude represen-tation shift register 60. As each stage of shift register 57 presents an output to adder (modulo 512) 56 the phase representation is incremented by the harmonic index kx and the updated value recirculated. In the modulation sampling interval, an additional phase change component corresponding to the modulating intelligence is provided as another input to adder 56. The modulating phase change is provided by ROM 54.

The read only memory 54 stores a multi-bit number for each 5 bit address representing a characterO This number may con-sist of 9 bits of phase information (~) and 3 bits of am-plitude information (A). Of course, the number of bits for both characters, phase and amplitude, may be varied.

The 3 bits of phase information are coupled as one input to an AND gate 55 (representing, of course, plural gates), which is enabled by a timing signal from the system clock during the modulation sampling interval. The output of the AND gate 55 is coupled as an input to adder 56 which also receives another input (representing kx) from the system clock 52. Finally, a 34-stage shift register 57, each stage 9 bits wide, provides a third input to the adder 56. Each stage of the shift register 57 stores a phase representation one of the 34 sub-carriers. The system clock input to the adder 56 represents a phase increment due to the passage of time, which increment corresponds to the harmonic index for the associated sub-carFier. Finally, during modulation s ~ 9 sampling intervals, a third input to the adder is phase change due to modulation. The output of the adder 56 is coupled back to the input of the shift register 57 and also provides one input to a ~urther read only memory 58.

The amplitude information is handled in a similar fashion, i.e., the 3 bit amplitude output is coupled to an AND gate 59 which, during the modulation sampling interval, is enabled by a timing signal from the clock 52. The output of the AND
gate 59 is coupled as an input to a 34-s~age 3 bit wide shift register 60. The output of the shift register 60 is coupled to the input of an AND gate 61 which is enabled at all times other than the modulation sampling interval. The output of the AND gate 61 is coupled to the input of the shift register 60. The output of the shift register 60 is also coupled as an input to the read only memory 58.

In typical sampling intervals, shift register 60 is completely cycled by the clock~52 once per sampling interval. Each stage represents sub-carrier amplitude. The recirculation path goes through AND gate 61. In a modulation sampling interval, the shift register contents are discarded by disabling ~ND
gate 61 and the modulating amplitude information ~ills the shift register through AND gate 59.

The trigonometric function A sin ~ is provided by ROM 58 when addressed by A, 0. ROM 58 can store data for phases from 0 to 2~, but this is not necessary. To conserve memory requirements the read only memory 58 can be considered as four, 256 word, 180 sin tables, i.e., a virtual table for each of the four dif~erent amplitudes that are produced by the memory. Information respecting the other 180 of the sin table is generated arithmetically by using the relation sin (~ + ~ = -sin(~l. Those skilled in the art will realize that a further reduction in the storage of the ROM 58 can be made by using the relation at sin (~ - ~) = sin (~).

In effect, the ROM 58 is addressed by 12 bits, 9 bits of phase and 3 bits of amplitude. Two of the amplitude select s ~ 9 bits determine which of the 4 sin tables are used and the remaining bit determines whether the stored amplitude will be employed or three times that clmplitude must be generated.
When three times the ROM output is selected, the ROM output is fed to adder 58a which, at its output, produces the de-sired result. The signal from adder 58a and that from ROM 58 is coupled to multiplexer 58b. The multiplexer 58b output is selected as either output of ROM 58 or adder 58a. The least significant 8 bits of ~he phase quantity address the sin table, and the most significant bit controls complementation. Suc-cessive outputs are coupled to an accumulator 6~ which is allowed to accumulate over a complete sampling interval~
i.e., a contribution from each of the 34 sub-carriers. Under control of the system clock 52, the accumulator is then allowed to make the sum available to the D/A convertor 63, and it is cleared and begins accumulation representing the next sampling interval. The output of the D/A converter 53 is coupled to the telephone Lines'through a low pass and interpolation filter 64.

It will be seen that each sampling interval is handled identically throughout the modulator, except that in the modulation interval input data, as encoded by ROM 54, is provided to the gates 55, 59, which are enabled for that sampling interval only. Since two of the timing channels are not modulated by data, they are handled separately. For one thing, the shift register 51 is periodically clocked throughout the modulation sampling interval in regular fashion except that the clocking is interxupted at the timing channel times.
At those times, the gates 55 and 59 are disabled and corres-pondingly, gate 61 is enab}ed~ Accordingly, the amplitudes of the timing channels are retained from one symbol interval to the n,ext. The phase of the timing channels are not modu-lated by data. Actually, the phase of one timing channel may be unchanged. The demodulator is provided with a timing mark with which to synchronize the correlation time. The timing mark corresponds to equal predetermined phases of the timing channels which are adjacent harmonics. Figure 3D
shows sin ~ as a function of time, wherein ~ represents `` ~;1~55~9 the phase of one timing channel TCl. Also shown in Figure 3D is the correlation time which will be established at the receiver. As shown, the phase A of TCl is predetermined ~for example, zero~ at the beginning of the correlation time.
To provide TC2 with the same phase may (and normally willl require phase adjustment, and so clock 52 enables multiplexer 49 to couple ~ to adder 56 in the portion of the modulation sampling interval corresponding TC2 interval. Likewise, to ensure that TCl phase is also zero, a predetermined quantity Al is coupled by multiplexer 49 in the TCl phase stage.
The quantities ~1 and ~2 are precalculated to provide the predetermined equal phase for TCl and TC2 at the beginning of the correlation time. As mentioned, only one such quantity ~2 is necessary, the other provides error protection.

Figure 3C illustrates significant components of the clock 52.
More particularly, the oscillator 53, operating at an appropriate frequency, drives a plurality of counters such as the counters 65, 66. One of the counter outputs, labelled CLK, is used to step the shift registers 57 and 60 to thereby establish the basic operating events in the modulator. A
signal of ~ike repetition rate steps shift register 51.
Since the channel indices are sequential but do not start from zero, an offset Q is added to the output of counter 65 by 65a to provide the C0 - C5 signal set providing a binary representation of the channel index. For example, if the channel indices are 8 to 41 then by adding the representation of 7 to the C0 - C5 outputs of counter 65, binary represen-tations of 8 to 41 are produced. The outputs labelled C0 through C5 are employed as one input to the adder 56. The outputs labelled C0 through C5 are also provided to a de-coder 67 which produces the signal TC and TC. TC is true when counter 65 has counted to a time slot corresponding to one of the timing channels. These signals are employed at the gates 55 and 59 in order to prevent "modulation" of the timing channels, and also at the shift register 51 to, in effect, create "spaces" in the data stream so that the timing channels in the shift registers 57 and 60 are not overwritten with modulation. A flip-fIop 68 provides the .~ .

, 1 1'~5S~9 MOD and MOD signals. MOD is high only in the first sampling interval of each baud time.

From the foregoing description, operation of the modulator of Figure 3A should be apparent, but it will be briefly described now that the apparatus making up the modulator has been described.

At the beginning o~ a baud time, the moduLate signal is true for one sampLing interval, allowing shift register 51 to step along, each step presenting a new character to the read only memory 54. For each step of the shift register 51, the read only memory 54 provides a phase word and an amplitude word corresponding to the character. This operation is continuous during the modulation intervals save that when the signal TC is high, indicating a time slot corresponding to a timing channel, the shit register 41 is momentarily inter-rupted. As a result, the read only memory 54, during the modulation portion of the symbol interval, produces a stream of phase and amplitude words, interrupted only during the time of each timing channel.

During the modulation interval, each phase wo~d, from gate 55, is added in the adder 56 with the present phase for the corresonding sub-carrier derived from shift register 57 through multiplexer 49. The phase added through the gate 55 corres-ponds to the modulation impressed on the sub-carrier. Since the shift register 57 recirculates through the adder 56, some means must be provided to account for the phase change from one sampling interval to the next. This is added in from the system clock 52 corresponding to the harmonic index K. As described above during the timing channel time, TCl and TC2, the phases are set to Al and ~2 by operation of the multi-plexer 49. The harmonic index X is added to A1 and ~2 in adder 56. As mentioned, the gate 55 is disabled for TC
and TC2.

Amplitude infoxmation i5 contained in the shift reglster 60.
The shift register 60 recirculates through the gates 61, which ~ 1 5 ~

is the normal data path except during the rnodulation sampling interval. During the modulation sampling interval this path is opened at gate 61, and instead the path through gate 59, passing new amplitude information from read only memory 54 is input to the shift register 60. Thus, during the modula-tion interval the shift register 60 is filled with entirely new amplitude information from the read only memory 54. This is true for each of the information sub-carrier channels.
However, in the timing channels, indicated bylthe signal TC
fixed amplitudes are impressed. The fixed amplitude can be selected as any amplitude that is high enough to be de~ected and low enough to prevent clipping at the demodulator. In one embodiment, we selected this fixed amplitude as about the rms value of the modulation amplitudes. Accordingly, at the conclusion of the modulation portion of the baud time, the shift register 60 is filled with amplitude information for each of the sub-carriers, both information and timing.
In the remaining portion of the baud time, the information contained in the shift register 60 merely recirculates through the gate 61.

Figure 3E represents operation of the modulator with regard to phase in~ormation. Figure 3E is a representation of phase changes as a function of time from left to right. At the top, Figure 3E represents the events taking place for transmission of an arbitrary baud, baud B, which follows baud A and pre-cedes baud C. The time axis is broken up into a number of sampling intervals. Each sampling interval itself comprises a number of sampling times, one for each chan~el. The samp-ling intervals are equal to the time taken for a comple.te cycle of shift register 57 or 60. The transfer o~ a phase or amplitude word in shift register 57 or 60 to the next stage is a sampling time. Thus, there are a number of sampling times in each interval at least equal to the number of chan-nels. Each phase is represented by a vector, with the angle equal to phase~ The phase vectors begin at the left at their position at the conclusion of baud A, that is, the phase in the last sampling interval. Thus, for channel 1, the phase at the conclusion of baud A is between ~/2 and ~. In the 5 ~ 9 first sampling interval, the modulation interval, two quanti-ties are added, ~MODl' the phase modulation impressed on the channell and Kl the harmonic index of the channel representing phase change due to time. In our example, the sum of these three quantities is 128 or a digital representation of ~/2 since 2~ is represented ~y 512. For channel 2, 0MOD2 ~ K2 ~
~ , and a commensura-te quantity is stored. The timing channeLs, TCl and TC2 are handled di~ferently. As shown, the sum of ~1 and the harmonic index R for TCl is zero.
Accordingl~, the phase of TCl goes to that value. A similar result occurs in TC2. The quantities ll and ~2 are selected so that, with TCl and TC2 phases reset to these values, the ph~ses of TCl and TC2 at expiration of the guard time or gap are equal and equal to a predetermined quantity such as zero. Note that the "old" phase does not enter into the opera-tion so errors do not accumulate.

In the next sampling interval phase of each channel is also updated. However, in the second and all subsequent sampling intervals, the only change is the addition of the harmonic index K corresponding to that channel. Accordingly, in the second and subsequent sampling lntervals, gates 55 and 59 are disabled as MOD goes low.

The foregoing explains how the shi~t reyister 57 and 60 are employed to generate and maintain amplitude and phase informa-tion for each of a plurality, for example 34, subcarriers.
Throughout the baud time, the output of the adder 56 and gate 59 or 61 provides addressing information to the sine tables contained in the read only memory 58. Accordingly, for each sub-carrier, the read only memory produces an output corres-ponding to A sin ~, where the ampIitude information is re-ceived from the adder 56. In each sampling interval, a sum of all such samples are accumulated in the accumulator 62.
At the conclusion of each sampling interval, the sum is con-verted to analog form and output to the switched network.
At the same time, a new sampling interval begins and the pro-cess repeats itself. This continues for an integral number of sampling intervals, comprising the baud time.

.~ 9 At the conclusion of the baud time, which repeats at the baud rate, i.e., for example, 60 times per second, a new modula-tion interval is begun. DurinS the modulation interval, a S bit character for each information channel is again con-verted to amplitude and phase information to modulate the sub-carriers which are, again, sampled and so forth.

In the modulator of Figure 3A, modulation is impressed on a sub-carrier whose phase at the beginning of a baud time is the same as that sub-carrier's phase at the end of the pre-ceding baud time, i.e., except for the new mo~ulating the phase is continuous across the baud boundary. This neces-sarily results in a differential modulation system wherein phase change is detected across the baud boundary, i.e., demodulation requires knowledge of the prior sub-carrier phase to determine the phase change engendered by the modulator. This is not essential to the invention since, by resetting the phase memory 57 for each sub-carrier to ~ero at the beginning of a baud time, direct modulation is produced wherein modulation is detected by comparing sub-carrier phase to a reference or constant phase to detect the modulating intelligence.
.
Furthermore, the discrete logic of Figure 3A is also not essential to the invention and coul~ be replaced by a micro-processor or stored program responsi~e device. In addition, the sequence in which phase change is effected, i.e., se-quentially in all channels for each sampling inter~al, is also not essential. For example, if we denote phase as 0xy' x representing channel (1 to n) and y representing sample number (1 to m) the modulator of Figure 3A generates ~
then 02L~ 031 0nl' then ~12 0n2~ to ~lm 0mn However, it is well within ordinary skill to generate phase in an off line fashion wherein all phase quantities are de-termined and stored be~ore the beginning of the baud time in which the modulating intelligence will be transmitted. A
discrete logic or random logic apparatus could then read out phase in proper order and transmit as does the modulator of Figure 3A. In such a system, phase could be generated in 1 15~9 the sequellce ~ 12 01mi then ~21~ ~22 0~m until 0nl' 0n2 to ~nm The demodulator, functionally illustrated in Figure 1, is shown in block diagram in Figure 4. It responds to signals received over a switched network, such as the switched tele-phone network, and derives from the received signals the in-formation used at the modulator to modulate the information sub-carriers. The equipment at the demodulator performs A/D
conversion correlation function and then determines, based on a correla~ion between the received signal and each of the locally generated sub-carriers, on the intelligence employed to modulate each of the information sub-carriers.

The correlation apparatus includes an analog processing unit as well as a digital processing unit.

The analog processing unit includes the coupling to the com-munication link which may be by way of a transformer and low pass ~ilter. The output o~ the filter is coupled to an auto~
matic gain control module comprising a controlled attenuator 20 and a control device to select attenuation level so as to produce the desired automatic gain control. The automatic gain control function enables the in~ormation system to adapt itself as gain levels change within the switched network.
One of the prime functions of the automatic gain control is to adjust the input level of the serially connected analog to digital converter 21 so as to employ as much of its ac-curacy as possible. Too much amplitude if not compensated for by the attenuator 20, will result in clipping in the A/D
converter 21 and perhaps in the multiplier. In one preferred embodiment of the invention, the automatic gain control func-tion is arranged to maintain the RMS level input to the A/D
converter 21 at about 1/4 of its clipping level. Those skilled in the art can readily employ analog or digital AGC
circuits to maintain the input to the A/D converter 21 at its proper level and therefore a detailed description of the AGC 19 will not be provided.

g The output o the A/D converter 21 is provided to the digital correlator 17. A multiplier in correlator 17 receives sam-ples of tha received signal from the A/D converter 21 at a convenient rate, for example, approximately every 30.6 micro seconds. During the period of each sample, it i5 mul-tiplied by 34 pairs of signals, each pair representing one of the sub-carriers. Sub-carriers are locally generated by generator 24. Each pair of the signals corresponds to a di-ferent one of the sub-carriers generated at the modulator.
The multiplication process, therefore, produces 34 pairs of products, for each sampling of the output of the A/D converter.
These products are provided to one accumulator which stores the 34 pairs of products. This process is repeated throughout the correlation inte--val (see Figure 2C~ and the accumulator therefore accumulates 34 pairs of sums. At the conclusion of a correlation interval, the 34 pairs of summed products are available at the decision unlt 25 which, based upon analysis of the 34 pairs of sUm5 produces two results. The first re sult is the data symbol, i.e., 160 bits, corresponding to the modulation input at the modulator. The second result is a correction, to account for distortion, effective at the sub-carrier generator 24 as well as at the timing apparatus 26.

The demodulator sub-carrier generator 24 is shown in detailed block diagram fashion in Figure 5. The sub-carrier generator 24 operates much in the same manner as does the sub-carrier generator at the modulator, except that only a single ampli-tude is necessary. Eowever, in contrast to the sub-carrier generator 12 at the modulator, sub-carrier generator 24 pro-duces sine as well as cosine signals.

The sub-carrier generator 24 includes a 34 stage shift regis-ter 70, a stage for each one of the 34 sub-carriers being generated. The output of the shi~t register, representing phase to be updated, is provided to adder 71~ The other input to the adder 71 is provided by one of two inputs through the symbolic OR gate 72. During the correlation interval, the effective input is provided by an adder 73 which provides a signal, coupled through the OR gate 72 representing the ~ ~55~

harmonic index K, similar in function to the input to adder 56 from the clock 52 ~see Figure 3A). Thus, this input rep-resen-ts the phase change due to the passage of time.

The output of adder 71, corresponding to the phase sample is provided to a further adder 74, and is also recirculated to the shift register 70. The adder 74 has, on its other input, a signal provided by an AND gate 75. The AND gate 75 has one output corresponding to a digital representation of ~/2 and a gating signal on its other input. The output of adder 74 is provided as the addressing input to ROM 76 which stores a sine table.

The arrangement of adder 74 and AND gate 75 is pxovided to enable the sub-carrier generator to produce signals correspon-ding, respectively, to sine and cosine from the read only memory 76.

Each interval during which the phase sample of a sub-carrier is pro~ided to adder 74 is divided in half by the gating sig-nal on the enabling input to AND gate 75. During one half this interval, AND gate 75 is disabled and accordingly, the ROM 76 produces, at its output, a digital signal representing the sine of the phase which corresponds to the phase sample represented by the output of adder 71; adder 74, during this period, receiving only a single input. In the second half of the interval, the AND gate 75 is enabled and therefore a quantity corresponding to ~2 is coupled to the second input of the adder 74. Accordingly, the output of adder 74 is the input phase plus ~/2, and, as a result, the ROM 76 produces cosine of the angle whose phase is the ouptut of adder 71.
In the example under discussion, since a count of 512 repre-sents 2 , ~/2 is represented by the digital quantity 128.
As in Figure 3A, the ROM 76 stores a sine table for 180 employing the relation sin (-9) = -sin ~; accordingly, the most significant bit output of adder 74 represents sign.

As the shift register 75 cycles, the output of the read only memory 76 corresponds to sine and then cosine of each of 1 1~55~9 the phases whose digital representation is produced by the adder 71. These signals are coupled to multiplier 22. For the present time, we will ignore the effect of the undiscussed inputs to adder 73 as well as the undiscussed input to the representative OR gate 72.

Figure 6 comprises a detailed block diagram of the correla-tor. As shown in Figure 6, the multiplier 22 is sub~ected to a pair of inputs, a first input corresponding to the output of the A/D converter 21, and the second input from the ROM
76. The output of the mlutiplier 22 is coupled to an adder 77 which provides outpu~s alternately to one of two shift registers 78 and 79. Each of the shift registers 78 and 79 is 34 stages long, one stage for each of the sub-carriers.
As the sine and then cosine outpu~s are provided by the read only memory 76, the products of the sine and cosine with the received signal sample is provided by the multiplier 22 and coupled through the adder 77 to the sine or cosine shift reyisters 78 and 79, respectively. The rate at which the received signal is sampled allows 34 pairs of products to be produced for each received signal sample. Since the shift register outputs are coupled as the second input to the adder 77, as the sampling and multiplication process proceeds, from one received signal sample to the next, the shift regis-ters 78 and 79 have built up therein, at each stage, the sum of the product of the sine or cosine signals with samples of the received signal. This process proceeds for the duration of the correlation interval. When the correlation interval terminates, the shift register 78 and 79 each have 34 quan-tities stored therein, from which the decision unit will determine the modulating intelligence.

For each of the 34 stages in the sine shift register 78, the quantity stored therein at the conclusion of the correlation interval can be represented as:
~ = 5~2 k m Y o r~m ~t~ * cos ~k m 2~/512 + 0k) 1 15~5B9 Corresponding~y, the cosine shift register 79 accumulates in each stage a sum which can be represented as follows:
m - 512 Yk = ~ ~ r(m ~t) * sin (k m 2~/512 + ~k~
m = 0 where, in both expressions, X identifies the harmonic index and r is the received signal. Accordingly, each pair of quantities corresponds to a single channel which may be a data channel or a timing channel.

A bi-directional tri-state bus 80 couples the outputs of shift register 78 and 79 as well as one input of adder 77 to the decision unit. The decision unit is shown, in block diagram form, in Figure 7.

Before describing the decision unit in detail, the function it performs will firs~ be discussed. Each pair of quantities in the shift register 78 and 7~ defines a vector of amplitude A and angle ~0, and it is these ~uantities from which the modulating intelligence can be determined. Accordingly, the decision unit has access to shift registers 78 and 79, over the bus 80, and processes each of the information channels in turn, to derive the modulating intelligence. This could be accomplish~d by comparing each vector to each of the 32 possi-ble vectors represented in the data array (see Figure 2).
Such a technique would require 32 comparisons for each of the 32 information channels. Although possible, a preferred ~ -technique is the technique actually employed in the decision unit which maps each o~ the data characters onto an XY co-ordinate system using the relation X = A*cos(Q~) and Y =
A*sin(Q0) to form an array of data points, similar to the ar-ray of Figure 2. The decision unit acutally operates on an array of squares, i.e., the squares-formed by the bold lines of Figure 8 wherein each data point lies at the center of a different square. The square surroundiny each data point is the decision region, and thus it is only necessary to deter-mine whih square contains the received vector to determine the modulatiny intelligence for that channel.

~ 1~5~

Denoting one halE the length of a side of each square as 1~, the decision region containing the vector can be determined by separately subtracting the quantity N from each of the vector components X and Y. Thus, the decision unit first notes the sign of the quantity and then forms the absolute magnitude. ~n iterative process is then entered in which the quantity N is subtracted from the absolute magnitude of both X and Y until the result goes negative, keeping track of the number of subtractions. Based on the number of subtractions required to produce a sign change, the decision region con-taining the received vector is determined. Because the array is, at most, 6N on a side, at most 5 subtractions are required.
An attractive feature of this technique is that, in addition to determining in which decision region the received vector lies, it is also possible to determine which quadrant of the decision region in which the vector lies, which information is useful for "tuning" the detection process.

Since the decision unit detects absolute phase, i.e., the phase of the received signal, it is necessary to "know" the channel phase at the beginning of the modulating interval to determine modulation. But this phase is merely the phase of the su~-carrier at the conclusion of the last correlation interval and is, indeed, "known". Accordingly, for differential modulation, wherein phase change is correlated with data, it is necessary to insure that the demodulator sub-carrier generator "tracks" the modulator. Accordingly, at the con-clusion of the data detection process, channel phase is aligned with the transmitted phase so that, in the next baud time, the new modulating intelligence can be detected as a phase change.

Those skilled in the art will understand that this is, how-ever, not essential to the invention, and that the data may be correlated with phase referenced to absolute phase. With such regime, the modulator sub-carrier generator has its phase set to zero at the beginning of each modu}ation inter-val and the modulating information changes that phase in accordance with the intelligence. At the demodulator, the 1 1S5S~

phase of each of the waveforms being genera~ed is unaltered, i~e., the demodulator sub-carrier phase does not track the modulator phase. Although either technique can be employed, the embodiment undex discussion employs the former technique wherein the demodulator phase is adjusted at the conclusion of each correlation interval, and accordingly, the demodu-lator phase tracks the modulator phase.

The magnitude of the quantity N nominally a system parameter dependent upon the gain of the communication link, is not known, and is also variable with frequency and time. Thus, the location of the vector within the decision region is employed to adjust for this extraneous phase shift.

These corrections are made by determining in which quadrant of the decision region the received vector lies. Ideally, these regions have boundaries composed of radial lines and are segments of a circle, i.e., they are not regular. It is much simpler, however, to implement these correction efects by employing decision sub-regions in the form of squares as i5 sho~n in Figure 8.

Accordingly, the results of the subtraction process, i.e., the number of subtraction cycles and the remainder for both X and Y coordinates, are mapped, for example, with a read only memory, into phase shift, phase correction, data and N cor-rection. The sum of the phase shit and phase correction are employed to adjust the phase of ~he sub-carrier to insure that the demodulator phase tracks modula~or phase and to compen-sate for phase distortion. The data is output and the N
correction is used to adjust the quantity N used for that channel in the next baud time. The ~oregoing description applies only to the information sub-channels.

The decision unit also processes the two timing channels to derive synchronization and control information. For one thing, the correlation interval must be precisely synchronized with the theoretical correlation interval, i.e., occupy the entire baud time following the guard space, and repeat at 5 ~ 9 the ~roper rate. In addition, frequency offset m~st also be eli-mina-ted. The decision unit, in processing the timing channels, detects the si~n of the phase of one of the channels the phase difference between the channels and the frame to frame rotation of that channel. The firs-t two quantities are used for synchron-ization, the last is employed to detect and correct for fre-quency offset.

The phase of both timing channels were adjusted, at the modulator, so that they would have a predetermined relationship (equal and equal to zero) at the beginning of the correlation interval.
The phase of each timing channel is determined by the decision unit. If the correlation interval at the demodulator is correctly located in time, the phase relationship is maintained.
If there is a difference between the phases in these channels then the correlation interval must be adjusted in time to drive this difference to zero. The sign of the phase o~ one of the channels is employed to determine in which direction to correla-tion interval must be moved to reduce the phase difference to zero. In order to simplify the correction process, only two different corrections are allowed, a small or a large correc-tion. A threshold level is set, and if the time error is larger than the threshold, the~ the large correction is employed and the sign of the phase of one channel is employed to deter-mine in which direction the correction should be made. The correction is made by adding a phase change to each timing channel of the form kp~ t, wherein ~ t is the amount of a time correction, p is a constant an~ k is the channel index. If the phase difference between the two timing channels is less than the threshold, the small correction is employed (i.e., a different quantity is selected for ~ t).

Frequency offset is determined by the direction of rotation of one of the timing channels. More particularly, the quantities in the registers 78 and 79 for this channel are matched against the "old" parameters ti.e., prior baud register ~uantities for this channel) and a determination is made as to the direction of phase change.

.

~ 15~5~g Figure 9 illustrates two vectors, one labelled "old", the other labelled "new", the old and the new vectors representing the processing results of one of the timing ch~nnels for adjacent baud times. This information is available to the decision unit from the shift register 78 and 79 (see Figure 61. To detect frequency offset, the sums shown in the upper right hand corner of Figure 9 are formed; that is, ~X0 - Xn + Yn ~ Yo) and (X0 + Xn + Yn + Yo) where 0 represents "old" and n represents "new". The decision unit notes the sign of the expressions, b is the sign of the first expression, b2 is the sign of the second expression. The sum bo = bl + b2 is formed, if bo is 0 then the phase is advancing from frame to frame whereas if bo = 1 the phase is retarding from frame to frame. The decision unit, based upon the result, makes the correction for frequency offset, the sense of the correction depending upon the result bo~

Returning now to Figure 7, a block diagram of the decision unit is illustrated. As shown, a program control 81 comprising a read only memory 100 has signals stored therein representing the desired processing functions. These functions fall into two major groups or routines, a first routine for processing an information channel and a second routine for processing timing channels. The program control is addressed by signals from the timing unit 26. The output of ROM 100 is latched in latch 101 and decoded in decoder 102 from which control signals are coupled to various other portions of the decision unit. A tri-state bus 80 interconnects the various units which enables them to pass information between accumulator, registers 78, 79, decision unit and the sub-carrier generator. The direction of inormation flow on the bus is established under the control of the program ROM 100 which signals are decoded and distributed by decoder 102.

As shown in Figure 7 then, the decision unit includes a buffer 85 coupled to the tri-state bus 80 to couple the quantities con-tained in the shift registers 78 and 79 to adder 86. The output of adder 86 is coupled to a register 87 which can pass informa-tion to a 34 stage shift register 88 or a single stage register 89. The output of both shift register 88 and the register 89 are 1 1 5~5~9 coupled also to the ~us 80~

A pair of latches 90 and 91 provide addressing inputs to a read only memory 92. One output of the read only memory 92 is coupled to an adder 93 which also receives, as another input, a frequency offset correction signal from the decoder. The sum produced by the adder 93 is coupled -to an adder 94. The output of the adder 94 is also coupled to the bus 80.

In processing an information channel~ the contents of the asso-ciated stage of shift register 78 is first coupled to the buffer 85 over the bus 80.

The sign bit is noted in the logic 104 and then the absolute value is coupled back as one input to adder 85. The corresponding N value from register 34 is also coupled to adder 86 over the bus 80 and the difference ohtained. Simultaneously, the latch counter 141 is incremented and the N value is again subtracted from the diference. The ~rocess is repeated until a sign change is detected. A~ a sign change, the X or Y count is re-tained in latch 90 or 91 and the same process is repeated but this time with the contents of the other shift register 79. At the conclusion, the decision region containing the information channel vector is identified by X and Y, the count in latches 90 and 91. Since there are at most 12 regions for each com-ponent, each component contributes 4 bits to the result.
Accordingly, the latches 90 and 91 produce an 8 bit result. The 8 bits form an address for ROM 92 which produces three outputs.
A first output is the 5 bit character word which is coupled to register 105 and in turn, to parallel to serial converter 106.
As each information channel is processed, in turn, the concaten-ated 5 bit output words produce the 160 bit data originally input at the modulator. The phase shift and phase correction, corres-ponding to the decoded vector phase are output as a 9 bit word.
Phase shift is the angle of the nominal vector, phase correction is the difference in angle between the received vector and the ideal vector. Adders 93 and 94 correct for effects to be dis-cussed later. The phase change (sum of phase shift, phase correction and frequency offset corrections to be discussed) is, 1 ~ 5~5~9 however, coupled to OR gate 72 (Figure S) where it is used to update the corresponding phase word for the channel. This enables the demodulator to both "track" the modulator phase and to correct ~or phase distortions introduced by the communication process. Finally, the third output of ROM 92 is 2 bits of data for correcting the quantity N associated with the channel. This data is coupled throu~h a driver 107 over the bus ~0 to adder 86 where it is summed with the previous N value. The result is coupled through register 87 and stored in the shift register 88 at the appropriate location. This completes the decision unit processing for an information channel. To process the next channel, shift register 88 is incremented to make available the N value associated with the channel to be processed, shift register 70 is incremented to make the channel's phase word available for correction, and the next X and Y values are ob-tained in turn from registers 78 and 79.

Processing of the timing channels is somewhat different. Actu-ally, two di~ferent routines are used to process the timing channels, these routines are used on alternate baud times which baud times are identified by the state of EOT, coupled from the timing unit to ROM 100. In one set of alternately occurring baud times, routine A is performed only to correct for errors in the initiation of the corrleation interval. ~o determine whether a small or large error is present a threshold is established by subtractlng ¦XTc2lfrom ~ ¦YTC ~ Y C ¦ i where the alphabetic character identifies a value obtained ~rom register 78 or 79 and the subscript identifies the channel.
Equality means the correlation time is within 650 ~s of ideal and so a small correction is used, as will be disclosed. If the difference is positive, the error is larger, and a large change is used. I~ the correlation time had begun exactly at the ' YTC2 YTCl since the phase of both were equal as transmitted. Comparing 4 ¦YTC2 YTCll to ¦ TC2¦
margin and establishes the threshold. A comparison of channel phases is used rather than comparing the phase of either to a determined quantity since that test would be rendered useless by phase distortion. The calculation is made in adder 86 and the l 1555~9 sign bit, coupled to logic 104 is used to determine the size of the corxection. The sense of khe correction determines ~ T and is controlled ~y the phase oE one of the timing channels, repre-sented, for example, by the sign of YTC . Thus, Q T indicates whether the phase of TC2 is positive or negative and determines the sense of the correction ~ T is controlled by the comparison and determines the magnitude of the correction. The apparatus can distinguish between transient or short term errors and long term effects, such as those caused by differences in the crystals in modulator and demodulator. Before further describing the apparatus of Figure 7, t~e demodulator clock will be briefly explained.

Figure 10 shows the demodulator clock and some of the significant signals generated thereby. An oscillator 120 producing an appropriately high frequency (approx. 11 MHz.) is divided down by divider 121. The divider produces several clocking signals which are sub-multiples of the frequency of oscillator 120. One of the clocking signals runs a counter 122. Counter 122 pro-duces the CTo ~ CT5 signal set which is decoded and provides the harmonic index input to adder 73 (Figure 5). Counter 122 also produces the EOC (End o~ Correlation) signal alter the given plurality o~ samples comprising the correlation interval ls concluded. EOC provides, through AND gate 123, an input to flip-flop 124, whose output is an input to flip-flop 125, whose Q output controls the CLR input of counter 122. Accordingly, counter 122 provides or a repetitive cycle but the delay between cycles is controlled by flip-flop 124, in a manner now to be explained. A further counter 126 operates at half the rate of counter 122. This counter produces the signal sets PS0 - PS5 and PC0 - PC5. The signal set PC0 - PC5 also corresponds to the various timing channels, i.e., decoder 127 produces the signals TCl and TC2, identifying the timing channels. These signals (TCl and TC2) and the signal set PS0 - PS5 are the addressing inputs to ROM 100 (see Figure 7) as well as EOT
(also produced by counter 125) identifying alternate ~aud inter-vals. A counter 129 is clocked at half the rate of counter 126 and is enabled by a signal from decoder 128 representing a specified point in the cycle established by counter 126. The 1 1~55~9 outputs of coun~er 129 are coupled to a decoder 130 which also receives the ~T and ~T signals from the logic unit 104. Based on the ~T and L~T signal combinations decoder 130 outputs a signal SSP advanced or delayed a small pre-determined time ~lysecl or a large predetermined time (+30~sec) ~rom nominal output. The ~T and L~T signals are produced by flip-flops in logic 104 (as will be disclosed~.
These signals are set during the operation of the decision unit in one baud time and are effective at decoder 130 in the next following baud interval. Accordingly, based on the phase comparison in one baud inter~al the start of the cor-relation time in the next baud interval i5 advanced or re-tarded by a large or small amount.

The SSP sîgnal sets a flip-flop 131 which enables counter 132, clocked a~ the same rate as counter 129. The actual beginning o the correlation interval is based on a comparison between the contents o counter 13~ and a further counter 133 as efected in comparator 134. On comparison, AND gate 135 is enabled to set a flip-flop 136 which allows counter 137 to count. The ripple count output o counter 137 is the signal SSPD, which also serves to reset flip-flop 136 to ensure that the counter 137 remains in the cleared state.
The SSPD signal enables AND gate 138 to reset flip-10p 124, which had been set on EOC. Change of state of flip-flop 124 causes a change in state of flip-flop 125 to enabIe coun~
ter 122 to count again. Accordingly, the gap or guard time, at the demodulator is established by the delay between EOC and SSPD, which, as has been explained, is varied by the ~T, L~T
signal combination based on a phase comparison of the timing channels TCl, TC2-In addition, the counters 133 and 139 are provided to compen-sate for drifts between the oscillators at modulator and demodulator. Since osciLlator drifts are cumulative, a long term drift could cause the correlation interval to move beyond the amount of correction provided by the decoder 130. To account for this possible effect the counter 133 can have its count changed. Since the relative delay between SSP
and SSPD depends in part on a comparison between cou~ters 132 and 133, incrementing or decrementing the count in coun-tex 133 can change the time relation between SSP and SSPD.
In each symbol interval, the L~T and ~T signals can increment or decrement counter 139, but only if a large phase difference is noted, î.e., one exceeding the threshold of 4 ~ IYTC - YTC ¦
-¦X~ ¦. C~unter 139 th~s represents a running indication of any bias in the direction of large phase errors. If the bias exceeds the threshold established by the capacity of counter 139, an output clocks counter 133, in the sense of the last error. In this fashion, the delay between SSP and SSPD can be changed. It should be noted that the count of counter 133 is effecti~e on each baud interval until the count is changed. This contras~s with the effect of decoder 130 which provides transient correction, i.e., only for a single baud time.

Referring again to Figure 7, the ~0 and L~0 signals from the logic 104 are also based on the comparison of 4 ~ ¦YTC - YTC ¦
- ¦ XTC ¦, but are used to make compensating corrections of phase to the phase words stored in shift register 70. Multi-plexer 140, during the processing of the timing channels couples the ~0 and LQ0 signals to latch counter 141. Latch counter 141 functions as a simple counter in processing of information channels, under control of the decoder 10Z.
Howeverj during processing of timing channels, it does not count but merely latches in the output of multiplexer 140.
Accordingly, during processing of timing channels, the ~
and L~0 signals are coupled to ROM 92 as addressing inputs via the latches ~0 and 91. The ROM 92 has stored quantities representing phase corrections for either large or small phase errors. These quantities follow the same path to the register 70 as does the phase corrections from ROM 92.

Finally, the program A also stores the values XTc2 and YTC2 from registsr 88 into register 89 where it will be used in ~ 1 ~ 5 ~

processing for frequency offset.

As mentioned, routing A, just described, is run on alter-nate baud in~erval~. Another routine B operates ln the inter-vening baud times as no~ed by EOT. Routine B is identical to routine A except for frequency offset correction which will now be explained. Frequency offset i5 detected by comparing the phase of one of the timing channels across a baud boundary.
This phase comparison requires noting phase sign on either side of the baud boundary as well as phase rotation across the ~aud boundary. The sign of YTC2 determines whether the phase is between ~ and 0 or be~ween ~ and 2~. To determine rotation, a pair of sums is formed ~X0 - Xn + ~n 0 0 n Yn + Y~ where X and Y refer to quantities from register 78 or 7~ and the subscripts 0 and n refer to preceding symbol and present baud, respectively (see Figure ~). The sums are formed in turn in register 87 and the sign bits bl and b2 are noted, for the first and second sums, respectively, by logic 104. The result ~Fu is the result of exclusive ORing of Bl and b2 and indicates the rotation direction. It can be shown that the first sum is equal to A sin 2~0 and the second is equal to A cos 2~ wherein ~ is the sign of YTC2, ~ is the rotation between symbol intervals and A
depends on ~ and ~9.

Referring again to Figure 7, the signal ~Fu is coupled as the UP/DOWN control input to counter 142. Counter 142 is enabled via OR gate 143 from L~0 or a gate from decoder 102.
Accordingly, the contents of counter 142 count up or down a predetermined amount representing a correction for the noted frequency offset. Counter 142 provides an input to decoder 104 and adder 144. The output of adder 144 is coupled to a latch 145, which provides a second input to adder 144. In effect, counter 142 retains the effective estimate of frequency offset correction, which is maintained by updating the quantity by the output of counter 142 for each processing cycle. The frequency offset correction circuit provides two outputs FBW indicating a negative count in counter 142 and FCY

l ~s~9 indicating overflow from adder 144. These signals are coupled to adder 73 where they are used to change the LSB input to adder 73. Accordingly, each of the channels receives an equal correction for frequency offset. More particularly, for a given correction the increment to phase on each cycle of the shift register 70 is changed in an equivalent manner for all channels. Since the frequency change is a rate of phase change, the compensation is able to compensate for the fre-quency offset since the incrementing or decrementing quantity changes the p~lase rate of change and does so equally (and not proportionally) for each channel.

Since the shift register 7Q, containing a phase word represen-ting the phase o~ each channel, operates discontinuously, i.e., only during the correlation intervall these phase words must be adva~ced to account for phase cha~ge during the gap time or guard space. Adders 93 and 94 provide this correction.

As each channel is processed, the phase advancement for each channel that would have occurred in the gap time or guard space is computed by decoder 147 which receives as an input the signal set PC0 . . . PC5 identifying the channel being pro-cessed. The gap time or guard space is a constant and so it is a simple ma~ter to provide a decoder to produce an output in terms of phase representation of phase change for this fixed time increment. Phase change corresponding to modula-tion and distortion for each information channel, in turn, is output from ROM 92. Adder 94 merely adds the phase change during the gap time or guard space thereto, and the sum is written into the appropriate location of shift register 70.

One final phase change that must be effected is the phase change due to detected frequency offset (for the processed baud interYal~ which took place in the gap space or guard time. The frequency offset detected for the symbol interval is available in counter 142. The equivalent phase change for the fixed gap time or guard space is computed in decoder 103 S ~ 9 and added, by adder ~3, to the sum of phase modulation and phase distortion provided ~y ROM 92.

The corrections produced by adders 93 and 9~ are the same for both timing and information channels.

The logic 104 is shown in logic level diagram in Figure 11.
As shown, the sign bit from register 87 i5 an input to flip flops 149, 151-1S3 and exclusive OR gates 160 and 161. OR
gates 154-159 receive decoder 102 output signals Xl - X6 and a clocking signal from AND gate 163. The output of OR gates 154-159 are the clocking inputs to flip-flops 148-153, respec~ively. The other input to exclusive OR gates 160 and 161 is the Q output of flip-10p 152. Finally, the Q out-puts of flip-flops 152 and 153 are the inputs to exclus,ive OR
gate 162. Flip-flops 148-151 produce, respectively, ~0, L~0 aT and L~T while gate 162 produces hFU.

The demodulator thus far explained employs diferential modulation where the phase of each channel at the demodulator tracks the corresponding modulator phase. This requires a phase word in the register 70 for each of the channels. How-ever, as explained above~ the diferential modulation is not essential and direct modulation can be used. ~ith direct modulation the modu~ating phase change is made with respect to a reference - such as one of the timing channels. Since the modulation can be decoded entirely within a single baud, a phase word memory is no longer required for each channel.
Assuming that the modulator phase is reset at the beginning of each baud time, then no phase memory at the demodulator is required across a baud boundary. Instead, the reference phase for any sampling time is generated as a function of frequency and time between the baud boundary and the sampling interval. Each other channel phase for the same sampling interval is obtained by merely adding a constant to the phase of the adjacent lower frequency channel~ Decision unit processing can also be simplified. A comparison is made bet-~een TC vector and nominal TC vector. The difference is 1 1~S~fi9 the reference vector a~ainst which other vectors are compared ~to derive the modulation.
If the switched network were free of distortion and noise, the information channel vectors would merely ha~e to be com-pared to the reference or timing channel to yield the modula-tion vectors.

However, because the phase and gain characteristics of the switched network are generally not flat w:ith respect to fre-quency, the values used for comparison must be adjusted for channel.s in different parts of the frequency spectrum.

The information channels nearest the reference or timing channel which may be in the middle of the spectrum are pro-cessed first. The closest received ~ector is determined and sub~racted from the actual normalized vector. The di~ference or error is an indication of the distortion characteristics.

~ased on the detected error vectors, the reference vector is adjusted ~or each transition from one channel to the next outer channel.
.
By progressing from ~he center channels to the outer channels and adjusting the reference vector at each step, the routine can track large values of phase and gain distortion without prior knowledge of the line characteristics~

Those skilled in the art will appreciate that many other changes can be made within the spirit and scope of the inven-tion. For example, the modulator disclosed herein marks the beginning of the correlation time be resetting phases of both timing channels to be equal and equal to zero. Neither is essential; any modulator which provides for a predetermined phase relationship between the timing channels at the begin-ning of the correlation time is adequate. In addition, as mentioned at the outset, the frequency correction for fre-quency offset, present in the demodulator, i.e., the FBW and 1 ~$S5~9 - ~5 -FCY inputs to aclder 73 can be eliminated by making this cor-rection at the modulator. More particularly, the signals FB~ and FC~r are transmitted back to the modulator where they are used, for example, at the adder 56, to compensate for frequency offset.

Claims (21)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY
OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A low baud rate high bit rate modem adapted for transmitting information through a switched network with compensation for frequency offset and with good tolerance to noise bursts, comprising:

a transmitter, including:

means for generating a plurality of harmonically related sub-carriers, means for modulating at least one characteristic of a plurality of said sub-carriers with modulating information, means for transmitting at least samples of said sub-carriers through a switched network, and a receiver including:

a sub-carrier generator for generating a plurality of sub-carriers each nominally identical in frequency to a different sub-carrier generated at said transmitter, correlating means responsive to signals received from said transmitter and said sub-carrier generator for correlation of the same and producing signals representing characteristics of said modulated sub-carriers, decision means responsive to said correlating means for producing signals corresponding to said modulating information and to detect frequency offset, distortion compensation means responsive to said decision means for compensating for said frequency offset by controlling said sub-carrier generator to increase or decrease the rate of change of sub-carrier phase, equally for all sub-carriers.

2. The modem of claim 1 wherein said means for generating a plurality of harmonically related sub-carriers generates representations of a plurality of sub-carriers, each a harmonic of a fundamental f0, said plurality including at least one timing sub-carrier, and information sub-carriers which are modulated once per baud time tb by said means for modulating in response to digital information signals, and wherein said receiver further includes:

analog-to-digital converting means coupled between said switched network and said correlating means to periodically produce a digital representation of a received signal and a timing unit for initiating operation of said analog to digital converting means, said timing unit responsive to said decision means with respect to correlation of a timing sub-carrier so that said analog-to-digital converting means is enabled only for a period t0, that is a period of the fundamental f0 but is less than the baud time tb.

3. The modem of claim 2 wherein said decision means responds to said correlating means with respect to correlation of the received signal with an identical timing sub-carrier and adjacent baud times.

4. The modem of claim 3 wherein said correlating means produces signals representing a pair of components of a vector defining amplitude and phase for at least one of said timing sub-carriers, and wherein said decision means includes means to detect phase rotation of the timing sub-carrier across a baud boundary for comparing said pair of components and adjacent baud intervals.

5. The modem of claim 4 wherein said receiver sub carrier generator includes means for generating a plurality of phase representing samples for each of said sub-carriers within each baud time, said means for generating a plurality of phase representing samples producing samples representing phase separated by a fixed increment of time, and frequency offset correction means for modifying each phase increment equally for each said sub-carrier in response to said detection of phase rotation of said timing sub-carrier.

6. The modem of any of claims 1-3 in which said receiver further includes means for detecting phase distortion separately for each sub-carrier and means for compensating for said phase distortion by advancing or retarding said sub-carrier generator.

7. The modem of any of claims 1-3, wherein said receiver further includes means for detecting amplitude distortion separately for each sub-carrier and means for compensating for said amplitude distortion by modifying a sub-carrier related parameter.

8. The modem of claim 2, wherein said correlating means produces signals representing a pair of components of a vector defining amplitude and phase of each of said plurality of information sub-carriers, and wherein said decision means includes means for subtracting a sub-carrier related parameter from each of said components to identify said modulating digital information and to also derive signals representing phase distortion and amplitude distortion, means for modifying said sub-carrier related parameter with said amplitude distortion representing signal and wherein said decision means responds to detection of phase distortion to control said receiver sub-carrier generator to compensate for said phase distortion.

9. The modem of claim 8, in which said receiver sub-carrier generator includes a register with at least a stage for each of said plurality of sub-carriers for storing in each stage a phase representing quantity, an adder coupling an output of said register back to an input of said register, said adder having an input for modifying a phase representing quantity and an output coupled to said correlating means.

10. The modem of claim 1, wherein said receiver sub-carrier generator further includes: means for periodically generating a signal representative of time related phase change coupled to said adder input, said last named means including means responsive to detected frequency offset for adjusting said time related phase change equally for each of said sub-carriers.

11. The modem of claim 10, wherein said means for generating sub-carriers includes a further register with at least one stage for each of said sub-carriers for storing sub-carrier amplitude representing information, and means for loading said further register at least once every baud time in response to said digital information signals.

12. The modem of claim 9, in which said adder input comprises: first means coupling phase change representing signals from said decision means, and second means for providing a signal representative of phase rate of change, said second means responsive to said decision means detection of frequency offset for adjusting said signal representative of phase rate of change equally for all said sub-carriers.

13. The modem of claim 12, in which said decision means includes: counter means for counting in one direction or another dependent upon the sense of detected frequency offset and for producing one output signal or another when said frequency offset exceeds a first or second threshold, and in which said second means responds to said one or another output signal for adjusting, in one sense or another, said signal representing phase rate of change.

14. The modem of claim 13, in which said decision means includes: generating means for generating an S signal representative of the sum of phase modulation and phase distortion for each of said information sub-carriers, means for generating an f.o. signal representative of frequency offset for each of said information sub-carriers, converting means responsive to said f.o.
signal for generating a p.c. signal representative of phase offset corresponding to said frequency offset for a predetermined time period for each of said information sub-carriers, an f.p.c. generating means for generating an f.p.c. signal representing phase change for a fixed time period for each of said information sub-carriers, and summing means for summing said S, p.c. and f.p.c. signals to generate said phase change representing signal for each of said information sub-carriers.

15. The modem of claim 9, in which said timing unit comprises: an oscillator and counter means driven thereby, said counter means having a ripple counter output and a clearing input, said counter means having further outputs for operating said receiver sub-carrier generator and said decision means, said ripple counter output representing termination of a baud time, and coupling means including a controllable delay responsive to said output signal for generating said clearing signal.

16. The modem of claim 15, in which said correlating means produces signals representing a pair of vector components defining amplitude and phase of at least two timing sub-carriers, and said decision means includes means generating a signal representative of sense and magnitude of phase difference between said timing sub-carriers, and means coupling said signal representative of sense and magnitude of said phase difference to said controllable delay.

17. The modem of claim 16, in which said decision means includes means to couple a further signal representative of sense and magnitude of phase difference between said timing sub-carriers to said receiver sub-carrier generator for compensation thereof.

18. The modem of claim 15, in which said coupling means includes summing means responsive to a succession of signals repre-sentative of a phase difference between said timing sub-carriers of identical sense for introducing a further delay between said output signal and generation of said clearing signal.

19. The modem of any of claims 1-3, wherein the transmitter includes means for accumulating a representation of each of said sub-carriers and transmitting a sum of said repre-sentations a fixed plurality of times within each baud time tb, and in the receiver said correlating means includes multiplying means for multiplying each digital representa-tion of a received signal by a quadrature offset samples of each of said plurality of sub-carriers and means for accumu-lating products of said multiplication for each sub-carrier for said baud time, and wherein said decision means includes:
means responsive to said accumulated products for comparing said accumulated products to a set of nominal products, each representing a different one of said digital informa-tion signals, to detect said digital information signal modulating a respective sub-carrier.

The modem of claim I, wherein said means for modulating modulates less than all said sub-carriers, said receiver including timing means responsive to unmodulated sub-carriers for detecting-frequency offset, said receiver sub-carrier generator including means to increment a phase word for each sub-carrier simulating phase change per unit time, said distortion compensation means including summing means to accumulate a running estimate of frequency offset, and means coupling signals from said summing means to said means to increment, to alter simulated phase change per unit time by a common amount for all said sub-carriers.

21. The modem of any of claims 1-3 in which said receiver further includes means for detecting phase distortion separately for each sub-carrier and means for compensating for said phase distortion by advancing or retarding said sub-carrier generator, and wherein said sub-carrier generator includes a shift register with a phase word stage for each said sub-carrier, a summer with a first input from said shift register and a phase increment input, and outputs to an input of said shift register and to trigonometric function apparatus, said phase increment input for said summer including an OR gate with a pair of inputs, and said dis-tortion compensation means including means coupling a phase increment signal to said OR gate.