CA1161956A - High speed data transfer for a semiconductor memory - Google Patents
High speed data transfer for a semiconductor memoryInfo
- Publication number
- CA1161956A CA1161956A CA000373194A CA373194A CA1161956A CA 1161956 A CA1161956 A CA 1161956A CA 000373194 A CA000373194 A CA 000373194A CA 373194 A CA373194 A CA 373194A CA 1161956 A CA1161956 A CA 1161956A
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
- G11C7/1033—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
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- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Abstract
HIGH SPEED DATA TRANSFER FOR A SEMICONDUCTOR MEMORY
ABSTRACT OF THE DISCLOSURE
A system is described for use in a semiconductor memory for rapidly transferring data between a plurality of successive memory locations and a data output buss.
The system includes a plurality of data latches for stor-ing data derived from successive locations in memory, and a corresponding plurality of serially coupled decoders, each associated with one of the data latches In response to an address input, one decoder is enabled for causing its associated data latch to output its stored data to the data buss. The latter decoder then disables itself and enables the next decoder so that a second latch out-puts its stored data. The process continues with each de-coder disabling itself and enabling the next decoder so that the data latches are caused to sequentially output their stored data.
ABSTRACT OF THE DISCLOSURE
A system is described for use in a semiconductor memory for rapidly transferring data between a plurality of successive memory locations and a data output buss.
The system includes a plurality of data latches for stor-ing data derived from successive locations in memory, and a corresponding plurality of serially coupled decoders, each associated with one of the data latches In response to an address input, one decoder is enabled for causing its associated data latch to output its stored data to the data buss. The latter decoder then disables itself and enables the next decoder so that a second latch out-puts its stored data. The process continues with each de-coder disabling itself and enabling the next decoder so that the data latches are caused to sequentially output their stored data.
Description
~ 3 ~3.g~6 HLGH SPEED DATA TRANSFER FOR A SEMICON~CTOR MEMOR~
BACKGF~OllND OF~ T~E INV NTION
The invention is directed generally to improve-ments in semiconductor memories, and particularly to a system for improving the speed with which data is trans-ferred to and from memory locations~
In computer systems and the like, it is fre-quently desired to rapidly read data stored in a nwnber of successive memory locations. In such circumstances, an indlvidual row and column address is not required for accessing the data in each ]ocation. All that is needed is the address of the first memory ]ocation and some means for automatically indexing the memory to the follow-in~ successive locations. Rapid writing of data into successive memory locations may be achieved in the same general manner.
Some conventional memories incorporate a feature referred to as "page mode" operation for rapidly reading the data stored in successive memory locations. In this 20 mode of operation, the data in one row of the memory is latched in a plurality of sense amplifiers. Then succes-sive column addresses are input to the memory to succes-sively output the data stored in each sense amplifier.
Because successive row addresses are not required to read the data in each successive location in the accessed row, a two-to-one time savings is achieved in reading data.
However, the ratio of a standard read~write cycle time to page mode cycle time (typically a factor of two) is frequently not large enough to warrant the added system 30 complexity required to implement page mode operation. The present invention overcomes this problem by providing a much faster rate of data read and wr;te.
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The invention generally seeks to provi.de an improved system for rapidly transferring data to and from successive memory locations in a semiconductor memory and more specific-ally to provide such a system which transfers data more rapidly and with less complexity than conventional page mode systems.
SUMMARY OF THE INVENTION
The present invention causes data stored in success-ive locations in a semiconductor memory to be rapidly read out of memory in response to a single address input.
The invention pertains to a semiconductor memory in which is provided a system for rapidly transfe~ring data between a plurality of successive memory locations and a data output buss in response to a single address input. The system comprises a plurality of N data latches for storing data associated with N successive memory locations which are defined by a plurality of bits of the address input, and a corresponding plurality of N serially connected decoders each associated with one of the data latches. Bach decoder is adapted to be enabled for causing its associated data latch to output its stored data to the data buss and each receives selected bits of the address input such that one of the decoders is initially enabled, in response to the selected bits having a given logic state, for causing its associated data latch to output its stored data to the data buss. The enabled decoder is adapted to then disable itself and to enable a successive decoder, the latter decoder and each remaining decoder being adapted to disable itself after having been enabled and to enable a successive decoder so as to cause the data latches to output, to the data buss, N successive bits of data in response to a single address input.
The invehtion also comprehends a semiconductor memory having a read mode and a write mode wherein a system for rapidly writing incoming data into four successive memory locations and for reading data out of four successi~e memory locations, includes four data latches Eor storing data associated with four successive memory locations which are de~ined by a plurality of bits of the address input, each data latch being adapted to output its stored data when selected by an enabled decoder.
The system lncludes four data input buffers each having an in-put for receiving incoming data, an output for coupling the data to memory, and each being adapted to output the data to memory t~
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wh~n selected by an enabled decoder. Four serially connected decoders are each associated with one of the data latches and with one of the input buffers, and each receives selected bits of the address input such that one of the decoders is initially enabled in response to the address input for selecting its associated data latch when the memory is in a read mode and for selecting its associated input buffer when the memory is in a write mode. The enabled decoder is adapted to disable itself and enable a successive decoder, the latter decoder and each remaining decoder being adapted to disable itself after having been enabled and to enable a successive decoder so as to rapidly write four bits of data into successive memory locations when the memory is in the write mode and to rapidly read four bits of data out of successive memory locations when the memory is in the read mode.
In the preferred embodiment, rapid writing of data in-to memory is effected by including N data buffers. The buffers receive incoming data and are adapted to output that data to N
successive memory locations when the memory is in its write mode. Each buffer is controlled by one of the decoders which are sequentially enabled as described above. When enabled, a decoder causes its associated buffer to output its data to memory. Hence, the N buffers are sequentially selected to cause the incoming data to be written into N successive memory locations.
BRIEF_ DESCRIPTIO~J OF T~E FIGURES
The objects stated above and other objects of the invention are set forth more particularly in the following detailed description and in the accompanying drawings, of which:
FIG. 1 is a block diagram of a system according to the invention for rapidly transferring data between successive memory locations and a data output buss;
FIG. 2 depicts waveforms useful in describing the system of Fig. l;
FIG~ 3 is a circuit diagram ,illustrat.ing the pre-ferred construction of each of the decode,rs of Fig. l;
FIG. 4 is a circuit diagram showi,ng the preferred construction of each of the data input buffers of Fig. l;
FIG. 5 is an inclex relating the signals generated by the circuitry of Fig. 3 to the various decoders of Fig. l;
and FIGo 6 illustra-tes the waveforms of various signals associated with the circuitry of Figs. 3 and 4.
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DESCRIPTION OF T~IE PREF~RRED EMBODIMENT
Referring now to Fig. 1, -there is shown a system for rapidly reading data from and writing data into ~uccessive locations in a semiconductor memory. In the preferred embodiment, "nibble mode" operation is effected whereby four bits of data are read from or written into four successive memory locations in response to a single address input.
The system includes four data latches, shown as output sense amplifiers A0, Al, A2, and A3, and four decoders D0, Dl, D2, and D3, each of the latter being associated with one of the sense amplifiers. The sense amplifiers store four bits of data, one bit per sense amplifier, received from four successive memory locations which are identified by six bits of an eight bit address input. Generally, each of the decoders is adapted to be enabled for causing its associated sense amplifier to output stored data to a data buss 10 via an output latch 12. To initiate the output of data, each decoder receives two bits of the address input such that one of the decoders, D0 for example, is enabled in response to the selected two address bits having a given logic state for causing the sense amplifier A0 to output a bit of stored data. Then the enabled decoder disables itself and enables a successive decoder, Dl for ex-ample, so that its sense amplifier Al outputs its stored data.
The cycle continues with each decoder disabling itself and enabling the next decoder so that the sense amplifiers are enabled in succession. Thus, four bits of data are output to the data buss 10 in response to a single address input.
As described hereinafter, the decoders D0-D3 are also adapted to be successively enabled for causing four associated data input buffers, B0-B3, to successively apply four bits of input data to four successive locations in memory in response to a single address input. Thus, the illustrated system operates in the "nibble mode" to effect rapid writing of data into memory and rapid reading of data out of memory.
More specifically, the output sense amplifier A0 is adapted to store a data bit and its complemen~ received ~ .
~ 1 6 ~
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~ 5 --from a memory location via data busses identiPied as DBo and DBo. The amplifier Al is adapted to store a dàta bit and its complement received from a successive memory location via data busses Dsl and Dsl. The amplifiers A2 and A3 are likewise adapted to store data bits and their complements received via busses Ds2, Ds2, and DB3, DB3, respectively. The data bits carried by the busses DBo-DB3 (and their complements) are received from four successive memory locations which are defined by six bits of an eight bit address input to the memory.
The output of the amplifier A0 is coupled to the drains of ~OS transistors 14 and 16, and the sources of the latter transistors are coupled via leads 18 and 20 to the input of the output latch 12. Thus, when the transistors 14 and 16 are turned on, the data stored in the amplifier A0 is coupled to the output buss 10 via the latch 12. In a similar manner, the amplifiers Al-A3 are coupled to the output latch 12 by means of transistors 22, 24, 26, 28, 30, and 32.
2Q The decoder D0 receives two selected bits, A0 and Al, of the input address via leads 34 and 36. The remaining decoders Dl-D3 receive the same address bits, but in different logic combinations, so that only one de-coder will be initially selected or enabled. The decoder Dl, for example, receives A0 and Al, the decoder D2 receives A0 and Al and the decoder D3 receives A0 and Al.
Thus, when A0 and Al are both at a low logic level, the decoder D0 is enabled. Consequently, the decoders Dl-D3 are all aisabled. However, when the A0 and Al are both at a low logic level, the decoder Dl is enabled and the other decoders are disabled. Suffice it to say that the decoders' input bits will have a ~iven logic state which will enable any one of the decoders DO-D3. The enablement of the re maining decoders is described below.
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The decoders D0-D3 also preferably receive a clock signal identified as 0POF A~ter a decoder has been selected, the signal 0POF clocks its operation as described below.
Assuming now that the decoder D0 is selected by each of the bits A0 and Al being at a low level, the decoder D0 develops an output signal Y0 when the clock signal 0POF goes low at time tl, as shown in Fig. 2. The signal Y0 is coupled via a lead 38 to the gates of tran-sistors 1~ and 16 for -turning them on. Hence, the data stored in the amplifier A0 is coupled via transistors 14 and 16 to the leads 18 and ~0, to the output latch 12, and then to the output buss 10. The high or low level data output thus applied to the buss 10 is represented by D0 in Fig. 2.
The decoder D0 then disables itself to turn off the transistors 14 and 16 and couples its output signal Y0 to the next successive decoder Dl via a lead 40. In response to the signal on the lead 40, the decoder Dl is selected so that when the signal ~POF goes low again at time t2 (Figure 2), it develops an output signal Yl on lead 42 for turning on transistors 22 and 24. Hence, out-put data Dl (Figure 2) from the amplifier Al is coupled to the output buss 10. The decoder Dl then disables itself to turn off the transistors 22 and 24 and couples - its signal Yl to the decoder D2 to select the latter for enablement. The process described above continues so that the decoders D2 and D3 are successively enabled for causing the output of ~ata D2 and D3 (Figure 2) in synch-ronism with the clock pulse 0POF
After the data has been read out of theamplifier A3, the decoder D3 selects the decoder D0 via a signal Y3 on a lead 44. Hence, each o~ the decoders may be selected for another cycle of rapid dat~ reading.
Alternately, the nibble rcad cycl~ descr:i~e~ above may 'l~e 1 -~ 6.~9~ ( ~ollowed by a conventional read cycle as shown in Fig. 2.
It should be understood that the nibble mode cycle may start with whatever decoder is first selected by a pair of low logic level input bits. Thereafter, the other decoders are successively selected until the four sense amplifiers A0-A3 have output their stored data.
To effect a nibble write mode, each of the data input buffers is coupled to associated data busses and receives input data via a pair of transi,stors which are controlled by one of the decoders. For example, the buffer B0 receives an input data bit Din and its comple-ment Din via transistors ~6 and 48. The output o~ the buffer B0 is coupled to the data busses DBo and DBo. The buffers Bl-B3 are similarly connected to couple input data to their respective data busses. With the memory in a write mode, the decoder D0 may be enabled as described previously for turning on the transistors 46 and 48 for coupling the input data to the busses DBo and DBo. The decoders Dl-D3 are then successively enabled a5 described above for reading three more bits of input data to the remaining busses. In this manner, four bits of input data may be rapidly written into four successive locations in memory.
In Fig. l, the output sense amplifiers AO~A3 and the output latch 12 may be conventional. The decoders D0-D3 are all' the same, each being,preferably constructed as shown in Fig. 3. The buffers B0-B3 are also of the same construction, one of which is shown in Fig. 4.
Fig. 6 depicts wave~orms of the various inpu~ signals, output signals and clock signals associated with the circuitry of Figs. 3 and 4.
Fig. 5 is an index which relates the signals developed by the circuitry of Figure 3 to the various decoders. For example, where the circuitry of Fig. 3 represents the decoder D0, Yi is the s;gnal Y0 developed by the decoder D0, and Yi+3 is the siynal Y3 developed by the decoder D3. Where the circuitxy of Flg. 3 repre-sents the decoder Dl, Yi represents the signal Y1 developed by the decoder Dl and Yi~3 represents the signal Y0 developed by the decoder Y0.
Referring now to Fig. 3, the illustrated decoder receives its address inputs A0 (or A0) arld Al (or Al) at the gates of transistors 50 and 52. An output lead 54 carries the output signal Yi developed by the decoaer~
That output is employed to cause t-ne decoder's associated sense amplifier to output its stored data, and it is also applied to the gates of transistors 56 and 58. In the case where the illustrated decoder represen'cs the decoder D0, the signal Yi represents the signal Y0 shown in ~
Fig. 1.
A signal identified as Yi+3 is applied to the gate of a transistor 60. In the case where the illustrated decoder is D0, the signal Yi+3 is the signal Y3 shown in Fig. 1 and corresponds to the Yi output of the decoder D3.
The illustrated decoder receives a precharge signal ~D (see Fig. 6) which is initially high and which is applied to the gate of a transistor 62 for raising its source (node 64) to a high level. Ano-ther clock signal, 00D2 (Fig. 6) is also high and is applied to the gate of a transistor 66 which is coupled to the node 64. ~ence, the drain of transistor 66 (node 68) is also driven high.
The signal 0D is also applied to the gat~ of a transistor 70 for precharging node 72 to a high level, Consequently, transistors 74 and 76 are turned on ~or pull-ing their drain connections (nodes 78 and 80) ~o a lowlevel.
The gate of another transistor 82 receiyes 0D for raising the voltage at node 8~ so as to turn on transiStors 86 and 88 and pull their drain connections (nodes 90 and 92) to a low level. A transistor 94 w}-ich is ccuplea to tne - ~ 3 ~19~
node 90 via its gate is thus turned off, as is a transis-tor 96 whose gate is coupled to node 92. The source of the transistor 96 is coupled via a node 98 to a transis-tor 100 whose gate receives the signal 0~. Consequently, the latter transistor is turned on to lower the voltage at the node 98. A transiStOr 102 whose gate is also coupled to the node 98 is therefore turned off. The drain of the latter transistor is coupled to the node 64 but, since the latter transistor is now off, it doe5 not ;~
disturb the high level to which the node 64 is precharged The signal ~POF (see Figs. 1 and 6) is high at this time and is applied to a transistor 104 wh~se gate is coupled to the node 78 and whose source is coupled to the node 80. Because the node 78 is at a low level, the transistors 104 is held off and the node 80 remains at a low level. The node 80 is also coupled to the gate of another transistor 106 which is also held off at this time.
The signal 0POF is also applied to the transis-tor 94. Because the gate of the transistor 94 is coupledto the low level on node 90, the transistor 94 remains off and the potential at its source (node 92) remains low.
Assuming now that the address inputs A0, Al to the transistors 50 and 52 are low, both the latter transis-tors remain off. Consequently, the llode 64 remains at a high level as does the node 68. The latter noae is coupled to the gate of a transistor 108 whose drain receives the signal 0YO. Because ~YO is high (see Fig- 6~, the transis-tor 108 develops a high level output Yi at the lead 54.
The lead 54 is also coupled to the drain of a transistor 109 whose gate lead 111 is coupled (via a connection which is not shown) to the node 80. It will be recalled that the node 80 was pulled low during the pre-charge cycle. Hence, the transistor 109 is held off to permit the signal Yi at lead 5~ to yo h:i~h. Thus, in the B
case where the illustrated decoder represents the decoder D0 (Fig. 1), Yi represents Y0 and the transistors 1~ and 16 (Fig. 1) are turned on. All the other decoders are off because at least one of their address inputs is high.
Consequently, at least one of the transistors ~hich cor-responds to transistors 50 and 52 in the other decoders is turned on for pulling low the voltage a-t nodes corre-sponding to nodes 64 and 68, thereby inhibiting ~Y0 from driving Yi high in the other decoders.
As stated previously, each of the decoders is adap-ted to disable itself after its associated sense amplifier has output its stored data.- For this purpose, the signal ~i at lead 54 is coupled to the gate of a transistor 110 via a lead 112 and also to the gate of transistor 58. Consequently, node 84 is pulled low to turn off transistors 86 and 88. In addition, transistor 110 is turned on to raise the potential at node 90 for turning on the transistor 94. When ~POF goes high again at time Ta lFig. 6), that high level is coupled to the 20 node 92 by the transistor 94. Consequently, transistor 96 turns on to drive the node 98 high, and transistor 102 turns on for pulling node 64 low. IIence, the decoder is disabled so that the next time the signal 0Y0 goes high, the output Yi will not be driven high.
Referring briefly to Fig. 6, it can be seen that, when 0POF goes high at time Ta, ~Y0 goes lowO The latter signal going low causes the output Yi at lead 54 to go low also.
Assuming that the operation described above relates to the decoder D0, the latter decoder will enable the decoder Dl for activation by the next hi9h level pulse from ~POF. To explain this phase of the operation, it will now be assumed that the circuitr~ shown in Fig. 3 represents the decoder Dl (all the decoders are construct-ed as shown in Fig. 3). Thus, the Yi~3 in~,ut to the decoder Dl represents the Yi output o~ the decoder D0.
When the ~i output of the decoder D0 went h:igh,the Yi+3 input to the decoder Dl was driven high at the gate of the transistor 60. Iience, the node 78 was driven high and turned the transistor 104 on. I~hen 0POF went high at time Ta, the transistor 104 pulled the node 80 high and turned on transistor 106. Because the source of the transistor 106 is coupled to the node 64, the latter node was driven high. 00D2 also went high at tlme Ta.
Hence, the node 68 was also pulled high. But because 0Y0 went low then, the transistor 108 held the Yi output of the decoder Dl at a low level. ~owever, when ~Y0 goes high at time tb (Fig. 6), the Yi output at lead 54 is pulled high.
The operation described above continues for each nibble cycle so that the ith decoaer primes the ith plus 1 decoder to fire when 0Y0 goes high.
Each decoder also includes an active hold off circuit coupled to the Yi output lead 54. This circuit 20 includes transistors 112, 114, 116, 118, and 120 which are arranged to actively hold the Yi output of the un-selected decoders at a low level.
The gates of transistors 114 and 120 each re-ceive the 0POF signal, wherefore their sources (nodes 122 25 and 124) are pulled to a high level during the precharge cycle. The gate of transistor 118 receives the ~YO signal so that, when that signal goes high, the drain of transis-tor 118 (node 124) is pulled low.
If node 64 is low (indicating that the decoder 30 is not selected), the transistor 116 remains of~ and the node 122 remains high. Consequently, the transistor 112 is turned on to hold the lead 54 at ground potential~
In the case in which the node 64 is high, the transistor 116 is turned on to pull node 122 low and hold 35 the transistor 112 off -to ~ermit the lead 54 to ~e ~riven ~ 16:195~
to a high level.
Referring now to Fig. 4, a data input buffer is shown whose construction is preferably of the type used for each of the buffers B0-B3 of Fig. 1. The illu-strated buffer includes input leads 126 and 128 for re-ceiving externally applied Din and Din data inputs and outputs leads 130 and 132 whic'n couple DBi and DBl out-puts to the data busses (such as DBo and DBo) of Fig. 1.
Other inputs include leads 134 and 136 which couple to node 64 of Fig. 3, lead 138 which couples to node 80 of Fiy. 3~ and lead 140 which couples to node 9Z of Fig. 3.
As described in detail below, an enabled decoder acti-vates its associated buffer to cause the latter to couple the data input (Din and Din~ to the DBi and DBi outputs.
When the decoder which is associated with the illustrated buffer is not enabled, the potential at the decoder's node 64 is low. That low level potential is coupled via the lead 134 to transistors 142 and 144 whose gates receive the signal ~OD2. Conse~uently, the sources (nodes 146 and 148) of transistors 142 and 144 are at a low level.
Nodes 146 and 148 are directly connected to the gates of transistors 150 and 152 which receive the Din and Din inputs. With nodes 146 and 148 at a low level, these transistors remain off to decouple the Din and ~in inputs from the output leads 130 and 132.
When the decoder which is associated with the illustrated buffer is enabled, the potential at the de-coder's node 64 is high. Consequently, buffer nodes 146 and 148 are both high and transistors 150 and 152 are turned on. In the case where the Din input is high and the Din input is low, the sources of transistors 150 and 152 (nodes 154 and 155) are driven hiyh and low, respectively.
l 9 ~ ~ 1 The node 154 is coupled to the gates o transistors 158 and 160, while -the no~e 156 is coupled to the gates of transistors 162 and 164. Consequently, transistors 162 and 164 are turned off and transistors 5 158 and 160 are turned on. Hence, the lead 130 is driven to a high level and the lead 132 is driven to a low level. The data coupled to leads 130 and 132 is thus written into a selected memory location via one of the data buss pairs of Fig. ~.
It will be appreciated that writing data into memory is a relatively time consuming operation. There-fore, the data output from the illustrated buffer is held available for reading even after the next successive de-- coder and buffer are enabled on the next nibble cycle.
15 Toward this end, transistors 166 and 163 are included to trap the logic levels on nodes 154 and 156, so that the logic leve!ls imposed on output leads 130 and 132 remain unchanged for the next three nibble cycles.
The gates of transistors 166 and 168 are 20 coupled via the lead 140 to node 92 in Fig. 3. The latter node is driven to a high level when 0POF goes high at the beginning of a nibble cycle. Consequently, transistors 166 and 168 are turned on. Because their drains are coupled to the gates of transistors 150 and 152, the 25 latter transistors are turned off. Thus, the high and ]ow levels previously applied to nodes 154 and 156 are trapped there. Hence, transistors 158 and 160 are held on while transistors 162 and 164 are held off. The high and low levels appearing on leads 130 and 132, respective 30 ly, are thus maintained. Hence, the write cycle time is shortened because writing can overlap into three succeed-ing cycles.
The illustrated buffer also preferably includes a pair of active hold off circuits to hold the bu~fer in-35 sensitive to further data inputs ~hen its associated r- ~61g56 decoder is disabled. The first hold off circuit ir,c]udes transistors 172, 174, 176, 17~, 180, 182, and 183. The other includes transistors 184, 186, ]88, 190, 192, lg4 and 196.
Referring to the first hold off circuit, the gates of transistors 174 and 180 receive the signal ~D
for precharging nodes 198 and 200 to a high level. The Din input is coupled via a lead 20Z to the gate of tran-sistor 182 so that, when Din is high, node 200 i.5 pulled low.
The gate of transistor 176 is coupled via lead 136 to node 64 in Fig. 3, its source is coupled to node 200,- and its drain is coupled to node 198. Thus, if the buffer's decoder is enabled, node 64 is high, transistor 176 is on, and node 198 is pulled low. Hence, transistor 183 is turned off and the potential at its drain (node 154) is allowed to vary in response to the Din input at lead 126_ If the illustrated buffer's decoder had been disabled, node 64 in that decoder would be low, where~ore transistor 176 would be off and node 198 would be at a high level. Consequently, transistor 183 would be on to pull the node 154 to ground potential.
The other hold off circuit operates in a manner similar to that described above. Suffice it to say that when the buffer's decoder is enabled, the transistor 196 remains off to allow node 156 to vary in response to the Din input at lead 128~ Otherwise, transistor 196 is on to hold node 156 at ground potential.
It is often desirable to write a full Vcc vol-tage into memory locations. In the present embodiment nodes 154 and 156 are boosted above Vcc to accomplish this, partly by driving Din and Din to 1.4 tim~s Vcc and partly by including capacitors 204 and 206 which are 35 coupled to nodes 154 and 156, res~ectively, and w;lich T ~ ;J 6 receive ~POF With this arrangement, the potentials at nodes 154 and 156 are driven even higher when ~pO~ rises.
Another feature which improves the speed of the Y ~OD2 g- 6, 00D2 generally follows 0POF' but ~OD2 varies between 7 volts and 4 volts whereas ~POF varies between 5 volts and zero volts. The use of ~OD2 considerably shortens the pre-charge portion of the nibble cycle as demonstrated by the comrnents below.
It-will be understood that it is desirable to drive the signal Yi (at lead 54) up to Vcc (five volts, for example). To do this, the voltage a~ lead 68 is driven higher than Vcc, preferably toward seven volts, in the following manner. Referring to Figure 6, it can be seen that 00D2 drops from seven volts to four volts just prior to 0yo going high at time tb. Just prior to that occurrence, ~pof had been high to precharge node 64 to about our volts via transistors 104 and ]06. ~ence, the transistor 66 has Eour volts at its gate and about four volts at its source. In this state, the transistor 66 is cut off, thereby releasing or isolating node 68 from node 64. Accordingly, when ~yo goes high to raise the voltage at the drain of transistor 108, node 68 is bootstrapped to about seven volts by the gate-to-drain capacity of the transistor and Yi is driven high. Had transistor 66 not been cut off by 00D2' node 68 would not have been released from the node 64, no such bootstrapping would have occurred, and the signal Yi would not have been driven to as high a level as is desired.
It will be appreciated that the transistor 66 could have been cut off by causing node 64 to be pre-charged to a higher level. However, the additional tirne required for such precharging to occur would lengthen the time required to enable the decoder. With the l l 61~6 illustrated arrangement, the decoder's enabling time is kept short while still retaining the ahility to bootstrap the node 68 and drive the s;gnal Yi up to Vcc.
An arrangement utilizing ~OD2 in a similar manner is shown in Figure 4 in which buffer noaes 146 and 148 are quickly released from node 64 when 0OD2 falls to four volts r thereby permitting efficient bootstrapping to occur at nodes 146 and 148.
T,he present system may be used with a pair of memories, each of which operate in the nibble mode.
Conventionally, each such memory is controlled by RAS
and CAS clocks to define the precharge and active (read or write) cycles. A first memory may have RAS and CAS
going low to initiate a nibble read (or write) cycle while a second memory is in a precharge mode. Then the RAS and CAS clocks in the first memory may be driven high to precharge the first memory while RAS and CAS in the second memory go low to initiate a nibble read cycle therein. By so stagyering the RAS and CAS clocks for both memories, a bit of data may be read for each nibble cycle for an indefinite period of time.
One of the advantages of the illustrated decoder and buffer is that virtually no D.C. power is consumed and reliable operation is obtained at low precharge voltages.
Of course, very high speed operation is obtained by vir-tue of each decoder disabling itself and enabling a suc-cessive decoder. In addition, input data is easily and rapidly read by virtue of the fact that each buffer maintains the status of its data outputs through four nibble cycles.
Although the invention has been described in terms of a preferred embodiment, it will be obvious to those skilled in the art that many modifications and alterations may be made without depart,ing from the invention. Accordingly, it is intended that all such 111 B19~6 f modifications and alterations be cons:idered as within the spirit and scope of the invention as defined hy the appended claims.
BACKGF~OllND OF~ T~E INV NTION
The invention is directed generally to improve-ments in semiconductor memories, and particularly to a system for improving the speed with which data is trans-ferred to and from memory locations~
In computer systems and the like, it is fre-quently desired to rapidly read data stored in a nwnber of successive memory locations. In such circumstances, an indlvidual row and column address is not required for accessing the data in each ]ocation. All that is needed is the address of the first memory ]ocation and some means for automatically indexing the memory to the follow-in~ successive locations. Rapid writing of data into successive memory locations may be achieved in the same general manner.
Some conventional memories incorporate a feature referred to as "page mode" operation for rapidly reading the data stored in successive memory locations. In this 20 mode of operation, the data in one row of the memory is latched in a plurality of sense amplifiers. Then succes-sive column addresses are input to the memory to succes-sively output the data stored in each sense amplifier.
Because successive row addresses are not required to read the data in each successive location in the accessed row, a two-to-one time savings is achieved in reading data.
However, the ratio of a standard read~write cycle time to page mode cycle time (typically a factor of two) is frequently not large enough to warrant the added system 30 complexity required to implement page mode operation. The present invention overcomes this problem by providing a much faster rate of data read and wr;te.
l.~
- ~ ~
The invention generally seeks to provi.de an improved system for rapidly transferring data to and from successive memory locations in a semiconductor memory and more specific-ally to provide such a system which transfers data more rapidly and with less complexity than conventional page mode systems.
SUMMARY OF THE INVENTION
The present invention causes data stored in success-ive locations in a semiconductor memory to be rapidly read out of memory in response to a single address input.
The invention pertains to a semiconductor memory in which is provided a system for rapidly transfe~ring data between a plurality of successive memory locations and a data output buss in response to a single address input. The system comprises a plurality of N data latches for storing data associated with N successive memory locations which are defined by a plurality of bits of the address input, and a corresponding plurality of N serially connected decoders each associated with one of the data latches. Bach decoder is adapted to be enabled for causing its associated data latch to output its stored data to the data buss and each receives selected bits of the address input such that one of the decoders is initially enabled, in response to the selected bits having a given logic state, for causing its associated data latch to output its stored data to the data buss. The enabled decoder is adapted to then disable itself and to enable a successive decoder, the latter decoder and each remaining decoder being adapted to disable itself after having been enabled and to enable a successive decoder so as to cause the data latches to output, to the data buss, N successive bits of data in response to a single address input.
The invehtion also comprehends a semiconductor memory having a read mode and a write mode wherein a system for rapidly writing incoming data into four successive memory locations and for reading data out of four successi~e memory locations, includes four data latches Eor storing data associated with four successive memory locations which are de~ined by a plurality of bits of the address input, each data latch being adapted to output its stored data when selected by an enabled decoder.
The system lncludes four data input buffers each having an in-put for receiving incoming data, an output for coupling the data to memory, and each being adapted to output the data to memory t~
1 '3~
wh~n selected by an enabled decoder. Four serially connected decoders are each associated with one of the data latches and with one of the input buffers, and each receives selected bits of the address input such that one of the decoders is initially enabled in response to the address input for selecting its associated data latch when the memory is in a read mode and for selecting its associated input buffer when the memory is in a write mode. The enabled decoder is adapted to disable itself and enable a successive decoder, the latter decoder and each remaining decoder being adapted to disable itself after having been enabled and to enable a successive decoder so as to rapidly write four bits of data into successive memory locations when the memory is in the write mode and to rapidly read four bits of data out of successive memory locations when the memory is in the read mode.
In the preferred embodiment, rapid writing of data in-to memory is effected by including N data buffers. The buffers receive incoming data and are adapted to output that data to N
successive memory locations when the memory is in its write mode. Each buffer is controlled by one of the decoders which are sequentially enabled as described above. When enabled, a decoder causes its associated buffer to output its data to memory. Hence, the N buffers are sequentially selected to cause the incoming data to be written into N successive memory locations.
BRIEF_ DESCRIPTIO~J OF T~E FIGURES
The objects stated above and other objects of the invention are set forth more particularly in the following detailed description and in the accompanying drawings, of which:
FIG. 1 is a block diagram of a system according to the invention for rapidly transferring data between successive memory locations and a data output buss;
FIG. 2 depicts waveforms useful in describing the system of Fig. l;
FIG~ 3 is a circuit diagram ,illustrat.ing the pre-ferred construction of each of the decode,rs of Fig. l;
FIG. 4 is a circuit diagram showi,ng the preferred construction of each of the data input buffers of Fig. l;
FIG. 5 is an inclex relating the signals generated by the circuitry of Fig. 3 to the various decoders of Fig. l;
and FIGo 6 illustra-tes the waveforms of various signals associated with the circuitry of Figs. 3 and 4.
, '1~
DESCRIPTION OF T~IE PREF~RRED EMBODIMENT
Referring now to Fig. 1, -there is shown a system for rapidly reading data from and writing data into ~uccessive locations in a semiconductor memory. In the preferred embodiment, "nibble mode" operation is effected whereby four bits of data are read from or written into four successive memory locations in response to a single address input.
The system includes four data latches, shown as output sense amplifiers A0, Al, A2, and A3, and four decoders D0, Dl, D2, and D3, each of the latter being associated with one of the sense amplifiers. The sense amplifiers store four bits of data, one bit per sense amplifier, received from four successive memory locations which are identified by six bits of an eight bit address input. Generally, each of the decoders is adapted to be enabled for causing its associated sense amplifier to output stored data to a data buss 10 via an output latch 12. To initiate the output of data, each decoder receives two bits of the address input such that one of the decoders, D0 for example, is enabled in response to the selected two address bits having a given logic state for causing the sense amplifier A0 to output a bit of stored data. Then the enabled decoder disables itself and enables a successive decoder, Dl for ex-ample, so that its sense amplifier Al outputs its stored data.
The cycle continues with each decoder disabling itself and enabling the next decoder so that the sense amplifiers are enabled in succession. Thus, four bits of data are output to the data buss 10 in response to a single address input.
As described hereinafter, the decoders D0-D3 are also adapted to be successively enabled for causing four associated data input buffers, B0-B3, to successively apply four bits of input data to four successive locations in memory in response to a single address input. Thus, the illustrated system operates in the "nibble mode" to effect rapid writing of data into memory and rapid reading of data out of memory.
More specifically, the output sense amplifier A0 is adapted to store a data bit and its complemen~ received ~ .
~ 1 6 ~
.
~ 5 --from a memory location via data busses identiPied as DBo and DBo. The amplifier Al is adapted to store a dàta bit and its complement received from a successive memory location via data busses Dsl and Dsl. The amplifiers A2 and A3 are likewise adapted to store data bits and their complements received via busses Ds2, Ds2, and DB3, DB3, respectively. The data bits carried by the busses DBo-DB3 (and their complements) are received from four successive memory locations which are defined by six bits of an eight bit address input to the memory.
The output of the amplifier A0 is coupled to the drains of ~OS transistors 14 and 16, and the sources of the latter transistors are coupled via leads 18 and 20 to the input of the output latch 12. Thus, when the transistors 14 and 16 are turned on, the data stored in the amplifier A0 is coupled to the output buss 10 via the latch 12. In a similar manner, the amplifiers Al-A3 are coupled to the output latch 12 by means of transistors 22, 24, 26, 28, 30, and 32.
2Q The decoder D0 receives two selected bits, A0 and Al, of the input address via leads 34 and 36. The remaining decoders Dl-D3 receive the same address bits, but in different logic combinations, so that only one de-coder will be initially selected or enabled. The decoder Dl, for example, receives A0 and Al, the decoder D2 receives A0 and Al and the decoder D3 receives A0 and Al.
Thus, when A0 and Al are both at a low logic level, the decoder D0 is enabled. Consequently, the decoders Dl-D3 are all aisabled. However, when the A0 and Al are both at a low logic level, the decoder Dl is enabled and the other decoders are disabled. Suffice it to say that the decoders' input bits will have a ~iven logic state which will enable any one of the decoders DO-D3. The enablement of the re maining decoders is described below.
6~.g~ ~
The decoders D0-D3 also preferably receive a clock signal identified as 0POF A~ter a decoder has been selected, the signal 0POF clocks its operation as described below.
Assuming now that the decoder D0 is selected by each of the bits A0 and Al being at a low level, the decoder D0 develops an output signal Y0 when the clock signal 0POF goes low at time tl, as shown in Fig. 2. The signal Y0 is coupled via a lead 38 to the gates of tran-sistors 1~ and 16 for -turning them on. Hence, the data stored in the amplifier A0 is coupled via transistors 14 and 16 to the leads 18 and ~0, to the output latch 12, and then to the output buss 10. The high or low level data output thus applied to the buss 10 is represented by D0 in Fig. 2.
The decoder D0 then disables itself to turn off the transistors 14 and 16 and couples its output signal Y0 to the next successive decoder Dl via a lead 40. In response to the signal on the lead 40, the decoder Dl is selected so that when the signal ~POF goes low again at time t2 (Figure 2), it develops an output signal Yl on lead 42 for turning on transistors 22 and 24. Hence, out-put data Dl (Figure 2) from the amplifier Al is coupled to the output buss 10. The decoder Dl then disables itself to turn off the transistors 22 and 24 and couples - its signal Yl to the decoder D2 to select the latter for enablement. The process described above continues so that the decoders D2 and D3 are successively enabled for causing the output of ~ata D2 and D3 (Figure 2) in synch-ronism with the clock pulse 0POF
After the data has been read out of theamplifier A3, the decoder D3 selects the decoder D0 via a signal Y3 on a lead 44. Hence, each o~ the decoders may be selected for another cycle of rapid dat~ reading.
Alternately, the nibble rcad cycl~ descr:i~e~ above may 'l~e 1 -~ 6.~9~ ( ~ollowed by a conventional read cycle as shown in Fig. 2.
It should be understood that the nibble mode cycle may start with whatever decoder is first selected by a pair of low logic level input bits. Thereafter, the other decoders are successively selected until the four sense amplifiers A0-A3 have output their stored data.
To effect a nibble write mode, each of the data input buffers is coupled to associated data busses and receives input data via a pair of transi,stors which are controlled by one of the decoders. For example, the buffer B0 receives an input data bit Din and its comple-ment Din via transistors ~6 and 48. The output o~ the buffer B0 is coupled to the data busses DBo and DBo. The buffers Bl-B3 are similarly connected to couple input data to their respective data busses. With the memory in a write mode, the decoder D0 may be enabled as described previously for turning on the transistors 46 and 48 for coupling the input data to the busses DBo and DBo. The decoders Dl-D3 are then successively enabled a5 described above for reading three more bits of input data to the remaining busses. In this manner, four bits of input data may be rapidly written into four successive locations in memory.
In Fig. l, the output sense amplifiers AO~A3 and the output latch 12 may be conventional. The decoders D0-D3 are all' the same, each being,preferably constructed as shown in Fig. 3. The buffers B0-B3 are also of the same construction, one of which is shown in Fig. 4.
Fig. 6 depicts wave~orms of the various inpu~ signals, output signals and clock signals associated with the circuitry of Figs. 3 and 4.
Fig. 5 is an index which relates the signals developed by the circuitry of Figure 3 to the various decoders. For example, where the circuitry of Fig. 3 represents the decoder D0, Yi is the s;gnal Y0 developed by the decoder D0, and Yi+3 is the siynal Y3 developed by the decoder D3. Where the circuitxy of Flg. 3 repre-sents the decoder Dl, Yi represents the signal Y1 developed by the decoder Dl and Yi~3 represents the signal Y0 developed by the decoder Y0.
Referring now to Fig. 3, the illustrated decoder receives its address inputs A0 (or A0) arld Al (or Al) at the gates of transistors 50 and 52. An output lead 54 carries the output signal Yi developed by the decoaer~
That output is employed to cause t-ne decoder's associated sense amplifier to output its stored data, and it is also applied to the gates of transistors 56 and 58. In the case where the illustrated decoder represen'cs the decoder D0, the signal Yi represents the signal Y0 shown in ~
Fig. 1.
A signal identified as Yi+3 is applied to the gate of a transistor 60. In the case where the illustrated decoder is D0, the signal Yi+3 is the signal Y3 shown in Fig. 1 and corresponds to the Yi output of the decoder D3.
The illustrated decoder receives a precharge signal ~D (see Fig. 6) which is initially high and which is applied to the gate of a transistor 62 for raising its source (node 64) to a high level. Ano-ther clock signal, 00D2 (Fig. 6) is also high and is applied to the gate of a transistor 66 which is coupled to the node 64. ~ence, the drain of transistor 66 (node 68) is also driven high.
The signal 0D is also applied to the gat~ of a transistor 70 for precharging node 72 to a high level, Consequently, transistors 74 and 76 are turned on ~or pull-ing their drain connections (nodes 78 and 80) ~o a lowlevel.
The gate of another transistor 82 receiyes 0D for raising the voltage at node 8~ so as to turn on transiStors 86 and 88 and pull their drain connections (nodes 90 and 92) to a low level. A transistor 94 w}-ich is ccuplea to tne - ~ 3 ~19~
node 90 via its gate is thus turned off, as is a transis-tor 96 whose gate is coupled to node 92. The source of the transistor 96 is coupled via a node 98 to a transis-tor 100 whose gate receives the signal 0~. Consequently, the latter transistor is turned on to lower the voltage at the node 98. A transiStOr 102 whose gate is also coupled to the node 98 is therefore turned off. The drain of the latter transistor is coupled to the node 64 but, since the latter transistor is now off, it doe5 not ;~
disturb the high level to which the node 64 is precharged The signal ~POF (see Figs. 1 and 6) is high at this time and is applied to a transistor 104 wh~se gate is coupled to the node 78 and whose source is coupled to the node 80. Because the node 78 is at a low level, the transistors 104 is held off and the node 80 remains at a low level. The node 80 is also coupled to the gate of another transistor 106 which is also held off at this time.
The signal 0POF is also applied to the transis-tor 94. Because the gate of the transistor 94 is coupledto the low level on node 90, the transistor 94 remains off and the potential at its source (node 92) remains low.
Assuming now that the address inputs A0, Al to the transistors 50 and 52 are low, both the latter transis-tors remain off. Consequently, the llode 64 remains at a high level as does the node 68. The latter noae is coupled to the gate of a transistor 108 whose drain receives the signal 0YO. Because ~YO is high (see Fig- 6~, the transis-tor 108 develops a high level output Yi at the lead 54.
The lead 54 is also coupled to the drain of a transistor 109 whose gate lead 111 is coupled (via a connection which is not shown) to the node 80. It will be recalled that the node 80 was pulled low during the pre-charge cycle. Hence, the transistor 109 is held off to permit the signal Yi at lead 5~ to yo h:i~h. Thus, in the B
case where the illustrated decoder represents the decoder D0 (Fig. 1), Yi represents Y0 and the transistors 1~ and 16 (Fig. 1) are turned on. All the other decoders are off because at least one of their address inputs is high.
Consequently, at least one of the transistors ~hich cor-responds to transistors 50 and 52 in the other decoders is turned on for pulling low the voltage a-t nodes corre-sponding to nodes 64 and 68, thereby inhibiting ~Y0 from driving Yi high in the other decoders.
As stated previously, each of the decoders is adap-ted to disable itself after its associated sense amplifier has output its stored data.- For this purpose, the signal ~i at lead 54 is coupled to the gate of a transistor 110 via a lead 112 and also to the gate of transistor 58. Consequently, node 84 is pulled low to turn off transistors 86 and 88. In addition, transistor 110 is turned on to raise the potential at node 90 for turning on the transistor 94. When ~POF goes high again at time Ta lFig. 6), that high level is coupled to the 20 node 92 by the transistor 94. Consequently, transistor 96 turns on to drive the node 98 high, and transistor 102 turns on for pulling node 64 low. IIence, the decoder is disabled so that the next time the signal 0Y0 goes high, the output Yi will not be driven high.
Referring briefly to Fig. 6, it can be seen that, when 0POF goes high at time Ta, ~Y0 goes lowO The latter signal going low causes the output Yi at lead 54 to go low also.
Assuming that the operation described above relates to the decoder D0, the latter decoder will enable the decoder Dl for activation by the next hi9h level pulse from ~POF. To explain this phase of the operation, it will now be assumed that the circuitr~ shown in Fig. 3 represents the decoder Dl (all the decoders are construct-ed as shown in Fig. 3). Thus, the Yi~3 in~,ut to the decoder Dl represents the Yi output o~ the decoder D0.
When the ~i output of the decoder D0 went h:igh,the Yi+3 input to the decoder Dl was driven high at the gate of the transistor 60. Iience, the node 78 was driven high and turned the transistor 104 on. I~hen 0POF went high at time Ta, the transistor 104 pulled the node 80 high and turned on transistor 106. Because the source of the transistor 106 is coupled to the node 64, the latter node was driven high. 00D2 also went high at tlme Ta.
Hence, the node 68 was also pulled high. But because 0Y0 went low then, the transistor 108 held the Yi output of the decoder Dl at a low level. ~owever, when ~Y0 goes high at time tb (Fig. 6), the Yi output at lead 54 is pulled high.
The operation described above continues for each nibble cycle so that the ith decoaer primes the ith plus 1 decoder to fire when 0Y0 goes high.
Each decoder also includes an active hold off circuit coupled to the Yi output lead 54. This circuit 20 includes transistors 112, 114, 116, 118, and 120 which are arranged to actively hold the Yi output of the un-selected decoders at a low level.
The gates of transistors 114 and 120 each re-ceive the 0POF signal, wherefore their sources (nodes 122 25 and 124) are pulled to a high level during the precharge cycle. The gate of transistor 118 receives the ~YO signal so that, when that signal goes high, the drain of transis-tor 118 (node 124) is pulled low.
If node 64 is low (indicating that the decoder 30 is not selected), the transistor 116 remains of~ and the node 122 remains high. Consequently, the transistor 112 is turned on to hold the lead 54 at ground potential~
In the case in which the node 64 is high, the transistor 116 is turned on to pull node 122 low and hold 35 the transistor 112 off -to ~ermit the lead 54 to ~e ~riven ~ 16:195~
to a high level.
Referring now to Fig. 4, a data input buffer is shown whose construction is preferably of the type used for each of the buffers B0-B3 of Fig. 1. The illu-strated buffer includes input leads 126 and 128 for re-ceiving externally applied Din and Din data inputs and outputs leads 130 and 132 whic'n couple DBi and DBl out-puts to the data busses (such as DBo and DBo) of Fig. 1.
Other inputs include leads 134 and 136 which couple to node 64 of Fig. 3, lead 138 which couples to node 80 of Fiy. 3~ and lead 140 which couples to node 9Z of Fig. 3.
As described in detail below, an enabled decoder acti-vates its associated buffer to cause the latter to couple the data input (Din and Din~ to the DBi and DBi outputs.
When the decoder which is associated with the illustrated buffer is not enabled, the potential at the decoder's node 64 is low. That low level potential is coupled via the lead 134 to transistors 142 and 144 whose gates receive the signal ~OD2. Conse~uently, the sources (nodes 146 and 148) of transistors 142 and 144 are at a low level.
Nodes 146 and 148 are directly connected to the gates of transistors 150 and 152 which receive the Din and Din inputs. With nodes 146 and 148 at a low level, these transistors remain off to decouple the Din and ~in inputs from the output leads 130 and 132.
When the decoder which is associated with the illustrated buffer is enabled, the potential at the de-coder's node 64 is high. Consequently, buffer nodes 146 and 148 are both high and transistors 150 and 152 are turned on. In the case where the Din input is high and the Din input is low, the sources of transistors 150 and 152 (nodes 154 and 155) are driven hiyh and low, respectively.
l 9 ~ ~ 1 The node 154 is coupled to the gates o transistors 158 and 160, while -the no~e 156 is coupled to the gates of transistors 162 and 164. Consequently, transistors 162 and 164 are turned off and transistors 5 158 and 160 are turned on. Hence, the lead 130 is driven to a high level and the lead 132 is driven to a low level. The data coupled to leads 130 and 132 is thus written into a selected memory location via one of the data buss pairs of Fig. ~.
It will be appreciated that writing data into memory is a relatively time consuming operation. There-fore, the data output from the illustrated buffer is held available for reading even after the next successive de-- coder and buffer are enabled on the next nibble cycle.
15 Toward this end, transistors 166 and 163 are included to trap the logic levels on nodes 154 and 156, so that the logic leve!ls imposed on output leads 130 and 132 remain unchanged for the next three nibble cycles.
The gates of transistors 166 and 168 are 20 coupled via the lead 140 to node 92 in Fig. 3. The latter node is driven to a high level when 0POF goes high at the beginning of a nibble cycle. Consequently, transistors 166 and 168 are turned on. Because their drains are coupled to the gates of transistors 150 and 152, the 25 latter transistors are turned off. Thus, the high and ]ow levels previously applied to nodes 154 and 156 are trapped there. Hence, transistors 158 and 160 are held on while transistors 162 and 164 are held off. The high and low levels appearing on leads 130 and 132, respective 30 ly, are thus maintained. Hence, the write cycle time is shortened because writing can overlap into three succeed-ing cycles.
The illustrated buffer also preferably includes a pair of active hold off circuits to hold the bu~fer in-35 sensitive to further data inputs ~hen its associated r- ~61g56 decoder is disabled. The first hold off circuit ir,c]udes transistors 172, 174, 176, 17~, 180, 182, and 183. The other includes transistors 184, 186, ]88, 190, 192, lg4 and 196.
Referring to the first hold off circuit, the gates of transistors 174 and 180 receive the signal ~D
for precharging nodes 198 and 200 to a high level. The Din input is coupled via a lead 20Z to the gate of tran-sistor 182 so that, when Din is high, node 200 i.5 pulled low.
The gate of transistor 176 is coupled via lead 136 to node 64 in Fig. 3, its source is coupled to node 200,- and its drain is coupled to node 198. Thus, if the buffer's decoder is enabled, node 64 is high, transistor 176 is on, and node 198 is pulled low. Hence, transistor 183 is turned off and the potential at its drain (node 154) is allowed to vary in response to the Din input at lead 126_ If the illustrated buffer's decoder had been disabled, node 64 in that decoder would be low, where~ore transistor 176 would be off and node 198 would be at a high level. Consequently, transistor 183 would be on to pull the node 154 to ground potential.
The other hold off circuit operates in a manner similar to that described above. Suffice it to say that when the buffer's decoder is enabled, the transistor 196 remains off to allow node 156 to vary in response to the Din input at lead 128~ Otherwise, transistor 196 is on to hold node 156 at ground potential.
It is often desirable to write a full Vcc vol-tage into memory locations. In the present embodiment nodes 154 and 156 are boosted above Vcc to accomplish this, partly by driving Din and Din to 1.4 tim~s Vcc and partly by including capacitors 204 and 206 which are 35 coupled to nodes 154 and 156, res~ectively, and w;lich T ~ ;J 6 receive ~POF With this arrangement, the potentials at nodes 154 and 156 are driven even higher when ~pO~ rises.
Another feature which improves the speed of the Y ~OD2 g- 6, 00D2 generally follows 0POF' but ~OD2 varies between 7 volts and 4 volts whereas ~POF varies between 5 volts and zero volts. The use of ~OD2 considerably shortens the pre-charge portion of the nibble cycle as demonstrated by the comrnents below.
It-will be understood that it is desirable to drive the signal Yi (at lead 54) up to Vcc (five volts, for example). To do this, the voltage a~ lead 68 is driven higher than Vcc, preferably toward seven volts, in the following manner. Referring to Figure 6, it can be seen that 00D2 drops from seven volts to four volts just prior to 0yo going high at time tb. Just prior to that occurrence, ~pof had been high to precharge node 64 to about our volts via transistors 104 and ]06. ~ence, the transistor 66 has Eour volts at its gate and about four volts at its source. In this state, the transistor 66 is cut off, thereby releasing or isolating node 68 from node 64. Accordingly, when ~yo goes high to raise the voltage at the drain of transistor 108, node 68 is bootstrapped to about seven volts by the gate-to-drain capacity of the transistor and Yi is driven high. Had transistor 66 not been cut off by 00D2' node 68 would not have been released from the node 64, no such bootstrapping would have occurred, and the signal Yi would not have been driven to as high a level as is desired.
It will be appreciated that the transistor 66 could have been cut off by causing node 64 to be pre-charged to a higher level. However, the additional tirne required for such precharging to occur would lengthen the time required to enable the decoder. With the l l 61~6 illustrated arrangement, the decoder's enabling time is kept short while still retaining the ahility to bootstrap the node 68 and drive the s;gnal Yi up to Vcc.
An arrangement utilizing ~OD2 in a similar manner is shown in Figure 4 in which buffer noaes 146 and 148 are quickly released from node 64 when 0OD2 falls to four volts r thereby permitting efficient bootstrapping to occur at nodes 146 and 148.
T,he present system may be used with a pair of memories, each of which operate in the nibble mode.
Conventionally, each such memory is controlled by RAS
and CAS clocks to define the precharge and active (read or write) cycles. A first memory may have RAS and CAS
going low to initiate a nibble read (or write) cycle while a second memory is in a precharge mode. Then the RAS and CAS clocks in the first memory may be driven high to precharge the first memory while RAS and CAS in the second memory go low to initiate a nibble read cycle therein. By so stagyering the RAS and CAS clocks for both memories, a bit of data may be read for each nibble cycle for an indefinite period of time.
One of the advantages of the illustrated decoder and buffer is that virtually no D.C. power is consumed and reliable operation is obtained at low precharge voltages.
Of course, very high speed operation is obtained by vir-tue of each decoder disabling itself and enabling a suc-cessive decoder. In addition, input data is easily and rapidly read by virtue of the fact that each buffer maintains the status of its data outputs through four nibble cycles.
Although the invention has been described in terms of a preferred embodiment, it will be obvious to those skilled in the art that many modifications and alterations may be made without depart,ing from the invention. Accordingly, it is intended that all such 111 B19~6 f modifications and alterations be cons:idered as within the spirit and scope of the invention as defined hy the appended claims.
Claims (9)
1. In a semiconductor memory, a system for rapidly transferring data between a plurality of succes-sive memory locations and a data output buss in response to a single address input, comprising:
a plurality of N data latches for storing data associated with N successive memory locations which are defined by a plurality of bits of the address input;
a corresponding plurality of N serially connect-ed decoders each associated with one of said data latches, each adapted to be en-abled for causing its associated data latch to output its stored data to the data buss, and each receiving selected bits of the address input such that one of the de-coders is initially enabled, in response to said selected bits having a given logic state, for causing its associated data latch to output its stored data to the data buss, the enabled decoder being adapted to then disable itself and to enable a successive decoder, the latter decoder and each remain-ing decoder being adapted to disable itself after having been enabled and to enable a successive decoder so as to cause the data latches to output, to the data buss, N
successive bits of data in response to a single address input.
a plurality of N data latches for storing data associated with N successive memory locations which are defined by a plurality of bits of the address input;
a corresponding plurality of N serially connect-ed decoders each associated with one of said data latches, each adapted to be en-abled for causing its associated data latch to output its stored data to the data buss, and each receiving selected bits of the address input such that one of the de-coders is initially enabled, in response to said selected bits having a given logic state, for causing its associated data latch to output its stored data to the data buss, the enabled decoder being adapted to then disable itself and to enable a successive decoder, the latter decoder and each remain-ing decoder being adapted to disable itself after having been enabled and to enable a successive decoder so as to cause the data latches to output, to the data buss, N
successive bits of data in response to a single address input.
2. A system as set forth in Claim 1 including a plurality of input buffers for writing input data into memory locations, wherein each of said decoders is asso-ciated with an input buffer, and wherein said decoders are responsive to a single address input for selecting said buffers sequentially so as to write the input data into successive memory locations.
3. A system as set forth in claim 2 wherein each buffer includes an input for receiving data, an output for coupling data to memory , and means for holding the data at its output while successive buffers are selected such that writing of the data at a buffer output may continue while successive buffers are selected.
4. A system as set forth in claim 3 wherein each buffer includes a hold-off circuit for rendering the buffer insensitive to data received at its input while its associated decoder is disabled.
5. A system as set forth in claim 1 wherein each decoder includes:
an address-input circuit receiving the selected address bits for developing an output signal in response to the selected address bits being in a given logic state;
means for coupling said output signal to an associated data latch for causing said data latch to output its stored data;
and a disabling circuit coupled to said address-input circuit, receiving the latter circuit's output signal and a clock signal, and being responsive to said control signal and to the clock signal for inhibiting the address-input circuit from developing a further output signal, whereby each decoder disables itself after having been enabled.
an address-input circuit receiving the selected address bits for developing an output signal in response to the selected address bits being in a given logic state;
means for coupling said output signal to an associated data latch for causing said data latch to output its stored data;
and a disabling circuit coupled to said address-input circuit, receiving the latter circuit's output signal and a clock signal, and being responsive to said control signal and to the clock signal for inhibiting the address-input circuit from developing a further output signal, whereby each decoder disables itself after having been enabled.
6. A system as set forth in claim 5 wherein each decoder further includes:
an enabling circuit coupled to said address-input circuit, receiving the output signal of a previous decoder and said clock signal, and responsive to the previous decoder's output signal and the occurrence of said clock signal for enabling its address-input circuit to develop an output signal, whereby each decoder is enabled by a previously enabled decoder.
an enabling circuit coupled to said address-input circuit, receiving the output signal of a previous decoder and said clock signal, and responsive to the previous decoder's output signal and the occurrence of said clock signal for enabling its address-input circuit to develop an output signal, whereby each decoder is enabled by a previously enabled decoder.
7. A system as set forth in claim 5 wherein said address-input circuit includes:
a first node adapted to be precharged to a positive voltage level;
transistor means receiving the address input bits for inhibiting the discharge of said first node in response to said address bits being in said given logic state;
a first transistor having a source coupled to said first node, having a gate receiving a second clock signal, and having a drain coupled to a second node;
a second transistor having a gate coupled to the second node, having a drain receiving a third clock signal, and a source output terminal for developing the control signal thereat, said second clock signal being selected to go high to turn on the first transistor and precharge said second node, and then to go low so as to substantially cut off said first transistor and thereby isolate said first node from said second node, said second clock signal being selected to go high while said first transistor is sub-stantially cut off, to bootstrap said second node to a higher voltage via gate-to drain capacitance associated with said second transistor and to drive the output terminal to a relatively high positive voltage.
a first node adapted to be precharged to a positive voltage level;
transistor means receiving the address input bits for inhibiting the discharge of said first node in response to said address bits being in said given logic state;
a first transistor having a source coupled to said first node, having a gate receiving a second clock signal, and having a drain coupled to a second node;
a second transistor having a gate coupled to the second node, having a drain receiving a third clock signal, and a source output terminal for developing the control signal thereat, said second clock signal being selected to go high to turn on the first transistor and precharge said second node, and then to go low so as to substantially cut off said first transistor and thereby isolate said first node from said second node, said second clock signal being selected to go high while said first transistor is sub-stantially cut off, to bootstrap said second node to a higher voltage via gate-to drain capacitance associated with said second transistor and to drive the output terminal to a relatively high positive voltage.
8. In a semiconductor memory having a read mode and a write mode, a system for rapidly writing in-coming data into four successive memory locations and for reading data out of four successive memory locations, comprising:
four data latches for storing data associated with four successive memory locations which are defined by a plurality of bits of the address input, each data latch being adapted to output its stored data when selected by an enabled decoder;
four data input buffers each having an input for receiving incoming data, an output for coupling the data to memory, and each being adapted to output the data to memory when selected by an enabled decoder;
four serially connected decoders, each asso-ciated with one of said data latches and with one of said input buffers, and each receiving selected bits of the address input such that one of the decoders is initially enabled in response to the address input for selecting its associated data latch when the memory is in a read mode and for selecting its associated input buffer when the memory is in a write mode, the enabled decoder being adapted to disable itself and enable a successive decoder, the latter decoder and each remaining decoder being adapted to disable itself after having been enabled and to enable a successive decoder so as to rapidly write four bits of data into successive memory locations when the memory is in the write mode and to rapidly read four bits of data out of successive memory locations when the memory is in the read mode.
four data latches for storing data associated with four successive memory locations which are defined by a plurality of bits of the address input, each data latch being adapted to output its stored data when selected by an enabled decoder;
four data input buffers each having an input for receiving incoming data, an output for coupling the data to memory, and each being adapted to output the data to memory when selected by an enabled decoder;
four serially connected decoders, each asso-ciated with one of said data latches and with one of said input buffers, and each receiving selected bits of the address input such that one of the decoders is initially enabled in response to the address input for selecting its associated data latch when the memory is in a read mode and for selecting its associated input buffer when the memory is in a write mode, the enabled decoder being adapted to disable itself and enable a successive decoder, the latter decoder and each remaining decoder being adapted to disable itself after having been enabled and to enable a successive decoder so as to rapidly write four bits of data into successive memory locations when the memory is in the write mode and to rapidly read four bits of data out of successive memory locations when the memory is in the read mode.
9. A system as set forth in claim 8 wherein each input buffer includes means for holding data at its output while successive input buffers are selected so that its data can continue to be read into memory after its associated decoder has been disabled.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/195,729 US4344156A (en) | 1980-10-10 | 1980-10-10 | High speed data transfer for a semiconductor memory |
| US195,729 | 1988-05-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1161956A true CA1161956A (en) | 1984-02-07 |
Family
ID=22722545
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000373194A Expired CA1161956A (en) | 1980-10-10 | 1981-03-17 | High speed data transfer for a semiconductor memory |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4344156A (en) |
| EP (1) | EP0049988B1 (en) |
| JP (1) | JPS5792473A (en) |
| CA (1) | CA1161956A (en) |
| DE (1) | DE3176726D1 (en) |
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| US3857046A (en) * | 1970-11-04 | 1974-12-24 | Gen Instrument Corp | Shift register-decoder circuit for addressing permanent storage memory |
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| JPS5410412A (en) * | 1977-06-23 | 1979-01-26 | Kyokuto Kikai Seisakusho:Kk | Low noise multi-stage axial flow blower |
| US4254477A (en) * | 1978-10-25 | 1981-03-03 | Mcdonnell Douglas Corporation | Reconfigurable memory circuit |
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| JPS5727477A (en) * | 1980-07-23 | 1982-02-13 | Nec Corp | Memory circuit |
| JPS6118837A (en) * | 1984-07-06 | 1986-01-27 | Yaskawa Electric Mfg Co Ltd | Wave-making apparatus |
-
1980
- 1980-10-10 US US06/195,729 patent/US4344156A/en not_active Expired - Lifetime
-
1981
- 1981-03-17 CA CA000373194A patent/CA1161956A/en not_active Expired
- 1981-10-05 EP EP81304605A patent/EP0049988B1/en not_active Expired
- 1981-10-05 JP JP56158570A patent/JPS5792473A/en active Granted
- 1981-10-05 DE DE8181304605T patent/DE3176726D1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| EP0049988B1 (en) | 1988-04-27 |
| DE3176726D1 (en) | 1988-06-01 |
| EP0049988A3 (en) | 1983-09-28 |
| JPS5792473A (en) | 1982-06-09 |
| EP0049988A2 (en) | 1982-04-21 |
| JPS6129069B2 (en) | 1986-07-04 |
| US4344156A (en) | 1982-08-10 |
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