CA1165900A - Process for manufacture of high power mosfet with laterally distributed high carrier density beneath the gate oxide - Google Patents

Abstract

PROCESS FOR MANUFACTURE OF HIGH POWER
MOSFET WITH LATERALLY DISTRIBUTED HIGH CARRIER
DENSITY BENEATH THE GATE OXIDE

ABSTRACT OF THE DISCLOSURE

A high power MOSFET structure consists of a plurality of source cells distributed over the upper surface of a semiconductor chip, with a drain electrode on the bottom of the chip. Each of the source cells is hexagonal in configuration and is surrounded by a narrow, hexagonal conduction region disposed beneath a gate oxide. The semiconductor material beneath the gate oxide has a relatively high conductivity, with the carriers being laterally equally distributed in density beneath the gate oxide. The high conductivity hexagonal channel is formed in a low conductivity epitaxially formed region and consists of carriers deposited on the epitaxial region prior to the formation of the source region. Symmetrically arranged gate fingers extend over the upper surface of the device and extend through and along slits in the upper source metallizing and are connected to a polysilicon gate grid which overlies the gate oxide.

Description

BACKGROUND OF T~E INVENTION

This invention relates to MO~FET devices, and more specifically to a novel process and to a novel confi~uration for the central high conductivity region disposed beneath the gate oxide of a high power MOSFET.

High power MOSFETS having low on-resistance and high breakdown voltage are kIlown and are shown in applicant's Canadian Patent No. 1,123,119, issued May 4, 1982. In the above application, the source electrodes are inter-digitated source regions spaced ~rom one another by two parallel channel regions covered by a common gate. The device has exceptionally low on-resistance and has the usual advantages of a MOSFET device over a bi-polar device.
The low on-resistance is obtained by virtue of a relatively hi~hly doped conductivity region disposed beneath the gate oxide and between the two adjacent channels. The highly doped region leads to a common drain electrode.
The increased conductivity of the region beneath the oxide in the path leading to the bottom drain does not adversely affect the reverse-voltage characteristics of the device.
As a result, it was possible to substantially decrease t~e forward resistance of the MOSFET wi$hout adversely affecting any of its other desirable characteristics.

The interdigitated source structure o~ applicant's Canadian Patent No. 1,123,119, issued May 4, 1982, has a relatively low packing density, requires relatively com plicated masks and has a relatively high capacitance.

The de~ice of a plicant's Canadian Patent No. 1,123, 119, issued ~ay 4, 1982, proyides ~ hi~h power MOFSET device with the low forward resistance of application Serial No.
337,182 where, however, a very hi~h packing density ~s available and which c~n be ~ade with relatively simpler ~ `:

masks. The device ;Eu~ther ha$ xelatiyely low capacitance.
T~pically, the device of applicant's Canadian Patent No, 1,123,119, issued ~ay 4, 1982, uses the increased conduc-tivity region beneath the gate oxide and D-MOS fabrication techniques. However, the individual spaced source regions are polygonal in configuration and are preferably hexagonal to ensure a constant spacing along the major lengths of the sources disposed over the surface of the body. An extremely large number of small hexagonal source elements may be formed in the same surface of the semiconductor body for a given device. By way of example, 6,600 hexagonal source regions can be formed in a chip area having a dimension of about 100 by 140 mils to produce an effective channel width of about 22,000 mils, thus permitting very high current capacity for the device. A polysilicon gate is used which has a hexagonal grid~ e configura~ion ~rhich is disposed atop an oxide layer. Each leg of the grid overlies two spaced channels which are capable of inversion by application of a voltage to the polysilicon gate. The gate structure is contacted over the upper surface of the device by symmetric, elongated gate contact fingers which ensure good contact over the full surface of the gate.
Each of the polygonal source regions is contacted by a continuous conductive source contact layer which enga~es the individual polygonal sources through openings in an insulation layer covering the source regions. These openings can be formed by conventional D-MOS photolithographic techniques. A
source pad connection region is then provided for the source conductor and a gate pad connection region is provided for the elongated gate Eingers and a drain connection region is made to the reverse surface of the semiconductor device.
A plurality of identical chips can be formed on a single semiconductor wa~er and the individual elements can be separated -from one another by scribing or any other suitable method after processing is com-ple~ed.
The process used to form the relatively high conductivity region beneath the gate oxide has been such that the conductivity beneath the gate oxide in the region containing the relatively high concentration o~ impurity carriers is relatively low in laterally central regions and high in the laterally removed side regions. As the result of this non-uniform lateral distribution, the avalanche energy of the device is not optimum. Moreover, the effective lateral resistance beneath the source region and extending from the channel regions to the metal on the surface of the device and circumscribed by the source is higher than optimum.
Since this resistance is relatively high, the effective bi-polar transistor formed by three alternate conductivity regions has a high gain and can turn on easily, intro-ducing second breakdown characteristics common to a bi-polar device but normally avoided by a ~IOSFET device.
As the region beneath the source region becomes more depleted, the problem of possible second breakdown increases. Commonly, this shorting or parallel resis-tance path defining parasitic base resistance cannot be reduced without varying the polysilicon gate width which would increase the on-resistance of the device.

BRIEF DESCRIPTION OF T~IE INVENTION

In accordance with the invention~ a rela-tively high conductivity implant beneath the gate oxide has a depth of about l micron beneath the surface o~
*he oxide but has a conductivity distribution or gradient highest toward the surface of the wafer and increasingly lower as it approaches a depth of approximately 1 micron. Moreover, the lateral distribution of carriers across the width of the region beneath the gate oxide receiving the high doping concentration is constant at any level at and beneath the surface and beneath the gate oxide. By having constant impurity concentration laterally beneath the gate oxide, the device has a higher avalanche energy. Moreover, the use of the novel zero lateral gradient produces a parallel resistance path beneath the source region consisting of parasitic , . .

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base resiStance which i~ lower than that previously ob-tained, thereby to reduce second breakdown proble~s due to the e~fect of the inherent bi-polar transistor which is formed by the various junctions. Thus, in a prior art N channel device, as the P region beneath the N source region is depleted, the parasitic base resistance would increase. With the novel configuration of zero lateral dis-tribution of impurities beneath the gate oxide, there is less depletion and the parasitic base resistance remains relatively low during operation of the device. Moreover, this reduction in the value of the ef~ective shorting resistor beneath the source is obtained without varying the polysillcon gate width, so that the device maintains a very short polysilicon gate width, for example, 13 to 15 microns.

While the zero lateral gradient distribution beneath the gate oxide of a high density impurity can be formed in many ways, preferably the high density region is implanted prior to the formation of the polygonal source cells and prior to the formation of the gate oxide.

Two implants may be used if desired, one before the gate oxide is formed and the othex after the gate poly-silicon pattern is formed if it is desired to reduce theMiller capacitance.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a plan View of a completed element on a semiconductor wafer prior to the sepaXation o~ the element awa~ from the remainder o~ the wafer, as described in ap-plicant's Canadian ~atent No. 1,1~3,119, is$ued ~a~ 4, 1982.

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Figure 2 is an enlarged detail of the ga~e pad o-f Figure 1 to illustrate the relationship of the gate contact and the source polygons in the region of the gate pad.
Figure 3 is a detailed plan view of a small portion of the source region of Figure 1 during one stage of the manufacturing process of the device.
Figure 4 is a cross-sectional view of Figure 3 taken across the section line ~-4 in Figure 3.
Figure 5 is similar to Figure ~ and shows the addition of a polysilicon gate, a source electrode means and drain electrode to the wafer.
- Figure 6 schema1:ically illustrates the concen-tration of impurities in the lateral dimension beneath the gate oxide in the prior art device of Figure 5.
Figure 7 shows the first mask pattern for processing a chip in accordance with the present invention.
Figure 8 shows a central region of the chip after diffusion through small diameter windows etched in the :Eield oxide when using the mask of Figure 7.
Figure 9 shows the chip section o Figure 8 ater the application of a second mask used to remove the remainder of the field oxide but retaining small oxide pads over the P+ diffusion and shows an N~ implant over the full exposed surface of the wafer.
Figure 10 sho~s the chip section of Figure 9 after the application o-f an oxide layer, a polysilicon layer and a second oxide layer.
Figure 11 shows the con-figuration o-f the third mask used in accordance with the present invention.
Figures 12a to 12e show the configuration of the peripheral boundary of the chip at different stages of the processing of the chip in accordance with the invention.

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t Figures 13a to 13E illustrate various steps in the processing of a typical elongated gate finger during the processing oE the chip o~ the invention.
Figure 14 is a top view of the wafer section of Figure 10 after processing with the mask of Figure 11 to remove polygonal-shaped sections from the upper - o~ide coating in the section of Figure 10.
Figure 15 is a cross-sectional view of Figure 14 taken across the section lines 15-15 in Figure 1~.
Figure 16 is a cross-sectional view similar to Figure 15 after the etching of the polysilicon laye.r and the underlying oxide layer to expose central hexagonal openings which extend to the surface of the C~lip .
Figure 17 shows the section o Figure 16 after the diffusion and drive of P~ rings into each of the hexagonal open.ings.
Figure lS shows the section of Figure 17 after the implanting o~ sonrce rings into the P-~ rings or cells a~ Figure 17 using self-aligned diffusion techniques to -form a plurality o:E he:`cag.onal channels which can be inverted by a gate voltage.
Figure 19 shows the doping concentration beneath the gate oxide in accordance with the present in~ention.
Figure 20 shows the waer of Figure 18 ater the formation oE an oxide layer, a si~ox layer and a photoresist pattern which is formed using the mask oE
Figure 21.
Figure 21 shows a mask pattern constituting the :~ourth mask of the process of making the novel device o~ the invention.

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Figure 22 show~ the chip section of ~iguxe 2Q ater etching away the cent~al oxide and silox areas coyering each of the hexagonal cells and after the deposition o~ an aluminum sheet over the entire top surface of the device to define the source electrode.

DETAI~ED DESCRIPTION OF THE DRAWING5 -There is first described the prior art arrangement of applicant's Canadian Patent No. 1,123,119, issued May 4, 1982. The manufacturing process described in applicant's Canadian Patent No~ 1,123,119, issued May 4, 1982 can be modified to make the device of Figures 1 to 5, ~hereby D-MOS fabrication techniques and ion implanation techniques can be advantageously employed for the formation of the junction and placement of the electrode in the most ad-vantageous way. The de~ice is described in an enhancement type device. It will be apparent that P channel devicesiand depletion ~ode devices could al~ ~e the features of the structure tQ ~g d~scribed.
~0 ~ he polygon configuration of the source regions is best sho~n in Figures 3, 4 and 5, which axe first described. Referring to Figures 3 and 4, the device is shown prior to the application of the gate, source and drain electrodes. Figures 3 and 4 show a plurality of polygonal source regions on one surface of the device, where these poly~onal regions are preferably hexagonal in shape. Other shapes such as squares or rectangles could be used but the hexagonal shape provides better uni-formity of spacing between adjacent source region peri-meters.

In Figures 3 and 4, the hexagonal source xegions are formed in ~ se~iconductor bod~ of wafer which is an .
1~ t~pe wafer 2~ of mon~crystalline silicon ~hich has a thin N-~pitaxial region 21 deposited ~, thereon as best shown in Figure 4. All junctions are ~ormed in epitaxial region 21. By using suita~le masks, a plurality of P type regions such as regions 22 and 23 in Figures 3 and 4 are formed in one surface of the semiconductor wafer region 21, where these regions are generally polygonal in configuration and, preferably, are hexagonal.
A very large number of such polygonal regions are formed. For example, in a device having a surface dimension of 100 by 140 mils, approximately 6,600 poly-gonal regions are formed to produce a total channel wldth of about 229000 mils. Each of the polygonal regions may have a width measured perpendicularly to two opposing sides of the polygon of about l mil or less. l'he regions are spaced from one another by a distance of about 0.6 mil when measured perpendicularly between the adjacent straight sides of adjacent polygonal regions.
The P~ regions 22 and 23 will have a depth d - 20 whîch is preferably about 5 microns to produce a high and reliable field characteristic. Each of the P
regions has an outer shelf region shown as shelf regions 24 and 25 for P regions 22 and 23, respectively, havin~
a dcpth s of about 3.0 microns. This distance should be as small as possible to reduce the capacitance o~
the device.
Each of the polygon regions includlng polygonal regions 22 and 23 receive N+ polygonal ring regions 26 and 27, respectively. Shelves 2~ and 25 are located beneath regions 26 and 27, respectively. N~ regions 26 and 27 cooperate with a relatively conductive N+ region 28 which is the N+ region disposed between adjacent P
type polygons to define the various channels between 9~3 the source re~ions,and ~ drain contact which will ~e later described. The hi~hl~ conductive N~ ~egions 28 a~e ~ormed in the manner descri~bed in applicantt~s Canadian Patent No.
1,123,119, issued May: 4, 1982 to ~roduce a very lo~
forward resistance for the device.

In Figures 3 and 4, it will be noted that the entire surface of the wafer is covered with an oxide layer or combined conventional oxide and nitride layers which are ~o produced for the formation of the various junctions. This layer is shown as the insulation layer 30. The insulation layer 30 is provided with polygonal shaped openings such as openings 31 and 32 immediately above polygonal regions 22 and 23. Ope~ings 31 and 32 have boundaries overlying the N+ type source rings 26 and 27 for the regions Z2 and 23, respectively. The oxide strips';30, which remain after the formation of the p~lygonal shaped openings, define the gate oxide for the device.

Electrodes may 'then be applied to the device as shown in Figure 5. These include a polysilicon grld which includes polysilicon sections 40, 41 and 42 which overlie the oxide sections 30.
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A silicon dioxide coating is then deposited atop the polysilicon ~rid 40 shown as coating sections 45,46 and 47, in Figuxe 5 which insulates the polysilicon control electrode and the source electrode which is subsequently de-posited oVer t~e entire upper surface of the wafer. In Figure 5 the source electxode is sho~n as conductive coating 50 which may ~e of an~ desired matexial, such as aluminum.
A drain electxode 51 ~s also a~plLed to the deyice.

The resultin~ deyice of Figu~e 5 is an N~channel type device wherein channel regions aXe formed between each of the individual sources and the body of the semiconductor ma,teri~l which ult~ateIy le~,ds to - lOa -.

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the drain electrode 51. Thus, a channel region 60 is formed bet~een the source ring 26, which is connected to source electrode 50, and the N~ region 28 which ultimately leads to the drain electrode 51. Channel 60 is inverted to the N type conductivity upon *he appli-cation of a suitable control voltage to the gate 40.
In a similar manner, channels 61 and 62 are formed between the source region 26, which is connected to the conductor 50, and the surrounding N+ region 28 which leads to the drain 51. Thus, upon application of a suitable control voltage to the polysilicon gate (includ-ing finger 41 in Figure 5), channels 61 and 62 become conductive to permit majority carrier conduction from the source electrode 50 to the drain 51.
~ach of the sources form parallel conduction paths where, for example, channels 63 and 64 beneath gate element 42 permit conduction -from the source ring 27 and an N type source strip 70 to the N+ region 28 and then to the drain electrode 51.
It is to be noted that Figrures 4 and 5 illus-trate an end P type region 71 which encloses the edge of the ~a-fer.
The contact 50 o-f Pigure 5 is preferably an aluminum contact. It will be noted that the contact region -for the contact 55 lies entirely over and in alignment ~ith the deeper portion of the P type region 22. This is done to prevent the aluminum used ~or the electrode 50 from spiking through very thin regions of the P type material. This permits the active channel regions defined by the annular shelves 24 and 25 to be as thin as desired ~o reduce device capacitance.
Figure 1 illustra~es one completed device using the polygonal source pattern of Figure 5. The completed device shown in Figure 1 is contained l~ithin .

the scribe regions 80, 81, 82 and ~3 which enable the breaking out o-f a plurality of unitary devices each having a dimension of 100 by 140 mils from the body of the wafer.
The polygonal regions described are contained in a plurality of columns and rows. By way of example, the dimension A contains 65 columns of polygonal regions and may be about 83 mils. The dimension B may contain 100 rows of polygonal regions and may be about 14~
mils. Dimension C, which is disposed between a source connection pad 90 and a gate connection pad 91, may - contain 82 rows o-f polygonal elements.
The source pad 90 is a relatively heavy metal section which is directly connected to the aluminum source electrode 50 and permits convenient lead con-nection for the source.
The gate connection pad 91 is electrically connected to a plurality of extending fingers 92~ 93, 94 and 95 which extend symmetrically over the outer surface of the area containing the polygonal regions and make electrical connection to the polysilicon gate as will be described in connection ~ith Figure 2.
Finally the outer circumference of the device contains a P~ deep di-ffusion ring which may be connected to field plate 96 shown in Figure 1.
Figure ~ shows a portion of the gate pad 91 and the gate fingers 94 and 95. It is desirable to make a plurality oE contacts to the polysilicon gate to reduce the R-C delay constant of the device. The polysilicon gate has a plurality of regions including regions 97a, 97b, 97c (Figure 2~ and the like ~hich extend outwardly and receive extensions of the gate pad and the gate pad elements 94 and 95. The polysilicon gate regions may be left exposed during the -formation of the oxide coating ~5-~6-47 in Figure 5 and are not coated by the source electrode 50. Note that in Figure

2 the axis 98 is the axis o-f symmetry 98 which is that shown in Figure 1.
The MOSFET shown and described in Figures 1 to 5 has operated very well. The device, however, has had limited avalanche energy and minor second breakdown problems. These problems are believed due to the variable density of the increased doping concentration region beneath the gate oxide and between two channels in a lateral direction. Thus, as shown in Figure 5, the concentration of impurities in a lateral direction beneath the surface of oxide 30 will vary in the manner shown in Pigure 6 which shows donor and acceptor concen-tration at the silicon surface as a function of thelateral distance along the gate oxide in Figure 5.
The concentration of the sources 26 and 27 is shown in the le~t and right, respectively, in Figure 6, but it will be seen that at the center of region 28 beneath the oxide the concentration of the N~ doping impurity atoms reduces.
As a result of this variable doping concentra-tion in the lateral direction, there will be greater depletion beneath the P+ regions 22 and 23 during operat~ion~ With this depletion, the effective resistance rb' o-f the bi-polar transistor comprised of regions 26, 22 and 21 is relatively high so that the transistor has high gain and can turn on easily. This turn-on causes a hot spot on the device and can destroy the device.
This second breakdown problem is associated with bi-polar devices but avoided by the MOSPET. Note that, as the P~ regions 22 and 23 of each of the cells of the device become more depleted, the second breakdown problems increase.
Another problem created by the nonlinear distribution o~ carriers across the relatively high - ~ - - - ., conductiyity re~ion beneath the ~ates 3Q is that the aYalan-che ener~ of the dev~ce is somewhat reduc~d so th~t the device is not as resistant as possible to destruction due to high voltage spikes.

As will be seen more fully hereinafter, the novel device of the invention and the process for production of he device provides a constant carrier density in a lateral direction beneath the gate 30 and between the source regions leading into the gates. This carrier density is relatively high immediately beneatht~e gate and gradually decreases with the distance beneath the device surface. As a result of this novel redistribution of carriers beneath the gate oxide, there is very little depletion of the P+ regions 22 and 23 during operation of the device so that the bypass resistance r~' beneath the source regions remains low and the bi-polar tr~nsistor inherently formed in the device has low gain so that second brea~down problems are avoided.
Moreover, the novel grading of the density of carriers in the region beneath the gate, such thcat there is a higher concentration immediately beneath the gate with a gradually decreasing concentration farther from the gate, establishes a higher avalanche energy for the device so it is more re-sistant to damage due to overvoltage spikes.
As will be later seen, a relatively minor modifi-cation is all that is needed in the process of manufacture of the device to obtain these advanta~es. This difference is the use of an N type implant and drive before the formation of the gate oxide in an N channel device embodiment. Note that in the embodiment 4f Figures 1 to 5 and using the process disclosed ~n applicantis Canadian Patent No. 1,123,119, issued May 4, 1~82, the ~ regions 28 axe formed after the ~ate oxide i$ deposited Qn the ~' device. This process leads to the nonlinear concentration of carriers along the surface of the device as depicted in Figures 5 and 6.

~IANUFACTURING PROCESS IN ACCORDANCE WITH THE INVENTION

In carrying out the present invention, the follo~ing description is for the production of a single device on a single chip portion, such as the chip shown in Figure 1 with slightly di-fferent surface geometry.
Moreover, the description is for an N- channel depletion device. It will be obvious to those skilled in the art that the invention can also be adapted for P channel devices and for bo-th depletion and enhancement mode devices.
In manu~acturing the device of the invention, the first step in the process is the deposition of a field oxide on the surface of a single wafer containing a plurality of identical chips. Note that a large number of identical wafers can be simultaneously processed.
Each wafer may be of the type partly shown in Figure 8 and consists of an N~ body having an N- epitaxially deposited region 100. Typically the wafer of Figure 8 can have an N+ substrate which is about 14 mils thick, with an N- epitaxial layer having a thickness and resistivity depending upon desired reverse voltage.
Typically~ the epitaxial layer 100 may be about 35 microns thick and have a resistivity of about 20 ohm centimeters for the embodiment described.
A field oxide 101 is deposited on the surface o~ the N- layer 100 in accordance with standard well-known techniques. Thereafter, a suitable photoresist is placed upon the upper surface of the o~ide 101 and the surface is exposed to ultraviolet ligllt through a mask having a pattern such as that shown in Figure 7 a for each chip element. Clearly, a conventional glass mask will contain a large number o-f patterns identical to that o-f Figure 7.
The photoresist pattern produced includes a large plurality of small diameter circular openings, produced by the dot areas 102, which are deposited over the full unshaded area of the mask in Figure 7. The dots are arranged in columns staggered from one another to align the dots of adjacent columns. ~ithin each vertical area bet~een gate finger regionsS such as regions 103 and 104, there can be about 24 columns of dots. Each column could contain, -for example~ 150 dots. Note that each of the dots ~ill correspond to the center of a respective hexagonal cell which is to be formed in the single c~lip element. Note also that the elongated inger areas 103 and 104 lead to a gate pad region 105.
The region 106 corresponds in location to a source pad connection region as ~ill be later described.
The oxide exposed through the photoresist pattern formed with the mask of Figure 7 is etched with a suitable etching solution to produce openings, such as typical openings 110, 111 and 112 shown in Figure 8 in the oxide lOl. These openings correspond to locations of three of the mask dots 102 in Figure 7, and are shown in Figure 8 in greatly enlarged but unscaled fashion.
After the etching operation, the photoresist mask is stripped of~ and the wafer is placed in ion implantation apparatus for implanting boron atoms into areas not covered by the oxide layer 101. Thus, P type conductivity boron atoms are implanted through the openings 110, 111 and 112. Typically, the boron atoms can have a dose of 5 x 1013 to 1 x 10 atoms/cm and can be implanted wi~h accelerating voltages grea-ter than about 5 kV.

This boron implant is followed by a heating drive ~o drive the boron impurity atoms deeper into the surface of the ~afer to form the P+ regions 113, 114 and 115 through the openings 110, 111 and 112, respectively.
At the same time, a relatively broad area elongated P+
region 116 underlying, for example, the finger region 104 in the mask of Figure 7 is -formed as shown in Figure 13a. Note tha~ in Figure 13a the finger 116 is disposed immediately between P+ regions 117 and 118 which are in columns of dots on opposite sides, respectively, of the finger 104. Similarly, an elongated P+ channel guard ring 120 is -formed around the periphery o-f the chip following mask region 121 in the mask of Figure 7 as shown in Figure 12a.
During the boron implant and drive operation, a small oxide layer grows over the oxide surface exposed through windows 110, 111 and 112, shown as the oxide layers 125 to 127 in Figure 8. These oxide layers are left in place to serve as a portion of a diffusion windo~ in a subsequent operation to be described in connection with the implantation of the source region.
A second photolithographic mask .is next provided to remove all of the oxide from the surface of region lO0 except those oxide patterns covering the P+
regions which have been diffused with the use of the mask of Figure 7. This mask will have the general appearance of the mask of Figure 7 but will have a reversed field.
A-fter the formation of the photolithographic mask pattern o~er all but the diffused P~ regions, an oxide etch takes place to produce the pattern shown in Figure 9 for the dot regions. Note that each of the oxide regions 125, 126 and 127 should have a diameter greater than about 6 microns after the oxide etch and the removal of the photoresist from the top surface of the oxide elements 125, 126 and 127.
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Thereafter, the wafer is cleaned and prepared for a phosphorus implant during which a beam of phosphorus atoms is applied to the surface of the chip area at a voltage of about 120 kV with an implantation dose o~
from l x 1011 ~o i x 1014 phosphorus atoms/cm2. This implantation produces the thin surface coating 9 shown in Figure 9 as the N~ region 130, in all regions not coated by the oxide dots or other oxide patterns above the P~ regions formed in the step of Figure 8 and defined by the mask of Figure 7. The N~ region 130 also is produced in the regions shown in Figure 13a at the gate contact finger regions. The N+ implant 130 permits the formation o-f the novel high conductivity region beneath subsequently formed gate oxîde, which high conductivity region has a constant lateral density and a gradient from relatively high concentration to relatively low concentration beginning from the chip surface beneath the gate oxide and extending down into the body of the chip.
Follo~ing the N~ implant 130, the wafer is placed in an oxidation tube and an oxide layer 131 is grown atop the upper surface o-f the wafer. Therea-fter, a polysilicon layer 132 is gro~n atop the oxide la~er 131. The polysilicon layer 132 typically could have a thickness of about 5,000 Angstroms and will constitute the gate electrode of the completed device, after further processing, as will be later described.
The polysilicon layer 132 is next covered with a second o~ide layer 133. Thereafter a third mask is applied to the surface o-f the device of Figure 10 and a photoresist is exposed through the mask pattern shown in Figure 11. In Figure 11, the opaque portions of tlle photoresist mask are shown in dark or cross-hatched lines. The surface of the device o-f Figure 10 is shown in Figure 15 after etching through the mask -formed with the pattern of Figure ll. The mask of Figure 11 has, in the large shaded areas between the gate contact fingers, a pattern of polygonal sections centered on each of dots 102 of the mask of Figure 7.
Each of these sections will, as will later be seen, define respective polygonal cells which are connected in parallel between the top and bottom surfaces of the chip After the photoresist pattern~ using the mask pattern of Figure 11, is formed on the surface of oxide layer 133, an oxide etch takes place to etch polygonal openings in oxide layer 133. This etch leaves a hexagonal grid remaining in the surface of layer 133 and beneath the corresponding photoresist grid.
Note that the typical polygonal openings 140, 141 and 142 in the oxide layer 133 are celltered over the P~ dot regions 113, 114 and 115~ respectively, in Figure 14 which is a plan view of a small portion o-f the polygonal cell region of Figures 11 and 15.
The oxide grid 133 which remains in Figures 14 and 15 ~ill then serve as a masX for a subsequent polysilicon etch. An etch is then carried out to etch polygonal openings in the polysilicon layer 132. Subse-quently using the polysilicon as a mask, the oxide layer 131 has hexagonal openings etched therein by an oxide etch as sho-~n in Figure 16. Ater these etching operations~ a polygonal networ~ remains on the surface of the N- epitaxial layer 100 formed of a lo~.~er oxide layer 131 and an upper polysilicon layer 132 which defines the gate for the devices which are subsequently formed in the remaining steps of the process.
~Yhile the hexagonal grid de~ining the polysilicon gate 132 and its`underlying oxide layer 131 are formed , in Figures 14, 15 and 16, the same oxide etch and polysilicon etch ~ill produce the pattern for the ex~ending ~ate contact fingers, such as finger 104 3 as is shown in Figure 7. Thus, in Figure 13b, polysilicon S layer 132 overlying oxide layer 131 extends along the surface of the chip, with the outer edges of the strip 131-132 serving the purpose of a cell edge which cooperates with ~he cell to be formed about the P+ regions 117 and 118, respectively. The same is true of all other cells in the columns of cells containing cells 117 and 118, respectively.
The polysilicon layer 13~ and oxide layer 133 encircle the periphery of the device as shown in Figure 12b. Note that the polysilicon layer is severed at the periphery of the device and at region 150 through appropriate masking and etching steps during the etching of the polysilicon layer 132 of Figures 14 and 15 to form the hexagonal grid pattern, and outer rings 132a and 132b are formed.
Follo~ing khe etching of the o~ide layer 131 and polysilicon layer 132 by the process just described, the wafers are placed in an implanting apparatus. A
boron implant is then applied to the wafer surface to implant P type conductivity carriers in the windows formed i~ the oxide and polysilicon coatings on the surface of the wafer which define a mas~ to the implanting boron beam.
The boron beam may have a voltage of abou-t 50 kV and applies a dose of from 5 x 10 to 5 ~ 1014 atoms/cm2. Th;s implant is followed by a diffusion drive which can vary from 30 minutes to 120 minutes at a temperature in the range of 1150C to 1250~C. This operation then -forms P+ annular rings 160, 161 and 162 shown in Figure 17 surrounding the individual P~ dot regions 113, 114 and 115, respectively. The N+ region , 130 is also driven deeper beneath the wafer surface, as shown in Figure 17, during the diffusion drive for driving the P~ regions 160, 161 and 162.
Following this drive, the exterior surface of the wafer is deglassed as by use of hydrofluoric acid and the wafer is then again placed in a furnace and e~posed to POC13 in an appropriate carrier gas for from 10 minutes to 50 minutes at a temperature of from 850C to 1000C. This step forms the N+ source rings, lQ such as the N+ rings 170 and 171 which surround P
regions 113 and 114 in Figure 18. Respective source rings~ such as rings 170 and 171, enclose each of the thousands of cells formed on the surface of ~he chip and have outer hexagonal peripheries ~hich have constant spacing of from 13 to 15 micons be-tween adjacent hexagonal elements.
The source rings 170 and 171 define, within the P~ regions 160 and 161, respectively, hexagonal channels such as channels 172 and 173 in Figure 1~
~hich lead to the common N+ region 130 beneath the gate oxide 131~
As a consequence of the process, the distribution of donors and acceptors in the N-~ region 130, beneath the gate oxide 131, is that shown in Figure 19. By comparing Figures 19 and 6, it will be apparent that the distribution of donors at the surface of the wafer is constant rather than varied as shown in Figure 6.
Moreover, the density of donors at the upper portion of the wafer is greater than that in the lower region, thereby to cause the beneficial results of reducing depletion in the regions 160 and 161 during operation of the device, to reduce the resistance beneath the source regions 170 and 171. This, in turn, reduces the affect of the bi-polar transistor defined unintentionally by the various junctions and avoids second breakdown :.:
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problems in connection with that transistor. The structure also increases the avalanche energy of the device.
~s shown in Figure 13c, hexagonal P+ regions 117 and 118 are also formed during the P+ and N+ implanta-tion steps described in connection with Figures 17 and 18. The edge of the cells of each of the columns containing regions 117 and 118 define channel sections 180 and 181 disposed beneath the opposide sides of the o~ide stripes 131 of the gate -finger.
Following the formation of the source regions in the steps of Figures 17 and 18, such as source regions 170 and 171, the device is again deglassed as by etching in hydrofluoric acid.
After deglassing, the wafer is again placed in an oxidation tube and, as shown in Figure 20, an oxide layer 190 is grown over the entire outer surface of the device. Thereafter, a silox layer 191 is deposited over the oxide surface. The wafer is then placed in a reflow tube to reflow the silox. Silox is well known and is a phosphorus-doped silicon oxide which can reflow to form a continuous glassy coating follo~ing the contours of the surface on which it is received. Preferably, the silox layer 191 contains 7% to 10% by weight of phosphorus~
Note that the oxide layer 190 and silox layer 191 are also deposited over the elongated gate finger region as shown in Figure 13d, and over the outer periphery o-f the device of Figure 12b (not shown).
Thereafter, and as shown in Figure 21, a fourth mask is applied to the upper surface of the ~afer and a photoresist pattèrn is formed on the upper surface of the wafer corresponding to the configuration of the mask of Figure`21, where the dark areas of the mask of Figure 21 represent unpolymerized areas of the photoresist. The dot pattern in the mask of Figure 21 -d~

forms openings aligned ~ith the initial P+ implant regions such as regions 113, 11~ and 115, while the lines, such as lines 200 and 201 for the gate finger regions, overlie the center of the gate finger patterns of the mas~ of Figure 7.
After the forma.tion of the photoresist mask, shown as the photoresist mask 202 in Figure 20, central areas of each of the polygonal cells are exposed and an oxide etch is carried out to etch a~ay the exposed silox 191, the exposed oxide 190 and the oxide 125 and expose the upper surface of expitaxial region 100 at the center of each of the polygonal cells.
The wafer is thereafter cleaned and aluminum is evaporated onto the entire upper exposed surface of the wafer as shown by the aluminum layer 210 in Figure 22.
In Figure 22, all of the P~ regions are merged - to define P+ cells 220 and 221 l~hich contain ring-shaped source elements 170 and 171. N+ regions 130 have a depth, for example, of greater than about 1 micron below the upper surface. Note that each of the P-~ regions has the desired shelf configuration beneath the N~ rings as was previously described in Figure 5.
The effect of the mask of Figure 21 on the extending gate fingers is shown in Figure 13d, where the mask of Figure 21 permits the formation of a slit in the photoresist pattern including .sect.ions 220 and 221 in Figure 13d leaving a central gap over the silox coating 191. Thus, during the oxide etch which follo~s the forming of the photoresist pattern, the exposed silox-l91 in Figure 13d and then the oxide layer 190 therebeneath will be etched away to expose the underlying polysilicon layer 132. Thereafter, and as shown in Figure 13e, the aluminum layer 210 is .coated over the entire exposed surface of ~he contact fingers.

s ~ 53~
- 2~ -The effect of the maslc of Figure 21 on the outer peripheral pattern of the chip is shown in Figure 12c. Thus, the mask o-f Figure 21 masks the surrounding peripheral region in such a manner that the subsequent oxide etch will etch elcngated windows 230 and 231 through the silox layer 191. This double cut prevents the polarizing of the reflowec. silox glass 191.
Thereafter, the aluminum coating 210 is laid down over the exposed gate finger region as shown in Figure 12d.
The ne~t mask to be employed in the process is a mask which enables the laying of a photoresist mask to permit the etch of strips or windows 250 and 260 in each of -the extending gate Eingers as shown in Figure 13f. Thus, an appropriate photoresist pattern is laid down and an aluminum etch is carried out using a suitable aluminum etch medium, thereby to isolate the central aluminum finger overlying onl~r the P~ region 116. This aluminum finger serves as a gate contact which is connected to the polysilicon 132 wh;ch is, in turn, a continuolls part of the polygonal mesh extending over the full surface of the chip. In this ~ay, the gate fingers are electrically connected to a large number of individual hexagonal regions, thereby to make good electrical connection to the entire gate surface available for the chip.
At the same time, the mask enables the further processing o-f the enclosing periphery of the chip by etching the aluminum layer in the regions 230 and 231 as shown in Figure 12e. Note in Figure 12e that the metallizing 210 has a se~Tered annular region 210a ~hich is electrically connected to polysilicon region 132a beneath it to act as a field stopper ring. Since region 210a is connected to the drain, the N- region below ring 210 and at the outer

3~ ~eriphery of the chip cannot invert due to a charge on '' , ,. , ~ - :

polysilicon rec~ion 132~. The outer periphex~ of metallizing 21~ is connected to ring 132b as shown in Fic3ure 12e where xin~ 132 acts as ~ field plate.

Following the aluminum etch, the photoresist is stripped and silox is deposited over the entire exposed sur-face of the wafer and of all the chips within the wafer.
This s~cond silox layer 250 (Figure 22) is for protective purposes and is not reflowed. The silox layer 250 has a lower phosphorus concentration than the first layer 191 and, for example, can be from 2~ to 4~ by weight.

Thereafter, a sixth mask is applied to the device which masks the entire surface except for the enlarged pad regions for connection to the gate and to the source (corresponding to regions 105 and 106 in Figure 7). The wafer is then immersed in a silox etch which removes the silox from the pad regions and exposes tne aluminum coating on the pads. The photoresist is then stripp~d from the wafer and the wafer is appropriately cleaned.

Thereafter, a back metal, consisting of layers of ehromium, niekel and silver, is applied to the wafer, shown as baek eleetrode 270 which serves as the drain con-nection region for the device.
All of the chips are then appropriately probed and broken out of the wafer along theix scribe lines, as was desc~iked in conneCtiQn with ~c~u~ 1 and ~re cleaned.
Suit~ble eleçt~ode ~es ~;re thçn eonneetçd to the source and c~ate pads and the deyice i~s ~ounted in a housing which ma~ be cQnnected to the drain eleetrode 270.

The inventiQn has been described above in connection with a cellul~r type arxangement ~or the source cells aS disclosed inapplieant'~ Canadian Patent No. 1,123, `5~

119, i$sued May 4, 1982. Clearly, the inVention is also applicable to interdi~itated source configuxations as disclosed in applicant's Canadian Patent No. 1,123,11~, issued l~ay 4, 1982.

- 25a -.

Claims (14)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A high current MOSFET having low forward resistance comprising a semiconductor chip having first and second parallel surface; said chip having a body portion which is relatively lightly doped with impurities of a first conductivity type; said body portion extending from said first surface for at least a portion of the thickness of said chip; a plurality of local regions of a second conductivity type distributed over and extending into said first surface of said chip; a plurality of source regions of said first conductivity type extending into respective ones of said plurality of local regions and having a depth less than the depth of their said respective local region and an outer periphery which is interior of and spaced by a fixed distance from the periphery of said local region at said first surface, thereby to define short conduction channels capable of inversion; each of said plurality of local regions being spaced from one another at said first surface by a symmetric mesh of said body portion; a mesh-shaped gate insulation layer extending over said mesh between said local regions and overlapping said short conductive channels surrounding said local regions; a mesh-shaped gate electrode disposed atop said gate insulation layer; a vertical conductive region of said first conductivity type extending from beneath said gate insulation layer and between adjacent local regions and toward said second surface; said vertical conductive region having a higher doping concentration than that of said body portion for a depth below said first surface which is less than the depth of said local regions; said doping concentration in said vertical conductive region having a constant value laterally across said first surface beneath said insulation layer.

2. The MOSFET of claim 1, wherein the doping concentration beneath said gate insulation layer decreases with depth below said first surface, and has a constant lateral concentration at any given depth.

3. The MOSFET of claim 1, wherein a source elec-trode is connected to each of said source regions and extends over said first surface and a drain electrode is connected to said second surface.

4. The MOSFET of claim 2, wherein said vertical conductive region has a depth beneath said first surface of about one micron.

5. The MOSFET of claim 2, 3 or 4, wherein said local regions and said source regions have corresponding peripheries which are polygonal.

6. The MOSFET of claim 2, 3 or 4, wherein said local regions and said source regions have corresponding peripheries which are hexagonal.

7. The MOSFET of claim 1, 2 or 3, wherein said local regions have a deep central region and a shallow outer periphery; said source regions overlying said shallow outer peripheries of their said respective local regions.

8. The MOSFET of claim 3 or 4, wherein at least one elongated gate contact is deposited on said mesh-shaped gate electrode for making contact to said mesh; said elongated gate contact being coplanar with said source electrode and electrically insulated there-from.

9. The MOSFET of claim 1, wherein said chip has a floating guard rina of said second conductivity type extending around the outer periphary of said first surface.

10. The MOSFET of claim 9 wherein said floating guard ring is covered by an oxide and wherein a conductive ring is deposited on the outer edge of said oxide to act as a field plate and wherein said source electrode is deposited on top of the inner surface of said oxide; said oxide having a silox coating; said silox coating having first and second gaps located on opposite sides of said guard ring and between said field plate and said source electrode.

11. The MOSFET of claim 2 wherein a source electrode is connected to each of said source regions and extends over said first surface and a drain electrode is connected to said second surface; said gate insulation layer being an oxide and said gate electrode atop said oxide being polysilicon.

12. The MOSFET of claim 11 which includes a silox layer overlying said polysilicon gate electrode and insulating said gate electrode from said source electrode.

13. A MOSFET power switching device having a relatively low on-resistance comprising: a flat thin wafer of monocrystalline silicon having an upper portion of relatively high resistivity material and extending to one surface of said body; at least first and second source regions of one conductivity type in said one surface of said body spaced from one another and first and second source electrodes connected to said first and second source regions; a drain electrode connected to the surface opposite to said one surface; insulation layer means on said one surface and disposed between said first and second source electrodes and a gate electrode disposed on said insulation layer means;
first and second regions of a conductivity type opposite said one conductivity type extending to said one surface of said body at locations beneath said insulation layer means; and a further region disposed between said first and second regions and disposed directly beneath said insulation layer means and in contact with said insulation layer means and extending a given depth which is less than the thickness of said upper portion of said body and which has a conductivity which is relatively high in comparison to the conductivity of said upper portion of said body; said further region having a substantially constant lateral doping concentration.

14. The device of claim 13 wherein said constant lateral doping concentration decreases with depth.