CA1168393A - System for diffusion of data - Google Patents

Abstract

--ABSTRACT OF DISCLOSURE

A system broadcasts videotext data in the form of data packets originating from numerical data coming from several paths. Each packet has a prefix which contains synchronization and path identification code signals, a format signal which indicates the length of the data which follow the prefix. The transmitting station has as many coupling devices as there are paths for originating data. The coupling device has a data memory coupled to drive to a multiplexing circuit under the control of a common governing circuit. An inhibition order is given either as soon as the memory is full, or as soon as a counter has reached a pre-determined count. Then, the memory is connected to the multiplexing circuit, into which the stored data is emptied. The system is characterized in that a small capacity buffer is used between the memory and the input circuit for reading data out of the buffer memory responsive to a programmer. A transcoder treats the broadcast data to fit it into the system format.--

Description

3~3 01 The presen-t invention relates to 02 modifica-tions, chanyes and improvemen-ts in the 03 unidirectional data transmission system described in 04 French Patent Application NoO 75 18319 (now U.S.
05 Patent 4,115,662) first appliecl for in France on June 06 6, lg75, in the joint names of the Applicants, and in 07 the First Certificate of Addition Certificate No~
08 7,717,625 (now U.S. Patent 4,317,132) first applied 09 for in France on June 3, 1977.
In the unidirectional or broadcast data 11 -transmission system of -the main patent and o-f the 12 First Certificate of Addition indicated above, the 13 transmit-ted data are arranged in packets, each packet 14 having, at most, the active duration of a line of television image. The packets are inserted either in 16 place oE the image signals or in place of the scan 17 return lines, i.e. between -the conventional 18 synchronization signals of television lines.
19 Each packet which is broadcast begins with a prefix containing, the synchronization signals of 21 conventional binary elements and of octets (i.e. eight 22 bit words) and the path iden-tification code signals.
23 A packet format siynal indicates the length of the 24 succession of data, which follows the prefix. More specifically, in the data packet, the useful data and 26 the prefix-composing data are grouped into octets.
27 Therefore, the format signal is an octet which 28 indicates the number of octets of useful data which 29 follows the prefix.
The tests carried out with the 31 transmission system, according to the above-defined 32 system, and using as transmission support a public 33 broadcast network, have shown that it was necessary -to 34 protect the data packet against transmission errors, the same conclusion being valid for -the informations 36 contained in -the prefix. As the data packet is formed 37 of octets, it proves especially simple to provide for 38 ~
39 ~ f 01 a protection agains-t errors arld Eor an error 02 correction, octet by octet. It is then normal -to 03 adopt an octe-t struc-ture conforming to a Hamming code, 04 that is to say a structure in which, for example, -the 05 binary elemen-ts bl, b3, b5 and b7 are reserved for the 06 correction of errors, while -the binary elements b2, 07 b4, b6 and b8 carry the data.
08 In order not to unduly extend the prefix, 09 it will be seen that a single format octe-t comprising only four useEul binary elements, can serve -to count 11 only to 16. Now, the number of the octets which 12 follow a prefix may, as described in the 13 above-indicated applications, exceed that value by 14 much.
One object of the present inven-tion is to 16 provide for a system which mades it possible, through 17 the use of a pre-determined convention, to use only a 18 single format octet, in each data packet preEix, the 19 format oc~et comprising four information carrying binary elemen-ts and four binary elements for the 21 correction of possible errors in transmission, for 22 useful data packets comprising more than sixteen 23 octets and, especially, up to fifty-one useful octets.
24 According to a characteristic of the present invention, a data broadcast system includes 26 the emitting station broadcasts in the form of data 27 packets, each packet comprising a prefix containing,

2~ in addition to the usual synchronization signals and 29 path identification code, a packet format signal which indicates the length of the succession of data which 31 follows the prefix. The emitting or sending station 32 comprises as many coupling devices as there are paths, 33 each coupling device comprising an input circuit 34 having an input which is connected to the output of the path associated with -the coupling device. The 36 output of tha coupling device is connected to a data 37 memory, the output of which can be connected to a :

3~3 01 multiplexing circuit uncler contro:l of a governing 02 circui-t which is common to all of -the coupling 03 devices. A coun-ter is Eed at a pre-deterrnined clock 04 rate or rhythm. The inhibition order of the input 05 circui-t is given either as SQOn as the memory is full 06 or as soon as the counter has reached a pre-determined 07 count. Thereafter, the memory is connected to the 08 multiplexing circuit, and then emptied. The counter 09 is set back to zero and the inhibition order is eliminated. A register has an adjus-table maximum 11 capacity causing or governing the inhi.bition order 12 when -the count of the data reaches a pre~determined 13 value. Between -the memory and input circuit, -there is 14 a buffer mernory of small capacity. The reading of the buffer memory data is governed by a programmer.
16 According to another characteris-tic, a 17 receiving equipment of the da-ta diffusion system, uses 18 the signals which follow the prefix, when the latter 19 is accepted in it. These signals are sent to a buffer memory, the output of which is connected to an outpu-t 21 circuit, with a Eormat signal register which stores 22 -the format signal of each prefix of each data packet 23 received. A counter is fed by a clock signal at the 24 frequency of the octets which, when it reaches a maximum count, empties the sequence of data from the 26 buffer memory into the output circuit. The length of 27 the sequence is limited by -the content of the format 28 register. The format register is :Eed by a transcoding 29 circuit which treats the broadcast format signal.
The above-indicated characteristics of the 31 present invention, as well as others, will appear more 32 clearly from the reading of the following description 33 of an embodiment. The description being given 34 relative to the attached drawing in which:
Figure 1 represents the block-diagram of a 36 data broadcast system in which the improvements 37 according to the present invention are incorporated.

01 Figure 2 is a diagram of data packe-ts 02 making i-t possible to illustra-te the functioning of 03 the system in Figure 1.
04 Figure 3 is a block-diagram of the logical 05 part of -the transmission equipmen-t.
06 Figure 4 is a diagram of a counter circuit 07 of a "programmer" or the coupling device in Figure 3.
08 Figure 5 i5 a block-diagram of a data 09 receiving equipment.
Figure 6 is a diagram of a transcoding 11 circuit of the receiving equipment in Figure 5.
12 The data broadcast system in Figure ].
13 comprises a transmitting or sending s-tation which has 14 transmission equipment 41 and an antenna 42, as well as a plurality of subscribers receiving stations, each 16 having a reception antenna 43, a television receiving 17 set 44 and a data receiving equipment 45.
18 The transmit-ting equipment 41 comprises a 19 unit 46 called "manager", which is responsive for time multiplexing the data messages coming Erom a plurality 21 of data sources which, in the described example, is 22 assumed to be limited to seven sources 47 to 53.
23 Equipment 41 further cornprises a modulation part 54 24 which receives, for one part, the signals transmitted by the manager circuit 46, and, for the other part, 26 video signals received through a connection 55, and 27 which transmits signals to a conventional transmitting 28 device, not shown, which feeds antenna 42. As an 29 example, a description of a modulation part 54, which is not part of the present invention, is found in the 31 Main Patent Application No. 75 18319 (U.S. Patent 32 4,115,662), already cited and, especially, with 33 respect to Figure 4 of such patent.
34 The data transmitted by the manager 46 are arranged in packets. In the modulation part 54, the 36 data packets are inserted in place of image signals, 37 between the conventional synchronization signals of ~, 01 the -television lines.
02 Figure 2 shows an example of data packets 03 transmit-ted by manager 46, and then, af-ter modulation, 04 by antenna 42.
05 The data packet has a length of N octe-ts 06 which are numbered from 1. to N, and it is composed of 07 two parts. The ~irst part, called prefix, i.9 prepared 08 under control of manager 46 and is constituted, in the 09 example represen-ted, by the first eigh-t octets 1 to 8. The second part of Figure 2, constituted by octe-ts 11 9 to N, with N-9 = M, constitutes the real data Oe the 12 data packet. The number N always remains inferior to 13 a number Nmax which may vary, depending on -the 14 standard of the television network which ensures the broadcast. The number N may be determined by 16 optimizing, taking into account the length oE -the 17 useful -television line and of the passing band. Thus, 18 in the French TV broadcast standard with 625 lines, 19 Nmax may reach 40, this corresponding to -the L
standard recommended by the CCIR.
21 In the prefix, the octets 1 and 2 are 22 reserved Eor synchronization of the binary elements of 23 the data packet. They are each composed of the 24 sequence of binary elements 10101010. Octet 3, called "beginning", conventionally makes it possible to 26 perform -the synchronization octet by octet and it may 27 correspond to the sequence 11100111. Octets 4, 5 and 28 6 are reserved for the identification of khe numerical 29 path, and they are prepared in coded form by the manager 46. Octet 7, called the "continuity" octet 31 makes it possible to count the numbers or the indices 32 of packets or of errors in the receiving equipment.
33 Finally, octet 8 indicates the "format" of the packet, 34 that is to say the number of octets M which follow the prefix to form the packe-t.
36 With reference again to Figure 1, the 37 television receiver 44 transmits, through its video 38 output, the video signals of the equipment 45. The 3~3 01 latter comprises a demodulating part ~6, a logica].
02 part 57 and a signal of b:lnary elements frequency 03 (bits) sent -through 60 and the last bl-t (N-3) x 8 of 04 the N octets sent through da-ta packet 61. rrh~
05 informations read by reader 58 are permanently applied 06 to a reception logic circuit 57. With respect to the 07 role of coded suppor-t circuit 59, it will be usefu:L to 08 refer to -the Main Patent Application (U.S. Pa-tent 09 4,115,662). The reception part 57 delivers in 62 -the data octets oE -the packets, through a suitable 11 terminal, such as 63, while the video signal delivered 12 by receiver 44 still is available in 64.
13 Figure 3 shows a data bus line 65, a 14 governing circuit 66 and one of a plurality of coupling agents 67, for connecting sources 47 to 53, 16 to line 65. In practice, data bus line 65, circuit 66 17 and coupling agents 67 cons-titute manager ~6, Figure 18 1. The governing circuit 66 is connected by bus 65 19 and it may govern coupling agents 67 and be connected by bus 65. Circuit 66 will not be described in detail 21 because it is iden-tical to circuit 76 in Figure 3 of 22 the Main Paten.t Application (U.S. Patent 4,115,662).
23 There will only be recalled from this patent that 24 circuit 66 sends in the form of addresses, questions 25 to the coupling agents, in order to collect the 26 identities of the coupling agents which may be ready 27 to emit. Then, it sends in successions transmission 28 orders toward those coupling agents.
29 In coupling agents 67, the interroga-tions coming from governing circuit 66 enter through 31 connection 68 which is connected to an address 32 identification circuit 69 comprising componen-ts 90, 92 33 and 126 in Figure 3 of the Main Patent Application 34 (U.S. Patent 4,115,662). Circuit 69 has its outlet connected to the Eirst input of an AND gate 111, the 36 output of which is connected to bus 65.
37 The data coming from the source associated 01 with coupling agen-t 67 are transmitted by a junction 02 70 of -the type described in -the French Pa-tent 03 Applica-tion No. 2,268,308, the title of which ls 04 "Standardized Inter:Eace Communications Device".
05 Through junc-ture 70, the data enter, in parallel 06 octets, into a logical circuit the input of which is 07 71 and the output of which is connected to an 08 intermediary buffer memory 72. In addition, the 09 "going" service wire of connection 70, which -transmits a change of state for each octet transmi-t-ted by 70, is 11 connected to -the input of an octet counter 73, the 12 ou-tput of which is connected to a reglster 74 wh:ich 13 contains the number of octets -transmitte-l by logic 14 circuit 71 to the intermediary buEfer memory 170.
Register 74 has a reset or se-tting back to zero input 16 connected to data bus line 65, an output connected to 17 the first input oE an AND ga-te 75, and an output 18 connected to the input of a memory counter 171.
19 Counter 171 has a governing input connected, through a connection 172, to bus line 65, and its output is 21 connected to memory 72.
22 Buffer memory 72 comprises two parts, one, 23 76, in which are registered -~he octets of the pacXet 24 prefix and the other, 77, in which are registered the 25 data octets coming from the source through 71 and 26 170. Part 76 has a firs-t input connected to a memory 27 78 which contains the octets 1 to 3, the 28 synchronization and 'start' octets, a second input 29 connected to a memory 79 whi.ch contains the three octets 4 to 6 for the identification of each packet 31 prefix, a third input connected to a packet counter 80 : 32 which delivers the number of the packet, that is -to 33 say the continuity octet, and a fourth input connected 34 to counter 171 which delivers, at the time of 35 transmission, the number of octets contained in part 36 77, that is to say the format octet.
37 An output of register 7~ also is connected nl to the first input oE a comparing device 81, the 02 second input of which is connected to -the output of a 03 memory 82 con-taining the number Mmax = Nmax -8, which 04 corresponds to the maximum number of the octets of 05 data which can be transmitted in a packet. Output 8l 06 is connected, on one side to an input of an OR gate 83 07 and, on the other side, -to the first input of an AND
08 gate 84. The output OR gate 83 is connec-ted to an 09 inhibition input of circuit 71.
The coupling age:n-t further comprises a 11 simulation circuit 85, which receives a speed 12 indication coming from c~overning circuit 66 through 13 da-ta bus 65 and a connection 86. The speecl indication 14 depends on -the speed of functioning of the recep-tion equipments which are capable oE receiving the data 16 from the source associated to the coupling agent.
17 With the speed information, simulator 85 simulates 18 emptyings of buffer memory 72. The emptyings are 19 counted in a counter 87 connected to the output of simulator 85. The outputs numbers 1 to 4 of counter 21 87 are connected to the inputs of an OR gate 88, the 22 output of which is connected to the second input of 23 AND gate 84. In addition, output "4" of counter 87 is 24 connected ko the second input of AND gate 75. The outputs of AND gates 75 and 84 are respectively 26 connected to the inputs of an OR gate 89, the output 27 of which is connected to the second input of AND gate 28 111. The output of AND gate 75 further is connected 29 to an input of the OR gate 83.
The output of memory 72 is connected to a 31 logical send or emission c.ircuit 90 which receives 32 from data bus 65, through connection 91, the frequency 33 signal of the binary elements and, through connection 34 92, the emission order coming from governing circuit 66. The output of logic send circuit 90 i.s connected 36 to line 65 through wire 93 which transmits in series, 37 bit by bit, the packet toward the modulation part of 01 the emission equipment. Connection 92 also is 02 connected to t.he inpu-t of counter ~0 which, in -this 03 way, can coun-t the packet emitted by coupling agent 04 67.
05 Circui-t 171 has an output connected, 06 through a connection 173, to part 76 of mernory 72, and 07 another output connected, through a connection 174, to 08 the reading governing inpu-t of buf:Eer memory 170.
09 Memory 170 is a memory the content oE which empties into part 77 o:E memory 72 at the time o:E each reading 11 order coming from memory 171.
12 A "programmer" or memory circuit 171, 13 shown i.n Figure 4, comprises four 'differen-t phase' 14 registers 175 to 178, :Eour OR gates 179 to 182, four AND gates 183 to 186, one OR gate 187, a binary coding 16 circuit 188 and a memory register 189. Registers 175 17 to 178 are fed in parallel through the "going" service 18 wire of connection 70. Register 175 has its ou-tpu-ts 19 Sl, S2, S3, S4, S8, S12, ..... S(4N), ... S(48), connected to the inputs of OR gate l.79. Register 176 has its 21 outputs Sl, S2, S3, S5, S9, .. , S(4N+l), .... ....S49, 22 connected to the inputs of -the OR gate 180. Register 23 177 has its outputs Sl, S2, S3, S6, S10, .... ...S(4N+2) 24 , S50, connected to the inputs of the OR gate 181. Register 178 has its outputs Sl, S2, S3, S7, 26 Sll, , S(4N+3), , S51, connected to the inputs 27 of OR gate 182. Coding device 188 comprises sixteen 28 inputs E0, El, E2, E3, E4, ... , E(4N), ...... , E48. The 29 count input El is connected in parallel, to outputs Sl of registers 175 to 178; in a similar manner, the 31 inputs E2 and E3 of coder 183 are respectively 32 connected, in parallel, to ou~puts S2, and S3 of those 33 registers. Input E4 of coder 188 is connected, in 34 parallel, to outputs S4 of 175, S5 of register 176, S6 of register 177 and S7 of register 178. In the same 36 manner, input EN of coder 183 is connected, in 37 parallel, to outputs S(4N~ of regis-ter 175, S(4N+l) of 3~

3~

01 register 176, S(4N+2) of reglster l77 and S(4N+3) of 02 register 178. Coding device 188 -transmi-ts, in binary 03 code, through connection 173, the rank of its las-t 04 activated input, to part 76 of memory 72 (Figure 3), 05 to form the Eormat oc-te-t, at the time of -transmission 06 oE -the data packet from memory 72 to line 65 for 07 broadcasting.
08 In addition, memory 189 has its data input 09 connected to connection 172, and four outputs Ll to L4 respectively connected to the first inputs of AND gate 11 183 to 186. Through connec-tion 172, line 65, 12 depending on the order given by the operator of -the 13 manager, transmits an order which causes one oE
14 outputs Ll to L4 to be marked. The outputs of the OR
gates 179 to 182 are respectively connected to the 16 second inputs of AND gates 183 to 186. The outputs of 17 AND ga-tes 183 to 186 are connec-ted to the 18 corresponding inputs of -the OR gate 187 the outpu-t of 19 which is connected to connection 17a,t toward the reading input of buffer mernory 170 (Figure 3).
21 If, for exarnple, it is assumed that output 22 Ll of 189 is marked, at each octet transmitted by 23 buffer memory 170 (Figure 3) to part 77 of 72, the 24 register with 'phase difference' moves Eorward. Each time the number of octets thus transmitted corresponds 26 to one of outputs (Sl, S2, S3, .. , S(~), .. , S48) 27 of register 175, the OR gate 179 transmits, through 28 the AND gate which has been opened by Ll, a signal 29 which, through the OR gate 189, is transmitted to the reading input of memory 170 which empties itself. It 31 therefore appears that the number oE octets in the 32 part 77 may be only "0", "1", "2", "3", "4"
33 "4N", .. , or "48". There can therefore be only 34 sixteen values oE octet numbers possible in part 77, which coding device 188 can code with four binary 36 elements. If, for example, output L2 of memory 189 is 37 marked, the outputs of register 176 are the ones which ~8~ 3 01 de-term.ine the read:ing times of buf:Eer memory l70.
02 There again, the number of those times o:E reading 03 limits -to sixteen -the number of the poss:ible values 04 for the numbers of octets in part 77. The result :Erom 05 the above is that as a func-tion of the marked outputs 06 oE memory 189, it is possible to make out four lists 07 oE octet numbers, indica-ted in the following Table.

09 T A ~ L E
b8 b6 b4 b2List 1List 2 List 3 List 4 11 Ll :L2 L3 L4 12 0 0 0 0 0 o 0 0 13 0 0 0 1 l 1 1.

17 0 1 0 1 ~ 9 0 11 18 0 1 1. 0 12 13 14 15 1 1 0 1 40 ~1 42 43 26 1 1 1 0 44 45 ~6 47 28 For block length L ranging from 0 ~o 3, 29 the lists are identical, above "3", they staisfy the following relationships:
31 List 1 L = 4N
32 List 2 L -- 4N + 1 33 List 3 L = 4N + 2 34 List 4 L = 4N + 3 It can be seen that, considered together, 36 the four above lists make it possible to choose any 37 maximum block size up ~o a value of "51". Thus, the ~16~393 01 freedom of choice o the blnary element frequency 02 which was acquired through -the use of the system 03 described in U.S. Patent 4,317,132 can thus be 04 integrally preserved.
05 The functioning of coupling agent 67 is 06 practically the same as that of U.S. Pa-tent 4,317,132, 07 except with respec-t to circuits 170 and 171.
08 Before the sending of information coming 09 from a particular source, the decision is reached to set the maximum length of the data blocks, this 11 determining list 1, 2, 3 or 4 which is going to be 12 used. The operator then has sent through data busses 13 65 and 172, the order -to mark the corresponding output 14 in memory 189 (Figure 4). One oE the AND gates 179 to 182 ls switched on to read the orders of the 16 corresponding register to buffer memory 170.
17 Moreover, the operator causes the 18 recording, in memory 82, of the number representing 19 the maximum size chosen.
It is known that memory 72 (Figure 3) 21 empties itself toward data bus 65 when the emission of 22 the packet is authorized and one of the following 23 conditions presents itself. Either the number of 24 octets introduced into memory 77 is equal to the maximum value written in memory 82, or the simulator 26 85 has caused counter 87 to pass to position "4"
27 before the maximum number has been reached. In both 28 cases, circuit 71 stops transmission on connection 70 29 because its governing input is inhibited by OR gate 83~ There may be any number of octets, between 0 and 31 4, in buffer memory 170; they remain there to be 32 transferred into memory part 77 on the occasion of the 33 formation of the following data packet. Registers 175 34 to 178 are set back to zero by their RESET inputs at each transmission of a data packet.
36 It must futher be noted that the operator 37 of the source associated with the coupling agent under 01 conslderation always transrnits only significant data, 02 and -that it does not have to worry about ei-ther the 03 maximum number, or the transmission frequency of -the 04 binary elements.
05 The demodula-tion part 56 of subscriber 06 recep-tion equipment is represented in Figure 5. The 07 vi.deo signals coming out of the television receiver ~4 08 are applied -to an impedance matching circuit 95, the 09 output signal of which is applied, on one side to a clock recovery circuit 96 or the recovery of the ;. 11 binary element Erequency and, on the other s:ide, to a 12 synchronization circuit 97. Synchronization circuit 13 97 is the same as circuit 97 in Figure 5 of the Main 14 Patent 4,115,662. It recognizes, especially, the starting octe-t so that it will -transmit to the logic 16 circuit 57, via connection 61, only -the fourth octet : 17 of each data packet and the following oc-tets. Circuit 18 96 comprises, as do the conventional circuits for the 19 recovery of the clock rate or binary element frequency, a tuned circuit comprising a variable 21 impedance component 98, which may be a varycap, the 22 impedance of which is governed by the television 23 channel selector 99O Circuit 96 delivers the clock 24 rate or binary element frequency signal on one side to synchronization circuit 97 and, to the other side, to 26 logic circuit 57 through connection 60.
27 In circuit 57, the signal at the frequency 28 of the bits is applied, on one side to an octet 29 register 100 and, on the other side, to a divider by eight 101 the output of which is connected to -the 31 input of an octet counter 102. The bits of the data 32 packet are applied by wire 61 to the data input of 33 octe-t register 100 which -transmits the octets in 3~ parallel to a switching circuit 103. Octet counter 102 has its first six outputs which correspond to the 36 first six octets received in 57, that is to say to 37 octets 4 to 9, connected to governing inputs of 01 switching circui-t 103, the inputs of which are 02 ac-tiva-ted in succession. Swltching circuit 103 03 orients, in succession, the oc-tets of the clata packeks 04 whi.ch are transmitted toward validation circult 106 05 for octets 4, 5, 6 and 7, -toward a Hamming correc-tion 06 circuit 190 for octet 8, and toward a data buffer 07 memory 105 for the following octets. The outpwt of 08 the Hamming correction circuit 190 is connected to the 09 input of a transcoding circuit 19l, the output oE
which is connected to Eormat reg.ister 104.
11 Validation circuit 106 may include 12 circuits 168, 179, 166, 171, 167 represented in F~igure 13 6 of the Main Patent 4,115,662 and, possibly, circui-ts 14 173 and 17~ of that same Figure.
The output of buffer memory 105 is 16 connected to the input of a switching circuit 107 17 which may be activated by a connection 108 coming from 18 validation circuit 106. The output of switch 107 is 19 connected to a junc-ture 62, of -the type of juncture 70 in Figure 3, which is connected to the subscribers 21 data terminal equipment 63 (Figure 1). One wire of 22 juncture 62 is connected to the input of a counter 109 23 which counts the octets transmitted by switch 107, and 24 the output of which is connected to the input of a comparing device 110. The other input of switch 107 26 is connected to the output of format register 104, and 27 the output of which is connected to the inhibiting 28 input of circuit 107. Finally, the output of octet 29 counter 102 is connected to a validation input of circuit 107.
31 Counter 102 activates its output when it 32 reaches the Nmax count. At that time, buffer memory 33 105 has recieved ~max octets of which possibly only P
34 data packet octets are valid, P representing the total length of the packet. Assuming that circuit 106 36 validates the packet, as soon as counter 102 validates 37 its output, the octets may be transferred from buffer 01 memory 105 to output 62 through switch 107. ~s soon 02 as P octets have thus been transferred, the two inputs 03 of comparing device 110 have the same values, and the 04 output of 110 forbids any other transmission Erom 05 memory 105 to output 62, for the television line under 06 consideration which serves as support to -the data 07 packet.
08 In the circuit in Figure 5, the Hamming 09 correc-tion circuit is a conven-tional circuit which will not be described, while transcoding circuit 191 11 makes it possihle, Eor bits b2, b4, b6 and b8 of the 12 format octet, to find the real length oE the block, 13 which is transmitted to format register 104. As an 14 example, circuit 191 may be provided for in the form indicated in Figure 6.
16 In the "transcoder" circuit 191 in Figure 17 6, the intake wires b2, b4, b6 and b8 transmit the 18 four binary elements delivered by the Ha~ning 19 correction circuit 190, in the increasing order of the weights. The input wire b8 is connected, on one side 21 to the input of an inverter 192 the output of which is 22 connected to an input of a NOR gate 193 the output o 23 which delivers a signal of the value 25 or 0 on wire 24 a5 and, on the other side, to an input of a NAND gate 195, the output of which is connected to an input of a 26 NAND gate 198, the output of which delivers a signal 27 of the value 24 or 0 to wire a4. Input wire b6 is 28 connected on one side to an input of a NOR gate 194, 29 the output of which is connected to the second input of -the NAND gate 195, and to the second input of the 31 NOR gate 193 and, one the other side, to an input of 32 an NAND gate 197 the output of which is connected to 33 the second input of NAND gate 198.
34 The input wire b4 is connected, on one side, to an input of an AND gate 196 the output of 36 which is connected to the second input of the NOR gate 37 194, to the second input of the NAND gate 197 and to :

:;
:~
:, 01 -the Eirst inpu-t of a three input NOR gate 200, and, on 02 -the other side, to the first input of an NOR gate 199, 03 the output of which is connected to the second inpu-t 04 of the NOR gate 200, -the output of which delivers a 05 signal of value a3 or 0 to wire a3. Input wire b2 is 06 connec-ted, one one side, to the second input of -the 07 NAND gate 199 and, finally, to the firs-t input of an 08 NOR ga-te 201 which delivers a signal of value a2 or 0 09 to wire a2. Input wire b4 is also connec-ted to an input of an AND ga-te 202, the output of which is 11 connected -to an input of an OR gate 203 which delivers 12 a signal oE a value 21 or 0 to the wire al. Input 13 wire b2 also is connected to the first inpu-t oE an AND
14 gate 205 the output of which is connected to an input of an OR gate 206 which delivers a signal of a value 16 2 or 0 to wire aO. Wire b6 also is connected to an 17 input of an NOR gate 204 the output of which is 18 connected, in parallel, -to the third input of the NOR
19 gate 200, to the second input of -the NOR gate 201, to the second input of the AND gate 202, to the second 21 input of the AND gate 205 and to -the input of an 22 inverter 209. The output of inverter 209 is connec-ted 23 to the first inputs of two AND gates 207 and 208. The 24 output of gate 207 is connected to the second input of - 25 t'he OR gate 203 and the output of the gate 208 is 26 connected to the second input of OR gate 206. The 27 second inputs of AND gates 207 and 208 are 28 respectively connected to two governing wires a and b.
29 The values of -the outputs a5 to aO are added in adding device 210 before being applied to 31 circuit 104.
32 It seems that wi-th the following 'truth' 33 Table:
34 a b 0 0 list 1 36 0 1 list 2 37 1 0 list 3 38 1 1 list .:

:
01 in which a ancl b represen-t -the binary elements which 02 may be applied to terminals a and b by -the users of 03 the receiver, transcoding of bits b8, b6, b4 and b2 by 04 transcoder 191 gives the results indicated in -the 05 foregoing Table.
06 It must be noted that transcoding 07 essentlally bears on the obtaining of signals in list 08 1, considering -that -those of lis-t 2 are deduced from 09 them through the adding of one uni-t to -the nu~bers starting from 0100, then those of list 3 through ll adding two units and, finally, those of list 4 -through 12 adding three units. With respec-t to the means used in 13 the circuit ln Figure 6, it must be noted that, in 14 order to obtain the last three lists, it is sufficient to add to the means necessary to ob-tain lis-t l, the 16 two AND gates 207 and 208, plus inver-ter 209.
17 If there is again considered the prefix of 18 a data packet, it appears that the choice of the list 19 must be agreed upon in advance between the operator of -the broadcasting transmitter and the subscribing 21 users. It is sufficient to that end to make known, by 22 a wide broadcast subscribing means: newspaper or 23 televised summary, the a, b code to be formed by each 24 user, for example by means of keys on the selector keyboard of the subscriber's apparatus.
26 In addition, it will be noted that, in -the 27 prefix, the continuity index, when same exists, rnust 28 also occupy only one service octet, thus implying, if 29 there is desired the possibility of correcting a transmission error on a binary element, that the 31 numbering of the packets runs from 0 to 15, then 32 starts again in a cyclic manner.
33 It is obvious that -the circuit in Figure 4 34 represents only one embodiment. In practice, with modern -technique, it would be executed, as would the 36 entire coupling device unit, using a 37 micro-processor.

.

Claims (2)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A system for broadcasting data in the form of data packets sent from a transmitting station; said data packets including numerical data received from at least one of a plurality of incoming paths and combining such data into a format comprising a prefix containing synchronization and path identification code signals, said packet also including a format signal indicating the length of the successive data words which follow the prefix; said system comprising:
a transmitting station having a plurality coupling means, one coupling means being individually associated with each of said incoming paths;
common governing means for controlling all of said plurality of coupling means, each of said coupling means having an individual input circuit means coupled to receive data over the incoming path which is individually associated with the coupling device;
multiplexing means for preparing said data packets for transmission;
data memory means individually associated with each of said input circuit means for driving said multiplexing means under control of said common governing means;

counter means operated at a pre-determined bit clock rate for retaining a memory of the amount of data stored in said data memory;
means responsive to at least a partial filling of said data memory means as indicated by said counter means for inhibiting the input circuit means associated therewith;
means responsive to said inhibiting of said input circuit means for connecting said data memory means to the multiplexing means and emptying the data memory means, and for resetting the counter means, the inhibition being removed on the emptying of said memory means;
a register means having an adjustable maximum capacity for causing said inhibition order to be given when the count of said data again reaches a pre-determined value; and a small capacity buffer memory means interposed between said input circuit means and its individually associated data memory means for smoothing the flow of said data into said data memory means, the reading of the data into and out of the buffer memory being governed by a programmer means associated with said coupling means.

2. The system of claim 1 and means for sending the signals which follow the prefix into said buffer memory when said prefix is accepted;
transcoding circuit means for converting the format signal;
format signal register means responsive to said transcoding means for storing the format signal of each data packet as it is received, means responsive to said counter means reaching a maximum count for emptying data from the buffer memory means and into the output circuit means, the length of the emptying data being limited by the content of said format signal register means.