CA1174297A - Bi-phase modulator/demodulator - Google Patents
Bi-phase modulator/demodulatorInfo
- Publication number
- CA1174297A CA1174297A CA000386402A CA386402A CA1174297A CA 1174297 A CA1174297 A CA 1174297A CA 000386402 A CA000386402 A CA 000386402A CA 386402 A CA386402 A CA 386402A CA 1174297 A CA1174297 A CA 1174297A
- Authority
- CA
- Canada
- Prior art keywords
- output
- signal
- amplifier stage
- transistor
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes
Abstract
ABSTRACT OF THE DISCLOSURE
A bi-phase modulator/demodulator circuit for converting uni-polar to bi-polar signals. The circuit can be used to bi-phase modulate a continuous wave (CW) input signal or to demodulate a bi-phase coded input signal by use of transistor-transistor logic (TTL) control signals. A tri-state logic gate is used to convert two digital signals to an unbiased AC
signal which is applied to one of two inputs of a double balanced mixer. The other input of the mixer is adapted to receive a continuous wave signal for bi-phase modulation, or a bi-phase coded signal for demodulation.
A bi-phase modulator/demodulator circuit for converting uni-polar to bi-polar signals. The circuit can be used to bi-phase modulate a continuous wave (CW) input signal or to demodulate a bi-phase coded input signal by use of transistor-transistor logic (TTL) control signals. A tri-state logic gate is used to convert two digital signals to an unbiased AC
signal which is applied to one of two inputs of a double balanced mixer. The other input of the mixer is adapted to receive a continuous wave signal for bi-phase modulation, or a bi-phase coded signal for demodulation.
Description
Z~7 BI-PHASE MODULATOR/DEMODULATOR
The Government has rights in this invention pursuant to Contract Number F33615-77-C-1251 awarded by the Department of the Air Force.
SUMMARY OF THE INVENTION
The present invention relates to a bi-phase modulator/
demodulator circuit for converting uni-polar to bi-polar signals.
The circuit can be used to bi-phase modulate a continuous wave (CW) input signal or to demodulate a bi-phase coded input signal by use of transistor-transistor logic (TLL) control signals. A
tri-state logic gate is used to convert two digital signals to an unbiased AC signal which is applied to one of two inputs of a double balanced mi~er. The other input of the mixer is adapted to receive a continuous wave signal for bi-phase modulation, or a bi-phase coded signal for demodulation.
In accordance with the present invention there is provided a bi-phase modulator-demodulator circuit for converting uni-polar to bi-polar signals, comprising:
a tri-state logic gate having first and second inputs for receiving first and second digital sianals and having an output;
a first amplifier stage including a first transistor having a base electrode connected to receive the signal from the output of said tri~state logic gate and having an emitter electrode and a collector electrode;
impedance means for interconnecting said electrodes of said first transistor between sources of first and second potential so as to allow the signal at the collector electrode to swing linearly by a predetermined voltage amount in either direction ~.~'7~297 from a reference potential;
means for providing DC isolation between the output of said tri-state logic and the base electrode of said first transistor;
a second amplifier stage including second and third complimentary transistors connected to receive an input signal at a common junction joining their respective base electrodes, and to provide an output at a common ]unction joining their respective emitter electrodes, and further having their collectors respectively connected to sources of positive and negative potential;
means for providing DC isolation between the output of said first amplifier stage and the input of said second amplifier stage;
means for limiting the voltage swing at the output of said second amplifier stage between predetermined positive and negative voltage levels; and a double balanced mixer having a first input connected to receive the signal from the output of said second amplifier stage and having a second input and an output.
The present invention may be particularly useful in the apparatus of United States Patent Number 4,328,495, issued on May 4, 1982, in the name of Baard H. Thue. In the apparatus of Figure 1 of said United States Patent, the present invention could perform the functions of ON/OFF switch 12 and decode switch 32.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 of the drawings illustrates the preferred embodiment of the present invention; and -la-~ .~ '7~29~
Figure 2 illustrates typical signals appearing at various points in the circuit of Figure 1.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referri.ng now to Figure 1, a tri-state logic gate 10 is shown having a data input 11 and an enable -lb-~7A~2~7 input 12, and having an output. Tri-state logic gate 10 can be a tri-state inverter of the type manufactured by Texas Instruments and identified by SN54125.
The output of tri-state loqic gate 10 is connected to the base of a transistor 20 through a capacitor 15. The function of capacitor 15 is to provide DC isolation. The base of transistor 20 is further connected to a source of positive potential through a resistor 21 and to a ground potential terminal through a resistor 22. Transistor 20 further has an emitter connected to a ground potential terminal through a resistor 24 and a collector connected to the source of positive potential through 15 a resistor 23. Transistor 20 is biased by transistors 21, 22, 23, and 24, for class A operation and serves as the first amplifier stage. The bias resistors and the voltage is selected in the preferred embodiment such that the voltage signal at the collector of transistor 20 can swing linearly between approximately +3 to +15 volts.
The collector of transistor 20 is connected throu~gh a series of paths comprised of a capacitor 25 and a resistor 27 to the ground potential terminal, 25 while the junction between capacitor 25 and resistor 27 is connected to the common base junction of transistors 40 and 50 through a resistor 26, The function of capacitor 25 and resistor 27 is to reference the swing of the signa~ which is applied to 30 the base electrodes of transistors 40 and 50 about ground potential.
Transistors 40 and 50 are complimentary transistors connected to recei~e an input signal at a common junction joining their respective base ~ ~7~297 electrodes. Together with the associated bias network, transistors 40 and 50 comprise the second amplifier stage, providing an output at the common junction joining their respective emitter electrodes.
5 The collector of transistor 40 is connected through a resistor 41 to a source of positive potential, while the collector of transistor 50 is connected, through a resistor 51, to a source of negative potential. The collector of transistor 40 is further connected to a lO ground terminal through a capacitor 48 and the collector of transistor 50 is connected to the ground terminal through a capacitor 58. A diode 30 is connected for forward current flow between $he base electrodes of transistors 40 and 50 and a common 15 junction between resistors 42 and 43. Resistors 42 and 43 form a voltage divider between the source of positive potential and the ground terminal and provide a ~ixed reference voltage for diode 30. A second diode 31 is connected between the base electrodes of 20 transistors 40 and 50 and a wiper arm 54 of a variable resistor 53, which is, in turn, connected in series between resistors 52 and 55 to form a voltage divider network between a source of negative potential and a ground potential terminal. Resistors 52, 53, and 55 25 are selected such that the center of resistor 53 provides a voltage equal to but of opposite polarity to the voltage at the junction of resistors 42 and 43.
Capacitors 32 and 33 provide the required AC bypassing for the voltages supplied to diodes 30 and 31, 30 respectively.
A capacitor 48 is connected between the collector of transistor 40 and ground potential terminal and a capacitor 58 is connected between the collector of transistor 50 and the ground potential ~ ~74;~
. I
terminal. Resistors 41 and 51 and capacitors 48 and 58 provide decoupling and current limiting in the manner well known in the art.
The output of transistors 40 and 50 taken at the common junction of the emitters is applied, through a series path comprised of resistors 61 and 62 in parallel with a capacitor 60, to input 72 of a double balanced mixer 70. Resistor 62 is variable to permit the selection of an optimum current level for the mixer. A resistor 64 is connected between input 72 of mixer 70 and the ground to provide a return for the mixer when neither transistors 40 or 50 are conducting. A capacitor 65 connected between input 72 of mixer 70 and ground potential terminal and 15 capacitor 60, connected in parallel with resistors 61 and 62, optimize the coded signal wave shape supplied to mixer 70 at input 72.
Double balanced mixer 70 may be of the SRA-3H type manufactured by Mini-Circuits. Mixer 70 20 further has a second input 71 for receiving a continuous wave (CW) input signal which is to be modulated by the signal appearing at input 72, or a coded input signal which i5 to be demodulated ~y the signal appearing at input 72. The resulting modulated 25 or demodulated signal appears at output 73.
Figure 2 illustrates typical signals appearing at various points in the circuit of Figure 1. The signals appearing at inputs 11 and 12 of tri-state logic gate 10 are uni-polar signals of the 30 type shown in the top two wave forms of Figure 2.
Both of these signals are shown to swing between zero voltage and some positive value which is typically ~5 volts. The signal at the output of tri-state logic gate 10 (shown in the third waveform of Figure 2) ~ ~42~317 .. , swings between ground and typically ~5 volts. When logic gate 10 is not enabled, the output is an open circuit.
The signal from the output of logic gate 10 is applied to the base electrode of transistor 20 and results in an amplified signal appearing at the collector of transistor 20. This amplified signal swings between first and second positive voltage levels, which in the preferred embodiment were selected to be between +3 and ~15 volts, as shown in the fourth waveform of Figure 2.
The signal from the collector of transistor is then applied to the base electrodes of transistors 40 and 50 through the series path of capacitor 25 and resistor 26. Through the action of capacitor 25 and resistor 27, the signal applied to the base electrodes of transistors 40 and 50 is referenced to swing about the ground potential.
Resistor 26 provides the necessary resistance against 20 which clamp diodes 30 and 31 can operate. Resistors 42 and 43 provide a fixed reference voltage for diode 3n and establish the maximum positive voltage available at the emitters of transistors 40 and 50.
Similarly, resistors 52l 53, and 55 provide a fixed reference voltage for diode 31 and establish the maximum negative voltage available at the emitters of transistors 40 and 50. The output signal appearing at the common emitter junction of transistors 40 and 5~
is illustrated in the lower curve of Figure 2~ It can 30 be seen that the signal appearing at the common emitter junction of transistors 40 and 50 is a bi-polar signal corresponding to the uni-polar signal appearing at input 11 of tri-state logic gate 10.
~.~ 7~%g7 A preferred embodiment of the present invention has been described in the foregoing specification. Various modifications of the inventive concept will be obvious to those skilled in the art, without departing from the spirit of the invention.
It is intended that the scope of the invention be limited only by the following claims:
What is claimed is:
The Government has rights in this invention pursuant to Contract Number F33615-77-C-1251 awarded by the Department of the Air Force.
SUMMARY OF THE INVENTION
The present invention relates to a bi-phase modulator/
demodulator circuit for converting uni-polar to bi-polar signals.
The circuit can be used to bi-phase modulate a continuous wave (CW) input signal or to demodulate a bi-phase coded input signal by use of transistor-transistor logic (TLL) control signals. A
tri-state logic gate is used to convert two digital signals to an unbiased AC signal which is applied to one of two inputs of a double balanced mi~er. The other input of the mixer is adapted to receive a continuous wave signal for bi-phase modulation, or a bi-phase coded signal for demodulation.
In accordance with the present invention there is provided a bi-phase modulator-demodulator circuit for converting uni-polar to bi-polar signals, comprising:
a tri-state logic gate having first and second inputs for receiving first and second digital sianals and having an output;
a first amplifier stage including a first transistor having a base electrode connected to receive the signal from the output of said tri~state logic gate and having an emitter electrode and a collector electrode;
impedance means for interconnecting said electrodes of said first transistor between sources of first and second potential so as to allow the signal at the collector electrode to swing linearly by a predetermined voltage amount in either direction ~.~'7~297 from a reference potential;
means for providing DC isolation between the output of said tri-state logic and the base electrode of said first transistor;
a second amplifier stage including second and third complimentary transistors connected to receive an input signal at a common junction joining their respective base electrodes, and to provide an output at a common ]unction joining their respective emitter electrodes, and further having their collectors respectively connected to sources of positive and negative potential;
means for providing DC isolation between the output of said first amplifier stage and the input of said second amplifier stage;
means for limiting the voltage swing at the output of said second amplifier stage between predetermined positive and negative voltage levels; and a double balanced mixer having a first input connected to receive the signal from the output of said second amplifier stage and having a second input and an output.
The present invention may be particularly useful in the apparatus of United States Patent Number 4,328,495, issued on May 4, 1982, in the name of Baard H. Thue. In the apparatus of Figure 1 of said United States Patent, the present invention could perform the functions of ON/OFF switch 12 and decode switch 32.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 of the drawings illustrates the preferred embodiment of the present invention; and -la-~ .~ '7~29~
Figure 2 illustrates typical signals appearing at various points in the circuit of Figure 1.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referri.ng now to Figure 1, a tri-state logic gate 10 is shown having a data input 11 and an enable -lb-~7A~2~7 input 12, and having an output. Tri-state logic gate 10 can be a tri-state inverter of the type manufactured by Texas Instruments and identified by SN54125.
The output of tri-state loqic gate 10 is connected to the base of a transistor 20 through a capacitor 15. The function of capacitor 15 is to provide DC isolation. The base of transistor 20 is further connected to a source of positive potential through a resistor 21 and to a ground potential terminal through a resistor 22. Transistor 20 further has an emitter connected to a ground potential terminal through a resistor 24 and a collector connected to the source of positive potential through 15 a resistor 23. Transistor 20 is biased by transistors 21, 22, 23, and 24, for class A operation and serves as the first amplifier stage. The bias resistors and the voltage is selected in the preferred embodiment such that the voltage signal at the collector of transistor 20 can swing linearly between approximately +3 to +15 volts.
The collector of transistor 20 is connected throu~gh a series of paths comprised of a capacitor 25 and a resistor 27 to the ground potential terminal, 25 while the junction between capacitor 25 and resistor 27 is connected to the common base junction of transistors 40 and 50 through a resistor 26, The function of capacitor 25 and resistor 27 is to reference the swing of the signa~ which is applied to 30 the base electrodes of transistors 40 and 50 about ground potential.
Transistors 40 and 50 are complimentary transistors connected to recei~e an input signal at a common junction joining their respective base ~ ~7~297 electrodes. Together with the associated bias network, transistors 40 and 50 comprise the second amplifier stage, providing an output at the common junction joining their respective emitter electrodes.
5 The collector of transistor 40 is connected through a resistor 41 to a source of positive potential, while the collector of transistor 50 is connected, through a resistor 51, to a source of negative potential. The collector of transistor 40 is further connected to a lO ground terminal through a capacitor 48 and the collector of transistor 50 is connected to the ground terminal through a capacitor 58. A diode 30 is connected for forward current flow between $he base electrodes of transistors 40 and 50 and a common 15 junction between resistors 42 and 43. Resistors 42 and 43 form a voltage divider between the source of positive potential and the ground terminal and provide a ~ixed reference voltage for diode 30. A second diode 31 is connected between the base electrodes of 20 transistors 40 and 50 and a wiper arm 54 of a variable resistor 53, which is, in turn, connected in series between resistors 52 and 55 to form a voltage divider network between a source of negative potential and a ground potential terminal. Resistors 52, 53, and 55 25 are selected such that the center of resistor 53 provides a voltage equal to but of opposite polarity to the voltage at the junction of resistors 42 and 43.
Capacitors 32 and 33 provide the required AC bypassing for the voltages supplied to diodes 30 and 31, 30 respectively.
A capacitor 48 is connected between the collector of transistor 40 and ground potential terminal and a capacitor 58 is connected between the collector of transistor 50 and the ground potential ~ ~74;~
. I
terminal. Resistors 41 and 51 and capacitors 48 and 58 provide decoupling and current limiting in the manner well known in the art.
The output of transistors 40 and 50 taken at the common junction of the emitters is applied, through a series path comprised of resistors 61 and 62 in parallel with a capacitor 60, to input 72 of a double balanced mixer 70. Resistor 62 is variable to permit the selection of an optimum current level for the mixer. A resistor 64 is connected between input 72 of mixer 70 and the ground to provide a return for the mixer when neither transistors 40 or 50 are conducting. A capacitor 65 connected between input 72 of mixer 70 and ground potential terminal and 15 capacitor 60, connected in parallel with resistors 61 and 62, optimize the coded signal wave shape supplied to mixer 70 at input 72.
Double balanced mixer 70 may be of the SRA-3H type manufactured by Mini-Circuits. Mixer 70 20 further has a second input 71 for receiving a continuous wave (CW) input signal which is to be modulated by the signal appearing at input 72, or a coded input signal which i5 to be demodulated ~y the signal appearing at input 72. The resulting modulated 25 or demodulated signal appears at output 73.
Figure 2 illustrates typical signals appearing at various points in the circuit of Figure 1. The signals appearing at inputs 11 and 12 of tri-state logic gate 10 are uni-polar signals of the 30 type shown in the top two wave forms of Figure 2.
Both of these signals are shown to swing between zero voltage and some positive value which is typically ~5 volts. The signal at the output of tri-state logic gate 10 (shown in the third waveform of Figure 2) ~ ~42~317 .. , swings between ground and typically ~5 volts. When logic gate 10 is not enabled, the output is an open circuit.
The signal from the output of logic gate 10 is applied to the base electrode of transistor 20 and results in an amplified signal appearing at the collector of transistor 20. This amplified signal swings between first and second positive voltage levels, which in the preferred embodiment were selected to be between +3 and ~15 volts, as shown in the fourth waveform of Figure 2.
The signal from the collector of transistor is then applied to the base electrodes of transistors 40 and 50 through the series path of capacitor 25 and resistor 26. Through the action of capacitor 25 and resistor 27, the signal applied to the base electrodes of transistors 40 and 50 is referenced to swing about the ground potential.
Resistor 26 provides the necessary resistance against 20 which clamp diodes 30 and 31 can operate. Resistors 42 and 43 provide a fixed reference voltage for diode 3n and establish the maximum positive voltage available at the emitters of transistors 40 and 50.
Similarly, resistors 52l 53, and 55 provide a fixed reference voltage for diode 31 and establish the maximum negative voltage available at the emitters of transistors 40 and 50. The output signal appearing at the common emitter junction of transistors 40 and 5~
is illustrated in the lower curve of Figure 2~ It can 30 be seen that the signal appearing at the common emitter junction of transistors 40 and 50 is a bi-polar signal corresponding to the uni-polar signal appearing at input 11 of tri-state logic gate 10.
~.~ 7~%g7 A preferred embodiment of the present invention has been described in the foregoing specification. Various modifications of the inventive concept will be obvious to those skilled in the art, without departing from the spirit of the invention.
It is intended that the scope of the invention be limited only by the following claims:
What is claimed is:
Claims (2)
1. A bi-phase modulator-demodulator circuit for converting uni-polar to bi-polar signals, comprising:
a tri-state logic gate having first and second inputs for receiving first and second digital signals and having an output;
a first amplifier stage including a first transistor having a base electrode connected to receive the signal from the output of said tri-state logic gate and having an emitter electrode and a collector electrode;
impedance means for interconnecting said electrodes of said first transistor between sources of first and second potential so as to allow the signal at the collector electrode to swing linearly by a predetermined voltage amount in either direction from a reference potential;
means for providing DC isolation between the output of said tri-state logic and the base electrode of said first transistor a second amplifier stage including second and third complimentary transistors connected to receive an input signal at a common junction joining their respective base electrodes, and to provide an output at a common junction joining their respective emitter electrodes, and further having their collectors respectively connected to sources of positive and negative potential;
means for providing DC isolation between the output of said first amplifier stage and the input of said second amplifier stage;
means for limiting the voltage swing at the output of said second amplifier stage between predetermined positive and negative voltage levels;
and a double balanced mixer having a first input connected to receive the signal from the output of said second amplifier stage and having a second input and an output.
a tri-state logic gate having first and second inputs for receiving first and second digital signals and having an output;
a first amplifier stage including a first transistor having a base electrode connected to receive the signal from the output of said tri-state logic gate and having an emitter electrode and a collector electrode;
impedance means for interconnecting said electrodes of said first transistor between sources of first and second potential so as to allow the signal at the collector electrode to swing linearly by a predetermined voltage amount in either direction from a reference potential;
means for providing DC isolation between the output of said tri-state logic and the base electrode of said first transistor a second amplifier stage including second and third complimentary transistors connected to receive an input signal at a common junction joining their respective base electrodes, and to provide an output at a common junction joining their respective emitter electrodes, and further having their collectors respectively connected to sources of positive and negative potential;
means for providing DC isolation between the output of said first amplifier stage and the input of said second amplifier stage;
means for limiting the voltage swing at the output of said second amplifier stage between predetermined positive and negative voltage levels;
and a double balanced mixer having a first input connected to receive the signal from the output of said second amplifier stage and having a second input and an output.
2. Apparatus according to claim 1, wherein said means for limiting the voltage swing at the output of said second amplifier stage includes:
a first diode connected between the common base junction of said second and third transistors and via a first voltage divider to said source of positive potential; and a second diode connected between the common base junction of said second and third transistors and via a second voltage divider to said source of negative potential;
whereby said first and second diodes further provide desirable temperature compensation.
a first diode connected between the common base junction of said second and third transistors and via a first voltage divider to said source of positive potential; and a second diode connected between the common base junction of said second and third transistors and via a second voltage divider to said source of negative potential;
whereby said first and second diodes further provide desirable temperature compensation.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US200,795 | 1980-10-27 | ||
| US06/200,795 US4361817A (en) | 1980-10-27 | 1980-10-27 | Bi-phase modulator/demodulator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1174297A true CA1174297A (en) | 1984-09-11 |
Family
ID=22743217
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000386402A Expired CA1174297A (en) | 1980-10-27 | 1981-09-22 | Bi-phase modulator/demodulator |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4361817A (en) |
| JP (1) | JPS57101458A (en) |
| CA (1) | CA1174297A (en) |
| GB (1) | GB2087693B (en) |
| IT (1) | IT1142961B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4584533A (en) * | 1985-03-01 | 1986-04-22 | Motorola, Inc. | Non-coherent BPSK demodulator |
| US5214526A (en) * | 1991-06-04 | 1993-05-25 | Apple Computer, Inc. | Pulse modulated infrared data communications link |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3483488A (en) * | 1967-10-12 | 1969-12-09 | Tektronix Inc | Balanced modulator-demodulator circuit with negative feedback in switching element |
| FR2345019A1 (en) * | 1976-03-19 | 1977-10-14 | Cit Alcatel | DATA TRANSMISSION DEVICE AND APPLICATION TO THE TRANSMISSION OF ANALOGUE SIGNALS AND DATA IN A NETWORK WITH DELTA MODULATION |
| US4176328A (en) * | 1978-05-30 | 1979-11-27 | Motorola, Inc. | DC coupled bi-phase modulator |
-
1980
- 1980-10-27 US US06/200,795 patent/US4361817A/en not_active Expired - Lifetime
-
1981
- 1981-09-22 CA CA000386402A patent/CA1174297A/en not_active Expired
- 1981-10-20 GB GB8131603A patent/GB2087693B/en not_active Expired
- 1981-10-23 IT IT49558/81A patent/IT1142961B/en active
- 1981-10-27 JP JP56170881A patent/JPS57101458A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57101458A (en) | 1982-06-24 |
| JPH0131742B2 (en) | 1989-06-27 |
| GB2087693A (en) | 1982-05-26 |
| US4361817A (en) | 1982-11-30 |
| IT8149558A0 (en) | 1981-10-23 |
| IT1142961B (en) | 1986-10-15 |
| GB2087693B (en) | 1984-06-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEC | Expiry (correction) | ||
| MKEX | Expiry |