CA1179754A - Time division multiplex switching network for multi- service digital networks - Google Patents
Time division multiplex switching network for multi- service digital networksInfo
- Publication number
- CA1179754A CA1179754A CA000396648A CA396648A CA1179754A CA 1179754 A CA1179754 A CA 1179754A CA 000396648 A CA000396648 A CA 000396648A CA 396648 A CA396648 A CA 396648A CA 1179754 A CA1179754 A CA 1179754A
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- Prior art keywords
- highway
- packet
- terminating
- time slot
- bits
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/64—Hybrid switching systems
Abstract
Abstract of the Disclosure An asynchronous time division multiplex switching network for multiservice digital network has a plurality of time division multiples bidirectional highways conveying digital data arranged in a hydrid frame including a time slot part and a packet channel part. The time slot part is formed of a plurality of time slots containing sample words having a variable number of bits and the packet channel part is formed of a plurality of channels for packets having a variable number of bits. A plurality of data transmit and receive stations are connected to and associated with said bidirectional highways. A plurality of buses connect-the transmit and receive stations therebetween and selectively interconnect an originating bidirectional highway to a terminating bidirectional highway through an originating and a terminating transmit and receive stations. An arrangement in each transmit station converts the sample words in the time slot part of the hybrid frame and the packets in the packet channel part of the hybrid frame of an originating highway into a message including, for the sample word in each time slot, the sample word, its number of bits, the address of the terminating highway, the number of the time slot in the hybrid frame of said terminating highway, and a first sort-of-data indicator marking sample words, and, for the packet in each packet channel, the packet, its number of bits, the address of the terminating highway, the number of the packet channel in the hybrid frame of the terminating highway and a second sort-of-data indicator marking the packets.
An arrangement transmits the messages from the originating highway to the terminating highway. An arrangement in each receive station for deletes from the messages the number of bits of the sample words and packets, the address of the terminating highway, the number of the time slots and packet channels and the first and second data indicators. An arrangement memorizes the time slot and packet channel numbers and the first and second data indicator. The sample words and packets depending on the time slot and packet numbers and data indicators are inserted in the hybrid frame of the terminating highway.
An arrangement transmits the messages from the originating highway to the terminating highway. An arrangement in each receive station for deletes from the messages the number of bits of the sample words and packets, the address of the terminating highway, the number of the time slots and packet channels and the first and second data indicators. An arrangement memorizes the time slot and packet channel numbers and the first and second data indicator. The sample words and packets depending on the time slot and packet numbers and data indicators are inserted in the hybrid frame of the terminating highway.
Description
1:~797S4 The present invention rela~es to a digital switching network for switching digital channels that serve in establishing communica-tions for multiservices such as telephony, data transmission, vi-deotelephony, etc.
Switching systems have already been put forward for multiservice digital networks suited to hybrid switching or, in other words, for switching time division multiplex circuits by synchronous digital time division switching networksand for packet switching using asynchronous packet switching networks.These switching systems do not allow :
I - circuits with any given bit-rates to be switched since a synchronous time division multiplex switching network has just a single bit-rate, e.g. 64 kbit/s for a PCM time division multiplex switching system having frames of 125 ~s containing octets of 8 bits.
Switching systems have already been put forward for multiservice digital networks suited to hybrid switching or, in other words, for switching time division multiplex circuits by synchronous digital time division switching networksand for packet switching using asynchronous packet switching networks.These switching systems do not allow :
I - circuits with any given bit-rates to be switched since a synchronous time division multiplex switching network has just a single bit-rate, e.g. 64 kbit/s for a PCM time division multiplex switching system having frames of 125 ~s containing octets of 8 bits.
2 - A variable proportion of circuits and packets to be switched unless of course each switching network (circuit or packet) is dimensioned for the overall maximum bit-rate processed by the switching system.
These switching systems therefore imply, in practice, a rigid association between service classes and switching techniques (in this case voice switching corresponds to circuit switching and switching of data corresponds to packet switching)which limits the possibilities of future development bound to new economic optima (e.g. packetized voice switching) or the introduction o~ new services (e.g. low bit-rate data circuit-mode switchingj.
;L 17~'7S~
An asynchronous time division switching system makes is possible, however, to switch a variable proportion of time division circuits and miscellaneous bit-rate packets by generalizing their processing in one and the same type of equipment.
Time division hybrid multiplex data arrangements are already known that are intended for either circuit-mode or packet-mode switching (see Design Approaches ard Perfor-mance Criteria for Integrated Voice/Data Switching by MyronJ. Ross, Arthur C. Tabbot and John A. Waite, Proceedings of the IEEE, Vol. 65, No. 9 of September 1977). The time-inter-val distribution of a hybrid frame containin~ sample words and packets is depicted in Fig. lA. F represents the frame, FL the frame limit indicator and L the limit between the synchronous time slot part of the frame containing time slots TSi and the channel Aintended for the packets.
In that part of the frame given over to the time slots (from FL to L), each time slot is allocated to a com-munication and only one. The bit-rate in a slot is thus guaranteed and characterized by the slot length. The various time slots TSl, TSi, TSI constitute a synchronous time-division multiplex.
That part of the frame received for the packets (from L to FL) is divided between several packet-mode com-munications channels. The packet making up one and the same communication are indicated by a packet number that they carry together with the data. This is the case of an asyn-chronous time division multiplex.
Described in British Patent Applicatlon No. 2,064,839 published June 17, 1981 to Quinquis, et al, is a multiprocessor system comprising a plurality B of buses, a plurality of at the most B(B-1)/2 microprocessors each connected to a bus pair where each of the pairs ~ r .~
i ~
connecting the multiprocessors are different and each bus is connected to at the most (B-l) microprocessors. It results from this that an originating microprocessor is connected directly via its two connection buses to 2(B-2) terminating microprocessors and in-directly to (B-2) (B-3)/2 terminating microprocessors via at the most one transit or relay microprocessor directly connected to both the originating microprocessor and the terminating microprocessor.
Consequently, considering one originating microprocessor amongst the B(B-1)/2 microprocessors, there are :
B(B-1)/2 - 1 = (B-2) (B+1)/2 terminating microprocessors possible. Out of these (B-2) (B+1)/2 terminating microprocessors, 2(B-2) are wired directly to the originating microprocessor and (B-2) (B-3)/2 are wired to it indirectly via a single relay micro-processor. It is confirmed that 2(B-2) + (B 2)2(B-3) = (B-2) (B+l) The system that has just been summarized for recap purposes affords numerous advantages, notably :
By taking as address of a given microprocessor the concatenation of the two addresses of the buses that are connected to it, i.e. by taking (ab) or (ba) as the address of the microprocessor connected to buses a and b, the microprocessor that recognizes its address transmitted by a bus connected thereto knows that it is the termina-ting microprocessor and, further, if it recognizes only a or only b in (ab) or (ba), then it knows itself to be a relay microprocessor 1.~7~3~5~
and automatically interconnects its two buses one to the other. This property will be brought into play hereinafter by expressing the addresses of the switching stations to which the multiplex highways are connected in the (x,y) form.
Means now exist for connecting thirty or so micropro-cessors to a series bus having a 10 Mbit/s bit-rate. Conse-quently, B-1=30 and B=31. The network has 31 buses to which can be connected a maximum of B(B-1)/2=435 microprocessors.
The maximum theoretical traffic is thus virtually 300 Mbit/s which permits a practical bit-rate of 200 Mbit/s.
According to the present invention there is provided asynchronous time division multiplex switching network for multiservice digital network, comprising: a plurality of time division multiplex bidirectional highways conveying digital data arranged in a hybrid frame including a time slot part and a packet channel part, said time slot part being formed of a plurality of time slots containing sample words having a variable number of bits and said packet channel part being formed of a pluraliiy of channels for packets having a variable number of bits; a plurality of data transmit and receive stations, connected to and associated with said bidirectional highways; a plurality of buses connecting said transmit and receive stations therebetween and selectively interconnecting an originating bidirectional highway to a terminating bidirectional highway through an originating and a terminating transmit and receive stations; means in each transmit station for converting the sample words in the time slot part of the hybrid frame and the packetsin the packet channel part of said hybrid frame of an originating highway into a message including, for the sample word in each time slot, the said sample word, its number of bits, the address of the terminating highway, the number of the time slot in the hybrid frame of said terrninating highway and a first sort-of-data indica-tor marking sample words and, for the packet in each packet channel, the said packet, 97~
its number of bits, the address of the terminating highway, the number of the packet channel in the hybrid frame of said terminating highway and a second sort-of-data indicator marking the packets; means for transmitting said messages from said originating highway to said terminating highway;
means in each receive station for deleting from said messages the numbers of bits of the sample words and packets, the address of the terminating highway, the number of the time slots and packet channels and the first and second data indicators; means for mernorizing said time slot and packet channel numbers and said first and second data indicator;
and means for inserting in the hybrid frame of the terminating highway the sample words and packets depending on said time slot and packet numbers and data indicators.
The invention will now be described in detail with reference being made to the accompanying drawings in which:-Fig. lA schematizes the breakdown of a hybrid frame and has been disclosed in the introductory part;
Figs. lB and lC represent the two directions of a bidirectional hybrid frame multiplex highway;
Fig. 2 depicts the rnultiprocessor system employed as an asynchronous time-division switching system in this invention;
Fig. 3 schematizes a switching station of the asynchronous time-division switching system as in Fig. 2;
Fig. 4 depicts, in block diagram form, the terminal switching equipment of a switching station as in Fig. 3;
Fig. 5 depicts, in block diagram form, the incoming sample word processing circuit included in the terminal switching equipment as in Fig. 4;
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Fig. 6 depicts, in block diagram form, the outgoing sample word processing circuit included in the terminal switching equipment as in Fig. 4; and Fig. 7 depicts, in block diagram form, the incoming and outgoing packet processing circuits included in the terminal switching equipment as in Fig. 4.
- 5a --~17~754 In reference to Figs. IB and lC, the hybrid frame F comprises time slots TSi m' TS (depending on whether the time slots are coming in or going out) where 1 ~ m ~ M and I ~ n ~ N. The time slots do not all have the same bit capacity. The bit capacity of time slot TSi or TSo n will be represented by ~ or ~n respec-tively. The hybrid frame also comprises time division channels marked as ~i or ~ and given over to packets. The total number of bits per frame is known and it is possible, from the clock signal Hi or Ho and the frame-limit signal FLi or FLo, to deduce pulses Fi TS' Fi ~ Fo TS' F ~ dividing respectively the incoming frame and the outgoing frame into a time slot part Fi TS and Fo TS and a packet part Fi ~ and Fo ~. The sample words Wm or Wn occupying the time slots TSl m and TSo n are transmitted during the time slot frame part FiTsand Fo TS and the packets Pm or Pn are transmitted during the packet frame parts Fi ~and Fo ~.
Fig. 2 depicts a transfer network 500 between the switching stations. There are B = 6 buses numbered ] to 6 and B(B-1)/2 = 15 stations each joined to two buses and having as addresses the conca-tenation of the addresses of those buses to which they are joined.
Connected to each station is a bidirectional time-division multiplex highway given as MUXi for the incoming direction and MUXo for the outgoing direction. These multiplex highways have the same addresses as the stations to which they are connected.
Fig. 3, in block diagram form, represents a switching station.
It is composed of a terminal switching equipment item controlled by a microprocessor I and a bus access controller coupled by two 1 17~7S4 buses 50 and 60 forming a par-t of network 500. The terminal switching equipment and the bus access controller communi-cate via two stack or ~ueueing circuits 9 and 29.
The bus access controller consists of a coupler for access to the two buses 50 and 60 controlled by a micro-processor 1'.
The receiver terminal switching half-equipment lC chiefly comprises a demultiplexer 3 and a circuit for con-verting sample words and packets into messages 10/20.
The transmit terminal switching half-equipment comprises stack or queueing circuits 2021...202 ...202M for the various hybrid frame time slots, a queueing circuit for the packets 301 where all these queueing circuits are connected to a multiplexer 13 itself connected to the outgoing multi-plex highway MUX .
Referring to Fig. 4, the reference number 2 desig-nates an incoming multiplex terminal equipment item. It is connected to the incoming multiplex highway MUXi and sep-aretes the ineoming data Di (sample words W and packets P) from the synchronization signals (clock signals Hi and frame-synchro signals FLi). Terminal multiplex equipment 2 is wired to a demultiplexer 3 via a line 4 and a counter 5.
This counter 5 delivers pulses Li whieh mark the boundary between that part Fi TS of the frame containing time slots TSi m and that part Fi ~ of the frame containing the packet channels ~i~ Demultiplexer 3 issues incoming sample words W along line 6 and incoming packets P along line 7. The time slots sample words are processed in processing circuit 10 (Fig. 5) and the paekets are processed in processing ~ ~'797S~
circuit 30 (Fig. 7). During the processing, the sample words W
and the packets P are converted into messages as explained by adding o the sample word W of time slot TS. and to the data in packet m l,m Pm of packet channel Ai m an indicator "w" or "p" which makes it known whether a sample word or a packet is concerned, the length of the sample word or packet and the addresses(x, y)q and n respectively designating the outgoing multiplex highway and the number of the time slot or packet channel in the hybrid frame of the out-going multiplex highway.
The meassage is fed into a local bus 8 and from there to the queueing circuit 9. The last stage of the queueing circuit supplies the bus access controller wi~h messages and the bus access controller sends the message to the terminating station of addresses (x, y)q via transfer bus network 500.
The message free of the address (x, y)q which served to guide it to the terminating station is switched either towards outgoing sample word processing circuit 20 (Fig. 6) or towards outgoing packet processing circuit 40 (Fig. 7). This switching operation is achieved by reading the "w" or "p" indicator present in the message.
Depending on the 1 or 0 value of this indicator, it opens one of AND gates 18 or 19, which guides the remainder of the message towards outgoing sample worcl processing circuit 20 or outgoing packet pro-cessing circuit 40.
In the processing circuits, the messages are stripped of their ~ltents other than the sample word W orthe packet P . The sample words and packets are applied via lines 16 and 17 to multiplexer 13. Mul-tiplexer 13 is connected by line 14 to terminal multiplex equipment 12.
i~79754 The latter receives, from time base 15, the cloc'~ pulses Ho and the frame-synchro pulses FL and the multiplexer receives the pulses L
from time base 15 that separate the time slot zone from the packet ~one.
Incoming sample word processing circuit 10 is illustrated in Fig. 5.
Line 6 which transmits the time slot sample words is connected to two shift registers 101 and 102 having capacities equal to the maximum number of bits that a word in the various time slots can carry. Shift registers 101 and 102 function as series-to-parallel converters and operate in opposition, i.e. one is being loaded in series whilst the other is being unloaded in parallel. As the bit capacity of the time slots A is not the same in different time slots, the going over from one series-to-parallel converter to the other comes about at the instigation of a bit number decrementer 103 and a register selector 104.
Decrementer 103, when it reaches 2ero controls register selector 104. The latter permits or inhibits the admission of clock pulses Hi into the registers through AND gates 105 and 106. Register selector 104 further controls a bus sequencer 107 that connects the parallel outputs of shift registers 101 and 102 to local bus 8 alternately through AND gates 108 and 109.
Bus sequencer 107 further controls two AND gates 110 and 111 which monitor the admission, into local bus 8, of ac1ditional informa-tion for converting the sample word into a message.
This additional information is stored in table 112 and comprises :
li79754 - the capacities or length ~ of the hybrid frame incoming time slot and packet channels ;
- the address (x, y) of the outgoing multiplex highway, obtained by microprocessor I during the communication-establishing phase ;
- the number n of the outgoing time slot, obtained by the microprocessor I during the communication-establishing phase. The station (x, y)q must seek a time slot TSo n that is both free and has the same capacity ~ as ~ in the multiplex highway (x, y)q.
Each time decrementer 103 goes through zero, conters 113 and 114 are incremented by unity.
Counter 113 controls the entry of the quality ~ +l into de-crementer 103.
Counter 114 controls the transfer of the information ~m' (x, y) related to the previous time slot along local bus 8 towards queueing circuit 9 across AND gates 110 and 111. Counter 113 is reset to zero by the frame-end pulse FLi and counter 114 is reset to zero when counter 113 marks up 1. At the same time as ~ n and (x,y) the indicator "m" is included in the message.
Referr;ng now to Fig. 6, the message receivedby the bus access con-troller is applied by the latter in parallel to queueing circuit 29.
The data "w" or "p" and n in this message, i.e. the indica-tor characterizing a sample word or a packet and the number oE the terminating time slot, are detected by AND gate 18 and input address decoder 200. Should the character "w" or "p" be a 1, then the decoder opens one of AND gates 2011, ... 201n, ... 201N which give access to queueing lines 2021, ... 202 , ... 202N respectively. These queueing circuits have parallel inputs and series outputs. The sample word W is introduced into the queueing circuit corresponding to the address n, at the instigation of sequencer 207 to which ~ has been transmitted.
Queueing circuits 2021, ... 202 , ... 202N transmit their content in series to multiplexer 13. They are activated by a signal coming from gates 2041, ... 204 , ... 204N which itself comes from the clock Ho during the pulse Fo TS and conveyed by wire 205. Gates 204 are selected by means of address decoder 206. This address decoder is controlled by bit-number decrementer 203 which each time zero is reached increments counter 213.
A table 212 contains :
- the capacities or ]engths ~ of the hybrid frame outgoing time slots. These are permanent data that describe the structure of the outgoing multiplex highway ;
- the status bits C; which enable microprocessor 1, during he communication-establishing phase, to find a time interval TS
o,n ith a capacity ~ equal to ~ . The bit C is set to 1 when TS
n m n o,n is seized and then reset to 0 upon its being freed, at the end of the communication.
Counter 213 causes table 212 to advance at the generally irreguIclr rhythm of the time sLots.
Fig. 7, in block diagram form, depicts the incoming ancl outgo;ng packet processing circuits.
The incoming packets arrive, via line 7 in HDLC circuit 302 at the clock rhythm Hi during the puLse Fi ~. The reccive HDLC circu;t 302 performs as usual the packet determination in the continuousbinary data flow and the series-to-paralLel transconversion. Tlle packets so formed by the receive HDLC circuit are sent at the arrival ryhthm along incoming-packet FIF'0 stack 311.
Once a complete packet has been received, microprocessor 1 is informed accordingly by the HDLC circuit and it stores the packet P and its length ~ , the terminating multiplex highway address (x, y)q and the output packet channel number n in memory 312.
When the message formed by the information items P , (x, y)q, , n and the indicator p is ready, microprocessor 1 advise transfer circuit 305 which, through gate 304, authorizes the transfer of the message to queueing circuit 9 during Fi Q period during which time local bus 8 is free.
The message received by the bus access controller is applied to overall queueing circuit 29. It is applied through gate 19, the state of which depends on the indicator p, to packet queueing circuit 301.
The microprocessor reads in this queueing circuit the packet length ~ , then the packet Pm and the output packet channel number n and next forms the corresponding outgoing packet that it places in outgoing packet FIFO 411.
At the Ho rate during Fo Q, these signals emanating from time base 15, transmit HDLC circuit 402 picks the packet out of FIFO 411 and transmits it according to the HDLC procedure along line 17 towards multiplexer 13.
These switching systems therefore imply, in practice, a rigid association between service classes and switching techniques (in this case voice switching corresponds to circuit switching and switching of data corresponds to packet switching)which limits the possibilities of future development bound to new economic optima (e.g. packetized voice switching) or the introduction o~ new services (e.g. low bit-rate data circuit-mode switchingj.
;L 17~'7S~
An asynchronous time division switching system makes is possible, however, to switch a variable proportion of time division circuits and miscellaneous bit-rate packets by generalizing their processing in one and the same type of equipment.
Time division hybrid multiplex data arrangements are already known that are intended for either circuit-mode or packet-mode switching (see Design Approaches ard Perfor-mance Criteria for Integrated Voice/Data Switching by MyronJ. Ross, Arthur C. Tabbot and John A. Waite, Proceedings of the IEEE, Vol. 65, No. 9 of September 1977). The time-inter-val distribution of a hybrid frame containin~ sample words and packets is depicted in Fig. lA. F represents the frame, FL the frame limit indicator and L the limit between the synchronous time slot part of the frame containing time slots TSi and the channel Aintended for the packets.
In that part of the frame given over to the time slots (from FL to L), each time slot is allocated to a com-munication and only one. The bit-rate in a slot is thus guaranteed and characterized by the slot length. The various time slots TSl, TSi, TSI constitute a synchronous time-division multiplex.
That part of the frame received for the packets (from L to FL) is divided between several packet-mode com-munications channels. The packet making up one and the same communication are indicated by a packet number that they carry together with the data. This is the case of an asyn-chronous time division multiplex.
Described in British Patent Applicatlon No. 2,064,839 published June 17, 1981 to Quinquis, et al, is a multiprocessor system comprising a plurality B of buses, a plurality of at the most B(B-1)/2 microprocessors each connected to a bus pair where each of the pairs ~ r .~
i ~
connecting the multiprocessors are different and each bus is connected to at the most (B-l) microprocessors. It results from this that an originating microprocessor is connected directly via its two connection buses to 2(B-2) terminating microprocessors and in-directly to (B-2) (B-3)/2 terminating microprocessors via at the most one transit or relay microprocessor directly connected to both the originating microprocessor and the terminating microprocessor.
Consequently, considering one originating microprocessor amongst the B(B-1)/2 microprocessors, there are :
B(B-1)/2 - 1 = (B-2) (B+1)/2 terminating microprocessors possible. Out of these (B-2) (B+1)/2 terminating microprocessors, 2(B-2) are wired directly to the originating microprocessor and (B-2) (B-3)/2 are wired to it indirectly via a single relay micro-processor. It is confirmed that 2(B-2) + (B 2)2(B-3) = (B-2) (B+l) The system that has just been summarized for recap purposes affords numerous advantages, notably :
By taking as address of a given microprocessor the concatenation of the two addresses of the buses that are connected to it, i.e. by taking (ab) or (ba) as the address of the microprocessor connected to buses a and b, the microprocessor that recognizes its address transmitted by a bus connected thereto knows that it is the termina-ting microprocessor and, further, if it recognizes only a or only b in (ab) or (ba), then it knows itself to be a relay microprocessor 1.~7~3~5~
and automatically interconnects its two buses one to the other. This property will be brought into play hereinafter by expressing the addresses of the switching stations to which the multiplex highways are connected in the (x,y) form.
Means now exist for connecting thirty or so micropro-cessors to a series bus having a 10 Mbit/s bit-rate. Conse-quently, B-1=30 and B=31. The network has 31 buses to which can be connected a maximum of B(B-1)/2=435 microprocessors.
The maximum theoretical traffic is thus virtually 300 Mbit/s which permits a practical bit-rate of 200 Mbit/s.
According to the present invention there is provided asynchronous time division multiplex switching network for multiservice digital network, comprising: a plurality of time division multiplex bidirectional highways conveying digital data arranged in a hybrid frame including a time slot part and a packet channel part, said time slot part being formed of a plurality of time slots containing sample words having a variable number of bits and said packet channel part being formed of a pluraliiy of channels for packets having a variable number of bits; a plurality of data transmit and receive stations, connected to and associated with said bidirectional highways; a plurality of buses connecting said transmit and receive stations therebetween and selectively interconnecting an originating bidirectional highway to a terminating bidirectional highway through an originating and a terminating transmit and receive stations; means in each transmit station for converting the sample words in the time slot part of the hybrid frame and the packetsin the packet channel part of said hybrid frame of an originating highway into a message including, for the sample word in each time slot, the said sample word, its number of bits, the address of the terminating highway, the number of the time slot in the hybrid frame of said terrninating highway and a first sort-of-data indica-tor marking sample words and, for the packet in each packet channel, the said packet, 97~
its number of bits, the address of the terminating highway, the number of the packet channel in the hybrid frame of said terminating highway and a second sort-of-data indicator marking the packets; means for transmitting said messages from said originating highway to said terminating highway;
means in each receive station for deleting from said messages the numbers of bits of the sample words and packets, the address of the terminating highway, the number of the time slots and packet channels and the first and second data indicators; means for mernorizing said time slot and packet channel numbers and said first and second data indicator;
and means for inserting in the hybrid frame of the terminating highway the sample words and packets depending on said time slot and packet numbers and data indicators.
The invention will now be described in detail with reference being made to the accompanying drawings in which:-Fig. lA schematizes the breakdown of a hybrid frame and has been disclosed in the introductory part;
Figs. lB and lC represent the two directions of a bidirectional hybrid frame multiplex highway;
Fig. 2 depicts the rnultiprocessor system employed as an asynchronous time-division switching system in this invention;
Fig. 3 schematizes a switching station of the asynchronous time-division switching system as in Fig. 2;
Fig. 4 depicts, in block diagram form, the terminal switching equipment of a switching station as in Fig. 3;
Fig. 5 depicts, in block diagram form, the incoming sample word processing circuit included in the terminal switching equipment as in Fig. 4;
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Fig. 6 depicts, in block diagram form, the outgoing sample word processing circuit included in the terminal switching equipment as in Fig. 4; and Fig. 7 depicts, in block diagram form, the incoming and outgoing packet processing circuits included in the terminal switching equipment as in Fig. 4.
- 5a --~17~754 In reference to Figs. IB and lC, the hybrid frame F comprises time slots TSi m' TS (depending on whether the time slots are coming in or going out) where 1 ~ m ~ M and I ~ n ~ N. The time slots do not all have the same bit capacity. The bit capacity of time slot TSi or TSo n will be represented by ~ or ~n respec-tively. The hybrid frame also comprises time division channels marked as ~i or ~ and given over to packets. The total number of bits per frame is known and it is possible, from the clock signal Hi or Ho and the frame-limit signal FLi or FLo, to deduce pulses Fi TS' Fi ~ Fo TS' F ~ dividing respectively the incoming frame and the outgoing frame into a time slot part Fi TS and Fo TS and a packet part Fi ~ and Fo ~. The sample words Wm or Wn occupying the time slots TSl m and TSo n are transmitted during the time slot frame part FiTsand Fo TS and the packets Pm or Pn are transmitted during the packet frame parts Fi ~and Fo ~.
Fig. 2 depicts a transfer network 500 between the switching stations. There are B = 6 buses numbered ] to 6 and B(B-1)/2 = 15 stations each joined to two buses and having as addresses the conca-tenation of the addresses of those buses to which they are joined.
Connected to each station is a bidirectional time-division multiplex highway given as MUXi for the incoming direction and MUXo for the outgoing direction. These multiplex highways have the same addresses as the stations to which they are connected.
Fig. 3, in block diagram form, represents a switching station.
It is composed of a terminal switching equipment item controlled by a microprocessor I and a bus access controller coupled by two 1 17~7S4 buses 50 and 60 forming a par-t of network 500. The terminal switching equipment and the bus access controller communi-cate via two stack or ~ueueing circuits 9 and 29.
The bus access controller consists of a coupler for access to the two buses 50 and 60 controlled by a micro-processor 1'.
The receiver terminal switching half-equipment lC chiefly comprises a demultiplexer 3 and a circuit for con-verting sample words and packets into messages 10/20.
The transmit terminal switching half-equipment comprises stack or queueing circuits 2021...202 ...202M for the various hybrid frame time slots, a queueing circuit for the packets 301 where all these queueing circuits are connected to a multiplexer 13 itself connected to the outgoing multi-plex highway MUX .
Referring to Fig. 4, the reference number 2 desig-nates an incoming multiplex terminal equipment item. It is connected to the incoming multiplex highway MUXi and sep-aretes the ineoming data Di (sample words W and packets P) from the synchronization signals (clock signals Hi and frame-synchro signals FLi). Terminal multiplex equipment 2 is wired to a demultiplexer 3 via a line 4 and a counter 5.
This counter 5 delivers pulses Li whieh mark the boundary between that part Fi TS of the frame containing time slots TSi m and that part Fi ~ of the frame containing the packet channels ~i~ Demultiplexer 3 issues incoming sample words W along line 6 and incoming packets P along line 7. The time slots sample words are processed in processing circuit 10 (Fig. 5) and the paekets are processed in processing ~ ~'797S~
circuit 30 (Fig. 7). During the processing, the sample words W
and the packets P are converted into messages as explained by adding o the sample word W of time slot TS. and to the data in packet m l,m Pm of packet channel Ai m an indicator "w" or "p" which makes it known whether a sample word or a packet is concerned, the length of the sample word or packet and the addresses(x, y)q and n respectively designating the outgoing multiplex highway and the number of the time slot or packet channel in the hybrid frame of the out-going multiplex highway.
The meassage is fed into a local bus 8 and from there to the queueing circuit 9. The last stage of the queueing circuit supplies the bus access controller wi~h messages and the bus access controller sends the message to the terminating station of addresses (x, y)q via transfer bus network 500.
The message free of the address (x, y)q which served to guide it to the terminating station is switched either towards outgoing sample word processing circuit 20 (Fig. 6) or towards outgoing packet processing circuit 40 (Fig. 7). This switching operation is achieved by reading the "w" or "p" indicator present in the message.
Depending on the 1 or 0 value of this indicator, it opens one of AND gates 18 or 19, which guides the remainder of the message towards outgoing sample worcl processing circuit 20 or outgoing packet pro-cessing circuit 40.
In the processing circuits, the messages are stripped of their ~ltents other than the sample word W orthe packet P . The sample words and packets are applied via lines 16 and 17 to multiplexer 13. Mul-tiplexer 13 is connected by line 14 to terminal multiplex equipment 12.
i~79754 The latter receives, from time base 15, the cloc'~ pulses Ho and the frame-synchro pulses FL and the multiplexer receives the pulses L
from time base 15 that separate the time slot zone from the packet ~one.
Incoming sample word processing circuit 10 is illustrated in Fig. 5.
Line 6 which transmits the time slot sample words is connected to two shift registers 101 and 102 having capacities equal to the maximum number of bits that a word in the various time slots can carry. Shift registers 101 and 102 function as series-to-parallel converters and operate in opposition, i.e. one is being loaded in series whilst the other is being unloaded in parallel. As the bit capacity of the time slots A is not the same in different time slots, the going over from one series-to-parallel converter to the other comes about at the instigation of a bit number decrementer 103 and a register selector 104.
Decrementer 103, when it reaches 2ero controls register selector 104. The latter permits or inhibits the admission of clock pulses Hi into the registers through AND gates 105 and 106. Register selector 104 further controls a bus sequencer 107 that connects the parallel outputs of shift registers 101 and 102 to local bus 8 alternately through AND gates 108 and 109.
Bus sequencer 107 further controls two AND gates 110 and 111 which monitor the admission, into local bus 8, of ac1ditional informa-tion for converting the sample word into a message.
This additional information is stored in table 112 and comprises :
li79754 - the capacities or length ~ of the hybrid frame incoming time slot and packet channels ;
- the address (x, y) of the outgoing multiplex highway, obtained by microprocessor I during the communication-establishing phase ;
- the number n of the outgoing time slot, obtained by the microprocessor I during the communication-establishing phase. The station (x, y)q must seek a time slot TSo n that is both free and has the same capacity ~ as ~ in the multiplex highway (x, y)q.
Each time decrementer 103 goes through zero, conters 113 and 114 are incremented by unity.
Counter 113 controls the entry of the quality ~ +l into de-crementer 103.
Counter 114 controls the transfer of the information ~m' (x, y) related to the previous time slot along local bus 8 towards queueing circuit 9 across AND gates 110 and 111. Counter 113 is reset to zero by the frame-end pulse FLi and counter 114 is reset to zero when counter 113 marks up 1. At the same time as ~ n and (x,y) the indicator "m" is included in the message.
Referr;ng now to Fig. 6, the message receivedby the bus access con-troller is applied by the latter in parallel to queueing circuit 29.
The data "w" or "p" and n in this message, i.e. the indica-tor characterizing a sample word or a packet and the number oE the terminating time slot, are detected by AND gate 18 and input address decoder 200. Should the character "w" or "p" be a 1, then the decoder opens one of AND gates 2011, ... 201n, ... 201N which give access to queueing lines 2021, ... 202 , ... 202N respectively. These queueing circuits have parallel inputs and series outputs. The sample word W is introduced into the queueing circuit corresponding to the address n, at the instigation of sequencer 207 to which ~ has been transmitted.
Queueing circuits 2021, ... 202 , ... 202N transmit their content in series to multiplexer 13. They are activated by a signal coming from gates 2041, ... 204 , ... 204N which itself comes from the clock Ho during the pulse Fo TS and conveyed by wire 205. Gates 204 are selected by means of address decoder 206. This address decoder is controlled by bit-number decrementer 203 which each time zero is reached increments counter 213.
A table 212 contains :
- the capacities or ]engths ~ of the hybrid frame outgoing time slots. These are permanent data that describe the structure of the outgoing multiplex highway ;
- the status bits C; which enable microprocessor 1, during he communication-establishing phase, to find a time interval TS
o,n ith a capacity ~ equal to ~ . The bit C is set to 1 when TS
n m n o,n is seized and then reset to 0 upon its being freed, at the end of the communication.
Counter 213 causes table 212 to advance at the generally irreguIclr rhythm of the time sLots.
Fig. 7, in block diagram form, depicts the incoming ancl outgo;ng packet processing circuits.
The incoming packets arrive, via line 7 in HDLC circuit 302 at the clock rhythm Hi during the puLse Fi ~. The reccive HDLC circu;t 302 performs as usual the packet determination in the continuousbinary data flow and the series-to-paralLel transconversion. Tlle packets so formed by the receive HDLC circuit are sent at the arrival ryhthm along incoming-packet FIF'0 stack 311.
Once a complete packet has been received, microprocessor 1 is informed accordingly by the HDLC circuit and it stores the packet P and its length ~ , the terminating multiplex highway address (x, y)q and the output packet channel number n in memory 312.
When the message formed by the information items P , (x, y)q, , n and the indicator p is ready, microprocessor 1 advise transfer circuit 305 which, through gate 304, authorizes the transfer of the message to queueing circuit 9 during Fi Q period during which time local bus 8 is free.
The message received by the bus access controller is applied to overall queueing circuit 29. It is applied through gate 19, the state of which depends on the indicator p, to packet queueing circuit 301.
The microprocessor reads in this queueing circuit the packet length ~ , then the packet Pm and the output packet channel number n and next forms the corresponding outgoing packet that it places in outgoing packet FIFO 411.
At the Ho rate during Fo Q, these signals emanating from time base 15, transmit HDLC circuit 402 picks the packet out of FIFO 411 and transmits it according to the HDLC procedure along line 17 towards multiplexer 13.
Claims (2)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1 - Asynchronous time division multiplex switching network for multiservice digital network, comprising :
a plurality of time division multiplex bidirectional highways conveying digital data arranged in a hybrid frame including a time slot part and a packet channel part, said time slot part being formed of a plurality of time slots containing sample words having a variable number of bits and said packet channel part being formed of a plu-rality of channels for packets having a variable number of bits ;
a plurality of data transmit and receive stations, connected to and associated with said bidirectional highways ;
a plurality of buses connecting said transmit and receive stations therebetween and selectively interconnecting an originating bidirectional highway to a terminating bidirectional highway through an originating and a terminating transmit and receive stations ;
means in each transmit station for converting the sample words in the time slot part of the hybrid frame and the packets in the packet channel part of said hybrid frame of an originating highway into a message including, for the sample word in each time slot, the said sample word, its number of bits, the address of the terminating highway, the number of the time slot in the hybrid frame of said ter-minating highway and a first sort-of-data indicator marking sample words and, for the packet in each packet channel, the said packet, its num-ber of bits, the address of the terminating highway the number of the packet channel in the hybrid frame of said terminating highway and a second sort-of-data indicator marking the packets ;
means for transmitting said messages from said originating highway to said terminating highway ;
means in each receive station for deleting from said messages the numbers of bits of the sample words and packets, the address of the terminating highway, the number of the time slots and packet channels and the first and second data indicators ;
means for memorizing said time slot and packet channel numbers and said first and second data indicator ; and means for inserting in the hybrid frame of the terminating highway the sample words and packets depending on said time slot and packet numbers and data indicators.
a plurality of time division multiplex bidirectional highways conveying digital data arranged in a hybrid frame including a time slot part and a packet channel part, said time slot part being formed of a plurality of time slots containing sample words having a variable number of bits and said packet channel part being formed of a plu-rality of channels for packets having a variable number of bits ;
a plurality of data transmit and receive stations, connected to and associated with said bidirectional highways ;
a plurality of buses connecting said transmit and receive stations therebetween and selectively interconnecting an originating bidirectional highway to a terminating bidirectional highway through an originating and a terminating transmit and receive stations ;
means in each transmit station for converting the sample words in the time slot part of the hybrid frame and the packets in the packet channel part of said hybrid frame of an originating highway into a message including, for the sample word in each time slot, the said sample word, its number of bits, the address of the terminating highway, the number of the time slot in the hybrid frame of said ter-minating highway and a first sort-of-data indicator marking sample words and, for the packet in each packet channel, the said packet, its num-ber of bits, the address of the terminating highway the number of the packet channel in the hybrid frame of said terminating highway and a second sort-of-data indicator marking the packets ;
means for transmitting said messages from said originating highway to said terminating highway ;
means in each receive station for deleting from said messages the numbers of bits of the sample words and packets, the address of the terminating highway, the number of the time slots and packet channels and the first and second data indicators ;
means for memorizing said time slot and packet channel numbers and said first and second data indicator ; and means for inserting in the hybrid frame of the terminating highway the sample words and packets depending on said time slot and packet numbers and data indicators.
2 - Asynchronous time division multiplex switching network as set forth in claim 1, in which the means for converting the sample words in the time slots of the hybrid frame and the packets in the packet channel of the hybrid frame of any originating highway into messages comprises storing means for storing a group of information items composed of the numbers of the time slot containing a sample word to be switched or the number of bits of a packet channel containing a packet to be switched, the address of the terminating highway and the address of the time slote or packet channel in the hybrid frame of said terminating highway, a decrementer of said number of bits, a parallel-to-series converter for serially entering into said converter the bits of the sample word or packet to be switched, means for controlling the parallel output of said converter by said decrementer reaching zero and means for adding to said sample word or packet, said group of information items.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR8103440A FR2500704A1 (en) | 1981-02-20 | 1981-02-20 | ASYNCHRONOUS TIME SWITCH FOR DIGITAL NETWORK WITH INTEGRATION OF SERVICES |
| FR81.03440 | 1981-02-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1179754A true CA1179754A (en) | 1984-12-18 |
Family
ID=9255466
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000396648A Expired CA1179754A (en) | 1981-02-20 | 1982-02-19 | Time division multiplex switching network for multi- service digital networks |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4446555A (en) |
| EP (1) | EP0059149B1 (en) |
| JP (1) | JPS581394A (en) |
| CA (1) | CA1179754A (en) |
| DE (1) | DE3260344D1 (en) |
| FR (1) | FR2500704A1 (en) |
Families Citing this family (72)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4408323A (en) * | 1981-06-29 | 1983-10-04 | Bell Telephone Laboratories, Incorporated | Processor facilities for integrated packet and voice switching |
| US4539676A (en) * | 1982-05-03 | 1985-09-03 | At&T Bell Laboratories | Bulk/interactive data switching system |
| FR2526615A1 (en) * | 1982-05-10 | 1983-11-10 | Bodros Christian | HIGH-THROUGHPUT COUPLER BETWEEN A MULTIPLEX OF MIC CHANNELS AND A PACKET SWITCH |
| FR2538984A1 (en) * | 1982-12-30 | 1984-07-06 | Devault Michel | SWITCH FOR MULTIDEBIT DIGITAL NETWORK WITH ASYNCHRONOUS TIME SWITCH ADAPTED TO VIDEOCOMMUTATIONS |
| US4569041A (en) * | 1983-03-17 | 1986-02-04 | Nec Corporation | Integrated circuit/packet switching system |
| US4577314A (en) * | 1983-03-31 | 1986-03-18 | At&T Bell Laboratories | Digital multi-customer data interface |
| IT1159480B (en) * | 1983-08-04 | 1987-02-25 | Cselt Centro Studi Lab Telecom | VARIABLE BAND DISTRIBUTED SWITCHING NODE WITH DYNAMIC MANAGEMENT OF HYBRID WEFT |
| DE3331632A1 (en) * | 1983-09-01 | 1985-03-21 | Siemens AG, 1000 Berlin und 8000 München | DIGITAL TELECOMMUNICATION SYSTEM WITH A STAR STRUCTURE OF ITS CONNECTION CABLES |
| US4525830A (en) * | 1983-10-25 | 1985-06-25 | Databit, Inc. | Advanced network processor |
| US4586175A (en) * | 1984-04-30 | 1986-04-29 | Northern Telecom Limited | Method for operating a packet bus for transmission of asynchronous and pseudo-synchronous signals |
| JPS61174851A (en) * | 1985-01-30 | 1986-08-06 | Agency Of Ind Science & Technol | Bus control system |
| US4763317A (en) * | 1985-12-13 | 1988-08-09 | American Telephone And Telegraph Company, At&T Bell Laboratories | Digital communication network architecture for providing universal information services |
| EP0257168B1 (en) * | 1986-08-27 | 1992-06-03 | International Business Machines Corporation | Pseudo synchronous transportation apparatus in a communication network |
| DE3777797D1 (en) * | 1987-01-28 | 1992-04-30 | Ibm | DEVICE FOR MEDIATING BETWEEN CHANNELS FOR SYNCHRONOUS MESSAGE AND FOR MEDIATING ASYNCHRONOUS DATA PACKAGES. |
| FR2611411B1 (en) * | 1987-02-27 | 1989-04-21 | Francois Joel | HYBRID TIME MULTIPLEX SWITCHING SYSTEM |
| FR2618965B1 (en) * | 1987-07-30 | 1989-11-17 | Servel Michel | TEMPORAL SWITCHING SYSTEM FOR PACKETS OF DIFFERENT LENGTHS |
| JPH01103043A (en) * | 1987-10-16 | 1989-04-20 | Mazda Motor Corp | Multiplex transmission equipment |
| US4965796A (en) * | 1989-09-29 | 1990-10-23 | At&T Bell Laboratories | Microprocessor-based substrate multiplexer/demultiplexer |
| SE500427C2 (en) * | 1992-07-01 | 1994-06-20 | Ellemtel Utvecklings Ab | Methods and systems for distinguishing at least two types of time slots in serial digital bit streams in a receiver of the flow |
| IL106363A (en) * | 1993-07-15 | 1997-02-18 | Scitex Corp Ltd | Apparatus and method for data communication between two asynchronous busses |
| US5509006A (en) * | 1994-04-18 | 1996-04-16 | Cisco Systems Incorporated | Apparatus and method for switching packets using tree memory |
| US5682386A (en) | 1994-04-19 | 1997-10-28 | Multi-Tech Systems, Inc. | Data/voice/fax compression multiplexer |
| US5757801A (en) * | 1994-04-19 | 1998-05-26 | Multi-Tech Systems, Inc. | Advanced priority statistical multiplexer |
| US5519704A (en) * | 1994-04-21 | 1996-05-21 | Cisco Systems, Inc. | Reliable transport protocol for internetwork routing |
| US5793978A (en) * | 1994-12-29 | 1998-08-11 | Cisco Technology, Inc. | System for routing packets by separating packets in to broadcast packets and non-broadcast packets and allocating a selected communication bandwidth to the broadcast packets |
| US5867666A (en) * | 1994-12-29 | 1999-02-02 | Cisco Systems, Inc. | Virtual interfaces with dynamic binding |
| GB2301992B (en) * | 1995-06-07 | 1999-07-21 | Nippon Telegraph & Telephone | Method and system for data communication |
| US6097718A (en) | 1996-01-02 | 2000-08-01 | Cisco Technology, Inc. | Snapshot routing with route aging |
| US6147996A (en) | 1995-08-04 | 2000-11-14 | Cisco Technology, Inc. | Pipelined multiple issue packet switch |
| US7246148B1 (en) | 1995-09-29 | 2007-07-17 | Cisco Technology, Inc. | Enhanced network services using a subnetwork of communicating processors |
| US6917966B1 (en) | 1995-09-29 | 2005-07-12 | Cisco Technology, Inc. | Enhanced network services using a subnetwork of communicating processors |
| US6182224B1 (en) | 1995-09-29 | 2001-01-30 | Cisco Systems, Inc. | Enhanced network services using a subnetwork of communicating processors |
| US6091725A (en) * | 1995-12-29 | 2000-07-18 | Cisco Systems, Inc. | Method for traffic management, traffic prioritization, access control, and packet forwarding in a datagram computer network |
| US6035105A (en) | 1996-01-02 | 2000-03-07 | Cisco Technology, Inc. | Multiple VLAN architecture system |
| US6243667B1 (en) | 1996-05-28 | 2001-06-05 | Cisco Systems, Inc. | Network flow switching and flow data export |
| US6308148B1 (en) | 1996-05-28 | 2001-10-23 | Cisco Technology, Inc. | Network flow data export |
| US6212182B1 (en) | 1996-06-27 | 2001-04-03 | Cisco Technology, Inc. | Combined unicast and multicast scheduling |
| US6434120B1 (en) | 1998-08-25 | 2002-08-13 | Cisco Technology, Inc. | Autosensing LMI protocols in frame relay networks |
| US6304546B1 (en) | 1996-12-19 | 2001-10-16 | Cisco Technology, Inc. | End-to-end bidirectional keep-alive using virtual circuits |
| US6122272A (en) * | 1997-05-23 | 2000-09-19 | Cisco Technology, Inc. | Call size feedback on PNNI operation |
| US6356530B1 (en) | 1997-05-23 | 2002-03-12 | Cisco Technology, Inc. | Next hop selection in ATM networks |
| US6862284B1 (en) | 1997-06-17 | 2005-03-01 | Cisco Technology, Inc. | Format for automatic generation of unique ATM addresses used for PNNI |
| US6078590A (en) | 1997-07-14 | 2000-06-20 | Cisco Technology, Inc. | Hierarchical routing knowledge for multicast packet routing |
| US6212183B1 (en) | 1997-08-22 | 2001-04-03 | Cisco Technology, Inc. | Multiple parallel packet routing lookup |
| US6512766B2 (en) | 1997-08-22 | 2003-01-28 | Cisco Systems, Inc. | Enhanced internet packet routing lookup |
| US6157641A (en) * | 1997-08-22 | 2000-12-05 | Cisco Technology, Inc. | Multiprotocol packet recognition and switching |
| US6343072B1 (en) | 1997-10-01 | 2002-01-29 | Cisco Technology, Inc. | Single-chip architecture for shared-memory router |
| US7570583B2 (en) * | 1997-12-05 | 2009-08-04 | Cisco Technology, Inc. | Extending SONET/SDH automatic protection switching |
| US6111877A (en) | 1997-12-31 | 2000-08-29 | Cisco Technology, Inc. | Load sharing across flows |
| US6424649B1 (en) | 1997-12-31 | 2002-07-23 | Cisco Technology, Inc. | Synchronous pipelined switch using serial transmission |
| US6853638B2 (en) * | 1998-04-01 | 2005-02-08 | Cisco Technology, Inc. | Route/service processor scalability via flow-based distribution of traffic |
| US6028867A (en) * | 1998-06-15 | 2000-02-22 | Covad Communications Group, Inc. | System, method, and network for providing high speed remote access from any location connected by a local loop to a central office |
| US6088748A (en) * | 1998-06-17 | 2000-07-11 | Advanced Micro Devices, Inc. | Personal computer system incorporating an isochronous multi-channel, multi-rate data bus |
| US6404771B1 (en) | 1998-06-17 | 2002-06-11 | Advanced Micro Devices, Inc. | Clock lead/lag extraction in an isochronous data bus |
| US6085270A (en) * | 1998-06-17 | 2000-07-04 | Advanced Micro Devices, Inc. | Multi-channel, multi-rate isochronous data bus |
| US6134698A (en) * | 1998-06-17 | 2000-10-17 | Advanced Micro Devices, Inc. | Reduced pin count isochronous data bus |
| US6920112B1 (en) | 1998-06-29 | 2005-07-19 | Cisco Technology, Inc. | Sampling packets for network monitoring |
| US6370121B1 (en) | 1998-06-29 | 2002-04-09 | Cisco Technology, Inc. | Method and system for shortcut trunking of LAN bridges |
| US6377577B1 (en) | 1998-06-30 | 2002-04-23 | Cisco Technology, Inc. | Access control list processing in hardware |
| US6182147B1 (en) | 1998-07-31 | 2001-01-30 | Cisco Technology, Inc. | Multicast group routing using unidirectional links |
| US6308219B1 (en) | 1998-07-31 | 2001-10-23 | Cisco Technology, Inc. | Routing table lookup implemented using M-trie having nodes duplicated in multiple memory banks |
| US6389506B1 (en) | 1998-08-07 | 2002-05-14 | Cisco Technology, Inc. | Block mask ternary cam |
| US6101115A (en) * | 1998-08-07 | 2000-08-08 | Cisco Technology, Inc. | CAM match line precharge |
| US6771642B1 (en) | 1999-01-08 | 2004-08-03 | Cisco Technology, Inc. | Method and apparatus for scheduling packets in a packet switch |
| US6853647B1 (en) | 1999-02-17 | 2005-02-08 | Covad Communications Group, Inc. | System method and network for providing high speed remote access from any location connected by a local loop to a central office |
| US7065762B1 (en) | 1999-03-22 | 2006-06-20 | Cisco Technology, Inc. | Method, apparatus and computer program product for borrowed-virtual-time scheduling |
| US6757791B1 (en) | 1999-03-30 | 2004-06-29 | Cisco Technology, Inc. | Method and apparatus for reordering packet data units in storage queues for reading and writing memory |
| US6603772B1 (en) | 1999-03-31 | 2003-08-05 | Cisco Technology, Inc. | Multicast routing with multicast virtual output queues and shortest queue first allocation |
| US6760331B1 (en) | 1999-03-31 | 2004-07-06 | Cisco Technology, Inc. | Multicast routing with nearest queue first allocation and dynamic and static vector quantization |
| US7095741B1 (en) * | 2000-12-20 | 2006-08-22 | Cisco Technology, Inc. | Port isolation for restricting traffic flow on layer 2 switches |
| US7076543B1 (en) | 2002-02-13 | 2006-07-11 | Cisco Technology, Inc. | Method and apparatus for collecting, aggregating and monitoring network management information |
| US7710959B2 (en) * | 2006-08-29 | 2010-05-04 | Cisco Technology, Inc. | Private VLAN edge across multiple switch modules |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2148571A1 (en) * | 1971-08-10 | 1973-03-23 | Ilikon Corp | Plastics articles prodn machine - for multi-layer items by sequential injection moulding |
| JPS5225550A (en) * | 1975-08-22 | 1977-02-25 | Biiba Kk | Automatic sound volume controller |
| FR2475827B1 (en) * | 1980-02-13 | 1987-05-29 | Dauphin Jean Louis | TIME DIVISION DIGITAL SWITCHING SYSTEM FOR MICROPHONE VEHICLES SPEAKING AND PACKET DATA |
-
1981
- 1981-02-20 FR FR8103440A patent/FR2500704A1/en not_active Withdrawn
-
1982
- 1982-02-19 EP EP82400301A patent/EP0059149B1/en not_active Expired
- 1982-02-19 DE DE8282400301T patent/DE3260344D1/en not_active Expired
- 1982-02-19 CA CA000396648A patent/CA1179754A/en not_active Expired
- 1982-02-19 JP JP57024652A patent/JPS581394A/en active Pending
- 1982-02-22 US US06/350,891 patent/US4446555A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| EP0059149B1 (en) | 1984-07-11 |
| FR2500704A1 (en) | 1982-08-27 |
| DE3260344D1 (en) | 1984-08-16 |
| US4446555A (en) | 1984-05-01 |
| JPS581394A (en) | 1983-01-06 |
| EP0059149A1 (en) | 1982-09-01 |
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