CA1180463A - Method and apparatus for hashing cache addresses in a cached disk storage system - Google Patents
Method and apparatus for hashing cache addresses in a cached disk storage systemInfo
- Publication number
- CA1180463A CA1180463A CA000406399A CA406399A CA1180463A CA 1180463 A CA1180463 A CA 1180463A CA 000406399 A CA000406399 A CA 000406399A CA 406399 A CA406399 A CA 406399A CA 1180463 A CA1180463 A CA 1180463A
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- Prior art keywords
- address
- addresses
- buffer
- memory
- cylinder
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
- G06F12/0871—Allocation or management of cache space
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
- G06F16/90—Details of database functions independent of the retrieved data types
- G06F16/901—Indexing; Data structures therefor; Storage structures
- G06F16/9014—Indexing; Data structures therefor; Storage structures hash tables
Abstract
ABSTRACT
A cache is accessed based upon addresses to a backing store having a larger address space than the cache. The backing store consists of plurality of devices exhibiting delay access boundaries. The cache accessing is based upon a hashing method and system derived from the arrangement of the backing store and in an ordered manner for accommodating the delay access boundaries and enable rapidly adjusting the hash parameters in accordance with changes and backing store capability and other hardware changes.
A cache is accessed based upon addresses to a backing store having a larger address space than the cache. The backing store consists of plurality of devices exhibiting delay access boundaries. The cache accessing is based upon a hashing method and system derived from the arrangement of the backing store and in an ordered manner for accommodating the delay access boundaries and enable rapidly adjusting the hash parameters in accordance with changes and backing store capability and other hardware changes.
Description
METHOD AND APPAR~TUS FOR HASHING
CACHE ADDRESSES IN A CACHED
DISK STORAGE SYSTEM
BACKGRO~ND OF THE INVENTION
Field of the Invention Present invention relates to hierarchical storage systems, more particularly it relates to addressing techniques used within such systems.
Discussion of the Prior Art Addressing large capacity memories have used so-called "hashing" techniques for years, particularly in the main memory area. Generally, a hashing operation includes generating an index indicator for a socalled hash class.
The index indicator directs the addressing mechanism to a so-called scatter index table (SIT) which contains the address of a memory-address directory entry supposedly relating to the area of memory to be accessed. The directory entry is lin~ed to other directory entries of the same hash class hy a singly linked list.
Accordingly, to access a given item within a memory, the index indicator is generated, the address to the directory entry is used to access a directory entry. If no match between the desired memory address and a memory address stored in the directory entry is found, then a succession of directory entries are examined within the hash class to see if the directory has an address indicating that the memory contains the data or has space allocated for receiving data. In the event such an area is identified in the directory, a so-called "hit" is madej access to the memory can proceed. If the area is not identiied through the hashing techniq~re, then a "miss" occurs. Following a miss in hierarchlcal systems, data is either transferred from a backing store to the memory or space is allocated within the mernory to receive data for recording.
It is desired in such hashing techniques to minimize hash time, i.e. reduce access time to the memory.
When the size of a hash class is large, many items are mapped into that class. This plural mapping is often re'erred to as "col'isions" in that multiple data items collide into the same hash class. Searching hash classes due to a large number of collisions can greatly increase the access time to a memory, particularly when the directory is not content addressable. Accordingly, in ~5 many memory applications it is desired to keep the size of the hash class to a minimum for reducing the searching time of the directory. In contrast, when a content addressable memory ls used for the directory, all searches are all conducted in one cycle. Unfortuna~ely, content addressable memories are expensive, there~ore in many applications such a content addressable memory is not feasible.
3 ~ ~
The problem becomes particularly acute in relativeLy large memories. For example, when a large cache is to act as a buffer for disk storage apparatus ~DASD) and the cache has the capacity of 8 megabytes or greater, there is a conflict between reducing the number of collisions and con~rolling costs of the storaye system. A further problem occurs in that disk storage apparatus e~hibits several delay access boundaries. A first delay boundary called latency, is based upon the rotational characteristics of the disk storage apparatus. One or two trar.sducers are positioned with respect to a rotating disk surface such that access to a given point on the surface depends upon the latency of rotation.
Further, in most disk storage apparatus, a single transducer is provided for a single surface. This means the transducer is moved radially from track to track (in a multi-surface disk storage apparatus the rnove is from cylinder to cylinder - a cylinder being all tracks on the same radius) called a cylinder seek. Both of these delays in addressing and accessing are due to the mechanical characteristics of the disk storage apparatus. Accordingly, the number of misses ln a cache that do not accommodate such mechanical delays can greatly increase access times to data areas.
Accordingly, it is desired to provide access to a cache which minimizes the effect of such mechanical delays in the backing store on total system operation.
Many prior hashi.ny techni~ues empl.oy random distribution of the addresses such that the number of collisions tend to be reduced. A corollary is that the addresses should be evenly distributed across the address space of the memory being accessed. Such principles are set forth in several articles published in the IBM Technical _ Disclosure Bulletin. For example, in May, 1977, pages 4822-4823, J. L. Carter, et al .in "Class of Fast Hash Functions Using Exclusive OR" and on page 4826 in the article "Method of Extending Hash Functions for Long Keys" teach that a pair~wise randvm hashing function produces an average runrling time which is linear to the numDer of transactions. While this is true for random access memories, such as employed for main memories, it is not necessarily true where access delay boundaries exist. Accordingly, the so-called "Constant of Proportionality" discussed in these articles does not validly apply to all situations particularly where access delay boundaries exist.
Prime numbers have also been used in hashiny techniques.
For example, see the article by R. P. Brent "Modified Linear Scatter Storage Technique" found on page 3489 o the April, 1972 edition of the IBM Technical Disclosure Bulletin. Again, this article relates to a hashing technique suitable for random access memories not having significant access delay boundaries.
Another aspect of hashing is to reduce the hash time, i.e. reduce the time it takes to generate an address.
Such reduction has been achieved by judiciously selecting names for data which are convertible to an address. For example, in the IBM Technical Disclosure Bulletin, June, 1975 issue on pages 38-39, L. J.
Waguespack "Predistributed Logical Name Generation"
shows a hashing technique wherein a single level Exclusive-OR hash is driven by predistributed logical names for accessing random access memories. A similar technique is shown in the article by D. C. Bossen, et al "Generating Unigue Names for Virtual Seqments" published 5 ~ 3 in the IBM Technlcal Disclosure Bulletin August, 1975, pages 880-881. This article is similar to Waguespack's article in that address predistributions and Exclusive OR functions result in a hash table addressing.
In an installed data processing system, memories can be changed in size. Accordingly, the hashin~ technique should be easily altered. This situation was addressed in one of th~ articles mentloned above, but also set forth in U.S. Patent 4,215,402 where the SIT and hash size are matched to main memory siæe. Again, the hashing was for a pure random access memory not exhibiting significant access delay boundaries.
A summary of desirable hashing techniques is set forth in the IBM Technical Disclosure Bulletin article by R. F.
Arnold, et al "Uniform Hashing Algorithm", pages 2214-2216 of the Dece~ber, 1973 issue. This article relates to mapping virtual address space into a real address space. Desirable properties of the hashing algorithm used to map the address spaces is uniformity of distribution, random distribution of the sequen ial virtual addresses, and below the granularity of hashing provide sequential virtual addresses that map to real addresses. All addresses should match one for one from virtual to real, minimum remapping is to be requi-ed in the hash for memory changes, computation should be r~pid (short delay) and repeatable. A portion of the hashing algorithm described in this article requires where a hit does not occur immediately, iterative processes. It does employ arithmetic techniques including carries and borrows as opposed to modulo two addition (such as Exclusive-OR functions). While this article shows hashing procedures desirable for a .andom access memory not having significant access delay boundaries; it is not seen how the teaching can be applied to backing stores exhibiting various access delay boundaries.
In addition to all of the ahove, a hierarchical storage system can have a plurality of disk storage apparatus. A
single cache should provide the caching ~unction for all of the apparatus. Therefore, in addition to the in~ernal access delay, boundaries of such apparatus, hashing should accommodate unique characteristics of a plurality lQ of such disk storage apparatus. For example, so~called cylinder "0" of each disk storage apparatt1s is usually used as an index to the contents of the data stored in the apparatus. Cylinder "0" is usually the radially outward-most cylinder of tracks. Accordingly, it is to be expected tha-t cylinder "0" may be accessed more fre~uently than other cylinders of the disk storage apparatus; therefore there should be no collisions between cylinder "0" of one disk storage apparatus and cylinder "0" of another stora~e apparatus. Any random dis-tribution, even though it be uniform, implies a possible collision of any relative address with another relative address. Accordingly, random distribution of hashing should be avoided when disk storage apparatus of usual design are employed.
Sut~mary o the Inventiorl It is an o~ject of the present invention to provide hashing methods and systems which readily accommoda-te variations in sl~e of address spaces and backing s~ores.
It is another object of the present invention to provide a hash~type access method and system that ensures a minimal num~er of ~ashing collisions for high use addresses.
It is another object of the invention to provide a method and system for hashing techniques which are readily expandable or contractable in size.
It is yet another object of the invention to provide a method and system for accessing which facilitates an accommodation of delay boundaries in a backing store when the hash access is for a cache or buffer related to a backing store.
In accordance with a first aspect of the present invention, a hashing method and system employs manipulation of address signals which are ordered in accordance with access delay boundaries of a backing store and with an ex~pected fre~1ency of access for certain addresses of the backing store.
An access method and system employing hashing in accordance with the invention, employs a predetermined SIT address space into which is mapped the number of delay units (for example, number of disk storage app2ratus) in a yiven order and equally spaced distributions in the SIT address space such that aL1 TU98101l hashing space beginning with a lowest ordered address begins at a unique address within the SIT address spaoe.The arrangement provides an ordered offsetting cf all hashing for common relative addresses in each of the units constituting access delay boundaries.
A method and system employing hashing in accordance with another aspect of the invention includes altering the address bein~ ~ashed by the size constant of the device addresses for addxessing a smaller capacity cache memory ln an ordered manner related to the constructural features o the device. For e~ample, the number of devices in a backing store constitutes a first hashing factor for distributing the addresses in an ordered manner while the number of delay boundaries, i.e.
cylinders in a disk storage apparatus, are a hashing factor for ordered cylinders hash addressing.
The foregoing and other objects, features, and advantages of the invention will be apparent from the following more particular description oî preferred ~0 embodiment of the invention, as illustrated in the accompanying drawing.
Description of Drawings Figure l is a block diagram of a hierarchical storage system employing the teachings of the present invention.
Figure 2 is a diagramatic showing of a disk storage apparatus and its constructional relationship to hash addressing in accordance with the invention as shown iIl Fig. l. ,~, Figures 3 and 4 diagramatically illustrate disk apparatus addressee distributions within an address space for a scatter index table for use in connection with the Figure l illustrated system.
Figure 5 is a map illustrating hash address distribution for a plural device embodiment of the Figure 1 illustrated system.
Flgure 6 is a logic diagram of a circuit for implementing the hash method and system in the Figure l illustrated system.
Figure 7 illustrates a directory construction and associated control circuits for implementing the invention shown in the Fiqure 1 illustrated system.
Figure 8 is a block diagram of a constructed ve.rsion of the present invention as illustrated in Figure l.
Figure 9 shows a data structure of a logical device control block used in connection with Fiqure 8.
Figure 10 is a logic flow diagram showing machine operations for avoiding hashing of sequential tracks within delay access boundaries in connection with the Figure 8 illustrated system.
S Figure 11 is a logic flow diagram showing an implementation of the inventive hashing method in a machine opera~ion sequence and system in the Fi~ure 8 illustrated ~mbodiment.
D tailed Description Referring now more particularly to the drawings, like numerals indicate like parts and structural reatures in the various diagrams. The present invention is preferably practiced in a hierarchical peripheral storage system lO, as shown in Figure l. A plurality of disk storage apparatus (direct access storage devices--DASD) ll (saparately enumerated as DO, D1, D2, ...) coupled to a shared cache 12 for transferring data to and from a host (not shown), such as a central processing unit or other computational facilities via input output connection 13. In a preferred mode, input output connection 13 is the input output connection used with the International Business Machines Corporation series 370 computers, no limitation thereto intended. Access to data or to data areas in either the cache 12 or DASDs ll is through address bus 14 which c:an be a portion of the inpu~ output connection 13 in the 370 series. A portion of the DASD addresses can be supplied over a bus indicated by dotted line 15 to actuate a pair o electronic swi'ches 16 and 18 whic:h respectively direct address signals and data signals through di'ferent paths of the system lO. Numeral 15 in a second embodiment can designate a separate peripheral command which actuates the switches 15 and 18. For example, a command may indicate that all data references are to be through cache 12, then switch 16 is set to the illustrated position.
On the other hand, a command may be received that all data references may be directed to DASDs ll which causes the switch 16 to be switched to the alternate position, i.e. connect DASDs 11 to bus 14. Other means of controlling switch 16 may also be employed.
The control indicated by numeral 15 also extends to switch 18 which either directs the DASD 11 connection to bus 21 for transferring data signals-to a host. Bus 2L in turn can be connected to input output connection 13, such connection is not shown. Bus 22 extends from switch 18 to cache i2 such that data can be transferred between DASD
11 and cache 12. System L0 further includes a control 20 which urther actuates electronic switch 18 such that the transfer of data.signals between DASD 11 and cache 12 car. be independent of and asynchronous to operation of the host. That is switch 18 position can be host directed or locally directed.
Assume that switch 16 is in the illustrated position.
DASD address signals on bus 14 are directed to old hash lS circuits 23 to determine whether or not a previous reference to cache 12 will enable access to cache 12 without hashing the address received on bus 14. Since DASD 11 has a large capacity for storing data and cache 12 has a lower capacity, all-be-it a significant capacity, hashing address techniques using the addresses of DASD 11 are used to determine whether or not space has been allocated in cache 12 for a data access or whether given data is in fact stored in cache 12. In any event, old hash circuit 23 upon detecting the occurrence of a previously closely rslated address, as later described, directly accesses scatter index table (SIT) 27 ~hich indexes the hash signal to directory 30 for accessing cache 12. LDCB 25, accessed via bus 24, contai~s the DASD address and the corresponding SIT 27 address.
Directory 30, as later described, contains one entr-i .~r each addressable segment of cache 12. Each entry will include an address indication for DASD 11 to indicate which data is replicated or cache space is allocated for cache 12. Since a hash class may consist of a plurality of directory 30 entries, a linking mechanism 31 links all of the entries in the same hash class 'ogether using a singly linked list. Once a directory entry is found that corresponds to the DASD 11 address, then cache 12 is accessed, via path 32, at the address indicated by directory 30. Then the data can be transferred directly between the.,host (not shown) and cache 12 via I10 connection 13. Of course, directory 30 may indicate a miss, i.e. no data space has been allocated in cache 12.
In this instance, actions beyond the present description of this figure are required.
In the event old hash circuit 23 indicates that the previous reference to cache 12 was not immediate but remote from the presently received DASD address; then the presently received address is supplied to hash c~rcuit 34 for the address hashing operation. As a result of the hashing operation, an address signal supplied over bus 35 identifies a given register in SIT
27. ~he contents of that register point to a directory 30 entry corresponding to a hash class. Then the directory 30 hash class is scanned as will be described.
In summary, access to cache 12 is via a set of DASD 11 address signals received on address bus 14 sent through old hash circuit 23 and then either through hash circuit 34 for a new hashing operation or directly to SIT 27 for generating an index or address signal for directory 30.
Directory 30 is then accessed for scanning the entries in tne hash class to look for a DASD 11 address corresponding to the received DASD address. On a hit or a favorable compare, cache 12 is accessed. Other~ise, a miss is indicated.
As mentloned, DASD 11 can be directly accessed. In this case, switch 1~ i5 to the alternate ~not shown) position, while switch 18 is also moved to its alternate position.
In this mode, access to data and access to data storage areas f~r recording on DAS~ 11 is as in any disk s-torage appara-tus system.
Upon a miss being indicated by directory 30, a control signal over b,us 33 to control 20 for actuating switch 18 to illustrated position for transferring data signals from an _ddressed ~ASD 11 corresponding to the received DASD 11 address signals for transferring data signals from such DASD over bus 22 to cache 12. Of course before such transfer can occur, DASD 11 has to be available, i.e. not busy, and the di.rectory 30 and hashing address must be setup such that access to cache 12 is enabled.
Figure 2 illustrates a general arrangement of DASD L1.
Generally each DAS device 11, such as D0, consists of a plurality of co-rotating dislcs 40, 41, each disk having a pair of surfaces for recording data signals. One of the surfaces of all of the surfaces in de-~ice D0 i5 reserved for positioning or servoing information. All of the tracks in a preferred form are concentric with all of the tracks being radially aligned with other tracks on other surfaces. For example, the two disks ~0 and 41. each have a radially outermost track 42, ~3 respectively. All of the trac}cs in the radially outermost position are termed cylinder 0 (C0). Since there is one head for each surface, when Lhe servo position (not shown) aligns the head (not shown) with the C0 tracks, then any surface can be accessed through electronic switching to access any track in C0. To access another cylinder, all of ~he heads (not shown) must be moved radially to the addressed ~U9&1011 i3 track, such as -the next innermost trac~s of cylinder Cl (not shown). This mechanical movement causes a substantial delay in accessing data areas and therefore is a significant delay access boundary. O~her cylinders, o which there may be over 500 cylinders in a single disk apparatus, include cylinder X having tracks 44 and 45 respectively on disks 41 and 40. In a similar manner, cylinder Y will have track 46 on disk 41, while disk 40 has a similar track.~In a similar manner, selecting DASD
11 devices requires substantial protocol and is also a delay access boundary.
All of the above characteristics are melded into the ` hashing method and system of the present invention in that a major factor in defining a hash class are the number of cylinders on each storage device. This results in a so-called cylinder ofset in the hash addressing.
All of the devices identified by device addresses have a balanced space assigned within the SIT 27 address space.
~ach hash class includes an address from each of the devices. In a small SIT 27, several cylinder address spaces from a siven de~ice may be within the same hash class, as will become more apparent. To further provide an ordered symmetry of hashiny, the devices are offset as a function of the address size of SIT 27, i.e. the number of registers therein. Therefore the total number of devices is an offset so that all addresses for all COs are never in the same hash class. Since C0 typically contains an index to data stored in the disk storage apparatus, it is a most commonly addressed cylinder. By keeping the most commonly addressed cylinder in different hash classes, the probability of a hash collision within the hashing operation is reduced. The adjacency of the tracks in the SIT 27 favors electronic switching between ~rac~s by relating the addresses of che tracks to adjacent registers of SIT 27. The offsets of cylinders an~ devices provide for an easy adjustment of the hashing algorit~ as the si~e of the cache 12 is varied or the size of SIT 27 is varled. It should be noted that when either cache 12 or SIT 27 is varied, all of the data in the cache lZ should be purged for data integrity purposes.
Figures 3 and 4 diagramatically show the SIT 27 address space as~extending from "0" thru "~" registers. The hashing algorithm enables all of the device addresses to be offset an identical amount from the base address "0"
of SIT 27. Eor example, in the address space 50 of Figure 3, fourteen devices (DASDs ll) are shown as having fourteen equally-spaced offsets 51. For example, device D0 has its cylinder "0" address at zero. Device Dl has its cylinder "0" address at N/14, device D2 has its cylinder "0" address at 2N/14. This means that each device DX will have a cflinder "0" indexed at SIT 27 a~dress NX divided by the number of devices.
~ccordingly, when 21 devices are installed in the system lO, the smaller offsets 52 result. Figure 3 shows all the devices 11 having an identical number of tracks.
This restriction is not necessary for practicing the present invention, even though it does simplify implementation. In Figure 4, the SIT 27 is divided into different offsets in accordance with the size or capacity in number of tracks of the various storage devices. For example, offsets 56 for larger devices are greater than offsets 5;. In a similar manner, of.~set 57 is for a yet larger device.
Figure 5 shows a map of how device addresses appear in SIT register addresses for aceessing directory 30. The separate device addresses are respectively setforth in columns 60, 61, 62, 63 for devices D0-D3 respectiveLy.
S The cylinder number C is indicated in the left hand column while the track number within the cylinder is indicated in the rlght-hand columns. As shown in ~igure 5, each cylinder has ten tracks, in a constructed embodiment ~ach cylinder had fifteen t^acks. The selection of ten is arbitrary and capricious and used for simplifying the illustration. The hash classes of the illustrated mapping of Figure 5 correspond to the rows of cylinder and track identifica~ions. For example, one hash class consists of address 660 of device D0, address 330 of device Dl and address 000 device D2 and no entry for device D3. For a small SIT 27, such a hash class could include one or more tracks from each of the devices. Cylinder C0 of device D0 is indicated by numeral 65 having tracks 00 thru 09. Cylinder Cl of device D0 also has tracXs 0 thru 9 whi~h in the illustrated embodiment are indicated by numbers 10 through 19. In a similar manner, all of the ~racks w-thin device D0 are identified wilh their respec'ive cylinders. For purposes of illustration, it is assumed that SIT 27 is relatively large such that one hash class includes only one track from a given device. In th-.s instance, device offset is three cylinders as indicated by a numeral 66; there is no overlap, i.e. there are relatively small devices with respect to the size of SIT
27. Cylinder C0 of device Dl appears at 67, while cylinder C0 of device D2 appears at 68. ~he ~-rangement is s~ch following the device distri~utior of ~igures 3 and 4 that none of the cylinders C0 of any device will share a hash class with any o'her cylinder C0 of another 18 v~
device. In device D2, numeral 70 identifies the three cylinder device offset while numeral 71 indicates empty space, i.e. that space in SIT 27 which contains no track addresses for device D2. On the other hand, for a small SIT 27 with respect to the size of DASDs 11, each hash class could include two tracks from each device, three tracks from each device and so forth. Still cylinder C0 of any device will never share a hash class from a cylinder C0~,of any other device. The principle is extended such that no like addressed cylinders are in the same hash class, i.e. cylinder X of D0 is always in a hash class different from cylinder X of any other device; X lS
an integer indicating a cylinder address.
Figure 6 is a logic diagram illustrating hash circuit 34.
Circuit 34 is an arithmetic circuit which results in an output at 84 with an SIr 27 register address which also identifies the hash class having a numerical value modulo the number of registers in SIT 27. Computation begins with the cylinder address C being supplied at 75 to binary multiplier 76, which multiplies it with the cylinder weight received at 77. Cylinder weight is the number of cylinders in the device. The resultant ?roduct is added in adder 78 to the track address H supplied over line 79. The product-sum is then supplied to modulo N
adder 80 wherein the product-sum is added to the device offset product constituting the device number D and device welght DW respectively received at 82 and 83.
Device weight i5 number of devices 11. The SIT 27 address signals at 84 access SIT 27 for fetching the directory 30 index to the hash class.
Figure 7 illustrates in more detail the hashing operation for system 10 shown in Figure 1. The device address ~HD (cylinder, head and device) are received via switch 16 into old hash circuit 23. In some addressing schemes a record R address can be also supplied which in the illustrated embodiment is not a part of the hashiny process because the entire contents of a track of DASD 11 can be transferred to cache 12. In the event that a record is separately addressable in DASD 11 then the record number R could be introduced into the hashing algorithm usi~g the inventive principles. In any event, the address CHD is supplied to comparator circuit 90 which compares the CH value of content of a register 91 selected by the D address signal supplied to registers 91 over bus 89. For a compare of C being equal, i.e. the track is in the same cylinder, compare circuit 90 supplies a difference signal to adder 92. The difference signal is the difference between the H value received from switch 1~ and the H value stored in register 91.
This difference value is added to the SIT address stored in the register 91 to generate a SIT address for CHD
without hashiny as described with respect to Figure 6.
This difference value plus the previous SIT address indicates the SIT 27 register containing the index to directory 30 for the track within the indicated cylinders. Accordingly, for all tracks within a cylinder, once a cylinder has been accessed, further hashing is not required whenever the hash result is temporarily saved. The sum of the old SI address plu5 the difference is supplied through OR circui-ts 93 to address SIT 27. The contents of the addressed SIT 27 register are supplied over bus 95 to address directory 30. When the contents of the SIT 27 register are 11 zeroes, a cache miss is indicated.
In the event compare circuit 90 indicates that a different cylinder is being accessed, then a new hash occurs. The address CHD is supplied over bus 96 to hash circuit 34; bus 96 leads to line 75 of Figure 6. Hash circuit 34 outputs a SIT 27 address over bus 35 through OR circui~s 93 to address SIT 27. Also, the newl~ hashed SIT value is supplled to the last 91 registe~ indica~ed by the D value supplied over bus 91 for addressing those registers. ,.
The directory 30 address signals on bus 95 select one of the entry registers 100 as the first entry of the hash class in directory 30. The accessed register supplies the DCH values over bus 101 to compare circuit 102. In the event the record value is also supplied for comparlson purposes, the record value in R section 111 of the directory 30 registers 100 is also supplied to compare circuit 102. The compare circuit 102 loo~s or equality between the DASD address stored in the directory 30 entry register lOC and the address received over bus 103. For a detected inequality, compare circuit 102 supplies an access signal over bus 106 to access HL
section 107. HL section 107 is a po_tion of a singly-linked list for indicating the address of the next register 100 containing an entry in the same hash class.
That nex' register ].00 is accessed as indicated by line 31. In the event HL section 107 indicates EOC (end of the chaln) a miss is indlcated over line 108 which cor.responds to line 33 of E'igure 1.
When compare circuit 102 indicates equality, a cache 12 hit is occuring. A signal supplied by com?are c -cuit 102 over line loa activates address generator 105 wr.ich takes the directory 30 address from bus 106 (access v;a TU~81011 bus 9S or through the HL section 107) and generates a cache 12 address based upon the directory 30 address.
Cache address is supplied over bus 32 for accessing cache 12. Generator 105 multiplies the register 100 offset address by a constant to calculate a cache 12 offset address. The constant is the ratio of number of bytes in an addressible segm~nt in cache 12 to the number of by~es in hash register 100. The cache 12 offset is then added to a cache L2 base address to obtain the cache 12 address. Instead of a calculation, the calculation result for each directory could be stored, either physically or logically with each directory entry.
Directory 30, in addition to containing the sections 101, 111 and 107, further includes an index 110 which is useful for identifying the directory entry. S section 112 contains the sector value of the record R, CCL
contains the logical cylinder number (such as provided for virtual disk on real disk) and FG 114 contains mis-cellaneous control flags not pertinent to an understanding of the invention. BP 115 and FP 115 are respectively backward and for~Jard pointers in an LRU
(least ecentiy used) list use in cormection with space management of cache 12, as is well known in the buffer management art.
Figure 8 illustrates a preferred implementation of the inverltion wherein two so called "strings" of DASDs 11 communicate with cache 12 and a host (not shown) via input-output connections 13. The input-ou'put connections are controlled through channel adaptors L20 separately denominated as CAA, CA3, C~C and CAD. I'hese channel adaptors employ the input-output connection TU9~1011 logic of design used with the aforementioned IBM 370 series computer. A computer or processor PROC 121 communicates with the host via charmel adaptors 120 through bus 122. For example, peripheral commands supplied by the host are transferred to PROC 121 via bus 122. PROC 121 in turn communicates over bus 123 with a so-called system storage 124. System storage 124 contains cache 12, the registers of directory 30 and the registers o,SIT 27. System storage 124 is preferably a 10 high speed random access memory of a semiconductor ty?e.
P.ll addrGssing is by base addresses plus offset or cache 12, SIT 27 and directory 30.
PROC 121 communicates with DASD 11 over bus 130 which extends to device adaptors 132, separately denominated 15 as OAA and DAB as well as to data flow circuits 131.
Device adaptors ~AA and DAB each respectively control and access one string of DASDs 11 and are constructed using known techniques. Data flow circuits 131 can include serializers; other circuits that are usually 20 found in connection with such circuits used with disk storage apparatus 3us 133 extends from ~a_a flow circuits 131 to channel adaptors 120 for providing direct access to DASDs 11. Bus 134 connects data flow circuits 131 to system storage ].29:, hence cache 12. ~3us 25 135 cormects system storage 1~4 to channel adaptors 120.
The functions of switch 16 of Figure 1 are performed in channel adaptors 120 using known electronic design techniques, while the functions of switch 18 are performed in data flow circuits 131.
30 :~ROC 121 has control storage i~O, a high speed -an~om access memory, which includes microcode type of com?uter programs for performing the hash circuit 34 functions as .
represented by program 34P. LDCB 25 registers are contained in control storage 140 at 25P. Other programs OP 141 provide for control of storage system 10 in the usual manner. Additionally, PROC 121 includes a plurality of high speed registers 142 for enhancing speed of microcode execution. Registers 142 constitute a scratch pad or work space for the processor. SIT
registers 143 contain one "page" of SIT 27 for processing by PROC 121"that is once the hash program 34P has been executed by PROC 121, a page of SIT 27 corresponding to one or more cylinders o hash are transferred to SIT
registers 143 such that the old hash 23 technique is expedited. Also, searching directory 30 results in a transfer of a page of directory entries to DIR REG 144 for similar rapid processing. In this manner, access to system st:orage 124 for control purposes is minimized to allow overlapping data processing signal transfers with control processing by PROC 121. Since there are four channel adaptors, four different operations can occur simultaneously. Further independent ree standing operations by DASD 11 can be occurring, therefore PROC
121 should be able to do p~ocessing indeoendent of system storage 124 as much as possi~le. Operation of the invention in the Figure 8 environment ls better understood by referring to Figures 9, 10 and 11. It is understood with respect to ~hose figures that PROC 121 ?rograms OP 141 including the usual idle scan or dispatching f~lnctions well known in the progra~ning and data processing arts.
LDCB registers 25P shown in Fi~u-e 9 contain the DASD 11 addresses associated with a particular cache 12 access.
For example, seek address 150 defines the cylinder while SID address and sector sections 151 and 152 identify which track and the portion of the track to be accessed in DASD 11. Index 153 corresponds to index 110 of Figure 7. Cache address 154 is the cache address generated by address circuits 105 as well as OP 141. SEQ bit 155 signals that a succession of consecutively addressed bLocks will be transferred in a so-called "sequential mode". SEQ 155 is set via a mode set command received from a host (not shown) signiyiny type of operations to be performed,~y syst~m 10. Numeral 156 denotes that LDCB
25 may contain additional entries not pertinent to an understa!~ding of the present invention.
Referring next to Figure 10, the old hash unction as performed by hash circuit 23 or by program OH 23P of Figure 8 are detailed in this machine operation flow lS chart. Initiation of the machiIle operations occurs at 160 which corresponds in Figure 1 to the output of switch 16 and to the activation of OH 23P of Figure 8. The first step is to access LDCB 25 to determine if SEO 155 is set for indicating a sequential mode. That is, there is a high proba'oility that a block of data residing in the same cylinder or in an i~media~ely adjacent track as the immediately preceding block will be accessed~ In the present implementation, only those addresses used during the sequential mode use the old hash principle. For a non-sequential mode, the hash operation pe-formed by circuit 34 or program 34P is activated via logic path 200 and as detailed at the machine operation level in Fiyure 11. For the sequential mode at step 161, processor 121 transfers the received address RDC~ for Ihe record R lnto an lnternal register IR (not shown). A. 163 processor 121 compares the received address RDCH to the pe-mitted e,xtent of addressing ~or the address via channel ada?tor 120, that is, a host (not shown) can send a so-called "define extent" command which sets the limits of access for a given channel path including a given channel adaptor 120. If the address RDCH is outside of the defined address space or extent, processor 121 follows logic path 164 to report an error condition to the host (not shown). Otherwise, at 166, processor 121 compares the received RDCH with the contents of the last registers 91, which in Figure 8 are some of the registers 142. In the illustra$ed embodiment, if the difference between the received address RDCH and the las~ address in register 91 is greater than unity, then hash function is activated via logic path 200. When the track addresses H
di~fer by one, one is added to the last register ~1 contents, independent of cylinder boundaries, to increment. or d~crement the SIT 27 address by unity. The adjacent SIT 27 register is read out to access directory 30 without hashing. In the se~uential mode only one hash operation may be necessary to access a plurality of data blocks from cache 12.
In an alternative embodiment, compare step 165 makes a compare to determine whether or not the received address RDCH is within the same cylinder as the address stored in last register 91. If so, the difference between the received address and the stored address will lndicate the offset address of the SIT 27 registers containing the pointer corresponding to the received RDCH and the address stored in last register 91. This difference then can be added~subtracted from the value in the last register to obtain the SIT 27 register for indexing into directory 30.
In the present embodiment, promo' on of da.a to cache before it is needed was limited to that data res ding in 6~
a given cylinder, i.e. residing within a given set of delay boundaries. No limitation to this implementatlon is intended in the practice of the present invention. At 170 the cylinder boundari~s are checked to see i' _he received address RDCH is in the same cylinder as the last address in register 91. If it is outside of the cylinder, processor 121 at 171 follows Logic path 1,2 to report a miss, i.e. it ~nows the data has not been promoted in~o cache, 12. On the other hand, when the received address R~CH is in the same cylinder as 'he address stored in last register 91, at 173 the directory 30 address is fetched from SIT 27 and a search for the hash class as described is conducted. Upon completion of the search, processor 121 at 174 determlnes whether the data has been identified as residing in cache 30. For example, if the SIT 27 entry was all zeros, then a miss is indlcated immediately. Otherwise, the hash class of directory 30 is searched in a sequential manner. For a miss, normal allocation and data promotion procedures are followed. For a hit, processor 121 at 175 determines whether or not the data is pinned or bound to cache 30.
Pinning or binding indicates that the data must remain in cache 30 until unpinned or unbound, i;e. it is not subject to a replacement algorithm. For plnned data, logic step 180 is followed to access the data frorn cach~
12 or to prepare for storing data in cache 12.
Otherwise, at 176 the record is made most recently used ln the replacement algorithm LRU (least recently used);
then loglc path 180 is followed.
Figure 11 illustrates operation o,~ hash microcode 34 After the old hash opera..ion 23 ndicating an out o' cylinder access, PROC 121 follows logic path 200 ~o'~ox 201 to take the address DCH from LDCB 25P and place _he ~U981011 address into registers 142. Steps 202 and 203 constitute the functions corresponding to hash circuit 34. Step 202 generates the address of SIT 27 and stores it into one of the registers L42 using the ec~ation setforth in the box 202. Note that the value is twice the modulus o SIT 27, i.e. 2N rather than N. AT 203 the hash offset (HO) is made e~lal to contents of -the one register 142 whi'e the hash cylinder is the value of the contents of the one register 142,divide~ by two. Then at 204, the contents of SIT 27 contain in system storage 12~ which contains the regi;ters identified by HO and HC are transferred to SIT register 143. At 205, the SIT register 143 corresponding to HC is read out for obtaining the pointer to the entry in directory 30 which contains the entry corresponding to the hash value. Then beginning at 217, directory 30 is searched within a search loop 210. End of chain (end of hash class) is always checked at 217; if SIT has a zero entry, EOC is also indicated at 217.
Searching directory 30 within a given hash class reauires a transfer of directory 30 portion to directory regis~er 144. This transfer s implied in cirec~ory 30 search loop 210. This loop corresponds to the Fisure 7 illustra~ion including compare circuit 102. At 211 the directory 30 entry is read and transferred ~o register 144. At 212, the value of the DASD address, DCH, contained in the directory entry, is ~ompared with the DCH value received from the host and stored in register la2 at step 201. When there is a non--compare, ,he scan must continue; PROC 121 follows logic path 215 to read the ~ink pointer, HL 107, for identifyiny the next directory 30 entry to be examined. At 217, the contents of the link pointer are exam ned to determine whether or not it is the end of the chain (~OC). I it is the end of ~U981011 ~. ~, 28 ~ 3 the chain, a cache miss has occurred and a miss flag in registers 142 is set at 218 for later use by PROC 121.
The program is exited at 214 for further processlng of command execution as is known in the data processing art.
In the event that the hash class does not inish at 217, steps 211 and 212 are repeated. The loop continues until either a miss occurs or a hit is indicated at 212.
For a cache ~it, PROC 121 follows logic path 104 (also Fig. to 7) step 213 for generating the cache address.
10 Step 213 corresponds to address generator 105. The cache address is generated based upon the address of the directory 30 register entry in register 144 as modified ` in a predetermined manner for generating the cache address or fetching the cache address from the directory 43 entry. That is, there is one directory 30 entry for each addressable segment of cache 12. Accordingly, the spatial relationship can be established. The index 110 is then set into index 153 of LDCB 25P. A flag (not shown) called hit in register 142 is also set and the L~U
list is updated by adiusting the backward and forward poin~e-s 115 and 116 to make ~he just-identi'ied segment of cache 12 the most-recently used. Updating LRU lists are well known and not described for that reason. The received address RDCH and the SIT 27 address are stored in last re~isters 91.
While the invention has been ~articular].y shown and described with reference to the preferred embodimen~s thereof, it will be unders~ood by those skilled in the art that various parting from the spirit an scope of ~he invention.
TUa81011
CACHE ADDRESSES IN A CACHED
DISK STORAGE SYSTEM
BACKGRO~ND OF THE INVENTION
Field of the Invention Present invention relates to hierarchical storage systems, more particularly it relates to addressing techniques used within such systems.
Discussion of the Prior Art Addressing large capacity memories have used so-called "hashing" techniques for years, particularly in the main memory area. Generally, a hashing operation includes generating an index indicator for a socalled hash class.
The index indicator directs the addressing mechanism to a so-called scatter index table (SIT) which contains the address of a memory-address directory entry supposedly relating to the area of memory to be accessed. The directory entry is lin~ed to other directory entries of the same hash class hy a singly linked list.
Accordingly, to access a given item within a memory, the index indicator is generated, the address to the directory entry is used to access a directory entry. If no match between the desired memory address and a memory address stored in the directory entry is found, then a succession of directory entries are examined within the hash class to see if the directory has an address indicating that the memory contains the data or has space allocated for receiving data. In the event such an area is identified in the directory, a so-called "hit" is madej access to the memory can proceed. If the area is not identiied through the hashing techniq~re, then a "miss" occurs. Following a miss in hierarchlcal systems, data is either transferred from a backing store to the memory or space is allocated within the mernory to receive data for recording.
It is desired in such hashing techniques to minimize hash time, i.e. reduce access time to the memory.
When the size of a hash class is large, many items are mapped into that class. This plural mapping is often re'erred to as "col'isions" in that multiple data items collide into the same hash class. Searching hash classes due to a large number of collisions can greatly increase the access time to a memory, particularly when the directory is not content addressable. Accordingly, in ~5 many memory applications it is desired to keep the size of the hash class to a minimum for reducing the searching time of the directory. In contrast, when a content addressable memory ls used for the directory, all searches are all conducted in one cycle. Unfortuna~ely, content addressable memories are expensive, there~ore in many applications such a content addressable memory is not feasible.
3 ~ ~
The problem becomes particularly acute in relativeLy large memories. For example, when a large cache is to act as a buffer for disk storage apparatus ~DASD) and the cache has the capacity of 8 megabytes or greater, there is a conflict between reducing the number of collisions and con~rolling costs of the storaye system. A further problem occurs in that disk storage apparatus e~hibits several delay access boundaries. A first delay boundary called latency, is based upon the rotational characteristics of the disk storage apparatus. One or two trar.sducers are positioned with respect to a rotating disk surface such that access to a given point on the surface depends upon the latency of rotation.
Further, in most disk storage apparatus, a single transducer is provided for a single surface. This means the transducer is moved radially from track to track (in a multi-surface disk storage apparatus the rnove is from cylinder to cylinder - a cylinder being all tracks on the same radius) called a cylinder seek. Both of these delays in addressing and accessing are due to the mechanical characteristics of the disk storage apparatus. Accordingly, the number of misses ln a cache that do not accommodate such mechanical delays can greatly increase access times to data areas.
Accordingly, it is desired to provide access to a cache which minimizes the effect of such mechanical delays in the backing store on total system operation.
Many prior hashi.ny techni~ues empl.oy random distribution of the addresses such that the number of collisions tend to be reduced. A corollary is that the addresses should be evenly distributed across the address space of the memory being accessed. Such principles are set forth in several articles published in the IBM Technical _ Disclosure Bulletin. For example, in May, 1977, pages 4822-4823, J. L. Carter, et al .in "Class of Fast Hash Functions Using Exclusive OR" and on page 4826 in the article "Method of Extending Hash Functions for Long Keys" teach that a pair~wise randvm hashing function produces an average runrling time which is linear to the numDer of transactions. While this is true for random access memories, such as employed for main memories, it is not necessarily true where access delay boundaries exist. Accordingly, the so-called "Constant of Proportionality" discussed in these articles does not validly apply to all situations particularly where access delay boundaries exist.
Prime numbers have also been used in hashiny techniques.
For example, see the article by R. P. Brent "Modified Linear Scatter Storage Technique" found on page 3489 o the April, 1972 edition of the IBM Technical Disclosure Bulletin. Again, this article relates to a hashing technique suitable for random access memories not having significant access delay boundaries.
Another aspect of hashing is to reduce the hash time, i.e. reduce the time it takes to generate an address.
Such reduction has been achieved by judiciously selecting names for data which are convertible to an address. For example, in the IBM Technical Disclosure Bulletin, June, 1975 issue on pages 38-39, L. J.
Waguespack "Predistributed Logical Name Generation"
shows a hashing technique wherein a single level Exclusive-OR hash is driven by predistributed logical names for accessing random access memories. A similar technique is shown in the article by D. C. Bossen, et al "Generating Unigue Names for Virtual Seqments" published 5 ~ 3 in the IBM Technlcal Disclosure Bulletin August, 1975, pages 880-881. This article is similar to Waguespack's article in that address predistributions and Exclusive OR functions result in a hash table addressing.
In an installed data processing system, memories can be changed in size. Accordingly, the hashin~ technique should be easily altered. This situation was addressed in one of th~ articles mentloned above, but also set forth in U.S. Patent 4,215,402 where the SIT and hash size are matched to main memory siæe. Again, the hashing was for a pure random access memory not exhibiting significant access delay boundaries.
A summary of desirable hashing techniques is set forth in the IBM Technical Disclosure Bulletin article by R. F.
Arnold, et al "Uniform Hashing Algorithm", pages 2214-2216 of the Dece~ber, 1973 issue. This article relates to mapping virtual address space into a real address space. Desirable properties of the hashing algorithm used to map the address spaces is uniformity of distribution, random distribution of the sequen ial virtual addresses, and below the granularity of hashing provide sequential virtual addresses that map to real addresses. All addresses should match one for one from virtual to real, minimum remapping is to be requi-ed in the hash for memory changes, computation should be r~pid (short delay) and repeatable. A portion of the hashing algorithm described in this article requires where a hit does not occur immediately, iterative processes. It does employ arithmetic techniques including carries and borrows as opposed to modulo two addition (such as Exclusive-OR functions). While this article shows hashing procedures desirable for a .andom access memory not having significant access delay boundaries; it is not seen how the teaching can be applied to backing stores exhibiting various access delay boundaries.
In addition to all of the ahove, a hierarchical storage system can have a plurality of disk storage apparatus. A
single cache should provide the caching ~unction for all of the apparatus. Therefore, in addition to the in~ernal access delay, boundaries of such apparatus, hashing should accommodate unique characteristics of a plurality lQ of such disk storage apparatus. For example, so~called cylinder "0" of each disk storage apparatt1s is usually used as an index to the contents of the data stored in the apparatus. Cylinder "0" is usually the radially outward-most cylinder of tracks. Accordingly, it is to be expected tha-t cylinder "0" may be accessed more fre~uently than other cylinders of the disk storage apparatus; therefore there should be no collisions between cylinder "0" of one disk storage apparatus and cylinder "0" of another stora~e apparatus. Any random dis-tribution, even though it be uniform, implies a possible collision of any relative address with another relative address. Accordingly, random distribution of hashing should be avoided when disk storage apparatus of usual design are employed.
Sut~mary o the Inventiorl It is an o~ject of the present invention to provide hashing methods and systems which readily accommoda-te variations in sl~e of address spaces and backing s~ores.
It is another object of the present invention to provide a hash~type access method and system that ensures a minimal num~er of ~ashing collisions for high use addresses.
It is another object of the invention to provide a method and system for hashing techniques which are readily expandable or contractable in size.
It is yet another object of the invention to provide a method and system for accessing which facilitates an accommodation of delay boundaries in a backing store when the hash access is for a cache or buffer related to a backing store.
In accordance with a first aspect of the present invention, a hashing method and system employs manipulation of address signals which are ordered in accordance with access delay boundaries of a backing store and with an ex~pected fre~1ency of access for certain addresses of the backing store.
An access method and system employing hashing in accordance with the invention, employs a predetermined SIT address space into which is mapped the number of delay units (for example, number of disk storage app2ratus) in a yiven order and equally spaced distributions in the SIT address space such that aL1 TU98101l hashing space beginning with a lowest ordered address begins at a unique address within the SIT address spaoe.The arrangement provides an ordered offsetting cf all hashing for common relative addresses in each of the units constituting access delay boundaries.
A method and system employing hashing in accordance with another aspect of the invention includes altering the address bein~ ~ashed by the size constant of the device addresses for addxessing a smaller capacity cache memory ln an ordered manner related to the constructural features o the device. For e~ample, the number of devices in a backing store constitutes a first hashing factor for distributing the addresses in an ordered manner while the number of delay boundaries, i.e.
cylinders in a disk storage apparatus, are a hashing factor for ordered cylinders hash addressing.
The foregoing and other objects, features, and advantages of the invention will be apparent from the following more particular description oî preferred ~0 embodiment of the invention, as illustrated in the accompanying drawing.
Description of Drawings Figure l is a block diagram of a hierarchical storage system employing the teachings of the present invention.
Figure 2 is a diagramatic showing of a disk storage apparatus and its constructional relationship to hash addressing in accordance with the invention as shown iIl Fig. l. ,~, Figures 3 and 4 diagramatically illustrate disk apparatus addressee distributions within an address space for a scatter index table for use in connection with the Figure l illustrated system.
Figure 5 is a map illustrating hash address distribution for a plural device embodiment of the Figure 1 illustrated system.
Flgure 6 is a logic diagram of a circuit for implementing the hash method and system in the Figure l illustrated system.
Figure 7 illustrates a directory construction and associated control circuits for implementing the invention shown in the Fiqure 1 illustrated system.
Figure 8 is a block diagram of a constructed ve.rsion of the present invention as illustrated in Figure l.
Figure 9 shows a data structure of a logical device control block used in connection with Fiqure 8.
Figure 10 is a logic flow diagram showing machine operations for avoiding hashing of sequential tracks within delay access boundaries in connection with the Figure 8 illustrated system.
S Figure 11 is a logic flow diagram showing an implementation of the inventive hashing method in a machine opera~ion sequence and system in the Fi~ure 8 illustrated ~mbodiment.
D tailed Description Referring now more particularly to the drawings, like numerals indicate like parts and structural reatures in the various diagrams. The present invention is preferably practiced in a hierarchical peripheral storage system lO, as shown in Figure l. A plurality of disk storage apparatus (direct access storage devices--DASD) ll (saparately enumerated as DO, D1, D2, ...) coupled to a shared cache 12 for transferring data to and from a host (not shown), such as a central processing unit or other computational facilities via input output connection 13. In a preferred mode, input output connection 13 is the input output connection used with the International Business Machines Corporation series 370 computers, no limitation thereto intended. Access to data or to data areas in either the cache 12 or DASDs ll is through address bus 14 which c:an be a portion of the inpu~ output connection 13 in the 370 series. A portion of the DASD addresses can be supplied over a bus indicated by dotted line 15 to actuate a pair o electronic swi'ches 16 and 18 whic:h respectively direct address signals and data signals through di'ferent paths of the system lO. Numeral 15 in a second embodiment can designate a separate peripheral command which actuates the switches 15 and 18. For example, a command may indicate that all data references are to be through cache 12, then switch 16 is set to the illustrated position.
On the other hand, a command may be received that all data references may be directed to DASDs ll which causes the switch 16 to be switched to the alternate position, i.e. connect DASDs 11 to bus 14. Other means of controlling switch 16 may also be employed.
The control indicated by numeral 15 also extends to switch 18 which either directs the DASD 11 connection to bus 21 for transferring data signals-to a host. Bus 2L in turn can be connected to input output connection 13, such connection is not shown. Bus 22 extends from switch 18 to cache i2 such that data can be transferred between DASD
11 and cache 12. System L0 further includes a control 20 which urther actuates electronic switch 18 such that the transfer of data.signals between DASD 11 and cache 12 car. be independent of and asynchronous to operation of the host. That is switch 18 position can be host directed or locally directed.
Assume that switch 16 is in the illustrated position.
DASD address signals on bus 14 are directed to old hash lS circuits 23 to determine whether or not a previous reference to cache 12 will enable access to cache 12 without hashing the address received on bus 14. Since DASD 11 has a large capacity for storing data and cache 12 has a lower capacity, all-be-it a significant capacity, hashing address techniques using the addresses of DASD 11 are used to determine whether or not space has been allocated in cache 12 for a data access or whether given data is in fact stored in cache 12. In any event, old hash circuit 23 upon detecting the occurrence of a previously closely rslated address, as later described, directly accesses scatter index table (SIT) 27 ~hich indexes the hash signal to directory 30 for accessing cache 12. LDCB 25, accessed via bus 24, contai~s the DASD address and the corresponding SIT 27 address.
Directory 30, as later described, contains one entr-i .~r each addressable segment of cache 12. Each entry will include an address indication for DASD 11 to indicate which data is replicated or cache space is allocated for cache 12. Since a hash class may consist of a plurality of directory 30 entries, a linking mechanism 31 links all of the entries in the same hash class 'ogether using a singly linked list. Once a directory entry is found that corresponds to the DASD 11 address, then cache 12 is accessed, via path 32, at the address indicated by directory 30. Then the data can be transferred directly between the.,host (not shown) and cache 12 via I10 connection 13. Of course, directory 30 may indicate a miss, i.e. no data space has been allocated in cache 12.
In this instance, actions beyond the present description of this figure are required.
In the event old hash circuit 23 indicates that the previous reference to cache 12 was not immediate but remote from the presently received DASD address; then the presently received address is supplied to hash c~rcuit 34 for the address hashing operation. As a result of the hashing operation, an address signal supplied over bus 35 identifies a given register in SIT
27. ~he contents of that register point to a directory 30 entry corresponding to a hash class. Then the directory 30 hash class is scanned as will be described.
In summary, access to cache 12 is via a set of DASD 11 address signals received on address bus 14 sent through old hash circuit 23 and then either through hash circuit 34 for a new hashing operation or directly to SIT 27 for generating an index or address signal for directory 30.
Directory 30 is then accessed for scanning the entries in tne hash class to look for a DASD 11 address corresponding to the received DASD address. On a hit or a favorable compare, cache 12 is accessed. Other~ise, a miss is indicated.
As mentloned, DASD 11 can be directly accessed. In this case, switch 1~ i5 to the alternate ~not shown) position, while switch 18 is also moved to its alternate position.
In this mode, access to data and access to data storage areas f~r recording on DAS~ 11 is as in any disk s-torage appara-tus system.
Upon a miss being indicated by directory 30, a control signal over b,us 33 to control 20 for actuating switch 18 to illustrated position for transferring data signals from an _ddressed ~ASD 11 corresponding to the received DASD 11 address signals for transferring data signals from such DASD over bus 22 to cache 12. Of course before such transfer can occur, DASD 11 has to be available, i.e. not busy, and the di.rectory 30 and hashing address must be setup such that access to cache 12 is enabled.
Figure 2 illustrates a general arrangement of DASD L1.
Generally each DAS device 11, such as D0, consists of a plurality of co-rotating dislcs 40, 41, each disk having a pair of surfaces for recording data signals. One of the surfaces of all of the surfaces in de-~ice D0 i5 reserved for positioning or servoing information. All of the tracks in a preferred form are concentric with all of the tracks being radially aligned with other tracks on other surfaces. For example, the two disks ~0 and 41. each have a radially outermost track 42, ~3 respectively. All of the trac}cs in the radially outermost position are termed cylinder 0 (C0). Since there is one head for each surface, when Lhe servo position (not shown) aligns the head (not shown) with the C0 tracks, then any surface can be accessed through electronic switching to access any track in C0. To access another cylinder, all of ~he heads (not shown) must be moved radially to the addressed ~U9&1011 i3 track, such as -the next innermost trac~s of cylinder Cl (not shown). This mechanical movement causes a substantial delay in accessing data areas and therefore is a significant delay access boundary. O~her cylinders, o which there may be over 500 cylinders in a single disk apparatus, include cylinder X having tracks 44 and 45 respectively on disks 41 and 40. In a similar manner, cylinder Y will have track 46 on disk 41, while disk 40 has a similar track.~In a similar manner, selecting DASD
11 devices requires substantial protocol and is also a delay access boundary.
All of the above characteristics are melded into the ` hashing method and system of the present invention in that a major factor in defining a hash class are the number of cylinders on each storage device. This results in a so-called cylinder ofset in the hash addressing.
All of the devices identified by device addresses have a balanced space assigned within the SIT 27 address space.
~ach hash class includes an address from each of the devices. In a small SIT 27, several cylinder address spaces from a siven de~ice may be within the same hash class, as will become more apparent. To further provide an ordered symmetry of hashiny, the devices are offset as a function of the address size of SIT 27, i.e. the number of registers therein. Therefore the total number of devices is an offset so that all addresses for all COs are never in the same hash class. Since C0 typically contains an index to data stored in the disk storage apparatus, it is a most commonly addressed cylinder. By keeping the most commonly addressed cylinder in different hash classes, the probability of a hash collision within the hashing operation is reduced. The adjacency of the tracks in the SIT 27 favors electronic switching between ~rac~s by relating the addresses of che tracks to adjacent registers of SIT 27. The offsets of cylinders an~ devices provide for an easy adjustment of the hashing algorit~ as the si~e of the cache 12 is varied or the size of SIT 27 is varled. It should be noted that when either cache 12 or SIT 27 is varied, all of the data in the cache lZ should be purged for data integrity purposes.
Figures 3 and 4 diagramatically show the SIT 27 address space as~extending from "0" thru "~" registers. The hashing algorithm enables all of the device addresses to be offset an identical amount from the base address "0"
of SIT 27. Eor example, in the address space 50 of Figure 3, fourteen devices (DASDs ll) are shown as having fourteen equally-spaced offsets 51. For example, device D0 has its cylinder "0" address at zero. Device Dl has its cylinder "0" address at N/14, device D2 has its cylinder "0" address at 2N/14. This means that each device DX will have a cflinder "0" indexed at SIT 27 a~dress NX divided by the number of devices.
~ccordingly, when 21 devices are installed in the system lO, the smaller offsets 52 result. Figure 3 shows all the devices 11 having an identical number of tracks.
This restriction is not necessary for practicing the present invention, even though it does simplify implementation. In Figure 4, the SIT 27 is divided into different offsets in accordance with the size or capacity in number of tracks of the various storage devices. For example, offsets 56 for larger devices are greater than offsets 5;. In a similar manner, of.~set 57 is for a yet larger device.
Figure 5 shows a map of how device addresses appear in SIT register addresses for aceessing directory 30. The separate device addresses are respectively setforth in columns 60, 61, 62, 63 for devices D0-D3 respectiveLy.
S The cylinder number C is indicated in the left hand column while the track number within the cylinder is indicated in the rlght-hand columns. As shown in ~igure 5, each cylinder has ten tracks, in a constructed embodiment ~ach cylinder had fifteen t^acks. The selection of ten is arbitrary and capricious and used for simplifying the illustration. The hash classes of the illustrated mapping of Figure 5 correspond to the rows of cylinder and track identifica~ions. For example, one hash class consists of address 660 of device D0, address 330 of device Dl and address 000 device D2 and no entry for device D3. For a small SIT 27, such a hash class could include one or more tracks from each of the devices. Cylinder C0 of device D0 is indicated by numeral 65 having tracks 00 thru 09. Cylinder Cl of device D0 also has tracXs 0 thru 9 whi~h in the illustrated embodiment are indicated by numbers 10 through 19. In a similar manner, all of the ~racks w-thin device D0 are identified wilh their respec'ive cylinders. For purposes of illustration, it is assumed that SIT 27 is relatively large such that one hash class includes only one track from a given device. In th-.s instance, device offset is three cylinders as indicated by a numeral 66; there is no overlap, i.e. there are relatively small devices with respect to the size of SIT
27. Cylinder C0 of device Dl appears at 67, while cylinder C0 of device D2 appears at 68. ~he ~-rangement is s~ch following the device distri~utior of ~igures 3 and 4 that none of the cylinders C0 of any device will share a hash class with any o'her cylinder C0 of another 18 v~
device. In device D2, numeral 70 identifies the three cylinder device offset while numeral 71 indicates empty space, i.e. that space in SIT 27 which contains no track addresses for device D2. On the other hand, for a small SIT 27 with respect to the size of DASDs 11, each hash class could include two tracks from each device, three tracks from each device and so forth. Still cylinder C0 of any device will never share a hash class from a cylinder C0~,of any other device. The principle is extended such that no like addressed cylinders are in the same hash class, i.e. cylinder X of D0 is always in a hash class different from cylinder X of any other device; X lS
an integer indicating a cylinder address.
Figure 6 is a logic diagram illustrating hash circuit 34.
Circuit 34 is an arithmetic circuit which results in an output at 84 with an SIr 27 register address which also identifies the hash class having a numerical value modulo the number of registers in SIT 27. Computation begins with the cylinder address C being supplied at 75 to binary multiplier 76, which multiplies it with the cylinder weight received at 77. Cylinder weight is the number of cylinders in the device. The resultant ?roduct is added in adder 78 to the track address H supplied over line 79. The product-sum is then supplied to modulo N
adder 80 wherein the product-sum is added to the device offset product constituting the device number D and device welght DW respectively received at 82 and 83.
Device weight i5 number of devices 11. The SIT 27 address signals at 84 access SIT 27 for fetching the directory 30 index to the hash class.
Figure 7 illustrates in more detail the hashing operation for system 10 shown in Figure 1. The device address ~HD (cylinder, head and device) are received via switch 16 into old hash circuit 23. In some addressing schemes a record R address can be also supplied which in the illustrated embodiment is not a part of the hashiny process because the entire contents of a track of DASD 11 can be transferred to cache 12. In the event that a record is separately addressable in DASD 11 then the record number R could be introduced into the hashing algorithm usi~g the inventive principles. In any event, the address CHD is supplied to comparator circuit 90 which compares the CH value of content of a register 91 selected by the D address signal supplied to registers 91 over bus 89. For a compare of C being equal, i.e. the track is in the same cylinder, compare circuit 90 supplies a difference signal to adder 92. The difference signal is the difference between the H value received from switch 1~ and the H value stored in register 91.
This difference value is added to the SIT address stored in the register 91 to generate a SIT address for CHD
without hashiny as described with respect to Figure 6.
This difference value plus the previous SIT address indicates the SIT 27 register containing the index to directory 30 for the track within the indicated cylinders. Accordingly, for all tracks within a cylinder, once a cylinder has been accessed, further hashing is not required whenever the hash result is temporarily saved. The sum of the old SI address plu5 the difference is supplied through OR circui-ts 93 to address SIT 27. The contents of the addressed SIT 27 register are supplied over bus 95 to address directory 30. When the contents of the SIT 27 register are 11 zeroes, a cache miss is indicated.
In the event compare circuit 90 indicates that a different cylinder is being accessed, then a new hash occurs. The address CHD is supplied over bus 96 to hash circuit 34; bus 96 leads to line 75 of Figure 6. Hash circuit 34 outputs a SIT 27 address over bus 35 through OR circui~s 93 to address SIT 27. Also, the newl~ hashed SIT value is supplled to the last 91 registe~ indica~ed by the D value supplied over bus 91 for addressing those registers. ,.
The directory 30 address signals on bus 95 select one of the entry registers 100 as the first entry of the hash class in directory 30. The accessed register supplies the DCH values over bus 101 to compare circuit 102. In the event the record value is also supplied for comparlson purposes, the record value in R section 111 of the directory 30 registers 100 is also supplied to compare circuit 102. The compare circuit 102 loo~s or equality between the DASD address stored in the directory 30 entry register lOC and the address received over bus 103. For a detected inequality, compare circuit 102 supplies an access signal over bus 106 to access HL
section 107. HL section 107 is a po_tion of a singly-linked list for indicating the address of the next register 100 containing an entry in the same hash class.
That nex' register ].00 is accessed as indicated by line 31. In the event HL section 107 indicates EOC (end of the chaln) a miss is indlcated over line 108 which cor.responds to line 33 of E'igure 1.
When compare circuit 102 indicates equality, a cache 12 hit is occuring. A signal supplied by com?are c -cuit 102 over line loa activates address generator 105 wr.ich takes the directory 30 address from bus 106 (access v;a TU~81011 bus 9S or through the HL section 107) and generates a cache 12 address based upon the directory 30 address.
Cache address is supplied over bus 32 for accessing cache 12. Generator 105 multiplies the register 100 offset address by a constant to calculate a cache 12 offset address. The constant is the ratio of number of bytes in an addressible segm~nt in cache 12 to the number of by~es in hash register 100. The cache 12 offset is then added to a cache L2 base address to obtain the cache 12 address. Instead of a calculation, the calculation result for each directory could be stored, either physically or logically with each directory entry.
Directory 30, in addition to containing the sections 101, 111 and 107, further includes an index 110 which is useful for identifying the directory entry. S section 112 contains the sector value of the record R, CCL
contains the logical cylinder number (such as provided for virtual disk on real disk) and FG 114 contains mis-cellaneous control flags not pertinent to an understanding of the invention. BP 115 and FP 115 are respectively backward and for~Jard pointers in an LRU
(least ecentiy used) list use in cormection with space management of cache 12, as is well known in the buffer management art.
Figure 8 illustrates a preferred implementation of the inverltion wherein two so called "strings" of DASDs 11 communicate with cache 12 and a host (not shown) via input-output connections 13. The input-ou'put connections are controlled through channel adaptors L20 separately denominated as CAA, CA3, C~C and CAD. I'hese channel adaptors employ the input-output connection TU9~1011 logic of design used with the aforementioned IBM 370 series computer. A computer or processor PROC 121 communicates with the host via charmel adaptors 120 through bus 122. For example, peripheral commands supplied by the host are transferred to PROC 121 via bus 122. PROC 121 in turn communicates over bus 123 with a so-called system storage 124. System storage 124 contains cache 12, the registers of directory 30 and the registers o,SIT 27. System storage 124 is preferably a 10 high speed random access memory of a semiconductor ty?e.
P.ll addrGssing is by base addresses plus offset or cache 12, SIT 27 and directory 30.
PROC 121 communicates with DASD 11 over bus 130 which extends to device adaptors 132, separately denominated 15 as OAA and DAB as well as to data flow circuits 131.
Device adaptors ~AA and DAB each respectively control and access one string of DASDs 11 and are constructed using known techniques. Data flow circuits 131 can include serializers; other circuits that are usually 20 found in connection with such circuits used with disk storage apparatus 3us 133 extends from ~a_a flow circuits 131 to channel adaptors 120 for providing direct access to DASDs 11. Bus 134 connects data flow circuits 131 to system storage ].29:, hence cache 12. ~3us 25 135 cormects system storage 1~4 to channel adaptors 120.
The functions of switch 16 of Figure 1 are performed in channel adaptors 120 using known electronic design techniques, while the functions of switch 18 are performed in data flow circuits 131.
30 :~ROC 121 has control storage i~O, a high speed -an~om access memory, which includes microcode type of com?uter programs for performing the hash circuit 34 functions as .
represented by program 34P. LDCB 25 registers are contained in control storage 140 at 25P. Other programs OP 141 provide for control of storage system 10 in the usual manner. Additionally, PROC 121 includes a plurality of high speed registers 142 for enhancing speed of microcode execution. Registers 142 constitute a scratch pad or work space for the processor. SIT
registers 143 contain one "page" of SIT 27 for processing by PROC 121"that is once the hash program 34P has been executed by PROC 121, a page of SIT 27 corresponding to one or more cylinders o hash are transferred to SIT
registers 143 such that the old hash 23 technique is expedited. Also, searching directory 30 results in a transfer of a page of directory entries to DIR REG 144 for similar rapid processing. In this manner, access to system st:orage 124 for control purposes is minimized to allow overlapping data processing signal transfers with control processing by PROC 121. Since there are four channel adaptors, four different operations can occur simultaneously. Further independent ree standing operations by DASD 11 can be occurring, therefore PROC
121 should be able to do p~ocessing indeoendent of system storage 124 as much as possi~le. Operation of the invention in the Figure 8 environment ls better understood by referring to Figures 9, 10 and 11. It is understood with respect to ~hose figures that PROC 121 ?rograms OP 141 including the usual idle scan or dispatching f~lnctions well known in the progra~ning and data processing arts.
LDCB registers 25P shown in Fi~u-e 9 contain the DASD 11 addresses associated with a particular cache 12 access.
For example, seek address 150 defines the cylinder while SID address and sector sections 151 and 152 identify which track and the portion of the track to be accessed in DASD 11. Index 153 corresponds to index 110 of Figure 7. Cache address 154 is the cache address generated by address circuits 105 as well as OP 141. SEQ bit 155 signals that a succession of consecutively addressed bLocks will be transferred in a so-called "sequential mode". SEQ 155 is set via a mode set command received from a host (not shown) signiyiny type of operations to be performed,~y syst~m 10. Numeral 156 denotes that LDCB
25 may contain additional entries not pertinent to an understa!~ding of the present invention.
Referring next to Figure 10, the old hash unction as performed by hash circuit 23 or by program OH 23P of Figure 8 are detailed in this machine operation flow lS chart. Initiation of the machiIle operations occurs at 160 which corresponds in Figure 1 to the output of switch 16 and to the activation of OH 23P of Figure 8. The first step is to access LDCB 25 to determine if SEO 155 is set for indicating a sequential mode. That is, there is a high proba'oility that a block of data residing in the same cylinder or in an i~media~ely adjacent track as the immediately preceding block will be accessed~ In the present implementation, only those addresses used during the sequential mode use the old hash principle. For a non-sequential mode, the hash operation pe-formed by circuit 34 or program 34P is activated via logic path 200 and as detailed at the machine operation level in Fiyure 11. For the sequential mode at step 161, processor 121 transfers the received address RDC~ for Ihe record R lnto an lnternal register IR (not shown). A. 163 processor 121 compares the received address RDCH to the pe-mitted e,xtent of addressing ~or the address via channel ada?tor 120, that is, a host (not shown) can send a so-called "define extent" command which sets the limits of access for a given channel path including a given channel adaptor 120. If the address RDCH is outside of the defined address space or extent, processor 121 follows logic path 164 to report an error condition to the host (not shown). Otherwise, at 166, processor 121 compares the received RDCH with the contents of the last registers 91, which in Figure 8 are some of the registers 142. In the illustra$ed embodiment, if the difference between the received address RDCH and the las~ address in register 91 is greater than unity, then hash function is activated via logic path 200. When the track addresses H
di~fer by one, one is added to the last register ~1 contents, independent of cylinder boundaries, to increment. or d~crement the SIT 27 address by unity. The adjacent SIT 27 register is read out to access directory 30 without hashing. In the se~uential mode only one hash operation may be necessary to access a plurality of data blocks from cache 12.
In an alternative embodiment, compare step 165 makes a compare to determine whether or not the received address RDCH is within the same cylinder as the address stored in last register 91. If so, the difference between the received address and the stored address will lndicate the offset address of the SIT 27 registers containing the pointer corresponding to the received RDCH and the address stored in last register 91. This difference then can be added~subtracted from the value in the last register to obtain the SIT 27 register for indexing into directory 30.
In the present embodiment, promo' on of da.a to cache before it is needed was limited to that data res ding in 6~
a given cylinder, i.e. residing within a given set of delay boundaries. No limitation to this implementatlon is intended in the practice of the present invention. At 170 the cylinder boundari~s are checked to see i' _he received address RDCH is in the same cylinder as the last address in register 91. If it is outside of the cylinder, processor 121 at 171 follows Logic path 1,2 to report a miss, i.e. it ~nows the data has not been promoted in~o cache, 12. On the other hand, when the received address R~CH is in the same cylinder as 'he address stored in last register 91, at 173 the directory 30 address is fetched from SIT 27 and a search for the hash class as described is conducted. Upon completion of the search, processor 121 at 174 determlnes whether the data has been identified as residing in cache 30. For example, if the SIT 27 entry was all zeros, then a miss is indlcated immediately. Otherwise, the hash class of directory 30 is searched in a sequential manner. For a miss, normal allocation and data promotion procedures are followed. For a hit, processor 121 at 175 determines whether or not the data is pinned or bound to cache 30.
Pinning or binding indicates that the data must remain in cache 30 until unpinned or unbound, i;e. it is not subject to a replacement algorithm. For plnned data, logic step 180 is followed to access the data frorn cach~
12 or to prepare for storing data in cache 12.
Otherwise, at 176 the record is made most recently used ln the replacement algorithm LRU (least recently used);
then loglc path 180 is followed.
Figure 11 illustrates operation o,~ hash microcode 34 After the old hash opera..ion 23 ndicating an out o' cylinder access, PROC 121 follows logic path 200 ~o'~ox 201 to take the address DCH from LDCB 25P and place _he ~U981011 address into registers 142. Steps 202 and 203 constitute the functions corresponding to hash circuit 34. Step 202 generates the address of SIT 27 and stores it into one of the registers L42 using the ec~ation setforth in the box 202. Note that the value is twice the modulus o SIT 27, i.e. 2N rather than N. AT 203 the hash offset (HO) is made e~lal to contents of -the one register 142 whi'e the hash cylinder is the value of the contents of the one register 142,divide~ by two. Then at 204, the contents of SIT 27 contain in system storage 12~ which contains the regi;ters identified by HO and HC are transferred to SIT register 143. At 205, the SIT register 143 corresponding to HC is read out for obtaining the pointer to the entry in directory 30 which contains the entry corresponding to the hash value. Then beginning at 217, directory 30 is searched within a search loop 210. End of chain (end of hash class) is always checked at 217; if SIT has a zero entry, EOC is also indicated at 217.
Searching directory 30 within a given hash class reauires a transfer of directory 30 portion to directory regis~er 144. This transfer s implied in cirec~ory 30 search loop 210. This loop corresponds to the Fisure 7 illustra~ion including compare circuit 102. At 211 the directory 30 entry is read and transferred ~o register 144. At 212, the value of the DASD address, DCH, contained in the directory entry, is ~ompared with the DCH value received from the host and stored in register la2 at step 201. When there is a non--compare, ,he scan must continue; PROC 121 follows logic path 215 to read the ~ink pointer, HL 107, for identifyiny the next directory 30 entry to be examined. At 217, the contents of the link pointer are exam ned to determine whether or not it is the end of the chain (~OC). I it is the end of ~U981011 ~. ~, 28 ~ 3 the chain, a cache miss has occurred and a miss flag in registers 142 is set at 218 for later use by PROC 121.
The program is exited at 214 for further processlng of command execution as is known in the data processing art.
In the event that the hash class does not inish at 217, steps 211 and 212 are repeated. The loop continues until either a miss occurs or a hit is indicated at 212.
For a cache ~it, PROC 121 follows logic path 104 (also Fig. to 7) step 213 for generating the cache address.
10 Step 213 corresponds to address generator 105. The cache address is generated based upon the address of the directory 30 register entry in register 144 as modified ` in a predetermined manner for generating the cache address or fetching the cache address from the directory 43 entry. That is, there is one directory 30 entry for each addressable segment of cache 12. Accordingly, the spatial relationship can be established. The index 110 is then set into index 153 of LDCB 25P. A flag (not shown) called hit in register 142 is also set and the L~U
list is updated by adiusting the backward and forward poin~e-s 115 and 116 to make ~he just-identi'ied segment of cache 12 the most-recently used. Updating LRU lists are well known and not described for that reason. The received address RDCH and the SIT 27 address are stored in last re~isters 91.
While the invention has been ~articular].y shown and described with reference to the preferred embodimen~s thereof, it will be unders~ood by those skilled in the art that various parting from the spirit an scope of ~he invention.
TUa81011
Claims (12)
1. The method of indirectly addressing a buffer memory having a plurality of addressable buffer segments and being operatively relatable to a backing memory having a larger plurality of like-sized addressable memory segments distributed among a first plurality of addressable units;
the machine-implemented steps of:
establishing a directory with entries for respectively identifying said buffer segments for individually addressing same including link elements for linking entries into address classes;
establishing and maintaining a scatter index table (SIT) for containing signals stored in a given member of addressable fields for pointing to said linked entries, one signal pointer for each of said address classes, in each of said addressable fields;
sequentially addressing said SIT fields for accessing said signal pointers to adjacently addressable memory segments stored in said buffer segments; and addressing said SIT for accessing said buffer segments related to corresponding ones of said memory segments in diverse ones of said addressable units in fields separated by a quotient number of said given number divided by said first plurality.
the machine-implemented steps of:
establishing a directory with entries for respectively identifying said buffer segments for individually addressing same including link elements for linking entries into address classes;
establishing and maintaining a scatter index table (SIT) for containing signals stored in a given member of addressable fields for pointing to said linked entries, one signal pointer for each of said address classes, in each of said addressable fields;
sequentially addressing said SIT fields for accessing said signal pointers to adjacently addressable memory segments stored in said buffer segments; and addressing said SIT for accessing said buffer segments related to corresponding ones of said memory segments in diverse ones of said addressable units in fields separated by a quotient number of said given number divided by said first plurality.
2. The method set forth in claim 1 wherein said memory segments are grouped into cylinders, each cylinder having a plurality of said memory segments and any change in memory segment accessing from one cylinder to another cylinder being an accessed delay boundary; and maintaining all of the addresses of said memory segments within a given cylinder to be sequential ones of said address classes.
3. The method set forth in claim 1 wherein said memory segments are grouped into cylinders of such segments with an access delay occurring in accessing the memory segment in one cylinder then accessing a second memory segment in another cylinder; and addressing cylinders within ones of said addressable units being like addresses and keeping all like addressed cylinders in different ones of said address classes
4. The method set forth in claim 2 wherein said memory segments are grouped into cylinders of such segments with an access delay occurring in accessing the memory segment in one cylinder then accessing a second memory seyment in another cylinder; and addressing cylinders within ones of said addressable units being like addresses and keeping all like addressed cylinders in different ones of said address classes.
5. The method set forth in claim 3 or 4 further including the step o:f saving the address class of the last accessed buffer segment; and receiving an address for accessing a memory segment, if said received memory segment address is within a same cylinder as a previously received address; modify said address class by the increment between the previous and newly received addresses and accessing said SIT in accordance with said modified address class; otherwise hashing a new address.
6. The method set Forth in claim 1 wherein said SIT
addressing includes multiplying a cylinder address by a cylinder weight equal to the number of cylinders in a device to yield a. cylinder product;
summing the cylinder products with a memory segment address; and summing said sum with the product of an addressable unit address as modified by the number of addressable units.
addressing includes multiplying a cylinder address by a cylinder weight equal to the number of cylinders in a device to yield a. cylinder product;
summing the cylinder products with a memory segment address; and summing said sum with the product of an addressable unit address as modified by the number of addressable units.
7. The method of evenly distributing addressing of a buffer store for a backing store having a hierarchy of addressing levels; a first-level including a plurality of addresses and each of the first-level addresses enabling access to a plurality of sequential addresses in a second- level of addressing, and wherein the buffer store is accessed based upon converting said backing store hierarchical addresses to first predetermined changeable and arbitrary buffer store addresses, the number of said buffer store addresses being fewer than the number of said hierarchical addresses; a directory containing said buffer store and corresponding hierarchical addresses of data stored in said buffer store, the automatic steps of:
arranging said hierarchical addresses into a given number of address classes wherein each class includes different ones of said sequential addresses from each address in said first addressing level;
generating an index -to said directory for buffer addresses from said hierarchical addresses wherein each index corresponds to a one of said address classes such that each index for an address in said second-level accessed via a first first-level address being offset from an identical second- level address, wherein said offset is greater -than zero, accessed via a second first-level address in accordance with a predetermined arithmetical relationship between the values of said first and second first-level addresses, modulo said given number; and accessing said directory in accordance with said index to fetch an address of said buffer store
arranging said hierarchical addresses into a given number of address classes wherein each class includes different ones of said sequential addresses from each address in said first addressing level;
generating an index -to said directory for buffer addresses from said hierarchical addresses wherein each index corresponds to a one of said address classes such that each index for an address in said second-level accessed via a first first-level address being offset from an identical second- level address, wherein said offset is greater -than zero, accessed via a second first-level address in accordance with a predetermined arithmetical relationship between the values of said first and second first-level addresses, modulo said given number; and accessing said directory in accordance with said index to fetch an address of said buffer store
8. The method set forth in claim 7 wherein said first- level of addresses are addresses for direct access storage devices (DASD) with access between diverse ones of said DASD constituting a first delay boundary; and said second-level addresses being cylinder addresses within each of said DASDs with accesses between diverse ones of said cylinders being a second access delay boundary and a third level of addresses being within each cylinder with no substantial access delays and keeping the sequential addresses of said third level in a sequence corresponding to successive ones of said indices.
9. The method set forth in claims 7 or 8 wherein each second-level address relates to a plurality of third-level addresses;
further including the steps of:
multiplying the first-level address by a number representing the number of addresses within the first level to form an offset product, multiplying the second-level address by the total number of second level aaddresses to provide a cylinder product, summing the third-level address with the cylinder product and the offset product to provide a hash class indication; and limiting said hash class indication to modulo said given number.
10. In an addressing apparatus for a buffer memory having addressable buffer segments serving as a buffer to a backing store having a plurality of addressable units, each unit having a plurality of addressable memory segments, said addressing apparatus being responsive to a backing store address to address said buffer segments the improvement comprising:
a directory unit means for containing addresses of said buffer segments storing signals relating to said memory segments together with the unit and memory segment addresses, and having a plurality of addressable entry means respectively, and having a given plurality of link means in said plurality of addressable entry means respectively for indicating address classes of said memory segments;
an index table means having plurality of addressable registers for containing an address of respective ones of said link means whereby a one of said entry means having a one of said link means can be addressed via said index table means within an address space having sequential addresses from a base address through a limit address for a given number of addresses;
further including the steps of:
multiplying the first-level address by a number representing the number of addresses within the first level to form an offset product, multiplying the second-level address by the total number of second level aaddresses to provide a cylinder product, summing the third-level address with the cylinder product and the offset product to provide a hash class indication; and limiting said hash class indication to modulo said given number.
10. In an addressing apparatus for a buffer memory having addressable buffer segments serving as a buffer to a backing store having a plurality of addressable units, each unit having a plurality of addressable memory segments, said addressing apparatus being responsive to a backing store address to address said buffer segments the improvement comprising:
a directory unit means for containing addresses of said buffer segments storing signals relating to said memory segments together with the unit and memory segment addresses, and having a plurality of addressable entry means respectively, and having a given plurality of link means in said plurality of addressable entry means respectively for indicating address classes of said memory segments;
an index table means having plurality of addressable registers for containing an address of respective ones of said link means whereby a one of said entry means having a one of said link means can be addressed via said index table means within an address space having sequential addresses from a base address through a limit address for a given number of addresses;
10. (continued) index table address generating means for receiving said backing store addresses, including unit and segment addresses and being responsive to receipt of anyone of said backing store addresses to supply an index table means register address having an address offset from said base address in accordance with said received unit address as modified in a predetermined manner by a combination of said given number with a number of said addressable units and having an address displacement from said address offset equal to said memory segment address, said generated address having an address value modulo said given number;
means responsive to said generated address to address said directory unit means at an entry address indicated by the contents of said index table means register indicated by said generated address; and compare means receiving said received backing store address and said stored signals in said directory unit means addressed entry to determine the address of said buffer segment, if any, that relates to the addressed memory segment 11. In a peripheral storage system having a plurality of direct access storage devices (DASD), each DASD
having a plurality of cylinders with access between diverse cylinders crossing an access delay boundary, each cylinder having a plurality of addressable DASD
segments, a high speed random access buffer having a plurality of addressable buffer segments having the same size as said DASD segments and means for transferring signals between said DASDs and said buffer, a programmed digital processor having a central store and connected to all of the units in said storage system for operating same in accordance with a program of instructions stored in a control store;
directory means operatively associated with said processor and said buffer for storing electrical indications of data stored in said buffer by storing in separate respective entries the buffer segment address having data stored therein associated with a respective DASD address together with a link indicator for linking entries within the directory means corresponding to a given class of DASD addresses, respectively;
Scatter Index Table (SIT) means having an address space modulo in given number of registers each for storing electrical indications of a respective one of said address classes such that the directory means entry storing a DASD address in the address class is identified by the stored electrical indications in said SIT means, said SIT means being operatively associated with said directory means and said processor;
means responsive to said generated address to address said directory unit means at an entry address indicated by the contents of said index table means register indicated by said generated address; and compare means receiving said received backing store address and said stored signals in said directory unit means addressed entry to determine the address of said buffer segment, if any, that relates to the addressed memory segment 11. In a peripheral storage system having a plurality of direct access storage devices (DASD), each DASD
having a plurality of cylinders with access between diverse cylinders crossing an access delay boundary, each cylinder having a plurality of addressable DASD
segments, a high speed random access buffer having a plurality of addressable buffer segments having the same size as said DASD segments and means for transferring signals between said DASDs and said buffer, a programmed digital processor having a central store and connected to all of the units in said storage system for operating same in accordance with a program of instructions stored in a control store;
directory means operatively associated with said processor and said buffer for storing electrical indications of data stored in said buffer by storing in separate respective entries the buffer segment address having data stored therein associated with a respective DASD address together with a link indicator for linking entries within the directory means corresponding to a given class of DASD addresses, respectively;
Scatter Index Table (SIT) means having an address space modulo in given number of registers each for storing electrical indications of a respective one of said address classes such that the directory means entry storing a DASD address in the address class is identified by the stored electrical indications in said SIT means, said SIT means being operatively associated with said directory means and said processor;
11. (continued) said control store including a buffer-address-generating control program for enabling the processor to access said SIT means for indirectly accessing the directory means -to address said buffer;
and said control program including control program portions for respectively enabling said processor to generate an address class indication modulo the given number including the steps of taking the DASD address and multiplying same by the number of devices to generate an offset product, taking the number of cylinders and multiplying it by the cylinder address to generate a cylinder product and then summing the cylinder product, the offset product and the memory segment address, modulo said given number to generate the address class and further for accessing said SIT
means and said directory means and said buffer using said address class.
12. In accordance with claim 1, the machine-implemented method of accessing a buffer memory having a plurality of addressable buffer segments operatively coupled to a backing memory having a first plurality of addressable units and each of said addressable units having a second plurality of addressable memory segments, said buffer segments having the same signal-storage capability as said memory segments, said memory segments in the various addressable units being addressable by a same memory address such that like-addressed memory segments are correspondingly- addressed segments; said memory segments being grouped into addressable cylinders of said memory segments, each unit having a certain number of cylinders, the automatic steps of:
arranging the addresses of said memory segments into a staggered array of addresses by unit within a limited address space extending from a base address through a limit address such that said memory segment addresses of each unit begin at a respective address displacement from said base address and continue sequentially in said address space in a wrap around fashion such that predetermined ones of like-addressed memory segments of said addressable units do not share an address in said address space;
receiving an access address of a given memory segment of a given addressable unit;
and said control program including control program portions for respectively enabling said processor to generate an address class indication modulo the given number including the steps of taking the DASD address and multiplying same by the number of devices to generate an offset product, taking the number of cylinders and multiplying it by the cylinder address to generate a cylinder product and then summing the cylinder product, the offset product and the memory segment address, modulo said given number to generate the address class and further for accessing said SIT
means and said directory means and said buffer using said address class.
12. In accordance with claim 1, the machine-implemented method of accessing a buffer memory having a plurality of addressable buffer segments operatively coupled to a backing memory having a first plurality of addressable units and each of said addressable units having a second plurality of addressable memory segments, said buffer segments having the same signal-storage capability as said memory segments, said memory segments in the various addressable units being addressable by a same memory address such that like-addressed memory segments are correspondingly- addressed segments; said memory segments being grouped into addressable cylinders of said memory segments, each unit having a certain number of cylinders, the automatic steps of:
arranging the addresses of said memory segments into a staggered array of addresses by unit within a limited address space extending from a base address through a limit address such that said memory segment addresses of each unit begin at a respective address displacement from said base address and continue sequentially in said address space in a wrap around fashion such that predetermined ones of like-addressed memory segments of said addressable units do not share an address in said address space;
receiving an access address of a given memory segment of a given addressable unit;
12. (continued) generating an address within said limited address space from said access address which is the sum, modulo said limited address space, of the memory segment address and the product of the device address multiplied by the number of devices and the product of the cylinder address multiplied by said certain number.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US293,648 | 1981-08-17 | ||
| US06/293,648 US4464713A (en) | 1981-08-17 | 1981-08-17 | Method and apparatus for converting addresses of a backing store having addressable data storage devices for accessing a cache attached to the backing store |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1180463A true CA1180463A (en) | 1985-01-02 |
Family
ID=23129946
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000406399A Expired CA1180463A (en) | 1981-08-17 | 1982-06-30 | Method and apparatus for hashing cache addresses in a cached disk storage system |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4464713A (en) |
| EP (1) | EP0072413B1 (en) |
| JP (1) | JPS5831460A (en) |
| AU (1) | AU552368B2 (en) |
| CA (1) | CA1180463A (en) |
| DE (1) | DE3278444D1 (en) |
| ES (1) | ES8305963A1 (en) |
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-
1981
- 1981-08-17 US US06/293,648 patent/US4464713A/en not_active Expired - Lifetime
-
1982
- 1982-06-29 DE DE8282105765T patent/DE3278444D1/en not_active Expired
- 1982-06-29 EP EP82105765A patent/EP0072413B1/en not_active Expired
- 1982-06-30 CA CA000406399A patent/CA1180463A/en not_active Expired
- 1982-07-08 JP JP57117886A patent/JPS5831460A/en active Granted
- 1982-07-16 AU AU86111/82A patent/AU552368B2/en not_active Ceased
- 1982-08-16 ES ES514998A patent/ES8305963A1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| ES514998A0 (en) | 1983-04-16 |
| JPS5831460A (en) | 1983-02-24 |
| EP0072413A3 (en) | 1985-01-23 |
| JPH0247775B2 (en) | 1990-10-22 |
| AU8611182A (en) | 1983-02-24 |
| EP0072413B1 (en) | 1988-05-04 |
| AU552368B2 (en) | 1986-05-29 |
| DE3278444D1 (en) | 1988-06-09 |
| ES8305963A1 (en) | 1983-04-16 |
| US4464713A (en) | 1984-08-07 |
| EP0072413A2 (en) | 1983-02-23 |
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