CA1191617A - Automatic calling unit control system - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
AUTOMATIC CALLING UNIT CONTROL SYSTEM

In a data communications system where a plurality of line adapters connect to remote peripheral units there is provided a control system for controlling selected Automatic Calling Units which can dial connection lines to remote peripherals or systems. A microprocessor having output control registers can select specific line adapters having an ACU-output register. It can then load dialing-digit data and ON/OFF control data into the ACU-output register for controlling the associated Automatic Calling Unit.

Description

AUTOMATIC CALLING UNIT CONTROL SYSTEM

FIELD OF THE INVENTION
This disclosure relates to data-comm systems using multiple line adapters, each of which handles a separate communica~ion line to a data terminal.
Several patents form a background and explanation for microprocessors used with the line adapters of this disclosure. These patents are:-.~ .

U.S. Patent 4,293,909 entitled 'IDigital System For Data Transfer Using Universal Input-Output Microprocessor", U.S. Patent 4,291,372 entitled "Microprocessor System with Special;zed Instruction Format", U.S. Patent 4,292,667 entitled "Microprocessor System Facilitating Repetition of Instructions".
U.S. Patent 4,18~,769 entitled "Input-Output Subsystem for Digital Data Processing System".
SUMMARY OF THE INVENTION
A group of line adapters used in a data com~unications system are organized to work with a microprocessor. The microprocessor provides control signals wh;ch permit seleetion of specified line adapters and selection and control of components in each of the line adapters. Each line adapter is connected to i~s own Automatic Calling Unit which can establish telephone line connections by its capahility of dialing phone numbers digitally. The microprocessor includes Output Control Registers which provides control signals to any one of a selected group of ACU-Output Registers. The ACU-Outpu~
Registers can be controlled to transmit dial digit da~a and special function control data to control operation of the Automatic Calling Unit connected to it. A combination of PUT operators and address signals from the microprocessor will select a desired ACU-Output Register to receive dial data and control signal data which will then be loaded into the desired Automatic Calling Unit.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic drawing of a data-comm I/O
subsystem with slide-in cards fitting into a base module backplane and having frontplane connections therebetween.
FIG. 2 is a block diagram of a multiple line adapter card.

6~7 FIG. 3 is a block diagram of the state machine processor which controls operations of the line adapter.
FIG. 4 is a block diagram of a single byte-oriented line adapter.
FIG. 5 is a drawing of logic circuitry used to select memory or other components for a given line adapter, FIG. 6 is a schematic drawing of the circuitry for iden~ifying a line adapter or its sub-components.
FIG. 7 is a timing diagram for dialing an lo Automatic Calling Unit (ACU).
FIG. 8a is a drawing showing the circuitry for addressing and loading of a selected ACU-Output Register.
FIG. 8b is a timing diagram showing the sequence of operatlons.
DESCRIPTION OP PREFERXED_EMBO~IMENT
lS T~e line adapter selection means of the present disclosure is designed to be used as part of a line suppor~
processor (also often called a frame recognition-data link processor) as part of a data comm I/O subsystem~
FIG. 1 sho~s such a data comm I/O subsystem wherein a state machine processor card 600 works in coordination with various types of line adapters. A single line adapter card 700 may be used as ~ell as Quad line adapters such as that shown in cards 400 and 500. These Quad line adapters constitute ~nits of four addressable line adapters, and each line adapter can h~ndle a single data communications line terminal through an electric interface.
FIG. 4 shows a bloc~ diagram of a "Single" byte oriented line adapter system. A remote data set or data input output terminal may be connected to input-output circuit means which includes timer 507 and USART 508.
This input-output circuit connects to a transceiver bus-controller 503 which can route the data to a multiplexor 504 for conveyance along I/O bus 10 to the state machine processor 600 or into a RAM buffer 5SOm.

Data i~ the sta~e mac~ine processor can be routed from the state machine's output control register 38 (FI~. 3) along bus 172 into the tr~nsceiver bus controller 503 for transmission to the input-outpu~ circ~it means. The multiplexor 504 receives control signals from the data link interf2ce unit 700 of FIG. 1 in addition to other control signals which identify units within the line adapter system. Also provided is an automatic calling unit output register 505 which can receive signals useful for dialing remo~e ~erminals on telephone lines.
FIG. 2 is a block diagram of a "Quad" Line Adapter used for byt~ oriented protocol operations. The input-output circuit means which connect to remote termi~als îs composed of four basic units such as 507, 5~8 (timer 0 and USART 0). Likewise, input-output service to a remote terminal is provided by timer 509 and USART 1 desig~ated 510. Likewise, units 511, 512 constitute an operating unlt for another remote terminal as do units 513 and 514 for yet another remote terminal.
As d~scussed under FIG. 4, t~e Line Adapter uses a trans eiver bus controller 503 and a set of multiplexors 504 and 506. It should be noted that the multiplexors such as 504 and 506 are in essence "dual" operating multiplexor sets in that they receive control signals from two different input-output units. Mul~iplexor 504 receives input signals from Line Adapters 0 and 1 while multiplexor 506 receives input signals from Line Adapters 2 and 3 of FIG. 2.
Corresponding to the Automatic Calling Unit Output Register o FIG. 4, the Quad Line Adapter of FIG. 2 uses 4 such ACU output registers. Also in the Quad L~ne Adapter ( FIG o 2 ) there is provided an extra set of RAM
buffer memories designated 550~1 and 550m2.

- s -FIG. 3 is a block diagsam of the State Machine Microprocessor which is used to control the single line adapter or multiple conflgurations of line adapters. The 5t~te Machine Processor (some~imes designa~ed as UI0 State Machine) resides on a circui~ board of C~ip5 which can be in~erted as a slide~in card into the base module (FIG. 1) where it connects to the backplane~ The State Machinc connects to the application dependent logic thrcugh the rontplane connectors as se n in FIG. 1.
A detailed description of the elements and use of the ~IQ State Machine has been the subjeet of several prior paten~s.
These pa~ents are:
U.S7 ~at@nt 4~293,909 entitled "~igital System For Data rransfer Usiag Universal Input-aueput Microprocessor", inventors Robert D. Ca~iller and Brian K.
For~s.
UOS. Patent.4,291,372 entitled "Microprocessor System ~ith Specialized Instructlon FormaE't, inventors 8rian K. Forbes and Robert D. Ca~iller.
U.S. Paten 4,292,667 entitled "Microprocessor System Facilitating ~epeei~ion of Instructions", inventors Robert D. Caeiller an~ Brian K. Forbes.
The use of a host computer wor~ing in conjunction with an I/0 subsys~em which uses peculiar co~mands c~lled I~0 descriptors~ data link descriptors, and resule descriptoTs is sho~n in U.S. Patent 4,189,769, February 19, 1980, to Dar~en J~ Cook and Donald A. Millers, II, and entitled "Ir~pue-Output Subsystem for Digital Data Processing System".

FIG. 5 is a diagram of rertain logic on the DLI /LA
card 700 which is used to select or "I)esignate" the RAM
buffer memory of the single Line Adapter card or a selected memory of ~ specific one of the four line adap~er memories on the Quad line adapter card. Shown as RAM storage means 550m in FIG. 5 is the particular memory used for the single Line Adapter. However, in the "multiple" Line Adapter situation, each Line Adapter has a similar selection system for selecting the particular memory associated with that Line Adapter, as seen in FIG. 2 with local RAM memory 550ml, 55m2~
In FIG. 5, address lines from the State Machine Processor (MADD~nn~ connect to a comparator 100c and also ~o the RAM buffer 550m~ A chip select signal CS/ is activated to the buffer memory 550m by means of logic signals from the ~omparator 100c and ~he Designate Flip-Flop (DESF). A unique jumper bit provides input to ~he Design~e Flip-Flop from ~he I/O bus 10 in order to particularly identify any given selected buffer memory in the systemO The particular bit line of the I/O bus 10, which is to be chosen, is se~ by the State Machine Microprocessor 600 of FI~. 3.
"BYTE ORIENTED" LINE ADAPTER
A functional section of the Line Support Processor (also called the Frame Recognition-Data Link Processor and/or Line Support Processor-DLP) is the Line Adapter called the "Byte Oriented Line Ad~pter".
This is sometimes also called a "Charac~er Oriented Line Adapter.

The data comm Line Adapter is basically a device which in~erfaces on one end to a data communication line "electrical interface",`and on ~he other end interfaces to a processor which has been designated as the UIO State Machine 600 (UIOSM). The primary function of t~e Line Adapter is to serialize "bit" information to/from "byte" information, to provide timing, to generate service requests, to supply a RAM memory, to provide automatic calling interfacing and to provide connection to level c~angers ~hich will match ~he da~a communication lines.
The Byte-Oriented Line Adapter is also buil~ in two basic configurations designated as (i) Quad Line Adapter and (ii) the Single Line Atapter. The Single Line Adapter is part of the Line Support Processor and the Single Line Adapter shares the same board with the Data Link Interface (DLI) circuitry. The Line Adapter is required regardless of the quantity of lines controlled by the Line Support Processor. The Quad Line Adapter contains essentially four (4) Line Adapters on one board. These boards are typical 10 inch by 13 inch boards which plug into the backplane of the Base Connection Module (FIG. 1).

As seen in FIG. 1 each of the Line Adapter cards 4003 500 connect both to the State Machine Processor 600 and to the DLI/LA 700 (Data Link Interface-Single Line Adapter).
As seen in FIGS. 2 and 4, connection to the data communications line is through an electrical interface (EI) which connects to the Line Adapter. There are various types of electrical interface boards which exist and which may be mounted in different combinations on the Quad Line Adapters. Thus, depending on the electrical characteristics of the data comm line, the only change required is that of the electrical interface, while the Line Adapter remains as is.
~ From one to 16 Line Adapters may variously be addressed by the State Machine Processor 600; thus, each Line Adapter is jumpered uniquely in order to identify its address. The Line Adapter must be "designated" for the State Machine Processor to communicate with it. Several addressable components are contained on a Line Adapter which the State Machine Processor may communicate with, in 30 the form of Write/Read data or "Status" or "Control"
signals.

The addressabl2 components of ~he Byte Oriented Line Adapter are:
~i) USART (508,510, 512, 514, FIG. 2) (ii) Timer (507,509, 511, 513, FIG. 2) (ili) Au~o Call Output Registers (5050, 5051, 5052, 5053).
(iv) Auto Call Status for each ACU
(ACUo, ACUl, ACU2, ACU3).
(v) Component Requestors (units within USART's and Timers) (vi) Memory (RAM) (single card LA RAM or Quad Card LA R~M).
The USART (Universal Synchronous/Asynehronous Receiver/Transmitter) accepts data "bytes" from the State Machine Processor 600 and converts them i~to serial "bits" for transmission; it also receives serial bit data and converts this to parallel data bytes. The USART
device is initialized by writing into its two internal eontrol registers ~hich specify the manner in which it operates.
A typical USART preferred for this purpose i~
manufactured by ~estern Digital Corpora~ion, 3128 Redhill Avenue, Newport Be~ch, California 92663, and is designated as UC1671 and descri~ed in a Technical Manual dated August 1978 as UC1671 Asynchronous/Synchronous Receiver/
Transmitter.
Various bits of the internal control registers of this USART unit speeify such things as: synchronous/
asynchronous mode; bits per charaoter; parity; baud rate;
~ransparent mode; Echo mode. The Timer used on the Byte Oriented Line Adapter serves two basic functions: (i) as program tlmers and (ii) as baud rate generators for asynchronous operation. Three independent internal timers _ 9 _ are contained in each chip~ ~wo of whieh are used by the software for timing purposes relative to the line opera~ions for "transmit" and for "receive" operation. The third timer is used to genera~e a square wave clock which is used by the USART for asynchronous operation. Each timer is initialized independentlyg which indicates the "mode" in which it is to operate. The two program timers are capable of activating a Flag signal to the State Machine Processor 600 when a pre determined timing value has been reached.
The ~uto Call Output Register, FIG. 2, (ACUOR 505) i5 a register which is loaded by the State Machine Processor with "dial digi~" and control information. The output of this register drives level-changer chips which conver~ the logic signals to EIA RS-232 voltages. These signals drive an automatic calling unit (ACU) such 2S a Bell 801, which provides dial-out capabilities.
Auto Call Status (ACUSTO, ACUSTl, ACUST3, of FIG. 2) i~s aL means of providing the condition or state o~
input llnes from the automatic calling unit (AGU) to ~he State Machine Processor 600. Lines from the ACU are recei ved by level-changer chips which convert the EIA
voltages to TTL logic levels. These logic levels may be re~d by the State Machine Processor ~o determine the pres~nt status.
The Component Requestors from a Line Adapter are as follows: (i) USART; (ii) Program Timer l; (iii) Program Timer 2.
Thes2 three components are capable of generating "service requests" independently of each other at unigue times relative to its initializa~ion. The "service requests" activate a flag signal to the State Machine Processor which indicates that Line Adapters require servicing. After the State Machine determines which Line Adapters are requesting service, it must then determine which "component" on a particular Line Adapter is requesting service.
Memory on the Line Adapter consists of 2,048 X
17-bit words of RAM for each line. Therefore, each Quad Line Adapter card actually contains 89192 X 17-bit words of RAM. The Single Line Adapter card (FIG. 4) contains ~,096 words of RAM 550m, one half for the data comm line and the remainder for DLI 700. The RAM is used by the software for transmit/receive message buffering, for tables and for statements associated with the line operationO
BYTE ORIENTED LINE ADAPTER - OPERATION
_ ~
Des~ ~nate: When the State Machine Processor 600 executes code relative to an addressable component on a Line A~apter (LA), the LA must be "d~signated". Each Line AdaptPr (as in FIG. 5) contains a flip-flop~ whose input is jumpered to a specific bit of the I/O bus, FIG. 5. In order to "designate" a Line Adapter, the State Machine Processor mus~ execute a PUT OP with Strobe No~ 1 and the corresponding bit of the I/O bus must be equal to 1. Executing the same OP with the I/O bus bit equal to O will reset the Designate Flip-Flop shown typically as "DESF" on FIG. 5.
Fla~ Qperation: The various components of a Line Adapter are capable of producing "service requests". These "service reques~s" are basically ORed together in order to drive a common FLAG line for all Li~e Adapters. A signal line, FLAG 2/, when being low active, notifies the State Machine Processor 600 that some Line Adapters are requesting ~-916~7 service. The State Machine Processor can determine which Line Adapters are requesting service by execu~ing a GET OP
wlth the variant field V-FLD (4:5) equal to OOOOlo The Line Adapter does not need to be "designated" for execution of this OP~
"Register address" (REGADRn) signals in ~he Line Adapters are the five V-FLD sig~als from the State Machine Processor.
Flag operation, with reference to FIG. 6, is accomplished by the FLAG 2/ line which when low active no~ifies the State Machine Processor that a Line Adapter i5 requesting service. For example in FIG. 6, if Line Adapter O requests service then NOR Gate Go is activated to provide a signal tlvw) on the ~LAG 2/ line.
Upon reeeiving this signal, ~he State Machine Processor will initiate a GET OP on ~he GET FLAG ID line.
Th.is will send the output signal of Gate Go ~o a particula line of the I/O bus (which is dedicated to a par~icular one of the Line Adapcers) which, when read by the Sta~e Maehine will iLdentify the particular Line Adapter involved, in this case, the Line Adapter 0.
Similarly each line Adapter as 1, 2, 3, etc.
will have a Gate Gl, G2 or G3 to aotiva~e the FLAG 2/
line and cause the State Machine to "read" the particular "jumper" connection to the line on the I/0 bus associated with that Line Adapter.
D-C- Dus Struc~ With the exception of the RAM (FIG. 5), memory 550ml~ m2~ all data sent to addressable components on the Line Adapter originate from the "Second" ~utput Control Register 38 (FI&. 3) in the State Machine Processor With the exception of RAM, all data "read" by the State Maehine Processor from addressable components on the Lin~
Adapter will go to the State Machine Processor via the I /0 bus 10 .-With reference to FIG~ 4 (DLI/LA data bus structure), the Single Line Adapter data bus structure is shown.
As seen in FIG. 4, the Second Output Control Register 38 (FIG. 3) lines 17~ (OCREG 20n) connect dlrectly to the inputs of the Auto Call Unit O~tput Register 505 (ACUOR); and they also connect directly to the Transceiver Bus Controller chip 503 which provides bidirec~ional bus drivers.
The Auto Call Unit Output Register 505 is a six bit "D" ~ype flip-flop register (D~6n). When the clock input is enab1ed, data from the Second Outpu~ Register 38 will be strobed into ACUOR 505.
Data sent to both the Timer 507 and to the USART
S08, FIG. 4, originate from the Second Output Register 38 in the State Machine Processor (FIG. 3) and is sent through the Transceiver bus con~roller 503; ~hen is sent ~o the addressed component The data lines for t~e Timer component are HI active and for the USART component they are LO active.
Being as both components share the same data bus, data to one of the components must be inverted. The Timer 507 is used to recelve the "inverted" data, that is, 1 8 0 and O = 1, while the USART 508 receives the conventional format.
Thus, a "one" bit from ~he Second Output Register 38 in the State Machine Processor (FIG. 3) will appear as a "one" bit to the USART (active low) and as a "zero" bi~ to the Timer.
The Transceiver bus controller 503, although being a ~ree-state device5 is not used in its third or high impedance state. It is used for driving either DIh (data in) to DO~T (data out) or DOUT to ROUT depending on the s~ate of t~e RE slgnal ~hich originates from bit 4 of the First Output Control Register 37 in the Sta~e Machine Processor.
When bit 4 of Register 37 is ON, the signal ~E is positive and "enables" the DXN to DOUT direction through the Transceiver bus controller 503.
Reading of information (except RAM read) from a Line Adapter is performed by decoded GET OPs, an~ the read information is available on the least significant 8 bits of the I/O bus 10. The 8-l multiplexor 504 is the source of the read information.
On the "Single" Line Adapter (FIG. 4) four of the eight inputs to MUX 504 are used by ~he Line Adap~er and the remainder are used by the Data Line Interface (DLI). The multiplexors (MUX's) are chip selected (low level) during a GET OP when the V-FLD (3:2) is equal to 7'1L" and either V-FL~ (4:1) equals O (DLI GET) or the Designate Flip-Flop (DESF) is ON (LA GET).
On ~he "Quad" Line Adap.~r cards (FIG. 2) there are 16 multiplexors, each having an eight-one ratio.
There are 8 multiplexors for each "pair" of Line Adapters.
As seen in FIG. 4, t~e eight input lines to MUX
504 are divided in half such that four lines connect to the DLI (Data Li~k Interface~, and four lines connect to the Line Adapter. Similarly in FIG. 2, in the Quad Line Adapter, the eight inpu~ lines of each group of eigh~
multiplexors is divided in half, similar to the Single Line Adapter, thereby making four groups. Any group of four inpu~ lines is selected by its "Designate Flip-Flop"
(DESF, FIG. 5) being 0~0 The selection of any one of four lines o~ any such group is performed by the two least significant bits of t~e V-FLD of a ~ET OP.

Data to be "written into" RAM memory in a Line Adapter (FI~So 2~5) is sent via t~e I/0 bus 10 in 16 bits plus parity format. The data "r~ad from" RAM memory ln a Line Adapter is placed on the M~MOUT bus 12 wi~h 16 bits plus parity.
: As seen in FIG. 4, the outputs of component~ to be "read" are routed to the inputs of the 8-1 multiplexor 504 which then drive the I/0 bus 10. There are five components OR a Line Adapter which may be "read" by the State Machine Processor~ these are-Component Requestor ID (CRID) USART ( 508 ) Timer ( 507 Automatic Calling Unit Status (ACUST) Adapter Type ID (ADPT.ID) Although these fire components on a Li~e Adapter may be read, the USART 508 and the Timer 507 share the same input line (ROUT) to the multiplexors. Selection of one of the four lnputs in either group (of inputs to the 8-1 multiplexors) is performed by the two least significant bits of the V-FLD of the GET OP. V-FLD ~3:4) equals llXX
and sele~tion of one of the four inputs is determined as shown ln TabIe Y-l (x~ VO(x~ _ComPonent Addressed . . ~ . .. .
0 0 . Component Requestor ID
O 1 USART/Timer 1 0 ACU Status 1 1 Adapter Type ID (Identifica~ion) In FIG~ 4 the Single Line Adapter multiplexor 504 allows thr2e components on a Line Adapter to be written into (not including R~M). These are: Automatic Calling Unit Outpu~ Register 505 (ACUOR)~ t.he USART 508 and the Timer 5070 The addressing of these three components occurs in two distinct fashions: decode of the V-FLD of PUT OPs and the decode of bits from the First Ou~put Conerol Register 37 in the State Machine Processor (FIG. 3).
The ACUOR 505 is addressed w~en a one-of-eight decoder 80p, FIG~ 8a decodes the PUT OP V-FLD (4:5) equal 01111 and a Strobe No. 2 is sent from ~he Sta~e Machine Processor. This decoding is performed only on the Single Line Adapter card and is sent to other Line Adapter cards via the frontplane connector. This decoded si~nal is received by a three input NOR gate (N3, FIG. 8a) in each Line Adapter (whose other in~uts are Cloc~ and Designate FF). The output of this gate drives the clock input of the six bit ACU OUt~tlt register.
Data from thc Second Output Control Register 38 (FIG. 3) will then be strobed into the ACUOR 505, FIG. 8a.
In FIG. &a, decoder 80p receives, as input, bits 0-4 from the d~co~ con~roller 23 of FIG. 3, and also the Strobe #2 signal from the State Machine Processor 600.
When the Register Address RA = 01111, ~OR gate N3 will clock data (from Register 38, FIG. 3) in~o ACU-output Register 5050 FIG. 8b shows the timing sequence whereby the PUT
Strobe, the Register Address, and the ACUOR-CLK signals permit loading of the ACU-Output Register 505.
To particularize the use of ACU~Output Registers for their ~unction of sending dialing digits and control signals to an Automatic Calling Unit (such as 505u):
(a) the State Machine 600 will use ies Second Output Control Regis~er 38 to accumulate dial digits and control signals.

~ 16 -(b) The State Machine 600 will initiate a PUT OP
to load dial digits and control bits into the Second Output ontrol Register 38 (FIG. 3) using a PUT Strobe 2. The fields used are:
OP V-FLD D-FLD Data _ .
PUT 01110 XOOl XXnn where nn = data put into the Second Output Contra,l Re~. 38 (OC~eg 20n~
(c) The State Machine 600 will then use ano~her PUT OP tc load ~he selected ACU-~utput Register ~he~e the ields are:
. OP V-FLD D-FLD
PUT 01111 XOOl As a result 3 ~he selected ACU-Output Register will now hold the dial-digit data and control data received from OCREG 20n on line 172 (FIG. 8a).
20 . (d) ~hen gate N3 of FI&. 8a is activated by the signals of CLK, DESF/ and RA = 01111, then the ACU-Output Register is clocked to pass its data onto the Automatic Calling Unit, as S05u in FIG. 8a.
It should be understood that each of the ACU-Output Reglsters (5050, 5051, 5052 and 5053) of FIG. 2 can be selected for conveying dial data and control data to its own Automatic Calling Unit.
The Second Output Control Regi~ter 38 (FIG. 3) is given the acronym OCREG20n i~ FIGS 2 and 8a_ Using ~
~its o t~e 8-bl-~s. of ~u~put Cofitrol Regis~er 38, the bit positions 0-5 are used as follows:

Seco d Output Control_ Re~ er Bit # ACU Si~
O NBl 1 NB2 Decimal

2 NB4 Dial-Digit

3 ~B8,

4 DPR - Digit Present CR~ - Call Requ~st ~hen OC-Register 38 has '~0" placed in bit positions 4:5, 10 (i-e-7 starting at bit position ~4~ the 5 positions 4,3,2,1,0 are set eo ~0~') 9 then this represents an "ON"
condition to the Automatic Calling Uni~
If a t'l" is placed in bit position #5, then this represents an "ON~' condition for the Call Request.
CRQ is a signal from the line adapter to the ACU
(Automatic Calling Unlt) such as an 801C, that the line adapter wishes to place a call (i.e., dial a number).
The DPR (digit present) is a signal from ~he line adapter to the ACU in response to a PND (Present Next Digit) signal from the ACU as seen in FIG. 7. It means that the data in NBl-NB8 is one of the dial numbers.
The RS-232 Electrical In~erface (EI) allows for many different styles and types of data sets (modems) to be eonnected. Some of these modems have extra or special functions which can be controlled via th~ electrical interface. For example, the Western Electric 201-A data set contains a signal "New SYnGI~_ NS; the 202 C/D data se~
contains a signal "Supervisory T~ansmit Da~a" - SA; the 811-B data set has an "EQT Detected" signal ED (end of transmission-detected).
In order to make use of ~he ~ew available lines on the interface between the line adapter and the electrical interface (EI), these line~ havP been doubly used for providing control over these "special function" signals.
Thus, logic circuitry was placed on the EI card and the existing lines (CRQ and NBl) were usecl to provide the control functions. Jumpers were used to connect the "special control" function to the appropria~e pin in the connection cable.
When CRQ is "off", then this represents the situation where no dialing is occurring and thus the NBn line is available for use and the firmware in the state machine processor would control the logic circuitry as desired.
The special con~rol func~ion signals NS, SA, ED
are indicated below for certain data sets. Manuals of the Bell Telephone Co. are availabl for detailed use of the N5, SA and ED signals.
For certain data sets, the ACU-Output Register

5~5 is used as a "special control" function. By malntaining OC Register 38 (FIG. 3) so that bit position ~5 is OFF (_"O") and by ~ontrolling bit position #0, the control lead to the data set can be turned ON/OFF.
This "special control" function is jumpered to one of the following listed signals on the Electrical Interface card to provide functions as follows.
SIGNAL FUNCTION DATA SET
25 NS New Sync 201 SA Reverse Channel Transmit 202 ED Fast Disconnec~ 811-B
Thus, operationally the special control function can be summarized as follows:

~9~

(a) The bit position #0 of OC-Reg. 38 can be loaded, via Strobe #2 signal, to r~ad "O" (=QFF) or "1"
(=ON). This is done by the ollowing instruction fields:
OP V~E'LD D-FLD DATA
..
PUT 01110 XOOl XXOn where n can be a "O" or "1"
(~) The ACU-Output Register (as 505, FIG. 8a) is loaded (with the data residing in the Second Output Con~rol . Register 38) by the following instruction fields:
OP V-FLD D-FLD
.
PUT Ollll XOOl (e) In this situation, if the bit position #O of the OC-Regis~er 38 held a "1", then the "special function"
control signal would be "ON". If the bit position #O held a "O", then the "special funceion" control signal would be "OFF".
: Addressing a USART or Timer on a d signated ~Q Line Adapter is the same as "chip selecting" the component.
This is ~ccomplished with bits O and 1 of the First Output Control Register 37 in the State Machine Processor along with the Desi~nate Flip-Flop (FIG. 5) in a Line Adapter.
Each Line Adapter will ~AND17 its Designate FF
2~ with bits O and 1 in order to provide a UCS (UâART Chip Select) or a TCS (Timer Chip Select3 for its USA~RT or Timer.
The use of bits O and 1 in the First Output Control Register 37 is as ollows:

_ . _ ~e Si ~nal De s i ~nati on Bit C~ = 1 USARTCS o USART Chip Select~UCS
Bi t 1 = 1 TMRCS = Timer Chi p . Sel ect TCS

The remaining bits of Register 37 are used for control signals, primarily for the USART and Timer.
Random Access Memory (550m, FIG. 5): Each data comm line has 2,048 words of RAM available for its use. A word is equal to 16 data bits plus one parity bit. In FIG. 5 the RAM chip 550m is a 4,096 X 1 bit static RAM with a Read Access time of 180 nanoseconds and is arranged with 17 chips making 4,096 words. On the DLI/LA card, 2,048 words are for the "Single" Line Adapter and 2,048 words are for the Data Link Interface. The "Quad" Line Adapter card (FIG. 2) provides 34 memory chips or 8,192 words of which 2,048 words are available for each line.
The data comm Line Adapter memory.~for any line~
is "pointed at" by the memory address lines, MADDR (15:5) equal 01110. This can be seen in FIG. 5 which shows the Data Link Interface/Line Adapter RAM 550m. A five bit Comparator 100c on the DLIILA eard compares tfor an "equal"
condition) for (i) DLI memory selection; or for a "greater than" conditio~ (MADDRnn 01110) which provides for (ii) Line Adapter RAM s~lection such as 550ml or 55m2. The signal "LARAMSEL" (Line Adapter RAM Select) will go to all Line Adaptes eards via the frontplane cable to select the "designated" Line Adapter RAM memory. If memory address lines MADDR ~15:5) equal Olllx (DLI or LA Select) then a slow memory flip-flop (SLMF) loosf will be set equal to 1.
The flip-flop loosf output (FIG. 5) drives an open collector NAND gate whose output connects to WAIT/ frontplane signal line to the State Machine Processor. This signal (WAIT/), when low~ will force the State Machine Processor to "wait"
until the signal goes "high". Using a RAM chip whose Read Access tim~ is 180 nanoseconds requires the State Machine Processor to wait for one clock time, thereby when ~he DLI
memory (550m~ FIG. 5) or any Line Adapter memory is selected, the SLMF (slow memory flip-flop) will be "on" for one clock and then toggle off.

Selection of the RAM memory 550m on the DLI/LA
card is done via MADDR (15:5) equal to 01110 or else if MADDR ~15:5) equal 01111 and the Designa~e Flip-Flop being ON then a particular Line Adapter RAM is selected.
This logic controls the chip~select input on the RAM
chips. The selection of RAM for DLI or for Line Adapter memory is handled by controlling the "A 11" address pin on the RAM chipo FIG. 5 illustrates the typical setup for each RAM in the system as having its own individual A~ inpu~ from its own indi~idual DESF. If MADDR (15:5) is equal to Qllll and the Line Adapter Designate Flip-Flop (DESF) is ON, the particular RAM is chip selected and the A-ll address input is TRUE.
The "Quad" Line Adapter card (FIG. 2) contains two groups of memory chips (550ml 9 55m2) wherein Data-Comm (D.C.) lines O and i on the card share the same group of RAM chlps and ~ata-Comm lines 2 and 3 ~hare the other group of RAM chips. The signal LARAMSEL (Line Adapter RAM Selec~, FI~. 5) goes to all Line Adapters and is then essentially ANDED with appropriate Designate conditions to allow the desired RAM group to be chip selected. A
"divlsio~' of RAM for the first or second data-comm line on a "Quad" Line Adapter i5 handled by controlling ~he "A-11" address pin (FIG~ 5) on the RAM chip (signal DESn where n = 1) and for the third and fourth line, the "A-ll" pin on the second group of RAM chips is con~rolled by DESn (FIG. 5) where n = 3.
A "Dual" Line Adapter will only contain one gro~p of memory chips (17) and will operate the same as line O and line 1 on the Qyad Line Adapter. Data to be written into RAM must be placed on ~he I/O bus 10 by the State Machine Processor and "read data" will be sent to the State Machine Processor on the ~EMOUTnn bus 12 (nn equal~
~0~ 16).

Clear: There are two methods of clearing used to clear the Line Adapters; these are "Power Up" Clear and "Designate" Clear.
The Power Up Clear is a signal which occurs during the power-up sequence for the cabinet housing ~he Line Adapters. The signal comes from the backplane of the Base Module cabinet and is active low.
The Designate Clear is a function controlled by the State Machine Processor, and only the Line Adapters which are designated are the ones that get oleared. The Clear signal originates from bit 7 of the First Output Control Register 37 of the State Machine Proc ssor (FIG. 3).
The "Power-up" Clear operates to clear three components on the Line Adapter. These are: ~he Designate Flip-Flop;
the Auto Call Output Register; and the USART.
The 'tDesignate'l Clear signal clears two components on the Line Adapter. These are: Auto Call Unit Output Register (ACUOR); and the USART.
~ : The USART is a MOS/LSI
device housed in a 40-pin Dual-in-line package and is TTL
compatible on all inputs and outputs. The USART performs the functions of interfacing a "~erial" data communications channel to a parallel digital system and is capable of full duplex communieations with synchronous or asynchronous systems.
One preferred embodiment of the USART is that manufactured by Western Digital Corporation, 3138 Redhill Avenue, Newport Beach, California 92663 and is designated as Model UC1671 Asynchronous/Synchronous Receiver/Transmitter 30 and described in their Technical Data Publication of August 1978 which includes a block diagram showing the various registers, controls and components which are briefly described herein below.

(i) Receiver Register (RR): this is an eight bit shift register which inputs the received data at a clock rate determined by an internal control register. The incoming data is assembled to the selected character in length and then transferred to the ~eceiver Holding Register with logic zeroes filling out any unused high-order bit positions. At this time the INTR (Interrupt) output is made active for informing the State Machine (600~ FIG. 3) ~hat the Receiver Holding Register contains valid data.
(ii) Receiver Holding register (RHR): this is an 8-bit parallel bufXer register which presents assembled receiver characters to the DAL
~Da~a Access Line) bus lines (FIG. 2) when requested through a Read operation.
(iii) Comparator: the 8-bit comparator is used in the Synchronous Mode to compare the assembled ~0 contents of the Receiver Register and the SYN
register or the DLE register. A "match"
between ~he registers sets up the stripping of the received character (when programmed) by preventing the data from being loaded into the Receiver Holding Register~ A bit in an internal Status Register is set when stripping is performed. The comparator output also enables character synchronization of the Receiver on two successive matches with the SYN regi~ter.
(iv) SYN Register: this is an 8-bit register which is loaded from the DAL tData Access Line) lines ~FIG. 2) by a Write operation and it holds the synchroni2ation code used to establish receiver char~cter synchronization. It serves as a fill character when no new da~a is available in the Transmitter Holding Register during transmission.
This register cannot he read onto the DAL linesO
It must be loaded with logic zeroes in all unused high-order bits.
(v) DLE Register: this is an eight bit register which is loaded from the DAL lines by a Write operation and holds the "DLE (Delimiter~
character used in the Transparent Mode of operation, in which an idl~ transmit period is filled with the combination DLE/SYN pair of characters rather than a single 5YN
character. In addition, the USAXT m~Y
be programmed to force a single DLE
character prior to any data characte~
transmission while in the '~transmitt~r transparent mode".
(vi) Transmitter Holding Register ~THR~: this is an eight-bit parallel buffer registcr which holds parallel transmit~ed data transferred from the DAL lines by a Wri~e opera~1n This data is transferred to the Transmit~er Registe~
(TR~ when the transmitter section is enabled and the Transmitter Register is ready to send new data. During ~his transfer, the signal interrupt (INTR) is made active for informing the Line Support Processor that the Transmitter Holding Register is empty.
(vii) Transmitter Register: This is an eight-bit shift register w~ic~ is loaded from the THR
(Transmitter Holding Registerj, the SYN
Register, or the 3LE register. The purpose of this register is to serialize data and present it to ~he transmitted Data Output Lines.
(viii) Control Register- There are two eight-bit control registers (CRl, CR2) in the VSART
which hold device programming signals such as: mode selection, clock selection, interface signal control, and data format~ Each of the control registers can be loaded from the data access lines (DAL) by a Write operation, or else read into the DAL lines by a Read operation. By designation, "C~l~" would represent bit 6 of Control Register 1. And "CR23" would represent bit 3 of Control Register 2.
(ix) Status Register: This is an eigh~-bit register which holds information on communication errors, interface data register status, match character conditions~ and communication equipment status. This register can be read onto the DAL lines by a Read operation-(x) Data Access Lines (DAL): The DAL is an eight-bit bi-directional bus port over which all addresses, data, control, and status transfers occur. Besides transferring data and control words, the DAL lines also transfer information relating to addressing of the device, reading and writing requests, and interrupting information.
Operation of USART of Byte Oriented Line Adapter:
ASYNCHRONOUS MODE: The framing of asynchronous characters is provided by a Start Bit tlogic low) at the beginn;ng of a character, and by one or more Stop Bits (logic high3 at the "end" of a character. Reception of a character is initiated on recognition of the first Start Bit by a positive transition of the receiver clock, right after a proceeding Stop Bit. The Start and Stop bits are "stripped off" while assembling the serial bit input into a parallel character.
The character assembly is completed by the reception of the Stop Bit after the reception of the last character bit. If this bit is a logic "high", the character is determined to have "correct" framing and the USART ls prepared to receive the next character. If the Stop Bit is logic "low", the Framing Error Status flag is set and the Receiver assumes this bit ~o be the S~ar~ Bit of the next character, Character assembly continues from this point if the inpu~ is still a logic "low" when sampled at the theoretical center of the assumed Star~ Bit. As long as the Receiver input is "spacing" (i.o. ~ receiving a Space rather than a ~rk), then all zero characters are assembled, and error flags and data received interrupts are generated so that line brea~s can be determined.
After a character o all zeroes is assembled along with a æero in the Stop Bit location, the first-received logic "high" is determined as a Stop Bit and this resets ~he receiver circuit to a "Ready" state for assembly of the next character.
In the Asynchronous Mode the character transmission occurs wh.en information contained in the THR
(Transmitter Holding Register) is transferred to the TR
~Transmitter Register)O Transmission is initiated by the insertion of a Start Bit 9 followed by the serial output of the character (least significant bit first) with parity, i enabled, following the most signiflcant bit; then there is the insertion of the 1-, 1.5-, or 2-bit length Stop - condition. If the T~R (Transmitter Holding Regis~er) is full, the next character transmission starts af~er the transmission of th~ Stop Bit of the present character in the TR (transmitter register). Otherwise, the "Mar~"
(logic hi~h~ condition is continually transmitted until the T~ (Transmitter Holding Register) is loaded.
S SYNCHRON WS MODE: The synchronization of messages is carried out by a special Synchroniza~ion Character Code (SYN) transmitted at the beginning of a block of characters. The Receiver~ when enabled, searches for two contiguous characters ma~ching the bit pattern contained in the SYN register~ During the time t~at the Receiver is searching9 data is not transferred to the THR (Transmitter Holding Register) and status bits are not updated; and the Receiver interrupt is not activated. After the detection of the first SY~ character, the Receiver assembles subsequent bits into characters whose length is determined by the contents of the USART internal control register. If, after the first SYN character ~etection, a serond SYN
character is present the Receiver enters the Synchroniza~ion Mode until the Receiver Enable Bit is turned "off". If a second successive SYN character is not found, t~en the Receiver reverts back to the Search Mode.
In the Synchronous Mode, a continuous stream of characters are transmitte~ once the Transmitter is enabled.
If the THR (Tran~mitter Holding Register) is not loaded at th~ time the Transmit~er Register has completed ~he transmission of a character, this "idle" time will be filled by a transmission of a character contained in the S~N register i~ the Non-Transparent Mode, or filled by the characters contained in the DLE and the SYN registers respectively (while in the Transparent Mode of operation).

- ~6 -RECEIVER OPE~ATION: The Receiver data input is clocked into the Receiver Register by a lX Receiver clock from a modem Data Set, or by a local 32X bit rate clo~k (asynchronous) selected from one of four timer chlps.
When using the lX Receiver Clock, the Receiver data is sampled on the positlve transition of the clock in the Sync~ronous Modes. When using a 32X clock in the Asynehronous Mode, the Receive Sampling Clock is phased to the "Mark-To-Space" transition of the Received Data Start Bit and defines (through clock counts) the center of each received Data Bit at the positive transition 16 clock periods later. When the complete character has been shifted into the Receive~ Register, it is transferred to the ~R (Recelver Holding Register); the unused, higher number bits are filled with zeroes. At this time the "R~ceiver Status Bits" (Framing Error/Sync Detect, Parity Error/DLE Detect, Overrun Error, and Data Received) are updated in the Status Regist~r and the Data Received "interrupt" is ac~ivated. Parity Error is set if encountered while ~he Receiver Parity Check is "enabled"
in the internal control register. Overrun Error is set if the Data Received Status Bit is not cleared through a Read Operation by an external device when a new character is ready to be transferred to the RHR (Received Holding Register). Th~s error flag indicates that a character has been lost, that is, new data is lost, and the old data and its status flags are saved.
The characters assembled in the Receiver Register that match the contents of the SYN or the DLE
register are not loaded in~o the RHR (Receiver Holding Register), and the DR (Data Received) interrupt is not generated if bit 3 of USART control register 2 (CR23 =
SYN Strip) or bit 4 of US~RT control register 1 (CR14 =

DLE Strip) are set respectively. The SYN-DET and the DLE-DET status bits are set with the nex~ non-SYN or DLE characeer. When bo~h control register bits CR23 and CR14 are set (Transparent Mode). the DLE-SYN
combination is stripped. The SYN comparison occurs only with the charac~er received after the DLE character. If two successive ~LE characters are received, only ~he first DLE character is stripped. No parity check is made in this mode.
TRANSMITTER OPERATIONS: Information is transferred to the THR (Transmitter Holding Regis~er) by a Write opera~ion.
Information can be loaded into this THR at any time, even when the Transmitter is not enabled. Transmission of data is initiated only when the Request-To-Send Bit is set to a logic "one" in the USART con~rol register and the Clear-To-Send input is at a logic "low". Informatlon is normally transferred from a THR ~o the Transmitter Register when the latter has completed transmission of a character. However, informatlon in the DLE register may be transferred prior to the information contained in the THR if the Force-DLE
signal condition is enabled (CR15 = Force, DLE and CR16 = TX
Tra~sparent and set to a logic "one"). The control bit C~15 m~st be "set" prior to loading of a new character in the THR to insure forcing the DLE character prior to transmission of ~he data character. The Transmitter Register output passes through a flip-flop which delays the output by one clock perlod. When using t~e lX clock generated by the modem Data Set, the output data changes state on the negative clock transition and the delay is Qne bit period.
When the Transmitter is enabled, a Transmitter "interrupt" is generated each time the THR is empty. If the THR is empty when the Transmitter Register is ready for a new character, the Transmitter enters an "idle"
state During this idle time, a logic "high" will be - 2~ -presented ~o ~he Transmit~ed Data Output in the Asynchronous Mode or the contents of the SYN register will be presented in ~he Synchronous Non-Transparent Mode (CR16 = O). In the Synchronous Transmit Transparent Mode (enabled by bit-6 S of IJSART contr~l register 1 - Logic 1), the idle s~ate will be filled by a DLE-SYN character transmission in ~hat order. When entering the Transparent Mode, the DLE-SYN
fill-in will not oceur until the first forced DLEo If the Transmi~ter section is disabled by a reset of the Request-to-Send signal ~RTS), any partially transmi~ted character is completed before the Transmitter section of the US~RT is disabled. As soon as the CTS
signal (Clear-to-Send) goes high, the transmitted data output will go high.
When the Transmit Parity is enabled, the selected Odd or Even parity bit is inserted into the last bit of the character in place of the last bit of the Transmitter Register. This limits transfer of eharacter information to a maximum of 7-bies plus parity or 8-bies without parity.
Parity cannot be enabled in the Synchronous Transparency Mode.
INPUT/OUTPUT OPERATION OF USART: A11 data, Control and Status words aFe transferred over the Data Access Lines (DALO-7) as seen in FIG. Z, DAL. Additional input lines provide controls for addressing a par~icular uni~ and regulating all input and outpu~ operatîons. Other lines provi~e lnterrupt capability to indicate to a controller that an input operation is requested by the USART. A11 input/output terminology is referenced ~o the Bus Controll-er-TransceiYer 503, FIG. 2, so that a 'lRead" or Inpu~ takes data from the USART and places it on the DAL
lines to the Transcei~er 503, while a '~rite" or an Ou~pu~
places data from the Transceiver 503 onto the DAL lines and into the USART. The following input/output terminology discussed below is referenced to the Bus Con~roller-Transceiver 503.
(i) READ: A Read operation is initiated by the placement of an 8-bit address from State Machine 600 on the DAL by the Bus Controller 503, FIG. 2. When t~e Chip Select signal goes to a logic "low: state (CS/ 3 FIG. 5~, the USART (as 508) compares bits 7-3 of the DAL with its hard-wired ID code ~on USART Pins 17, 22, 24, 25, 26) and becomes selected on a "Match" condition. The USART then sets its RPLY line "low" ~o acknowledge its readiness ~o transfer data. Bits 2 0 of the address are used to select th~ USART registers to "read from" as follows:

Bits 2-0 Selected Register of USART
0~0 Control Register 1 010 Control Regis~er 2 . lO0 Status Register llO Receiver Holding Register When the Read Enable (RE) input line of the USART
is set to a logic "low" condition by the State Machine 600, ~he USART gates the contents of the addressed register onto the DAL bus. The Read operation terminates, and the devices become unselected, and both the Chip Select and Read Enable return to the logic "high" conditionO Reading of the Receiver Holding R~gister clears the DR (Data Received) status bito Bit zero must be a logic "low" in Read or in Write operationsO
(ii) ~RITE: A Write operation is initiated by making a Chip Seleot input to go to the logic "low" state. Bits 2-0 of the address are used to select USART registers which are written into as follows:

TABL
Bits 2-0 Se~ r~ ister of USART
,.. . .
000 Control Register 1 010 Control Register 2 100 SYN and DLE Regi ster 110 Transmitter Holding Register When the Write Enable (WE) line is set to a logic "low'~ condition by the State Machine, the USART
gates the data from Transceiver 503 onto the DAL bus and into the addressed register. If data is written into the Transmitter Holding Register (THR), the THRE (THR
empty) S~atus Bit is cleared to a logic zero.
The "100" address loads both ehe SYN and DLE
registers. After ~riting into the SYN register, the device is conditioned to write into the DLE register if followed by another Write pulse which has the "10~"
address. Any intervening Read or Write operation with another address resets this condition sueh that the next "100" will address ~he SYN register.
(iii) INTERRUPTS: The following condi~ions will generate internlpts:
1. Data Received (DR) -- in~icates transfer of a new character to the Receiver Holding Register (RHR) while t~e Receiver is enabled.
2. Transmitter Holding Register Empty (TH~E) -- indicates that the THR register is empty while the Transmitter i5 enabled.
The first interrupt occurs when the Transmitter becomes enabled if there is a~ "empty" THR; or after the character is transferred to the Transmitter Register, thus making the THR empty.

3. Carrier On - ~his indicates the Carrier Detector input has gone "low" when DTR
is "on". (DTR = Data Terminal Ready)O
4. Carrier Off -- indicates that the Carrier 5Detector input has gone "high" when DTR
is "on".
5. DSR On -- indicates the Da~a Set Ready input has gone "low" when DTR is "on".
60 DSR Off -- indicates the Data Set Ready lOinput has gone "high" when DTR is "on".
7. Ring On - indicates the Ring indicator input has gone "low" when DTR is off.
Each time an Interrupt Condition exists, the INTR output from the USART is made a logic "low". The . State Machine then acknowledges the Interrupt Request by setting the CS (Chip Select) and Interrupt Acknowledge Input (IACK) t~ the USART to a "low" state,-otherwise the Interrupt Condition (INTR) would never get reset.
Auto Call ~ration: (For oPerations Usin~ an 801 Auto Call Unit~
. The 801 ACU has a 4-bit interface for receiving dlgits of the call number to be dialed. This interace is defined by the EIA Standard RS-366 and involves the followlng signals:
~BLE Y-5 Call Request CRQ
Data Line Oecupied DLO
Pre~ent Next Diglt PND
Digit Present - DPR
Data Set,Status DSS
Abandon Call and RetryAC~

L'7 'AI~L-- Y--5 ~,~n~
NB 8 Digit NB 4 Digit NB 2 Digit NB 1 Digit The dialin~ sequence~ as illustrated in FIG. 7, operates as follows:
The Line Adapter turns CRQ 'ton: provided that the DLO is "off". After detection of the dial tone, which is done by the ~01, the digits are transferred one at a time.
to the 801. The 801 conYerts the digi~s ~o signals which duplicate the unction of a rota~ing dial-pulse or a ~ouch-eone fr~guency compatible signal. These signals are transmitted to the phone line. At call completlon, DSS
comes "on" to signify receipt of answer tone from the called Data Set. ~eceipt of DSS allows the line to be transferred to the ACU associated data set. If DSS fails to come "on", the Abandon Call and Retry (ACR~ timer begins timing out.
With pulse dialing, a typical 10 digit number takes lS seconds to dial; for touch-tone dialing the same n~mber requires approximately one second. The answer sequence begins sometime after the last digit has been sent by the 801.
Interface Operation (Data-Comm Line-AdaPter/State Machine):
The UIO Data-Communication Line-Adapter is an application dependent device which is controlled by the UIO State Machine Processor 600. Two basic types of Line Adapters are available these are the l'Character Oriented"
Line Adapter and the "Bit Orientedl' Line Adapter, each of which may have a variety of electrical interfaces to the data communication lines~
One to eight Line Adapters may be serviced by one State Machine Processor on a individual basis. Each Line Adapter contains components which are addressable and are -serviced by the State Machine Proce~sor with PUT or GET
instructions. The components on the Line Adap~er are serviced with one or a series of inst~ructions whic~, in some cases, provide sequen~ial con~rol of the component.
The "communication" between the State Machine Processor and the Line Adapter can be separated into two basic groups:
(i) Undesignated (ii) Designated The "Undesignated" operations do not require the Line Adapter to be designated to execute those instructions.
"~esignated" type operations require the Lin~ Adapter to be designated or "identified" to execute those instructions or series of instructions.
The following operations (except for ACUOR) in addition to requiring the Line Adapter to be "Designated"
will use the First Control Register 37 in the State Machine Processor 60C for control purposes to components on a Line Adapter. With the exception of the Clear OP, all other operations will be a series of PUT/GET OPs to provide the necessary sequential control.
"Data" outputted to the Line Adap~er for these operations will originate from the Second Output Control Register 38 of the State Machine in FIG. 3.
The bits of ~he First Output Control Register 37 o the State Machine ~FIG. 3) are organizPd for control functions as follows:

- 3~ -(Output Control Register Bi~s for First Control Register 37) Bit Si~al S O UCS - USART Chip Select - This bit must be a "1" when the USAXT requires a chip select.
1 TCS Timer Chip Select - This bit must be a "1" when the Program Timer/Baud Rate Genera~or requires a chip select.
2 IACKI - Interrupt Acknowledge In - This bit must be a "O" ~o acknowledge an interrupt from a designated and chip selected USART.
3 WE - ~rite Enable - This bit must be "O"
to enable writing to the USART or Timer.
4 RE - Read Enable - This bit must be "O" to enable read~ng from t~e USART or Timer.
5,6 AO, Al - Address Bit O or 1 - These t~o bits select a register within the Timer.
7 CLR - Clear - This bit must be "1" to provide a c~ear to the Line Adapter.

Regarding paragraphs (i) Read and (ii) Wr~te just discussed above, the USART Read procedure is used when reading the USART data registers, status registers or control registers discussed previously u~der the top of "USART Organization and Operation".
Thus, in the (i) Read procedure, the following series of opera~ions occur:

(ia) OP V-FLD D-FLD aL]L~ C~de~
PUT 01110 XOOl kk Here, the second output control register 38 of the State Machine Processor 600 (FIG. 3~ is strobed by Strob~ #2 signal to load it with the register-address of the USART. Also kk = the address of the US~RT register to be read as per Table Y-7, shown hereinafter below.
(ib) PUT 01101 XOOl ID
Here, the first control register 37 (FIG. 3) is ~trobed by Strobe #~ to signal a USART Chip Select (pointer to selected USART).
(ic) PUT 01101 XOOl OD
Here, upon the occurrence of Strobe #2, the irst output control register 37 will initiate the RE
(read enable) 5ignal-(id) GET 11101 ~ FFnn (where FF represen~s the "upper" 8 bits of I/O
bus 10).
This OP gets the data read out from the selected register and onto the IlO bus lO, FIG. 2, (via the Data Access Line, DAL, bus-controller 503 and MUX 50~), and where nn = the data (read-out) on the least significant 8-bits of the I/O bus 10.
(ie) PUT 01101 XOO1 IC
This OP takes the control signal from the first register 37, during Strobe #2, in order to remove (discon~ect) the chip select of the USART
just read.
30 * The address (kk) of the various USART registers to be ~Iread~ is shown in Table Y-7 below.

6~7 T~L~ Y- 7 Address __ 06 (=110) Receive Holding Register 04 (=100) Status Register 02 (=010) USART Control Register #2 00 (=000) USART Control Register #l Now, when it is required to "write" into a designated register of a selected USART, the following (ii) WRITE prscedure is used: 0 ~ a) OP V-FLD D-FLD Data (Hex code) PUT 01110 X0~1 k'k' Here, when Strobe #2 strobes the second output control register ~8 (FIG. 3), then the USART
register address k'k' will be loaded with the 1~ USART address.
Here, k'k' = the address of the USART regiseer to be wrltten into as per Table Y 8.
(ii-b) PUT 01101 X001 ID
Here, Strobe #2 will strobe t~e first output control register 37 (FIG. 3) to chip select the desired USART.
(ii-c) PUT 01110 X001 nn Here, S~robe #2 will strobe data into the second output control register 38 (FIG. 3) which data (~RITE DATA) is later destined for t~e addressed register of ~he selected USART.
(ii-d) PUT 01101 X001 15 Here, when Strobe ~2 occurs, then the first output control register 37 (FIG. 3) provides a Write Enable (WE) signal to the selected USART
so that da~a from 2nd OC register 38 will be written into the addressed register of the selected USART.

.

(ii-e) op V-FLD D-FLD Data (Hex code) Here, upon occurrence of Strobe #2, ~hen firs~
OC register 37 will continue the Write Data cycle for one extra clock for data to be written into the addressed register, after Chip Select and Write Enable are turned off.
The address k'k' of the USART registers to be "written into" are shown in Table Y-8 below:

Ad~ress USART RIE~ o be written into 06 Transmit Holding Register 04 SYN/DLE Register 02 Control Register ~2 00 Control Register #l USART Interfacin~: Three procedures are used when communicating with a USART on a Line Adapter; these are:
~i) Read Procedure (ii) Write Procedure (iii) Interrupt Acknowledge Procedure Timer/Baud Rate Generator Interfacin~:
Two basic proc~dures are used when communicating with the timer components; these are: (i) Write Procedure and (ii) Read Procedure.
Five control signals originating from unique bits of the First Output Control Register 37 are used for the Timer. These are:
TCS - Timer C~ip Select A0, Al - Register Addressing Lines WE - Write Enable RE - Read Enable - 3~ -Baud Rate ~enerator- The "character" oriented UI0 Data Comm Line Adapters will use a USART which requires an inpu~ clock that is 32 times faster ~han the bit-time of the Asynchronous line it is communicating with. To obtain thls X32 clock it is preferred to use an Intel*8253 programmable timer chip, whose squarewave output is connected to the USART. This timer is driven by a crystal controLled clock whose frequency is 1.228~ megahertz.
After initializing the Timer, a divisor value must be loaded which ~ill produce the necessary X32 cloc~.
Read-Write: Selec~ed Timer-Re~isters In order to "write" into any of the timer registers (residing in 507, 509, 511, 514 of FIG. 2) a timer-write procedure (tw3 is used as follows, whereO
k = 1 is the Program Timer ~l address k = 3 is the Program Timer #2 address k = 5 is the Baud Rate Generator Data field address k = 7 is t~e mode word address OP V-FLD D-FLD Data (Hex Code) , .
(tw-l) PUT 01101 X001 kE
Here, the PUT OP will put selection and mode data in the first output control register 37 (FIG. 3) which will chip select the desired timer register (Ao Al) per value of "k".
(tw-2) PUT 01101 X001 k6 Here, the PUT OP (an occurrence of 5trobe ~2) will turn on the "~rite Enable" lines for permitting data transfer to the selected register of the selected timer.

*Trade Mark OP V-FLD D-FLD Da~a (He~
(tw-3) PUT OllO XOOl nn Here, the PUT OP (on occurrence of Strobe #2) will transfer data residing in Second Output Control Register 38 (FIG. 3) to the selec~ed register of the selected timer.
(tw-4) PUT OlllO XOOL nn Here, Strobe #2 enables Second Output Control Register 38 (FIG. 3) to WritP (transfer) data as in (tw-3), thus permitting two clock perlods for "write".
(tw-5) PUT OllOl XOOl kE
Here, on Strobe #2, the PUT OP ~ill seleot t~e First Output-Control Register 37, and turn off WE.
15 (tw-6) PUT OllOl XOOl IC
Here, on Strobe #2 the PUT OP will take control data from First Register 37 (FIG. 3) to turn off the timer chip select, and turn off the address of t~e selected timer register.

When it is desired to "read" out data from either Program Timer #l or #2~ then the "Read-Procedure" for timer-read (tr) is used as follows~ ~here:
k = 1 repr~sents the Pr~gra~ Timer #I ~ata field address value k D j represents Progra~ Timer ~2 data field address value (k~ O represents Program Timer #l data field address value and ~ (read enable - on) k = 2 represents Program Timer #2 data field address value and ~ (read enable-on).

~o (t~ ) PuT Ovll~ol XOOl D~
be ~2 the PUT OP wi 11 ~11 bi~S to address s 1 1 ~ bi t s S, 6 ) and t Ch r (bit 1 of Table Y 6) (tr-2) PUT ~llol XOol (k-l~ E
g ter 37 (FIG. 3) is ~ d om Timer register ca b (tr-3) Y e SalRe as (tr_2) Thi data from the Select d g~Ster ont0 t~e I/o b (tr-4) GET lllol __ nn the select d takeS the read_0ut d timer-register) ~hic~ i 2) an~ puts it into t~
micrProcessOr, The d ~nVerted" f orm ( = nn) (tr_5) PuT ollol X001 kE
_P (on Strobe ~2) will (tr-6) llol X001 IC er 37, (on Strobe #2) wi ChRegiSter 37 to "0" t ~
ntrl 9ignal, to re~ov h

Claims (7)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:-

1. In a data communications subsystem for controlling data transfer operations between a host computer and remote data terminals connected by telephone lines through an automatic calling unit and an associated data set, and wherein said subsystem uses a plurality of line adapters controlled by a microprocessor and said line adapters have multiplexor connection means for communicating to an I/O bus of said microprocessor and wherein said microprocessor has first and second output control registers for providing control data and information data to said plurality of line adapters, an automatic calling unit control system for establishing telephone line connections for a selected line adapter comprising:
(a) a plurality of automatic calling unit-output registers, each of which is dedicated to a particular line adapter, said automatic calling unit-output registers being connected to receive dialing digit data from said second output control register of said microprocessor, and providing an output for connection to an automatic calling unit which has capability for connecting a telephone line to a designated line adapter;
(b) means to designate a particular line adapter for transmit/receive operations or for service operations, said means to designate also providing an enabling signal to a selected one of a plurality of automatic calling unit-output register gating means;

(c) a plurality of said automatic calling unit-output register gating means for enabling a selected one of said automatic calling unit-output registers to provide digit dialing and control signals to said automatic calling unit associated with a designated line adapter, said gating means having input lines from the said designate means and from an address decoder means;
(d) said address decoder means for receiving and decoding address signals from said microprocessor for activating a selected one of said automatic calling unit-output register gating means, said gating means, when activated, enabling the clocking of data from said automatic calling unit-output register to said automatic calling unit;
(e) means in said automatic calling unit for signaling said microprocessor, via said multiplexor means, as to the completion or incompletion of connection of a telephone line usable by the selected line adapter.

2. The control system of claim 1, wherein said second output control register of said microprocessor includes a plurality of signal lines for transmitting information signals to said automatic calling unit, said signal lines including:
(a) a call-request signal line for enabling said automatic calling unit to receive information signals;
(b) a digit-present signal line to enable said automatic calling unit to receive digital-dialing signals;
(c) a plurality of digital-dialing signal lines for transferring binary coded decimal data for dialing a telephone number.

3. The control system of claim 2, wherein one of said plurality of digital-dialing signal lines can be used for turning on or off said automatic calling unit when no digital-dialing information is being transmitted.

4. The automatic calling unit control system of claim 1, wherein each of said automatic calling unit-output registers includes four bit-lines to said automatic calling unit for the dialing of digits to establish a telephone line connection and wherein one of said bit-lines is used for control of said data set associated with said automatic calling unit when said bit-line is not being used for digit dialing.

5. In a data communications subsystem for controlling data transfer operations between a host computer and remote data terminals connected by telephone lines through an automatic calling unit and an associated data set, and wherein said subsystem uses a plurality of line adapters controlled by a microprocessor and each said line adapters has an associated automatic calling unit with data-set and multiplexor connection means for communicating to an I/O bus of said microprocessor and wherein said microprocessor has first and second output control registers for providing control data and information data to said plurality of line adapters, an automatic calling unit control system for establishing telephone line connections for a selected line adapter comprising:
(a) a plurality of automatic calling unit-output registers connected to receive digit dialing data from said microprocessor, each of said automatic calling unit-output registers being dedicated to a specific line adapter;
(b) addressing means for addressing a specific one of said automatic calling unit-output registers, said addressing means providing an output signal to a gating means associated with a specific automatic calling unit-output register;
(c) designate logic means receiving instruction signals from said microprocessor for activating a designated line adapter;
(d) gating means, enabled by said addressing means and said designate logic means, for generating a clocking signal to a selected automatic calling unit-output register to clock digit dialing data to said automatic calling unit;

(e) a microprocessor having first and second output control registers for respectively providing control data and information data to said addressing means and to a selected line adapter, and including:
(e1) I/O bus for connection to a multiplexor means;
(e2) instruction means in said microprocessor to instruct a selected line adapter to execute transmission/reception data operations on an established telephone line connection;
(f) multiplexor means controlled by said microprocessor for routing data from a designated line adapter and for receiving control signals from said automatic calling unit;
(g) an automatic calling unit connected to said automatic calling unit-output register and to said designated line adapter for establishing a telephone line connection to a remote data terminal through an associated data set, said automatic calling unit including:
(g1) data signal means in said automatic calling unit for connection to said microprocessor via said multiplexor means, for informing said microprocessor of the status of the desired telephone line connection;
(h) bit-line connection means from each of said automatic calling unit-output registers to transmit control signals and digital dialing signals to its associated automatic calling unit.

6. The automatic calling unit control system of claim 4, wherein said bit-line connection means includes:
(a) four bit-lines for transmitting binary coded decimal digital-dialing data;
(b) two bit-lines for control signals to enable the receipt of digital-dialing data by said automatic calling unit.

7. The control system of claim 5, wherein one of said four bit-lines is used to control operating conditions of said data set associated with said automatic calling unit while said two bit-lines are inactivated.