CA1194955A - Digital signal communication system - Google Patents
Digital signal communication systemInfo
- Publication number
- CA1194955A CA1194955A CA000421561A CA421561A CA1194955A CA 1194955 A CA1194955 A CA 1194955A CA 000421561 A CA000421561 A CA 000421561A CA 421561 A CA421561 A CA 421561A CA 1194955 A CA1194955 A CA 1194955A
- Authority
- CA
- Canada
- Prior art keywords
- digital signals
- trains
- digital signal
- digital
- signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
Abstract
ABSTRACT
A digital communication system in which parity checking of all the bits can be effected, even if differential logic is used is described. In the trans-mitter section first digital signals of n trains, where n is a whole number equal to 3 or larger, are differentially converted to provide second digital signals which are used to provide a modulated signal with 2n (=N) modulation levels. This modulated signal is transmitted and received in the receiving section and there it is demodulated to provide third digital signals of n trains corresponding to the second digital signals. The third signals are dif-ferentially converted to provide fourth digital signals of n trains corres-ponding to the first digital signals. One novel aspect of the system is that the Hamming distance between two words of the second digital signals corres-ponding to the adjacent two modulation levels is either 1 or 2 and there are N/2 Hamming distances equal to 1 and N/2 Hamming distances equal to 2.
A digital communication system in which parity checking of all the bits can be effected, even if differential logic is used is described. In the trans-mitter section first digital signals of n trains, where n is a whole number equal to 3 or larger, are differentially converted to provide second digital signals which are used to provide a modulated signal with 2n (=N) modulation levels. This modulated signal is transmitted and received in the receiving section and there it is demodulated to provide third digital signals of n trains corresponding to the second digital signals. The third signals are dif-ferentially converted to provide fourth digital signals of n trains corres-ponding to the first digital signals. One novel aspect of the system is that the Hamming distance between two words of the second digital signals corres-ponding to the adjacent two modulation levels is either 1 or 2 and there are N/2 Hamming distances equal to 1 and N/2 Hamming distances equal to 2.
Description
Digital Signal Communication System Background of the Invention The present invention relates to a digitaL signal communication system employing multi-phase or multi-phase multi-amplitude modulation and, more particularly relates to a digital signal communication system of the modulation level of 2n(n ~ 3) which includes differential logic circuits on the transmission and the receiver s:ides respectively.
As disclosed in "Differential Encoding for Multiple Amplitude and Phase Shift Keying Systems" (W. J. Weber), IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. COM-26, No. 3l pp. 385-391, March 1978, PSK (Phase Sh:Lft Keying) modulation, QAM (Quadrature Amplitude Modulation)~and the likes have been widely used in digital signal comrnunication systems.
In these systems, however, since there may arise phase ambiguities in the carrier waves regenerated at a receiver, a differential logic circuit is genera:Lly used in order to eliminate such phase ambiguities.
In the digital radio communication systernsl on the other hand, a parity check system is u3ed to monitor the channel ~uality by the use of an odd or even parity bit for one monitoring section of transmission signals. As to such check systems, reference should be made to; K. Nakagawa et al "W-4DG Code Converters", Reviews of the Electrical Communication Laboratories, NTT, Japan, Volume 23, Nos. 7 -8, 25 July - August, 1975, pp. 799 -817.
9~5 The conventional systems employing the differential logic circuits, however, are detrimentLl in that one bit error in the transmission path would cL~Ise two bit errors in the received and decoded signals to incapacitate the parity check, or largely deteriorate the error rate.
A parity check system, which enables pLrity check even in such a system by counting alternate bits, has been proposed in the United States Patent No. 4,182,988 assigned to this applicant. The proposed system is still incapable of checking all the bits and using the conventional monitoring circuits.
Summary of the Invention The object of the present invention is to provide a digital signal communication system which does not impair the advantage thereof even if differen1ial logic conversion is effected, which can effect parity checking of all the - bits; and which has a code constellation with a lower error rate deterioration.
The present invention can provide a digital signal communication system comprising a transmitter provided with first means for differentially convertilng first digital signals of n trains (n is an integer oi- 3 or larger) to provide second digital signals of n trains compr:ising a plurality of words, second means responsive to said second digital signals for providing a modulat:ed signal with 2n(=N ) modulation levels and third means for transmiting said modulated signal, and a receiver provided with fourth means for receiving said modulated signal, fifth means for demodulating the output from said fourth means to provide third digital signals of n trains corrQsponding to said second digital signals, and sixth means for differentially converting said third diyital signals to provide fourth digital signals of n trains corresponding to said first digital signals, characterized in that the Hamming distance between two words of said second digital signals corresponding to the adjacent two modulation levels is either 1 or 2 and that the numbers of the ~mming distances of 1 and 2 equal to N/2, respectively.
Brief Description of the Invention The present invention will now be described in more detail referring to the attached drawings:
Figs. lA and lB are block diagrams showing a transmitter and a receiver of a digital signal con~unication system.
Fig. 2 is a vector diagram illustrating signal constellation in a 8-phase PSX system.
FigD 3 shows an embodiment of an encoder which encodes Gray codes to natural binary codes.
Fig. 4 shows an embodiment of a decoder which decodes natural binary codes to Gray codes.
Fig. 5 illustrates an embodiment of an encoder which converts codes of the present invention to natural binary codes.
Fig. 6 shows an embodiment of a decoder which decodes natural binary codes to codes of present invention.
Fig. 7 is a vector diagram showing signal constellation in a 16-phase PSK system.
The Detailed Description of the Invention In Figs. lA and lB, a transmitter comprises an encoder 1, a differential logic converter 2, a modulator 3 and a transmitter section ~ while a receiver comprises a receiver section 5, a demodulator 6, a differential logic converter 7 and a decoder 8.
The encoder 1 of the transmitter converts binary codes (for instance, a Gray code which is described hereinafter) of n trains (in this case 3 trains~ into other binary codes (for instance, a natural binary code to be described herein-aiter) of n trains, and converts the same differentially by a known differential logic converter 2 to feed it to a modulator 3. A word comprises a binary code of n trains of the same bit or time slot. The modulator 3 modulates a carrier wave with the differentially converted binary codes of the n trains to provide a modulated carrier wave of 2n(=N ~ modulation levels (for instance, 2n =8 phase PSK modulation). The modulated carrier wave is fed to the transmission section ~, which frequency converts and amplifies the modulated carrier wave and transmits the same through a radio or wire transmission pa-th to the receiver section 5.
~he receiver section 5, on the other hand, receives frequency-converts and amplifies the modulated carrier wave to feed the same to the demodulator 5~ The demodulator 6 35~
demodulates the modulated carrier wave to binary codes of n trains. The differentia] logic converter 7 converts the demodulated binary codes o~ the n trai.ns to binary codes (i.e. natural binary codes) of the n t.rains which correspond to the output from the above-mentioned. encoder 1, and the decoder 8 converts it to binary codes of the n trains (i.e A
Gray codes). The conversion effected by the differential logic converters 2 and 7 has been described assuming it is conducted with natural binary codes as their circuit structures are simple. For details of an example of such systems, reference is made to Y. Tan et al, "2-GHz Band Digital Radio Equipment Employing 8-level PSK with Cosine Roll-off Spectrum Shaping", ICC '78, pp- 33.3.1 - 33.3.5.
Fig~ 2 shows the constellation of the signals PO - P7 in the case of 8-phase PSK system. Ta.bles 1 and ~ are the vector diagrams of conventional systems to show the 3 bit words (Gl -G2) and (No -N2) which are assigned to the signals PO P7 of Fig, 2.
Table 1 Table 2 G~ Gl Go N2 Nl No PO O O O PO O O O
Pl o o 1 Pl p3 o 1 0 P3 p7 1 P7 Table 1 illustrates an assignment of the so-called Gray codes to the signals P0 to P7 where words are selected in a manner to make the known ~mmi ng distance between words corresponding to adjacent signals to be constantly 1.
Fig. 3 shows in detailed a circuit of the encoder 1 shown in Fig. lA, which comprises Exclusive-OR gates 91 and 92 and converts the Gray codes to natural binary codes.
Fig. 4 shows in detail a circuit of the decoder 8 shown in Fig. lB, which comprises Exclusive-OR gates 93 and 94 and converts natural binary codes to Gray codes.
If 3-bit words are represented by Gray codes (G2, Gl, Go) and natural binary codes (N2, Nl, No)~ encoding from Gray codes into natural binary codes effected by the circuit shown in Fig. 3 can be expressed by the formula (1);
No = Go~ Gl~ G2 1 1~3 2 OO..................................... (1) N2 = G2 J
wherein the symbol ~ denotes exclusive OR.
Encoding from the natural binary codes to Gray codes effected by the circuit shown in Fig. 4 is expressed by the formula (2);
Go No~ 1 1 1~9 2 ~ ..................................... (2) G2 = N2 Table 2 shows an assignment of natural binary codes to the signals P0 to P7. In this case, the encoder l and the decoder 8 shown in Figs. lA and lB are not required.
In the prior art when the conventional method of the word assignment was applied to the differential logic converters~
a one-bit error caused in the transmission path inevitably caused the error of two bits in the regenerated or decoded signals in Gray codes shown in Table l; therefore the above-mentioned parity checking cannot be applied or, even if applied, cannot be fully effective. In the case of the natural binary codes shown in Table ~, since the ~Ammi ng distance may take the value of 3, the error rate was greatly deteriorated.
The present invention aims at obviating these problems and is characterized in that the Hamming distances between adjacent words in the digital signal communication system take the value of either 1 or 2, that substantially half of these distances are l whi'e the other half are 2, so that the merit in the differential code conversion is not impaired, the parity checX method can be applied/ and the deterioration of the error rate can be reduced.
Table 3 X2 Xl Xo Po O o Pl O 0 P4 1 1 o Table 3 shows an assignment of 3-bit codes (or words) to the signals P0 to P7 according to the present invention wherein the ~mm; ng distance between words corresponding to the adjacent signals is selected either to be 1 or 2.
One half of the 8 adjacent signal com~inations have the ~mi ng distance of 1 while the other half have the ~mmi ng distance of 2.
Fig. S shows a detailed circuit of the encoder of Fig. 1, which comprises an Exclusive-OR gate and converts the codes (Xo, Xl, X2) of present invention into natural binary codes (No~ Nl, N2) while Fig. 6 indicates a detailed circuit of the decoder of Fig. 1, which comprises an Exclusive-OR gate and converts natural binary codes (No~ Nl, N2) into the codes (X0, Xl, X0)oE~resent invention.
More particularly, encoding from the present invention codes (X0, Xl, X2) into the natural binary codes (No~ Nl, N2) effected by the circuit shown in Fig. S can be expressed by the formula (3);
No = X,~
Nl = Xl(~) X2 r ,, ~ ( 3 ) N2 = X2 5 Decoding from the natural binary codes (No~ Nl, N2) into the codes (X0, Xl, X2) effected by -the circuit of Fig. 6 can be expressed by the formula (4);
X0 = No Xl = N163 N2 J .................................... t4) X2 = N2 The present invention provides a digital signal communic~tion system for the transmitter/receiver provided with differential logic conversion circuits wherein the R~mmi ng distance between two words which is corresponding to the adjacent levels is so set as to take either the value 1 or the value 2 and the two types of distance are substantially for a 16-phase PSK system equal in number.
A code assignment according to the present invention is shown in Table 4 which assigns 4-bit codes (or words) to signals P0 to P15 shown in Fig. 7. As is obvious from Table 4, one half of the 16 adjacent signal combinations have the ~mmi ng distance of 1 while the other half have the ~mmi ng distance of 2.
Table 4 X3 X2 Xl X0 PO O O O O
Pl O 0 1 0 Pg 1 1 1 0 Plo 1 0 Pll 1 1 0 Because of its unique structure the system according to the present invention does not impa:ir the effect of the differential logic conversion even if :Lt is ernployed therefor~
The system is structure in a manner to generate a one-bit error and a two-bit error corresponding to an error caused in the transmission path, thereby reducing probability to cause odd number errors and eve.n number. errors by 1/2 without impairing performance in the parity checking.
5~
-- 11. --As the Hamming distance is restricted to either 1 or 2, the error rate cannot deteriorate greatly.
As disclosed in "Differential Encoding for Multiple Amplitude and Phase Shift Keying Systems" (W. J. Weber), IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. COM-26, No. 3l pp. 385-391, March 1978, PSK (Phase Sh:Lft Keying) modulation, QAM (Quadrature Amplitude Modulation)~and the likes have been widely used in digital signal comrnunication systems.
In these systems, however, since there may arise phase ambiguities in the carrier waves regenerated at a receiver, a differential logic circuit is genera:Lly used in order to eliminate such phase ambiguities.
In the digital radio communication systernsl on the other hand, a parity check system is u3ed to monitor the channel ~uality by the use of an odd or even parity bit for one monitoring section of transmission signals. As to such check systems, reference should be made to; K. Nakagawa et al "W-4DG Code Converters", Reviews of the Electrical Communication Laboratories, NTT, Japan, Volume 23, Nos. 7 -8, 25 July - August, 1975, pp. 799 -817.
9~5 The conventional systems employing the differential logic circuits, however, are detrimentLl in that one bit error in the transmission path would cL~Ise two bit errors in the received and decoded signals to incapacitate the parity check, or largely deteriorate the error rate.
A parity check system, which enables pLrity check even in such a system by counting alternate bits, has been proposed in the United States Patent No. 4,182,988 assigned to this applicant. The proposed system is still incapable of checking all the bits and using the conventional monitoring circuits.
Summary of the Invention The object of the present invention is to provide a digital signal communication system which does not impair the advantage thereof even if differen1ial logic conversion is effected, which can effect parity checking of all the - bits; and which has a code constellation with a lower error rate deterioration.
The present invention can provide a digital signal communication system comprising a transmitter provided with first means for differentially convertilng first digital signals of n trains (n is an integer oi- 3 or larger) to provide second digital signals of n trains compr:ising a plurality of words, second means responsive to said second digital signals for providing a modulat:ed signal with 2n(=N ) modulation levels and third means for transmiting said modulated signal, and a receiver provided with fourth means for receiving said modulated signal, fifth means for demodulating the output from said fourth means to provide third digital signals of n trains corrQsponding to said second digital signals, and sixth means for differentially converting said third diyital signals to provide fourth digital signals of n trains corresponding to said first digital signals, characterized in that the Hamming distance between two words of said second digital signals corresponding to the adjacent two modulation levels is either 1 or 2 and that the numbers of the ~mming distances of 1 and 2 equal to N/2, respectively.
Brief Description of the Invention The present invention will now be described in more detail referring to the attached drawings:
Figs. lA and lB are block diagrams showing a transmitter and a receiver of a digital signal con~unication system.
Fig. 2 is a vector diagram illustrating signal constellation in a 8-phase PSX system.
FigD 3 shows an embodiment of an encoder which encodes Gray codes to natural binary codes.
Fig. 4 shows an embodiment of a decoder which decodes natural binary codes to Gray codes.
Fig. 5 illustrates an embodiment of an encoder which converts codes of the present invention to natural binary codes.
Fig. 6 shows an embodiment of a decoder which decodes natural binary codes to codes of present invention.
Fig. 7 is a vector diagram showing signal constellation in a 16-phase PSK system.
The Detailed Description of the Invention In Figs. lA and lB, a transmitter comprises an encoder 1, a differential logic converter 2, a modulator 3 and a transmitter section ~ while a receiver comprises a receiver section 5, a demodulator 6, a differential logic converter 7 and a decoder 8.
The encoder 1 of the transmitter converts binary codes (for instance, a Gray code which is described hereinafter) of n trains (in this case 3 trains~ into other binary codes (for instance, a natural binary code to be described herein-aiter) of n trains, and converts the same differentially by a known differential logic converter 2 to feed it to a modulator 3. A word comprises a binary code of n trains of the same bit or time slot. The modulator 3 modulates a carrier wave with the differentially converted binary codes of the n trains to provide a modulated carrier wave of 2n(=N ~ modulation levels (for instance, 2n =8 phase PSK modulation). The modulated carrier wave is fed to the transmission section ~, which frequency converts and amplifies the modulated carrier wave and transmits the same through a radio or wire transmission pa-th to the receiver section 5.
~he receiver section 5, on the other hand, receives frequency-converts and amplifies the modulated carrier wave to feed the same to the demodulator 5~ The demodulator 6 35~
demodulates the modulated carrier wave to binary codes of n trains. The differentia] logic converter 7 converts the demodulated binary codes o~ the n trai.ns to binary codes (i.e. natural binary codes) of the n t.rains which correspond to the output from the above-mentioned. encoder 1, and the decoder 8 converts it to binary codes of the n trains (i.e A
Gray codes). The conversion effected by the differential logic converters 2 and 7 has been described assuming it is conducted with natural binary codes as their circuit structures are simple. For details of an example of such systems, reference is made to Y. Tan et al, "2-GHz Band Digital Radio Equipment Employing 8-level PSK with Cosine Roll-off Spectrum Shaping", ICC '78, pp- 33.3.1 - 33.3.5.
Fig~ 2 shows the constellation of the signals PO - P7 in the case of 8-phase PSK system. Ta.bles 1 and ~ are the vector diagrams of conventional systems to show the 3 bit words (Gl -G2) and (No -N2) which are assigned to the signals PO P7 of Fig, 2.
Table 1 Table 2 G~ Gl Go N2 Nl No PO O O O PO O O O
Pl o o 1 Pl p3 o 1 0 P3 p7 1 P7 Table 1 illustrates an assignment of the so-called Gray codes to the signals P0 to P7 where words are selected in a manner to make the known ~mmi ng distance between words corresponding to adjacent signals to be constantly 1.
Fig. 3 shows in detailed a circuit of the encoder 1 shown in Fig. lA, which comprises Exclusive-OR gates 91 and 92 and converts the Gray codes to natural binary codes.
Fig. 4 shows in detail a circuit of the decoder 8 shown in Fig. lB, which comprises Exclusive-OR gates 93 and 94 and converts natural binary codes to Gray codes.
If 3-bit words are represented by Gray codes (G2, Gl, Go) and natural binary codes (N2, Nl, No)~ encoding from Gray codes into natural binary codes effected by the circuit shown in Fig. 3 can be expressed by the formula (1);
No = Go~ Gl~ G2 1 1~3 2 OO..................................... (1) N2 = G2 J
wherein the symbol ~ denotes exclusive OR.
Encoding from the natural binary codes to Gray codes effected by the circuit shown in Fig. 4 is expressed by the formula (2);
Go No~ 1 1 1~9 2 ~ ..................................... (2) G2 = N2 Table 2 shows an assignment of natural binary codes to the signals P0 to P7. In this case, the encoder l and the decoder 8 shown in Figs. lA and lB are not required.
In the prior art when the conventional method of the word assignment was applied to the differential logic converters~
a one-bit error caused in the transmission path inevitably caused the error of two bits in the regenerated or decoded signals in Gray codes shown in Table l; therefore the above-mentioned parity checking cannot be applied or, even if applied, cannot be fully effective. In the case of the natural binary codes shown in Table ~, since the ~Ammi ng distance may take the value of 3, the error rate was greatly deteriorated.
The present invention aims at obviating these problems and is characterized in that the Hamming distances between adjacent words in the digital signal communication system take the value of either 1 or 2, that substantially half of these distances are l whi'e the other half are 2, so that the merit in the differential code conversion is not impaired, the parity checX method can be applied/ and the deterioration of the error rate can be reduced.
Table 3 X2 Xl Xo Po O o Pl O 0 P4 1 1 o Table 3 shows an assignment of 3-bit codes (or words) to the signals P0 to P7 according to the present invention wherein the ~mm; ng distance between words corresponding to the adjacent signals is selected either to be 1 or 2.
One half of the 8 adjacent signal com~inations have the ~mi ng distance of 1 while the other half have the ~mmi ng distance of 2.
Fig. S shows a detailed circuit of the encoder of Fig. 1, which comprises an Exclusive-OR gate and converts the codes (Xo, Xl, X2) of present invention into natural binary codes (No~ Nl, N2) while Fig. 6 indicates a detailed circuit of the decoder of Fig. 1, which comprises an Exclusive-OR gate and converts natural binary codes (No~ Nl, N2) into the codes (X0, Xl, X0)oE~resent invention.
More particularly, encoding from the present invention codes (X0, Xl, X2) into the natural binary codes (No~ Nl, N2) effected by the circuit shown in Fig. S can be expressed by the formula (3);
No = X,~
Nl = Xl(~) X2 r ,, ~ ( 3 ) N2 = X2 5 Decoding from the natural binary codes (No~ Nl, N2) into the codes (X0, Xl, X2) effected by -the circuit of Fig. 6 can be expressed by the formula (4);
X0 = No Xl = N163 N2 J .................................... t4) X2 = N2 The present invention provides a digital signal communic~tion system for the transmitter/receiver provided with differential logic conversion circuits wherein the R~mmi ng distance between two words which is corresponding to the adjacent levels is so set as to take either the value 1 or the value 2 and the two types of distance are substantially for a 16-phase PSK system equal in number.
A code assignment according to the present invention is shown in Table 4 which assigns 4-bit codes (or words) to signals P0 to P15 shown in Fig. 7. As is obvious from Table 4, one half of the 16 adjacent signal combinations have the ~mmi ng distance of 1 while the other half have the ~mmi ng distance of 2.
Table 4 X3 X2 Xl X0 PO O O O O
Pl O 0 1 0 Pg 1 1 1 0 Plo 1 0 Pll 1 1 0 Because of its unique structure the system according to the present invention does not impa:ir the effect of the differential logic conversion even if :Lt is ernployed therefor~
The system is structure in a manner to generate a one-bit error and a two-bit error corresponding to an error caused in the transmission path, thereby reducing probability to cause odd number errors and eve.n number. errors by 1/2 without impairing performance in the parity checking.
5~
-- 11. --As the Hamming distance is restricted to either 1 or 2, the error rate cannot deteriorate greatly.
Claims
1. A digital signal communication system comprising a transmitter provided with first means for differentially converting first digital signals of n trains (n is an integer of 3 or larger) to provide second digital signals of n trains comprising a plurality of words, second means responsive to said second digital signal for providing a modulated signal with 2n(=N) modulation levels and third means for transmitting said modulated signal, and a receiver provided with fourth means for receiving said modulated signal, fifth means for demodulating the output from said fourth means to provide third digital signal of n trains corresponding to said second digital signal, and sixth means for differentially converting said third digital signal of n trains to provide fourth digital signal of n trains corresponding to said first digital signal, characterized in that the Hamming distance between two words of said second digital signal corresponding to said adjacent two modulation levels is either 1 or 2 and each of the digital distance of 1 and that of 2 is equal to N/2.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57023399A JPS58141059A (en) | 1982-02-15 | 1982-02-15 | Multilevel digital radio communication system |
| JP23399/1982 | 1982-02-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1194955A true CA1194955A (en) | 1985-10-08 |
Family
ID=12109427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000421561A Expired CA1194955A (en) | 1982-02-15 | 1983-02-14 | Digital signal communication system |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4523323A (en) |
| EP (1) | EP0086482B1 (en) |
| JP (1) | JPS58141059A (en) |
| CA (1) | CA1194955A (en) |
| DE (1) | DE3361090D1 (en) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2136248A (en) * | 1983-02-25 | 1984-09-12 | Philips Electronic Associated | Text error correction in digital data transmission systems |
| US4752953A (en) * | 1983-05-27 | 1988-06-21 | M/A-Com Government Systems, Inc. | Digital audio scrambling system with pulse amplitude modulation |
| US4622670A (en) * | 1984-12-10 | 1986-11-11 | At&T Bell Laboratories | Error-correction coding for multilevel transmission system |
| US4675863A (en) | 1985-03-20 | 1987-06-23 | International Mobile Machines Corp. | Subscriber RF telephone system for providing multiple speech and/or data signals simultaneously over either a single or a plurality of RF channels |
| US4825448A (en) * | 1986-08-07 | 1989-04-25 | International Mobile Machines Corporation | Subscriber unit for wireless digital telephone system |
| US5228059A (en) * | 1989-11-21 | 1993-07-13 | Nippon Hoso Kyokai | Differential code transmission system |
| US5127022A (en) * | 1989-11-21 | 1992-06-30 | Nippon Hoso Kyokai | Differential coding system |
| US5596715A (en) * | 1993-07-06 | 1997-01-21 | Digital Equipment Corporation | Method and apparatus for testing high speed busses using gray-code data |
| US5546383A (en) | 1993-09-30 | 1996-08-13 | Cooley; David M. | Modularly clustered radiotelephone system |
| JPH09284353A (en) * | 1996-04-18 | 1997-10-31 | Matsushita Commun Ind Co Ltd | Receiver |
| US7206272B2 (en) | 2000-04-20 | 2007-04-17 | Yamaha Corporation | Method for recording asynchronously produced digital data codes, recording unit used for the method, method for reproducing the digital data codes, playback unit used for the method and information storage medium |
| JP3506330B2 (en) * | 2000-12-27 | 2004-03-15 | 松下電器産業株式会社 | Data transmission device |
| US7693179B2 (en) * | 2002-11-29 | 2010-04-06 | Panasonic Corporation | Data transmission apparatus using a constellation rearrangement |
| DE60102296T2 (en) * | 2001-02-21 | 2004-07-29 | Matsushita Electric Industrial Co., Ltd., Kadoma | HYBRID ARQ METHOD WITH REORGANIZATION OF SIGNAL CONSTELLATION |
| DE60114849T2 (en) | 2001-11-16 | 2006-04-20 | Matsushita Electric Industrial Co., Ltd., Kadoma | ARQ retransmission with request repeating scheme that uses multiple redundancy versions and receiver / sender for it |
| EP1313248B1 (en) * | 2001-11-16 | 2005-08-31 | Matsushita Electric Industrial Co., Ltd. | Hybrid ARQ method for packet data transmission |
| KR100630143B1 (en) * | 2002-09-30 | 2006-09-29 | 삼성전자주식회사 | Method and apparatus for receiving and deshuffling shuffled data in high-rate packet data telecommunication system |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3311878A (en) * | 1963-02-14 | 1967-03-28 | Ibm | Error checking system for binary parallel communications |
| US3818442A (en) * | 1972-11-08 | 1974-06-18 | Trw Inc | Error-correcting decoder for group codes |
| US3831145A (en) * | 1973-07-20 | 1974-08-20 | Bell Telephone Labor Inc | Multilevel data transmission systems |
| GB1505342A (en) * | 1973-12-05 | 1978-03-30 | Post Office | Encoders |
| GB1473084A (en) * | 1974-06-06 | 1977-05-11 | ||
| JPS5261424A (en) * | 1975-11-17 | 1977-05-20 | Olympus Optical Co Ltd | Encode system |
| US4199809A (en) * | 1976-04-05 | 1980-04-22 | The United States Of America As Represented By The Secretary Of The Navy | Programmable data terminal set |
| US4182988A (en) * | 1976-09-17 | 1980-01-08 | Nippon Electric Co., Ltd. | PCM channel monitoring system for detecting errors using single parity bit |
| CA1106067A (en) * | 1977-07-19 | 1981-07-28 | Katsuhiro Nakamura | Error correction system for differential phase-shift- keying |
| JPS5836867B2 (en) * | 1977-09-06 | 1983-08-12 | 防衛庁技術研究本部長 | Error control method by monitoring propagation path conditions |
| NL7804674A (en) * | 1978-05-02 | 1979-11-06 | Philips Nv | MEMORY WITH ERROR DETECTION AND CORRECTION. |
| US4276647A (en) * | 1979-08-02 | 1981-06-30 | Xerox Corporation | High speed Hamming code circuit and method for the correction of error bursts |
-
1982
- 1982-02-15 JP JP57023399A patent/JPS58141059A/en active Granted
-
1983
- 1983-02-11 US US06/465,789 patent/US4523323A/en not_active Expired - Lifetime
- 1983-02-14 CA CA000421561A patent/CA1194955A/en not_active Expired
- 1983-02-14 EP EP83101401A patent/EP0086482B1/en not_active Expired
- 1983-02-14 DE DE8383101401T patent/DE3361090D1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58141059A (en) | 1983-08-22 |
| EP0086482B1 (en) | 1985-10-30 |
| DE3361090D1 (en) | 1985-12-05 |
| EP0086482A3 (en) | 1984-02-22 |
| JPH0370420B2 (en) | 1991-11-07 |
| EP0086482A2 (en) | 1983-08-24 |
| US4523323A (en) | 1985-06-11 |
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