CA1194958A - Communication system with distributed control - Google Patents

Abstract

COMMUNICATION SYSTEM

ABSTRACT

A communication system is disclosed for a distributed control arrangement comprising a plurality of communication nodes, each corresponding to a separate physically remote operating unit of a common installation. Each node includes a set of port buffers respectively associated with separate subsystems of the corresponding operating unit, a common node bus and a controller. Each port buffer is adapted to establish a 2-stage transfer link between its corresponding subsystem and the controller, in which the port buffer provides intermediate data storage. One port buffer of each node is coupled to a secondary station associated with that node which is slaved to a primary station. The primary station issues commands through a common data link to the secondary stations and communicates with selected subsystems associated with each node through the secondary station corresponding to that node.

Description

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The present inventi3n relates in seneral to a communication system ror a di.stri~uted control arrangement and to individual communication nodes o. such a communication system, wherein each node enables a plural:it~ of external 5 circuits associated therewith to co~munica1:e through the i~
node. _~

BACKGROU2~D OF THE I~JENTTO~i The control of a large operating inst:allation, such as an electric power generating plant or the Like in which ~-the respective operating units may be physi.cally remote 10 from each other, presents a number O.c problems that do no~
arise in more cor~.pact ins allations. For example, each operating unit may be controlled by a number of subsyste~s, each of which may constitute a separate data processor for performing a specific control function. The respective 15 subsystems associat~d with an op~rating unit may be located in a common cabine~, or they may be physicaLiy remote from each other.
In the operation of such a distributed control arrange~
ment, data must be collected fxom the respec~ive subsystems 20 of each operating unit, often asynchronously; the data must be recognized and perhaps processed; and responsive data or control signals must be transmitted to the same subsys~em, . or to other subsystems of either the same operating unit or o~ other operating units of tile installation, in order to 25 achieve the desired performance. Thus a communication system r is required which is capable of handling the interchange and transfer of th~ ~arious data and controL signals.
In general, ~hen two or more subs~s~ems are in communi- w~
cation with each other in a comm.unication system of the 30 type that is Cound in use with prior art control arrangements, , ~ ~ 94958 18~1T-0013

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each data processor sp-cifically addresses, (or is addressed by), the data processor with which information is to be exchanged~ In order to hold the communication line between them open, the transmitting data processor must 5 interrupt the receiving data processor if the latter is ` ~_ at that moment involved in another task. By its very n~ture, the interrupt command will con1ict with the demands of the receiving data processor. For example, if the receiving unit is operating on a specific routine, the interrupt command will normally cause it to branch off on a subroutine and to leave the original routine unserviced until the communication with the transmi.ting data processor is complete.
Where multiple communications between data processors occur, as is the case in a distributed control arrangement for a large installation in which a relatively large number of subsystems is employed, the number of interrupt commands E~
that must be issued is substantial. This ~nay have important effects on the opera~ion of the dis~ribu~ed control system, 20 which may show up as a reduction in the speed of response. ~_ While the reduced speed may not be important in the operation of an electric power generating plant, the effect may be significant in other applications where the control system is critically dependent on a rapid response.
A characteristic feature of a prior art COllu~lunicatiOn ~
system in which interrupt orders must be issued to gain access ~.
to a receiving data processing system which may be engaged in ~.
another operation, is the requirement for setting up levels of priority, i.e. pre-established conditions under which 30 interrupt orders will be honored. In a system where a large W~
number of data processors are required to communicate with ~--each other, as many as fifty separate prior.ity levels may have to be established for this purpose. l~hese priority levels t together with the required branch routines that must ~.

be established to enable the receiving dat.a processor 1~
to hold its ongoin~ operation in abeyance pending the _~
completion of the communication with tAe transmitting unit serve to make the communication system considerably more complex to build to operate and to maintain than is the case where interrupt commands do not have to be taken into account. ~-Another factor that tends to raise the level af ~P
complexity in prior art co~munication systems of the type under discussion ste~s from the necessity of two uncoordinated data processors i.e. two uncoordinated subsystems 7 having to commllnicate with each other. This entails not only the requirement to subordinate the operation of the receiving data processor to that of the trans~itting unit, (which may be the slower unit) but it also requires each processor to be familiar with certain informatior concerning the unit with which it is in co~munication. For example a block of data stored at a certain address in the transmitting unit, --may be written into 2 different location i:n the receiving unit, and be stored at yet another address in a third unit. Since there is no common discipline which requires that the same data be identi-~ied and stored in ~he same inanner in each data processor, the -e~uirement to cope with these situations increases the complexity of each aata processor.
A further problem that may arise in prior art communi- ;
cation systems of the type under discussion is the problem ~.
of obtaining a co~unicat.ion line when one is required. Sincs ~-for reasons of cost and complexity, the num~er of existing lines will generally be less than the number demanded at any given point of the operation a priority system must be set up to prevent contention among competing subsystems for a line together with suitable safeguards that wil:l enable a subsystem to retain possession until its co~munication is complete. .
Here again the necessity for the additional priorities and .~ ~
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safeguards serve to raise the complexity and the cost of such a com~unication system.
The complexity of prior art communication systems, as disc,ussed above, is largely responsible for elevating 5 relatively simple system changes to the le~el of major problems that require undue amoun~s of time and effort ~,;
to solve. For example, in a large operating installation it is not unusual to add an operating unit, or to withdraw r one from operation. Since each operating lmit is controlled 10 by a plurality of subsystems, suitable mod:ifications of the associated communication system are required by such a change.
Where the latter system is complex, these rnodifications may ~, entail changes in the priority levels with respect to intexrupt comm~n~s. Changes with respect ~o access to the c~ I;cation 15 line$ of the newly added subsystems may also be required or, if an operating unit is withdrawn, with respect to access to the subsystems that remain. Simply stat:ed, the complexity of prior art communication systems of the t:ype under discus-sion limits their flexibility to adapt easil~ to changes of p~
20 the distributed control arrangement with which such systems are associated.

OBJECTS OF THE INVENTIO~
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It is a primary object of the present; invention to ~A
provide a new and improved communication system for a distributed control arrangement comprising a plurality of 25 operating units, which is not subject to ~e foregoing disadvantages.
It is another object of the present invention to provide a communication system for a distributed control axrangement in which the asynchronously operating subsystems are capable 30 of setting up communication links with each other without ,:
the necessity of interrupting the ongoing operation of the L
recelvin~ subsystem.

It is a 'urther object of the prese:nt invention to 7_ provide a communicaticn system for a dist.ributed control system wherein the necessity for se.ting up different priority levels for the respective operat.ions is obviated.
S It is also an object of the present invention to provide a communication system for a dist:ributed control arran~ement wherein the respective components com~ln; cate in accordance with a common discipline.
It is yet a further object of the present invention 10 to provide a communication system for a distributed control arrangement wherein contention among competing subsystems for a limited number of communication lines is avoided.
It is an additional object of the presen~ invention to provide a communication system for a disti-ibuted control 15 arrangement ~hich is sufficiently flexible to accommodate changes of th? associated control arrangement without undue expenditure Oc time and effort.
It is still another object o~ the present invention to provide a co~ml~nication system in which a separate com~llni 20 cation node corresponds to each of a plura.lity of operating units of a common installation and wherein. the system may comprise a selectively variable number of said nodes capable o communicating with each other through a. common data link.
It is still a further object of the present invention 25 to provide a communication system comprising a plurality of communication nodes in which each node is associated with a set of subsystems each of which is adapted. to perform a -~
different control function, wherein the nodes are coupled to a common data link through respective secondary stations, and L
30 wherein a primary station coupled ~o the data link is able to communicate on command with selected subsystems associated with each node.

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It is yet another object of the present invention to provide a communication system comprising a plurality of communication nodes each associated ~ith a set of external circuits adapted to perform different functions, wherein 5 each node includes a common node bus, a controller, and a -port buffer corresponding to each externa;l circuit and adapted to establish a 2-stage transfer link between the external circuit and the controller.
It is yet a further object of the present invention to provide a communication node comprising a co~mon node bus, a controller and a plurality of por~ buffers each correspond-ing to a separate circuit external to the node, wherein each port buffer is adapted to establish a 2-stage trans~er ~
in which information is transferred between the controller ~æ
and a port buffer in synchronism ~lith the controller clock, and wherein the ~iming of information trans~eLs between the port buffer and its corresponding e~ternal circuit is determined ~y the latter.

SU~ RY OF THE INVENTION s~
_ In accordance with the foregoing objects, the present invention is directed to a communication system for a distributed control arrangement and to the structurP and operation of communication nodes employed in such a communication system. Each node includes a common node bus, also referred to as a subsystem co~munication bus. Each circuit external to the node, i.e. each external subsystem or other external source associated with that node, is coupled to the node bus through a port buffer adapted to provide a 2-stage transfer link for data bytes.
The operation of each external circuit and of its dedicated port buffer are relatively lGosely tied to each other and per-mit the external circuit to operate in an asynchronous manner.

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The port bufLer serves as translator between the protocol of the external ci-cuit and that of the node. Traffic within the node, i.e., the transfer of data and/or control bytes from and to each node-connected external circuit, is regulated by a controller which is directly coupled to the common node bus and which prevents contention between competing port bufrers for access to the node bus. The operation of the node controller and of the port buffers are tightly meshed, the latter operating in synchronism with the con-troller.
In the overall (global) communication system of the distributed control arrangement, where the latter includes a plurality of physically re~ote operating units, each node is associated with the set o~ su~sys.ems of a separate 15 operating unit. A separate pre-orogramm~ed secondary station ~, is associated with each node but external thereto and it is coupled to the com~on node bus through a port buffer in substantially identical manner as the other external circuits ~`
of such node. All secondary stations interf,ace with a co~mon data link ex~ernal to the node.
A progra~able primary station also interfaces with the data link. By regulating all data and control signal traffic between the data link and each secondary station, the primary station exercises control over each secondary ,`
station and its associated node and prevents contention bet~een secondary stations for access to -the data link. The primary station thus commands access to selected ones of the external circuits associated with each node. The regulation of traffic wi.hin _he node is, however, relegated to the local node controller.
~ith the communication system described above, ongoing ~~
operations Oc indi~idual receiving,subsys~ems are no longer subject to interruption at the re~uest of the transmitting subsystems and hence the necessity for se1tin~ priority ,35 levels in this context is also elimina.ed,. Similarly, l~r~.T-00l3 contention between compe.ing subsystems for access to the communication lines is avoided. As a consequence, the communication system wnich forms the subject matter of the present invention is superior in its implementation and 5 operation to heretoore available systems of this type. = ~
Further, the system is less costly to implement, operate, and ~-maintain and it is sufficiently flexible to acco~ndate changes of the associa~ed control arrangement without undue expenditure of time and effort.

BRIEF DESCRIP~ION OF T~ DRAWINGS

Fig. 1 is a block diagram of a global communication system which illustrates the environment in which the nodes opera'e; S
Fig. 2 illus~rates in greater detail one of the secondary stations sho~.~n in the communication system of ~ig. l;
Fig. 3 illustrates in greater detaiL the primary station shown in Fig. l;
Fig. 4 illustrates a preferred embodiment of a co~munication node in bloc~ diagram form, simplified to include only a sinyle port buffer;
Figs. 5A - SE jointly illustrate in ~rea~er detail the port buffer portion o' the node shown in ]?ig. 4;
Figs. 6~ - 6D jointly illustrate in greater detail the controller portion of the node of Fig. 4; '~
Fig. 7 shows certain waveforms illustrative of the ~:-operation of a portion of the circuit of Fig. 5E; '~-Fig. 8 shows certain waveorms illustrative of the relationship between corresponding signals generated by the circuit shown in Fis. 6~
Fig. 9 shows certain waveforms illustrative of the signals applied to the circuit shown in Fi.gs. 6C and 6D;

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Fig. 10 illustrates a preferred format of the control ~, word used in connection with a data transferi ~ iy 11 illustrates certain ~iaveforms pertinent to the ~EA~ o~eration of the apparatus shown in Figs. 5 5 and 6; and ~ ig. 12 illustrates waveforms pertinent to the WRITE
operation of the apparatus of Figs. 5 and 6. ~, ~ lith reference now to the drawings, the global communication sys.em shown in Fig~ 1 inc]udes a plurality of nodes 10, 12... ~1, whic~, because they may correspond to physically remo.e operating units, may themselves be physicall~y remo~e Crom each other. Eacil node is coupled to ;' a common com~unicaiion conduit or data link. Although a single communication channel is adequate for the purpose, a pair of redundant channels A and B may be used to enhance the overall reliabili.y of the ~a~a link. In an exemplary embodiment OL' tne invention, between four and eight nodes may be tied to the daia link, using synch~ronous data link r~
control (SDLC) protocol. Ho~,~ever, the invention is not so limited and it will be understood that the number of nodes that may be tied to the data lin~ using SDLC or another link control, may vary up to several hundred nodes.
Node 10 includes a common node bus 15. A controller 18 and a plurality of port buffers PBo, PBl, PB2,..PB~ are 25 coupled to no~e bus 15, each through a bidirectional r~
connection. Each of port buffers PBl...PB~ communicates through a bidirectional coupling with a corresponding subsystem or other signal source external to the node, designated SSl, SS2... SSK. r~
The co~u~ica~ion system illustrated in Fig. 1 may operate in conjunction with differen~ kinds of equipment, for example wi,h a heat recovery steam generator set which is part of a combined cycle electric power generating plant. In such an installation the respective subsystems ~.

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- -- 10 -- s ., SSl, SS2 and SS,, ma~ comprise a feedwa~er. flow control subsystem, a pressure control subs~s~em and a monitoring -~
subsystem for Lhe steam Generator. Corresponding subsystems may be provided for a steam t~rbine and for 5 other opera~ing units of the power sener2~-ting plant. Each subsystem typically includes a pre-prosra.mmed local da-ta processing capability, whereby it performs a specific control function with respect to the corresponding operating unit by modirying signals collected rrom~ or applied to, 10 the operating unit. Thus, the number of subsystems associated with each node may vary and as many as sixteen subsystems may be coupled to the com~on node bus in a ~.
preferred embodiment of the invention. b'_.
In addition ,o the external subsystems mentioned 15 above, the extern21 circuits associated with each node may include one or moxe peripheral starions. In Fig. 1 a peripheral station 29 is shown associated with no,de 10.
Station 29 is co~pled to node bus 15 by way of a port buffer ,~, PBR. Although the invention is not so limited, in a typical ~, example peripheral station 29 may be bidirectionally coupled through an as~nchronous serial link to a data terminal 31, perhaps located at a physically remote site with respect to node 10.
Terminal 31 is coupled to the connection between 25 peripheral station 29 and a driver~receiver isolation module ;~
33. The latter may be further connected 1:o a source of data ~ ~r signals, e.~. through a modem or the li~e,. to translate r~
between the signals of a commercial telephone line and of the peripheral station. In the example under consider-30 ation, terminal 31 may comprise a forms memory terminal adapted to provide inrormation on a page form displayed '~
by a CRT, or a ~age form printed b~ a prin,ter in which certain blank spaces are filled in.in accordance with data received rrom ?eri?heral station 29, which in turn ~, ., .~

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receives data ins~ructions by way of the modem. ~`
The external circuits associated ~ith node 10 further include a secondary station 28 which is bidirection-ally coupled to node bus 15 by means of a port buffer PBo.
Further, secondary station 28 is bidirect:ionally connected =
to redundant channels A and B or the data link, by means ;-~
of a pair of line driver/receiver is~lation modules 30 -~
and 32.
Node 12, wnich corresponds to a separate one of the aforementioned ?lurality of operating unit:s of the distributed control arrangement, is connected in substantially the same manner as node 1~. Specifically, the external circuits comprising secondary station 36 and subsystems SSl, SS2...SSK, are bidirectionally col;?led to port buffers PBo, PBl, PB2...PBK, respectively. As previously pointed out, the total number of subsystems used ma~ be different for each node.
The port bu~fers of node 12 are bidirectionally connected to a common node bus 17, to wnich a controller 20 is also directly coupled. Secondary station 36, which may have a pre-programmed da~a processing capa;bility in the preferred embodiment or the invention, is Eurther connected to communications channels A and B of the data link through a pair of isolation modules 38 and 40 respectively, substantially in the manner of station 28.
Node N is substantially identical to nodes 10 and 12, although ~he numbers of associated subsystems and their ,~
corresponding port buffers may dif~er. As shown, the node ~;
includes a common node bus 19 to which a controller 24 is directly connected. A set of port buffers PBl, PB2...PB
is tied to bus 19 and to a corresponding set of subsystems SSl, SS2...SS~ respectively, the latter being external to the node. A secondary station 44, which is li~et~ise external to node ~, inter'aces with cllannels A and B
of the data lin'~ through modules 46 and 4~ respectively, ., .. . .

8 '-18~1T -0013 and is coupled to bus 19 through port buffer PBo of node N.
A primary station 50 which has programmable data processing capability in the preferred embodiment of the invention, is bidirectionally linked to redundant channels A
5 and B of the data link through a pair of l:ine driver/ _ ~_ receiver isolation modules 52 and 54 respectively. In a ~-preferred arrangement, the primary station may be bidirection-ally connected to a display unit 56 as we:Ll as to an auxiliary panel 58.
The port burfers P~ illustrated in F:Lg. 1 are preferab-ly substantially identical to each other in construction but differing from each other by the address decoding circuitry of each port buffer. Likewise, the contro:Llers of the respective nodes and the secondary stations associated with the nodes may be standarized for a multi-node communlcation system. Similarly th~ isolation modules that connect the separate stations to data lin~ channels A and B may all constitute substantially identical circuit Fig. 2 illus~rates one of the secondary stations e.g.
station 28 shown in Fig. 1 in yreater deta~ herever applicable, corresponding reference numera:Ls from Fig. 1 have been retained. Port buffer PBo is seen to be bidirectionally coupled to node bus 15 by way of a bus comlectox 100. A
random access memory 104, which is preferably of the type that is commercially available wsder the designation R~'l-IO 8156 has 8-bit input/output ports A B and C. IO
port ~ is connected to apply control transEer information to ~j_ port buffer PBo. IO port C is connected to receive station status information from a line busy detect unit 110 and from ~-phase error detect unit 112. IO port C is also coupled to a link controller 114 which is commercially available under the designation number 2652. ~~
A preprogra~med memory 106 which is commercially available under the designation EPROM-IO 8755, has its IO pOl-t A connected to provide additional control transfer .. . ~

~9~ 8 information to port buffer PBo. The IO port B of memory 106, which is used for seneral station control, is connected to the port buffer control lines and it is further coupled to provide an output sisnal to phase error deteGt unit 112, 5 to link controller 114 and to an in.erface and channel =
detect/lock unit 118. A data processor 108, which is ,~
commercially available under the designation number 8085, is bidirectionally cou~led to a common bus 116 within secondary station 28. Units 104, 106 and 114 are similarly connected bidirectionally to co~mon bus 116 Interface and channel detect/lock unit 118 has its outpu~ connected to respective inputs of the aforesaid ~
units 110 and 112, as well as to a synchronizing unit 120 !~---and z decGdins unit 122. The output of the synchroniziny unit is coupled to a clock unit 124, which provides another input to link controller 114. A further clock output is CQUpl ed to an encoding unit 126, as well as to decoding unit 122. The output of decoding unit 122 is connected to the SI serial data input or link controller 114. The serial data output SO of the link controller provides a further input to an encoding unit 126, whose own output is coupled to unit 118. Unit 118 is bidirectionally coupled to communication channels A and B o~ the data link through line driver/receiver ~~-isolation units 30 and 32 respectively. .
Fig. 3 illustrates primary station 50 of Fig. 1 in greater detail, ap~licable referen.ce numerals having been carried forward. An interface and channel select unit 140 is bidirectionally coupled to channels A a]~d E of the data ,~
link by way of the aforesaid line driver/receiver isolation units 52 and 5~ xespectively. The output or unit 140 is coupled to a line busy detect unit 142, a phase error detect unit 144, a synchronization unit 146 and a decoding unit 148.
The primary station rurther includes a random access ~.
memory 150, commercially availa~le under t]ne designation ~'I-IO 8156; a pair OL pre-progra~med memories 152 and 154, 5~

l8rAT-00l3 each co~mercially available under the designation EPROM-IO 8755; a data processor 156, commercially available under the designation number 8085; and a link controller 158, which is commercially available under the designation number 2652. Units 150 to 158 are each bi.directionally coupled to a common bus 160.
Synchronization unit 146 has i.s out:put connected to A`~`
a clock unit 162 which, in turn, has one output connected to link controller 158 and a second output: connected to decoder 148, as well as to an encoding uni.t 164. Encoder 164 receives a further input for the serial da.ta output 50 of link controller 158 and has its own ou.put conn.ected to unit 140.
Link controller 158 receives the output of decoding unik 148 at its serial data input SI.
A further output of link controller 158 is connected to IO port C o~ R~rl 150, which receives further inputs on the same terminal from line busy de~ect unit 142 and from phase error detect unit 144. A display subsystem interface ~~
connector unit 166 receives inputs from IO ports A and B .~' of RAM 150. Further, unit 166 provides the display subsystem control interconnections to IO port A of EPROM 154. ~
IO port B or the latter memory i5 coupled to an input of link ~, controller 158, as well as to an input of interface and channel select unit 140. The last-mentioned B terminal 25 further provides an input to phase error detect unit 144. ;~
Unit 166 is connected to a display unit by way of connections ~~
PA, PB and PC. A connector unit 168 provides input and output connections between the auxiliary panel and IO port A of preprogrammed memory 152. ~' Fig. 4 illustrates in block diagram form one of the nodes shown in Fig. 1, node 10 being taken as an example. ~' Since all port buffers have substantially .identical circuits except for the address decoding circuitry, the node illustrated in Fig. 4 is shown with only a single port buffer PBl in l r .
.. . . . . . . . _ __ . . . .... _ .. . _ . .. . . . .

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order to sim~ y the exp~anation. It will be understood, however, that a plurality o~ port DuL~ers is employed in ~~
a typical node. .~s before, applic2ble reference numerals have been retained.
Fig. 4 represents a schematic illustration of the --~
node in which con~roller 18 is to tne right of node bus 15 i~ the drawing, while port buffer PBl is positioned to the `:
le~ in the drawing. The controller comprises a controller memory 170 ~Jhich is addressed by a controller memory counter 172 so as to either write 8-bit data bytes into memoxy 170 or to read such data bytes out by way of an 8-bit data bus 174. A port select/memory control unii 176 controls the ?-operation of memory 170 and memory counter 172 through control lines 178 and 180 respec.ively.
The oort bu fe~ oortion of the circuit shown in Fig. 4 includes a port control unit 182 whicn communicates with the external worl~, (in the case under discussion with subsystem SSl), by means or a set of lines desisnated respectively ERDY, ELDl, rLD2 and ELD3. Unit 182 is ~urther connected to 20 port select/memory control unit 176 by way of a port address '~
line 184, which further interconnects with bus 15. A control r line 186 is adapted to apply con~rol signal SXFR (transfer) to unit 176 and is likewise connected to common node bus 15.
Data is transferred to and from the external circuits, 25 e.g. to or from subsystem SSl, by way of an 8-bit information bus 188 which carries data as well as control information, as explained ~elow. Bus 188 is connected to first and second control byte latches 190 and 192 and to a first bidirectional switch 194, which allows bidirectional data transfers between 30 the port buffer memory and ar. external subsystem. Latch 190 is connected to receive signals ~rom port control unit 182 by way of lines 196 and to apply a P~AD/r..RITE signal R/W to unit 182 via line 198. Latch 192 is connected to port control unit 182 by means Oc a con~rol line 200 which applies a signal XFR LD2 to latch 192.

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A control line 201 couples a signal XFR-LD3 to bidirectional switch 194, as well as to a memory control unit 220. A number of output connections of control ~yte latches 190 and 192 are combined to ~orm a 10-bit address bus 202, which is coupled to controller memory address counter 172 as well as to node bus 15. Port select~memory control unit 176 in the controller circuit is connected to memory control unit 220 by ~ay of a control line 222, which is further connected to bus 15. Unit 220 is coupled to por~ burfer memory unit 208.
A second bidirectional switch 204 i, coupling to switch 194 by an 8-bit bus 206, which further connects ~' bidirectionally to a port bu~fer memory 208. Switch 204 allcws bidirectional data transfers between the port buffer memory and controller memory 170. A tran,fer signal XFR, derived from port control unit 182, is adapted to be applied to bi~lrectional switch 204 throush a control line 210.
Switch 204 is bidirectionally coupled to controller memory 170 hy means of the aforesaid 8-bit data bus :L74.
A byte count comparator 214 is coup:Led to control byte latch 190 as well as to port buffer memory 208 and to a transfer ~yte counter 212. The lat~er is further connected to receive a counter reset signal via control line 218.
A byte count equal line 216 is adzpted to couple signal BTEQ ~.
from unit 214 to port control unit 182. . . ~
Figs. 5A to 5E jointly illustrate the logic circuit of ~;
port buffer P31. Wherever applicable, the reference numerals employed in Fig. 4 have been retained. A:Lthough the magnitude and complexity of the port buffer logic c:ircuit necessitate ~`
its illustration by means of five separate drawing Figures, the division into the circuit portions shown on the respective drawing Figures is determined by considerations such as ease of e~planation, rather than by purely function considerations.
In each instance, lines terminating in a circle designated by a number and a letter, are continued wherever the -correspondingl~ nu~bered counterpart circle appears on the particular ~igure called out by the letter. For example, the letter B of connections lB, 2B, 3B, etc. of Fig. 5A
are continued in Fig. SB, specifically through connections lA, 2A, 3A, etc. Similarly, the letter A in the latter =
designations points to Fig. 5A, i.e. to connections lB, 2Br 3B, etc. Since each number/letter combination thus -~a unequivocally designates the continuation of the connection, it is considered unnecessary in the discussion below to call them out specifically in eacn instance.
With reference now to Fig. 5A, control signals ELDl, ELD2, and ELD3, which are derived from the connected subsystem, are applied to a set of non-inverting ~uffers 250, 252 and 254 respectively. These buffers, which are used extensively throughout the circuit, provide no storage and may reside on ~ single chip in a preferred embodi~ent of the invention.
These buffers, unless they also perform logical signal inversion, provide protection through isolation on the user side (subsystem side) of the system, as we]l as providing thP ability to drive a hisher load, e.g. one with higher P~
capacitance.
The outputs of buffers 250, 252 and i~S4 are applied to a set of NAN~ gates 256, 258 and 260 respectively.
NAND gate 260 receives a signal on its other input designated XFR. The output OL gate 260 is applied to an inverting buffer 262 and a non-inverting buffer 264. The output signal of the latter buLfer designated LD3X, is provided by signals LD3 XFR. NA~ID gates 258 and 256 each receive a "ready" ~
30 signal at their other input, designated RD~. The output of ~~
gate 258 is applied to an inverting buffer 266 whose output signal is desigrated LD2 RDY. The output of NAND gate 256 is applied to an inverting buffer 268 whose output signal is designated LDl ~D~. In a preferred er.~bodiment of the invention, inverting buffers 262, 266 and 268 ma~ be located on a common chi~, together with a pair of inverting ~;~

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`-- 18 --,._ buffers 270 and 272, which are discussed below.
Signal LD2 RDY is applied to a latching circuit, specifically to a ~AND gate 274 thereof ~hich further receives signal R/W at another input thereof. The output of gate 27~ is coupled to one input of a further NAND gate = ~r~- -278 by way of a resistor 276. An inverting bufer 270 receives signal R/l~l at its input and has its output ~
connected to a NAND gate 280 of the aforesaid latching ~-circuit. The latter gate further receive;s signal XFR
at its input, as well as signal BTEQ. The output of NAND
gate 280 is coupled to NAND ~ate 278, together with a further input designated 282. ~-The output of NAND gate 278 is applied to the clock input C of a "ready" latch 284 which com~letes the aforesaid la~ching circuit. Latch 284 preferably comprises one-half of a chip containing a pair of such latches. The D and S
inputs of latch 284 are coupled to a pull-up resistor 286 which has a po~7er supply voltage Vcc applied thereto selected to be ~5V DC in a preferred embodiment of the invention.
Ready latch 28~ further receives a signal at its reset input R, the derivation of which will be explained in connection with Fig. 5D. Latch 28~ also contains a pair of outputs Q and Q. The aforesaid "ready" s:ignal RDY is ~:
derived at output Q.
A set of address signals designated PA0 - PA3, derived from controller 18, is applied to a correspoIlding set of input terminals in Fig. 5A. These signals address a selected one of a maximum of sixteen port buffers tied to ~
bus 15. As such, they must be decoded to provide the ~' desired port buffer address signal PADR. In the illustrated ~mbodiment, signals PA~ - PA3 are applied to a NAND gate 290, ~.
which provides the decoding function for a port buffer address which is binary 1111. Each of the other port buffers requires a decoder suitable to the port buffer address.

r ~L9'~

`_--~ g _ ~_ Fig. 5D includes a NAN~ gate 300 tc whose input the ~-aforesaid signal PADR is coupled by way cf a resistor 302.
A further input is received rrom the Q output of ready latch 284 in Fig. 5A. The output of gate 300 is coupled 5 to an inverting buffer 304, which in turn is connected to--- t the cloc~ input C of a controller memory transfer request latch 306. Inputs D and S of latch 306 are coupled to receive reference voltage Vcc as in the case of latch 284.
The reset input R of latch 306, as well as of latch 284 in Fi~. 5A, is connected to the output of an inverting buffer 318. In a preferred embodiment of the invention, latches 284 and 306 are located on a common chip that is ~-commercially available under the designation 54C74. The Q -~
output of transrer request latch 306, ~hich provides a transfer request signai TREQ, is connected to one input of a NAND gate 308 whose other input is derived from an inverting buffer 310. The latter is connecte~ to the aforesaid resistor 302 so as to receive signal PADR a~ i.s input.
The output of N~D gate 308 is connected to an inverting buffer 310, which is urther connected to a non-inverting buffer 312. The output of the buffer 312 provides transfer signal XFR. The output of NAND gate 308 is also coupled to a .
non-inverting buffer 314 whose output signal is designated XFR.
Signals XFR and BTEQ are coupled to the inputs of a NAND gate 316 whose output is coupled to a further NAND gate 320. A l.
second input or the latter gate is coupled to an input -terminal on which the signal PEN~ is provided. This signal is derived from the controller and it is indicative of a "powex up" condition. The output of NAND gate 3~0 is connected to the input of the aforesaid inverting buffer 318 wllose output, as explained above, is coupled to the reset inputs of latches 284 and 306.
Signal RD~', which is deri~ed-at the Q output of ready latch 284 in Fig. 5A, indicates in its high state that the port buffer is ready for a data transfer with respect to its ~.
.. ..... .. . .. ,~_ g~
1 8MT--() O 1 3 connected subsystem. When signal RDY is low, it indicates that a data transfer is taking place between the port buffer and the controller memory. As shown in Fig. 5D, the RDY signal is coupled to an output ~erminal 323 by way of a non-inver-ting buffer 322 which provides isolation for the connected subsystem. The signal applied to terminal 323 '~
is designated ER~Y, the R prefix indicating a signal external ~
to port buffer PB1. In the example under consideration, this r signal is applied to subsystem SSl. Similarly, in conformance with the adopted convention, signals BTEQ and R/W are coupled to output terminals 325 and 327 respectively, by way o non-inverting buffers 324 and 326 respect:ively. The latter terminals thus provide signals EBTEQ and ER/W respectively, ~
to the connected subsystem. F3 Fig. 5D further shows bidirectional switch 204 as being comprised of a set of gated bidirectiQnal switch elements 330, 332, 334, 336, 338 and 340. The latter are coupled to corresponding terminals 331, 333, 335, 337, 339 ._ and 341 respectively, for connection to the controller. Thus, signals SXFR, SR/W, SA9, SA8, are applied to the controller by way of terminals 331, 333, 335 and 337 respectively.
Signals S~ICS and SMr,~RT, which are derived from the controller, are applied to the port buffer by way of t:erminals 339 and 341 respectively. The prefix S in each of the aforesaid signals designates a connection to common node bus 15, which permits -:
a transfer relative to the controller or relative to the port buffer. IL
Transfer signal XFR is coupled to the gate input G of each of bidirectional switches 330 - 340. The input/output 30 connection of switch element 330 on the port buffer side ,_ is connected to ground by way of a non-inverting buffer 342.
As a consequence, when bidirectional switch element 330 is gated by transfer signal XFR, the signal applied to the connected output terminal 331 will be the inverse of that 35 signal, de~ignated S~FR in the drawing. Signal XFR is local ~-358 i,l ( to the port burfer, while the prefiY~ S OL SXFR designates the node bus co~nection, as discussec' above.
Bidirectional switch element 33Z rec~ives signal R/W at one connection thereof, such .hat signal SR/W
5 is applied to the connected terminal 333 when swi.tch 33~ is -gated by the transfer signal. Similar conditions pertain ~.
to the remaining bidirectional switch elements. Thus, the application of signal LA9 to switcn element 334 resul-ts in the application of signal SA9 to terminal 335, the S prefix designating a connection to the controller by way of node bus 15. Switch element 336 receives signal LA8 at one connection and, when gated, it applies a corresponding signal SA8 to the connec~ed terminal 337. The application of a signal SMCS to ter~inal 339 provides a signal PMCS at the port buffer side o s~itch element 338. The application of siynal Si1~T to terminal 341 results in signal PMRD
at the port buf,er side of swit~h element 340. In the case of the sigr.als applied to switch elements 334 - 340, the L
prefix or the P prefix respectively, designate signals ~.
internal to the port bu'fer.
The circuit portion of the port buf:Eer illustrated in Fig. 5B comprises ~irst control byte latch 190, which preferably takes the form of an octal D f:Lip flop commercially available und~r the designation 54C374. ]~atch 190 receives input signals ~D0 - ED7 on an 8-bit in~ut bus connected to latch input terminals Dl - D8. The latch disable terminal DIS is grounded and its clock terminal CLK is connected to receive the a'oresaid signal L~l~RDY which was derived from invertin~ buf'er 268 in Fig. 5A. Reference voltage o~
Vc~ is cou~led to the individual lines of the aforesaid input bus by means OL resistors 34~. La~ch 190 further has a set of output terminals Ql - Q8. Control signals ~F
LA8, LA9 and R/~l are derived at latch out:put terminals Q2 and Q8 respec~ively, whence they are applied to bidirec~ional switches 336, 334 and 332, ZIS discussed in 4l connection with Fig. 5D.
Byte count comparator ~14 includec; first and second comparator units 346 and 343 respective]y, each commercially available in chip form under the designation 54C85. Output terminals Q3, Q4, Q5 and ~6 of control byte latch 190 are connected to inputs A0, Al, A2 and ~3 respectively o~
comparator unit 346. Latch output terminal Q7 is connected to inpu~ A0 of comparator unit 348.
Transfer byte counter 212 comprise!s a pair o~
substantially identical counter units 350 and 352, each capable of providin~ a binary count from 0 to 15. In a preferred embodiment of the invention, both counter Ulli~
350 and 352 reside on a co~mon chip which is commercia~ly aYailable ur.der the designation C34520. Input E of transfer byte counter unit 350 has an input line 356 conn~cted thereto. The derivation of the signal so coupled to input E
is discussed below in connection with Fig. 5C. Inpuk E
of counter unit 352 is connected to output Q4 of counter unit 350. Clock inputs C of both counter units 350 and ~52 are connected to a common ground. Outputs Ql, Q2, Q3 and Q4 of counter unit 350 are connected to inputs B0, Bl, B2 and B3 respectively of comparator unit 346. Outputs ~1 ~nd Q2 of counter unit 352 are connected to inputs B0 and Bl respectively o comparator unit 348. The remaining outputs o~ coun~er-unit 352 are not used.
Inputs ~B and A~B of comparator unit 346 are grounded together with inputs A1, A2, B2, A3 and ]33 of comparator unit 348. Input A=B of comparator unit 346 has reference voltage Vcc couDled thereto by way of a resistor 354. Outputs ~Bt A~B and A=B of comparator unit 346 are connected to correspondingly designated inputs of comparator unit 348.
outputs ..P.~B and A=B of the latter comparator unit remain unused.

~ .: ......

18~T-0013 , Signal BTEQ is derived at output A<B of comparator ;~
unit 348 and is coupled to an inverting buffer 272. The output of buffer 272 is connected to a NAND gate 288. The latter receives a further input from NAND gate 258 in Fig. 5A. The output of gate 288 is coupled to reset input R of both counter units 350 and 352.
. Fig~ 5C illustrates control byte latch 192, which preferably takes the form of an octal D flip flip substantially r identical to latch 190. The 8-bit input kus 188 which provides signals ED0 - ED7, is connected to input terminals Dl - D8 respectively of latch 192. Signals SA0 - SA7 are derived at output terminals Ql - Q8 respectively of latch 192 and serve as source address Cor the controller, as explained in greater detail below. The dis~ble terminal DIS of latch 192 has signal XFR coupled thereto, while clock terminal CLK of the same la~ch receives signal LD2~RDY, as derived from the circ~it portion discussed in connection with Fig. 5A.
Bidirectional switch 19~ comprises bidirectional switch elements 358, 360, 362, 36A, 366, 370 and 372, which are prefera~ly implemented on a pair of substantially identical chips. Gate input G of each of the latter switch ele~ents is connected to receive signal LD3~, which is derived from the circuit portion discussed in connection with F~g. 5A.
25 One terminal of each of bidirec,ional switch elements 358 - ~
372 is connected to lines ED0 ED7 respectively, of the .r 8-bit input bus which is couDled to the connected external subsystem. The terminals on the port buffer side of switch ~, elements 358 - 372 are connected to terminals D0 - D7 of 30 port buffer me~ory 208, as well as to corresponding terminals ,~
of a set of s~itc~ ele~ents of bidirectional switch 204, which is shown in greater de~ail in Fig. 5E.
In a preferred embodiment of the invention, port buffer memory 208 consti~utes a 32 ~ 8 random access memory. Input terminals ~, Al, A2 and A3 of R~`l 208 are connected to L_ ~;~

9i5~

., . ;~
- ou~put termlnals Ql, Q2, Q3 anc Q4 res?ecti.vely, of counter unit 350 of transfer byte counter 212. Input terminal A4 of R~:l 208 is connected to out~ut terminal Ql of counter unit 352 of the same counter. Port buffer memory 208 ~
further includes a set of input terminals designated MWR, ~RD and CS respectively, which are coupled to the ~r:
ou~puts of a ~A~D gate 374, a ~AND sate 376 and an inverting buf~er 378 ~es~ectively. N~D ga.e 374 receives a first input from an EXCLUSIVE OR gate 380 which itself is connected to receive an input signal on line 382 and the aforesaid sisnal ~ ~. ~ second inDut of NAND gate 374 is ~.
derived frum an inverting buf'er 384 which is connected to the output of a second EXCLUSIVE OR gate 386. The inputs of the latter ga~e are provided by sisn21s XFR and R/W, both derived as ?reviously discussed.
The aforesaid signal LD3X is applied to an inverting buffer 388 whicn provides one input of a thi.rd EXCLUSIVE OR
gate 390, The other input ol gate 390 is provided by ~.
signal P~`ICS, which is derived ~rom the circuit of Fig. 5D, as .~
20 discussed... above. The output of gate 390 is applied to one ~~
input of NAND sa.e 376, as well as to inverting huffer 378. ;-A second inpu~ ol gate 376 is derived from the output of ;~
EXCLUSIVE OR gate 386. ~
Fig. 5E sho~s bidirectional switch 204 which comprises a r`
set o bidirectional switch elements 400, 402, 404, 406, 408, ~`
410, 412 and 414, wnich are preferably implemented on a pair of ~
substantially identical chips. Gate input G of each .~$
bidirectional switch element 400 - 414 receives the aforesaid signal X~R. The terminals located on the port buffer side of switch elements ~00 ~ 414 are connected to corresponding ~:
terminals o~ bidirectional s~itch elements 3.58 - 373 as discussed above, as well as to terminals D~ - D7 of port bufer memory 208. T~.e terminals of switch elements 400 - 414 which r are located on tne con.roller side are connected to an 8-bit L
bus 174 that carries sisnals SD~ - SD, to the controller.

~4~8 Reference voltage Vcc is coupled to bidirectional ~.
switches 338 and 240 in Fig. 5D b~ means of resistors 416 and 418 respectivel~f. A resistor 420 furt:her couples reference voltage Vcc to terminals J and ~ of a pair of flip flop circuits 422 and 424, which are preferably located = ~:
on a common chip that is co~mercially available under the designation 54C107. The cloc~ input C of flip flop 4~2 is coupled to the output of a NAND gate 426,one of whose F
inputs is coupled to output Q of flip flop~ 424. The other input siynal coupled to gate 426 constitutes a clock signal derived from the controller and designated SCLK.
Both xeset inputs R of flip 1Ops 422 and 424 have signal LD3X coupled thereto, which was derived in the circuitry or ~ig. 5A discussed above. Output Q of fLip flop 422 is coupled to clock input C of flip flop 424, as well as to one input of a NA~D gate 428 which receives a furth~r input from the output of NAND gate 426. The output of gate 428 is coupled to line 382 in Fig. 5Cr which constitutes one input of EXCL~SIVE OR gate 380.
Figs. 6A - 6D illustrate in greater detail the E
controller portion of tlle node shown in Fig. 4, wherein applicable re erence numerals have been carried forward.
~ig. 6A illustrates controller me~ory address counter 172, which is seen to comprise three substantiaLly identical address counter units 450, 452 and 454. E~ch of the latter counter units compriaes a cnip that is commercially available under the designation 54C193 and wnich is capa~le of providing a binary count 0 - 15. The respec~ive address units each~' have a set of input terminals designated +:L, -1, GD, R and '~
Dl, D2, D3 and D4. Each of counter units 1150 and 452 has ;~
output terminals designated Ql, Q2, Q3, Q4" as well as an ~`
output terminal pair 15~1 and 0-1. Counter unit 454 has output terminals desi~nated Ql and-Q2~ Input terminal ~1 r of address counter unit 450 is cou?led to a line 4S6, which applies a signal whose derivation is explalned in connection with the discussion of Fig. 6B below. ~nput terminal -1 .... .

~ ~4~58 of the same addr2ss counter unit has reerence voltage V
coupled thereto by way of a resistor 458. In the case of address counter unit 452, input terminals +1 and -1 are connected to output terminals 15~1 and 0-1 of address counter unit 450. Similarly, input terminals -~1 and -1 of address counter unit 454 are connected to output terminals 15~1 and 0-1 or unit 452. Terminal GD in all three address counter units 4~0 t ~52 and 454 is connected to receive a signal LADR, which is derived from ihe circuit portion discussed in con~ection with Fig. 63. Input terminal R
in all of th~ acdress counter units is grounded.
The 10-bit input bus 202, which is conr.ected to terminals Dl - D; o~ address counter units 450 and 452 and to terminals Dl and D2 of unit 454, applies address signals SA0 - SA7, derivec in Fig. 5C, to units ~50 and 452. Further, control signals SA8 and SA9, which are derived from bidirectional switching elements 336 and 334 respectively in Fig. 5D, are applied to input terminals D1 and D2 of unit 454.
The Q ou. u~s of address counter units 450r 452 and 454 20 are connected by way of a 10-bit bus to controller memory 170, which is illustrate~ in Figs. 6C an~ 6D. As shown, t~e controller memorv comprises eight substantially identical 1~ x 1 R~ chips numbered 460, 462, 466, 468, 470, 472 and 474, which are individually available under the designation 6508.
25 Each chip is seen to have ten input terminals, of which ,~
terminals A~, Al, A2 and A3 are connected to output terminals ``
Ql, Q2, Q3 and Q4 respectively, of address counter unit 450. _ Input terminals A~, A5, A6 and A7 o' each controlle.r memory chip are connec,ed to output terminals Ql, Q2, Q3 and Q4 respectively, of address counter unit ~i2. Output terminals Ql and Q2 of a~.cress counter unit 45~ are connected to input terminals A8 ~nd A9 respectively, of each controller mem~ory chip.

5~

As shown in Figs. 6C and 6DI each controller memory ~`
chip further includes a pair of control terminals designated R/W and CS respectively, which are adapted to receive control signals WRT and CS respectively. Further, each controller memory chip comprises a pair of read in/read out =
terminals DI and D0, tied together and connected to a single controller Data input/output terminal. The signals written into or read out from controller memory chips 460, 462, 464 and 466 are designated SD0, SDl, SD2 and SD3 respectively.
For controller chips 468, 470, 472 and 474 these signals are designated SD4, SD5, SD6 and SD7 respectively.
The control circuitry illustrated in Fig. 6B includes a pair of input terminals 487 and 489 to whicn the aforesaid signals SR/W and SXFR respectively, are applied. Signals SR/W and S~F~, w'nich are derived from bidirectional switching elements 332 and 330 respectively in Fig. SD, are coupled to a pair of inverting buf'ers 48,3 and 490 respective-ly. Buffer 488 further has reference ~oltage Vcc resistively coupled to its input. The oultputs of buffers 488 and 490 are applied to a pair of inpu1ts of a NAND gate 49~, which furtner receives the output of an inverting buffer ~94. The output of gate 49~ is applied to a non- "
inverting buffer 493 which provides the a:Eorementioned signal ~`
WRT for application to the R/W input of each of controller memory chips 460 - 472.
A clock oscillator 495 is capable of.- providin~ a signal frequency of approximately 500 KH:~ and comprises three series-connected inverting buffers 496, 498 and 500. .~, The output of buffer 500 is fed back to the input of ~-buffer 496 by means of a pair of resistor 502 and 504 ~
connected in series with each other. The latter resistors, ~~
which each have a value of 10K ohms in a preferred embodiment of the invention, have their junction pOillt coupled to the output of l~uffer 498 by means of a capacitor 506 which preferably has a value of 100 Pf Clock oscillator 495 i8 genera-tes signal CLK at the output of buffer 500, which ~-is coupled to a ron-inverting bufLer 480 to provide a .
corresponding s~gnal SCLK for a2plication to the port buffer, as shown in Fiss. 63 and SE. The output of the clock oscillator is ~ur her connected to a timi:ng circuit 507 adapted to generate timing signals. Spec.ifically, the ~,~
output of inverting buffer 500 is coupled to clock input C ~;
of each of a pair or J-K flip flops 508 and 510, which ~~
are pre~erably ~plemented on a common ch:ip commercially available under the designation 54C108. Timing circuit 507 includes a further pair of D flip flops 5L2 and 514, which are commerciall~ available under the designation 54C~4 and which likewise reside on a common chip. Inputs J, K and R of flip flo~ ~08, inputs J and K of flip flop 510 and inputs D and S on each of flip flo~s 512 and 514 are connected in co~umon to a resistor 517 to which reference voltage Vcc is a?plied. Outout Q of rlip flop 508 provides a sign~l, desisnated HACL~ in the drawing, which has one-hall the clock frequency provided by clock oscillator 20 495. Signal H.~CLX is applied to clock input C of flip flops r~
512 and 514 and 'o ~he cloc~ input of a port address ~r counter 524 The Q outoui o~ flip flop 508 is coupled to a NAND
gate 516, which receives further inputs fr.om the Q output of flip flop 512 and the Q output of flip flop 514. The r, a~orementioned sianal LADR is generated at the output of ~' gate 516. The Q output of flip flop 510 i.s coul~lcd to a ~;
N~ND gate 518 which receives a further input from the output of clock oscill~tor 495. A signal C~IWRT i.s provided at the ~
30 output of gate 5'8, t~hich is applied to the input of inverting ~_ buffer 494, as ~.:ell as to line 456 in Fig. 6~. Signal C~IWRT
is further coupled to a non-inverting isol.ation buffer 482, which provides 2 corresponding signal, designated SMWRT
ts.Ystem memory ~irite), at its output L'or application to 35 bidirectional s~ ch element 340 in Fig. SD. L
~.

~:~l9~58 Output Q of flip flop 510 provides a signal CMCS, which is applied to a non-inverting buffer 520. The latter buffer provides the aforesaid signal CS al its output for application to the identically designated control terminals of the respective memory chips illustrated in Figs. 6C and 6D. Signal~CMCS is further coupled -to a non-inverting buffer ~ , to provide the ~foresaid signal SMCS at the output thereof for application to bidirectional switching element 338 in Fig. 5D. Outputs Q of flip flop 512 and 514 are coupled to the reset inpu1s R of latches 514 and 510 respectively. Input R of flip flop 512 is connected to the output of inverting buffer 490. ~-Port address counter 524 is capable of providing a ~--binary count 0 - 15 and is incremented by the application 15 of signal HACLK to its clock input C. A i-urther input ', terminal, designated EP, is connec_ed to xeceive signal SXFR from terminal 489, as well as reference voltage Vcc ~-by way of a resistor 522. Reference voltage Vcc is also applied to jointly connected input terminals ET and GD ;i`~
of counter 52~ by way of a resistor 526. An ~C network comprising a reslstor 528 connected in series with a capacitor 530 is coupled between voltage Vcc and ground.
Tne junction point of the resistor/capacit:or combination is coupled to the input of an inverting buffer 532, whose output is connected to a further inverting buffer 534. The output of buffer 534 is connected to the reset input R of ,~
port address counter 524 and to a non-inverting buffer 486.
A port enable signal PE~lA is derived is derived at the output of buffer 486.
Port address counter 524 com?rises a set of outputs Ql, Q2, Q3 and Q4, which are connected to non-inverting isolating buffers 536, 538, 540 and 542 respectively. Signals PA0, PAl, PA2 and PA3, which were discussed in connection with Fig. 5A, are derived at the output of thes,e buffers.

. .. .. . . _ .. . ... _ .. _ In the operation of the preferred embodiment of the ,~
global communication system illustrated in Fig. 1, primary station 50, ~hich may have a programmable data processing capability in a preferred embodiment of the inve~tion, e~ercises control over its satellite secondary stations 28, 36...44, to which it is selectively coupled by way of the data link represented by communica~ions channels A and B. ', The secondary stations, ~hich may have a pre-programmed ~`
data processing capability, operate in synchronism ~ith the primary station in accordance with SDLC (syndronous data link control) protocol. Thus, all data transfers that involve the ~ata link are performed under SDLC protocol.
A data transmission may contain up to five data frames, each frame containing the necessary control bytes plus a data '~
block havins up to 32 data bytes.
The primary station contains the source and the destination addresses for all data an it issues commands to selected secondary stations for data transfers. The secondary stations in the global co~m~nication system are slaved to the primary station and are only capable of responding to primary station co~mands. They do not them-sel~es initiate any data transfers with respect to the primary station and, accordingly, there can be no contention between competing secondary stations for access to the data link.
Prior to each transmission, the primary station initializes the secondary station which is addressed. ~nder the adopted protocol, each transfer, whether to or from a secondary station, must be acknowledged to the primary station. b~`
If not, the addressed secondary station will again be initialized. Thus, the timing of the secondary stations is tightly controlled by the primary station. The primary station execut2s a time-out routine 'ollowing each transmission, with the time tailored to each e~ected response.
The function and operation of the primary and secondary stations within the global communication system, as well as their structure, are believed to be sufficiently clear from _ .

94~8 the discussion and dra~ings herein to convey a full under- ~.. !'`, standinc3 of the present invention to one skilled in the art. `*:
To preclude any questions of completeness of this disclosure, the software documentation for the primary and secondary 5 stations is provided in Appendix A and B respectively.
By virtue of the access afforded each secondary station L
to its associated node, as explained in greater detail hereinhelow, the primary station is able t:o receive information provided by the external subsystems, or by the 10 external peripheral port buffers. Likewise, the primary station can transmit signals to these external circuits.
Accordingly, it is the prima~y station whlch controls the operation of the physically remote operating units linked by -;
the global communication system. However, notwithstanding ~~
15 the preeminent function of the primary stc3tion in the global 3 com~3unication system, each node controls all traffic within such node and all traffic with its associated external circuits. Thus, the node has an independent existence r-apart from the overall communication system and it is capable ~, 20 or performing its assigned communication t:asks relative to its associated subsystems even if a failure of the global communication system were to occur. Accordingly, such a failure will not cause the control functions performed by the respective subsystems of the distributed c:ontrol arrangement 25 to fail instantly. The respective operating units will be able to carry on their assigned functions for either a limited time period or on a limited function basis.
If the failure of the ~lobal communication system were ~,`
to continue at length, the performance of the r`espec~ive 30 o~eratin~ units would, of course, deteriorate due to the absence of any control exercised by the primary station.
It should be noted, however, that the external subsystems are made aware of the condition OL other connected subsystems, ~liL9~58 including the co~u~unication system, by the timely modifica-tion of particular locations in the controller memorv. Each subsystem is assisn~d the responsibility ~f maintaining a special byte in memory indicative of its condition. Further 5 it is the responsibility of these subsystems to monitor the memory locations oL interest and, when a failure to update is noted, to act ap~ropriately. Deending on the nature of the information which is no longer ava;ilable or current, r~
the subsystem may continue to operate in a limited manner, ~o 10 into a hold mode, or shut down the s~stem altogether.
As previo~sly explained, each port buffer serves as a translator between the protocol of tne exlernal circuit and the protocol of the node. Specifical:Ly, port buffer ~-A
PBo converts SDL~-formated data to make it accevtable to 15 node 10. In similar manner, ~ort bu fer PBR serves to translate the pro,ocol of an asyncnronous serial link, in this case employing a universal asynchronous receiver/transmit-ter ~ART), to ma~e it acceviable to noe 10. In this ~
capacity, each ~or. buffer is adavted to establish a $
20 2-stage bidirectional transfer link betr.;een the corresponding external circuit, e.g. between subsystem ';Sl and controller 18, in which the port buIfer provides intermediate data storage.
On a WRITE co~n~ t~.e port ~uffer addressed by the controller, e.g. port buffer P31, after accepting data from its connected 25 external subsystem SSl, transers the data to the controller memory for storage, all un~er the control exercised by ~;
controller 18. On a RE~D command, the addressed port buf~er PBl receives information from the controller memory~and ,~
makes it available to the connected e~ternal subsystem SSl.
30 In either case, in accordance with the protocol of the node, subsystem SSl must previously have entered a RE~D or WRITE
transfer request. It should be noted that a request for a data transer between a ~ort bufLer and the controller may arise , asynchronously and a data transler between a port buffer 35 and a subsyste~ (or other external circuit) may be performed asynchronously. However, txansfer Oc data between the ,vort ~;

ss~ 1, .;~r buffer and the con.roller will occur only in synchronism ~-~
with the controller clock.
As shown in Fig. 10, bit 7 of the first control byte PC-l indicates whether the instruction is a RE~D
or a WRITE command and thus establishes the direction of data transfer. The first control byte furtller includes ~, a 5-bit count, indicative o~ the number of data bytes to ~;
be transferred. Bit ~6 of control byte PC-l is the most significant bit and bit ~2 is the least significant bit. ~-The two final bits of control byte PC-l, together with the eight bits or the second control byte PC-2, contain the `
address of ~he first data byte to be transferred. '~
The 2-byte control word is entered into the port buffer on the 8-bit information bus 188,one byte at a time. F~
This is represented by signals ED~ - ED7, which are applied in parallel and stored in latches 190 and 192. ~See Figs. 4, 5B and 5C.) As will become clear lrom the explanation below, only the 10-bit address and the R/W bit are passed ~
on to the controller. The byte count remains in the port ;~-buffer which controls the number o' data bytes transferred in either direction between itself and the controller, as well as during transfers from an external circuit to the port ~, buffer. ,~
If the first bit of control byte PC-l denotes a WRITE i operation, i.e. if information is to be written into controller memory 170, data bytes are entered into the port bu~fer directly following the second control byte. ~he number of data bytes so entered must equal the byte count de~ined in the control bytes. If the first bit of the first con~rol byte indicates a READ operation and data is to be read out from controller memory 170, a short wait period follows af~er the second control byte. This allows data fxom the controller memory to be transferred to the port buffer. In a preferred embodiment o~ the invention, 3s the wait period is normally less than 1 millisecond. ~_ , . ~ ~

,__ The number o aata bytes so transfe-red to the port buffer must again eaual the byte count defined by the control bytes.
As stated above, t~o control b~tes must be entered 5 into the port buffer for each transfer request. If ER~Y is ~_ high, (Figs. 4 and 5D), the first 8-bit con-trol byte is ehtered into control byte latch 192, (Figs. 4 and 5C), ~-when signal ELD2 goes high. IL `he first control byte denotes a W~IT~ cormand, the port ~ufLer expects the following byte;s) to be data from tne connected subsystem for transfer in~o controller ~emory 170. (See Figs. 4, 6C ~_ and 6D). Ir the first con,rol Dyte denotes a READ command, the hish sta~e OL ELD2 will tric~er ready latch 284 (Fig. SA) and set tne por. buf~er to e~?ect data from the controller.
T~iggering of the ready latch causes signal RDY to go low, thereby preventing further cata entries into the control byte latches until tne data transfer from the controller memory to the port buCfer has been complete~
It is a reature of the present invention that the 20 second control by~e latch, i.e. latch 192, has a high impedance -~
output state when the disable inpu, DIS of the latch is high.
Accordinglv, until DIS goes low, latch 192 will not produce the address stored therein on its output. This feature allows thP out?uts OL- the second control byte latch of the -25 respective port buffers of node 10 to be operated in parallel on ~he node bus 15. The output of tne port bufEer to the bus y is enabled onlv when sisnal XFR, sJhich is applied to the control byte latch 192, goes lo~J. ,~;
As previously explained, port buffer PBl includes 1: ~

first and .second bidirectional switches 194 and 204 respectively, each comprising a set of biclirectional switch elements. The ~urpose of -these switches i.s to prevent tying input data bus 188 directly to system data bus 174~
The operation is such that, when one set of switch elements _ _ _ allows an information transfer, the other set is disabled. -~
The bidirectionality of the individual swi.tch elements allows information to flow from the connected external subsystem to port buffer memory 208, or from the latter memory to the connected subsystem. Similarly, the bidirectional switch elements of switch 204 allow information to flow from port buffer memory 208 to controller memory 170, .~~
or in reverse. Bidirectional st-i~ch elements 400 - 414 are enabled when information transfer signal XFR is high.
15 Switch elements 358 - 372 of st~itch l9a are enabled when XF~-is high and coincident with signal ELD3 to provide signal LD3X. r The byte count stored in control byte latch 190 is E~
com~ared by ~yte count comparator 214 with the count o 20 transfer b~te counter 212. The latter is incremented upon ~
the transfer o~ each data byte through line 356. Incrementing ._ occurs on the ~alling edge of the waveform of either signal LD3X which is derived from the connected subsystem, or of signal S~"~CS derived from the controller. The output of 25 transfer byte counter 212 is further used to address port ;~
buffer memory 208.
- ~s will be seen from Fig. 5C, line ;56 derives its ,~
signals from the output of EXCLUSIVE OR gate 390 which, when high, further enables port buffer memory 208. Thus, -~
transfer byte counter 212 is incremented when LD3X ~ PMCS, i.e. it is incremented from either the connected subsystem or from the controller, depending on the direction of data flow.
Specifically, signal LD3X is used .to read from, or write data into, port bu fer memory 208 ~ith respect to the connected subsystem SSl, or with respec~ to some other external ~94~5~3 circuit, e.g. a secondary s~ation. Signal P.~'CS is used ~-to read data from or write data into tne port buffer memory with res~ect to controller memory 170.
Byte count com~aratar 214 monitors the output of transfer byte counter 212 to deter~ine when this count exceeds the 5-bit byte count loade~ into control byte latch 190 by the connected subsystem SSl. When that point is r reached, output A<B of comparator unit 348 generates a byte count equal signal BTEQ which per~orms a number of functions:
(1) Resets transfer byt~ counter 212 through inverting ~uffer 272 and NA~JD gate 288, to prepare the counter ~_ ~or the next data transfer. ,-~
12) Clocks ready latch 284 by way of ~ANO gates 280 and 278, if data is being ~Jritten into the controller memory.
~3) Resets ready latch 284 by way OI ~NI) gates 316 and 320 and inverting buffer 318, provided transfer byte counter 212 was used to .ransfe- data between the port burfer and the controller.
0 (4) Signals the external subsystem by way Qf terminal 325 that all data bytes have been transferred between -the port buffer and the subsystem.

In connection with the functions enumerated above, it should be noted that the number count of bytes to be trans-ferred is latched into control byte latch 190 more thanonce during a r.l~IT~ operation and consequently signal BTEQ
is asserted more than once during such an operation. The controller does not count bytes. The number count remains in -the port buffer and only it knows ho-~J many bytes are to be 30 transferred. Thus~ it is the ~ort-huffer and not the control- -ler t~hich shuts o~ tne latter when the count of data bytes actually transferred e~uals the nu~ber count defined in the first control by~e. Conversely, the port buffer has no ,,, s~

clock of its own for -timing the transfer of data bytes there-to. Accordingly, signal Sl~,CS, which occurs in synchronism with the controller clock pulses, is used ~hen the data transfer is from or to the controller. This arrangement illustrates the dual utilization of existing circuit components by the controller and -~:he port buffer, which serves to reduce the overall cost and increase the operating speed of the system. Further, it shows the closely meshed timing relationship which exists between the operation o tne controller and of the port buffer.
In turn, this permits the timing relationship between the port bufer and t~e external subsystem to remain loose, so Fa that data transfers between them may be timed by the subsystem out of synchronism with the controller clock.
Trans~er byte counter 212 is incremented on the falling edge of the waveform of each LD3 pulse. Accordingly, signal ~TE~ is generated on the falling edge o~ the last LD3 pulse. Upon the generation o~ the a~oresaid BTEQ signal, the ~^
data stored in random access port buffer rnemory 208 is ready to be moved into the controller. The coincident relationship o~ signals XFR high, (data not presently being transferred bet~een the controller and the bu~fer); R/W
low, (WRITE condition); and BTEQ asserted, (a pulse); sets the ready latch. I~ the port buffer address :is not coincident, ~he ready latch will set the transfer request latch to assert -.
trans~er request signal TREQ.
~ hen now tne address o~ the port buffer in question, i.e. PBl, comes up during the polling procedure, signal SXFR goes low and stops the polling. Further, signal SXFR loads the 10-bit starting address S~J~ to S~9 into controller memory address counter units 450~ 452 and 454. ~-This action enables writing into controller memory 170 ~' to ta~e place. The actual pulses that write into the controller, i.e., pulses Csr are counted by the port buffcr's transfer byte counter 212. ~hen the byte count is again .

~949S~

~ 38 -, "equal", signal SXFR goes high. It stops the writin~ into the controller memory and it releases the controller to continue its sesuential polling ot the port buffers~
Transfer byte counter 212 supplies the buffer address for each data byte stored by the 32 x 8 random access port =
buffer memory 208. In the follo~ing dis(_ussion it must be ~ept in mind that RE~D and WRITE commands are issued with respect to controller ~emory 170, rather than with respect to the port buffer memory. STi~h:in the framework of these commands, the port buf~er memor~ has four separate modes of o~eration:

(1) READ co~m~nd. Data bytes, (not cont:rol bytes), flow from controller memory 170 to port buffer memory 208. The port buffer r.emory is heing written into.
(2) READ com~and. Data bytes flow from port buffer memor~ 208 to external subsystem SS~. The contents ~;
of the ~ort buffer memory are being read out. ~`
(3~ WRITE command. Data bytes flo~ ~rom external subsystem SSl to port buffer memor~ 208. The port buffer memory is being written into.
(4) ~RITE com~and. Data bytes flow from port buf~er --memory 208 to controller memory 170. The contents of the port buffer memory are being read out.

The READ and ~RITE operations outlined above will f become clear wi~h reference to Figs. ll and 12 in which ~
~aveforms are illustrated for a number of pertinent signals. :-The encircled numbers on the time scale at the bottom of these Figures re er to selected points in time. These are set orth in greater detail below in the respective tabulations of the complete sequ~nce of events of both operations.
.

¢~8 L~
).r';~' ~' WRITE OPERATION
r 1. Port bulfer ready for transfer, READ or WRITE: RDY.
2. First control byte entered: LDl RDY.

3. Second control byte entered: LD2 RDY.
c~

4. Data byte(s) entered: LD3 XFR. -~

5: Byte count equal ~o control word byte count.BTEQ.

6. Ready disabled-latched: RDY = BTEQ XFR R~

7. Port address not asserted: PADR.

8. Transfer request-latched: TREQ = RDY PADR~

9. Port address asserted: PADR.
I0 10. Transer enabled: XFR ~& SXFR) = TREQ-PADR. '~
11. Port address held.
12. Transler star.ing address.
13. As long as SXFR is true (SXFR), controller controls transfer of data from buffer memory ~o system memory at con~roller clock rate. The port's "BTEQ" terminates transfer when:
14. Byte count equal to control word byte count: BTEQ. ~-1;. Ready enab'ed: RDY = BTEQ XFR.
Ready and transfer request latches cleared. ~' In the ~RITE operation tabulated above and illustrated in Fig. 11, the initial events apply to the first stage of the transfer lin~ established by the port buffer, wherein the latter interfaces with external subsystem SSl. As shown, the "ready" signal RDY is asserted, indicative of the fact 25 that the port buffer is ready for either a READ or a WRITE r~
transfer. Initially, the first control by~te PC-l is placed on information bus 188, comprising signals ED0 - ED7. ~
Thereafter, signal LDl is asserted over a separate line. This ~;
occurs at point (2) in Fig. 11 and effects the latching of 30 control byte PC-l into control byte latch 190 on the rising _' pulse edge.

~,...
... , , . . . ... . , . , _ . . .. . ~

As previously explained in connection with the discussion of Fig. 10, the first control byte PC-1 contains a READ/WRITE bit as well as the number count of bytes to be transferred. The assertion of signal LD1 at point (2) concurrently moves this information -to the input of byte count comparator 214 The 5 bits that define the number count now remain a-t -the inpu-t of the byte count comparator until such time as the e~ternal subsystem provides control signal LDl again, i.e. preceding the subsequent data transfer. At such time, the assertion of control signal LDl will place a new count into latch 190 and into compara-tor 214.
The second control byte PC-2 is subsequently placed on bus 188. The subsequent control signal, i.e.
signal LD2, is also provided on a separate control line by the subsystem. When the signal LD2 is asserted, as shown at point (3) in Fig. 11, control byte PC-2 is latched into control byte latch 192 on the rising pulse edge.
Subsequent informa-tion transferred by bus 188 consists exclusively of data bytes. Upon the assertion of signal LD3 at each point (4) in Fig. 11, bidirectional switch l9A is opened and the first data byte is placed into port buffer memory 208. Specifically, a pulse is generated internally on the output of NAND gate 428.
This pulse, which is illustrated in Fig. 7, effects the actual writing of data into port buffer memory 208.
As signal LD3 is reset, transEer byte counter 212 is incremented, such that the second data byte will be placed into the nex-t location of port k,uffer memory 208.
Each time counter 212 is incremented, a new byte count is placed on the input of byte count comparator 214. A continuous comparison is made between the number count stored in the comparator and the count of the newly transferred byte.

!

-95~ ,, !

function of the controller clock period, the byte count and the nu.7nber of port buffers at tne node. The total transfer period, i.e. the time in wnich the port buffer is not available to the external subsystem, is indicated by 5 the interval during which signal RDY is low, i.e. from ~
point (5) to point (14) in Fig. 11. The ,~ctual transEer, L_ the setup time in the controller and the movement of data all take place while the port buffer ad~ress is held high ~PADR), i.e. from point (11) to point (15) in Fig. 11.
The remainder of the period during which RDY is low, point (5) to point (9) in Fig. 11, represents the time it takes, during ,he polling of the port buffers by the controller, to reach this port buffer after its transier request has been asserted. This latter time period is variable to the extent of the nu~ber of other port buf ers requesting concurrent transLers in the sa~e controller polling cycle.
It ~.7ill be noted ~hat there is a significant difference between the ti.~.e noted with respect to Figure 11 to enter data from an external subsystem to the pOl.t buffer, and the 20 time required to transfer data from the port buffer to the ;~
controller~ In a standard, and practical~ application, the data ~ay be entered into the port buffer under 8080 or 8085 type microprocessor (soft~.7are) control. By contrast, the transfer bet7Jeen the port buffer and t:he controller occurs under hardware control. In the pr~iferred embodi.ment of the invention, the trans er rate of the port buffer/ ~`
controller will be at least eight times faster than the ~;
external subsystem/port buffer transfer capability.
Transfer signal XFR is generated as the result of an existing trans~er request TR~Q and the port buffer's address PADR. Signal ~R, in turn, senerates signal SXFR, ~.7hich stops the controller polling at the address of this port buffer. Transfer Oc data between the port buffer and the controller ta~es lace while the address is held. A unique timing rela.ionship must thus exist between TREQ and PADR, ,C ' ~:~.9'~5~

ls~q~r-ool 3 before XFR can be generated. This will be clear Wit]l ~
reference to the discussion above concerning the generation ~D
of signal TREQ. PADR must not be coincident with the initial transition of the ready latch. The setting of the transfer request latch, (see Fig. 5D), is blocked unless PADR is in the low state. This requirement prevents a ~;
condition that could occur where, if PADR were about to yo _~
low again as TREQ goes high, there may be insufficient time for SXFR to stop the polling sequence The circuit described effectively prevents such an ambiguous condition frcm arising.
Chip select signal CS for port buffer memory 208 is generated by signal LD3 and it is therefore synchronous with the latter. ~rite signal M5~R, applied to memory 20 is also generated by L~3. However, MWR is delayed an appropriate time by the circuit shown in Fig. 5E, as explained in connection with the discussion of that Figure.
Read signal ,~D, applied to memory 208, remains high while ~.;
the external subsystem is writing data into the port buffer. ~;
At point (9), transfer signal XFR is asserted and remains positive until the end of the negative RDY signal, which occurs at point (14). This causes SXFR (Fig. 6B) to go low and stop counter 524. As a consequence, the port address is held duxing this interval and signal PADR is r`
asserted throughout. As long as signal XFR remains high, the controller controls the transfer of data from port buffer *
memory 208 to con~roller memory 170.
As indicated in Fig. 11, a delay occurs between point (9) ~5 ancl the transfer of the first data byte to the controller memory, shown by the first CS pulse. This delay takes into account the interval required for the specified controller ~~
memory address to be loaded. The port buffer polling sequence and the loading operation must both occur before data bytes can actually be transferred to controller 3~ memory 170.
~ < _ 5~3 As successive bytes are transferred in clock pulse synchronism from the port buffer rnemory into the controller memory, tr~nsfer byte counter 212 is incremented. When the fourth byte is transferred, in the example under conslderation at point: (14), pulse BTEQ is again generated. The function of this pulse at this particular time is to terminate the WRITE
operation by terminating further data transfers between the port buffer and the controller memory.
Signal RDY again becomes positive at point (14) and XFR goes low while SXFR goes high. PADR goes low and hence the port buffer address polling is again allowed to continue.
It should be noted that in the WRITE
operation described above there is no participation by the external subsystem after the last data byte is entered. It is only necessary that the external subsystem test the state of the ready line, (RDY), when another transfer is desired.
READ OPERATION
1. Port ready for transfer, READ or WRITE. RDY.
2. First control byte entered: LDl RDY.
3. Second control byte entered: LD2-RDY.
4. Ready disabled-latched: RDY = LD2-RDY-R/W +
(BTEQ-XFR-R/W).
5. Port address not asserted: PADR.
6. Transfer request-latched: TREQ = RDY-PADR.
7. Port address asserted: PADR = PA0-PAi-PA2-PA3.
8. Transfer enabled: XFR (& SXFR) = TREQ-PADR~
9. Port address held (stop counter in controller).

10. Transfer starting (source) address: XFR.

11. As long as SXFR is true (SXFR), controller controls transfer of data to buffer memory at controller clock rate. Port's "BTEQ" terminates transfer when:

12. Byte count equal to control word byle count: BTEQ.

13. Ready enabled: RDY = BTEQ-XFT.
Ready and transfer request latches cleared.
~( ~:~9'~S~3 - ~5 -

14. Data transferred to subsystem, each byte: LD3-XFR.

In the READ operation tabulated above and illustrated in Fis. 12, control bytes PC-l and PC-2 are transferred into the port buffer in identical manner as was the case 5 for the WRITE operation. At this point, the port buffer ~
knows that the READ request has been entere~d (R/W = 1). ~' ~ ..
It also knows how many bytes are to be read out from the controller memory and the address where theise bytes are stored. As before, control bytes PC-l and PC-2 are latched in on the rising (leading) edge of pulses LDl and LD2 respectively, which occur at points (2) and ~3) respectively ~~
in Fig. 12. Once these control bytes have been transferred to the port buffer from the external subsystem, "ready"
signal ~Y goes low. The first stzge of the 2-stage transfer link es~ablished by the port buffer is now cut off by the low state of RDY so that communications bet:ween the external subsystem and the port buffer are disabled. Simultaneously, ~-the second s~age of the transler link is enabled, permitting ~_ communication between the port buffer and ~:he controller.
The period during which RDY remains :Low, i.e. the time interval between points (4) and (12~ in Fig. 12, is a function of the number of active port buffers simultaneously requesting access to the data contained in the controller .-memory, as well as the number count of each. In one example `~
25 of the invention, with four port buffers on the bus, the ~-average access time may be on the order of 200 microseconds. ~~
At point (7) port address signal PADR for ~his port buffer is asserted and will be held until the dat~3 transfer from the controller to the port buffer is complete. Simultaneously ~
30 with PADR, transfer signal XFR goes high and enables ther~-transfer of the requested information from the controller ~æ
memory to the port buffer. - j-_ _;

18MT-00]3 Successive da-ta bytes are read out of controller ~
memory through oidirectional switch 204 and into port r buffer memory 208. Their location in controller memory 170 is determined hy the starting address pre~7iously latched into latches 190 and 192, which determines the initial count of controller memory address counter 172. Successive bytes so transferred to the port buffer are counted by transfer byte counter 212 and compared by comparator 214 against the number count previously loaded in by control byte PC-l via latch 190. When the proper number of data bytes has been transferred, signal BTEQ is generated at point (12). This results in the termination of transfer ~' by resetting the transrer request latch 306, which in turn lowers sign21 X~R, raises SXFR, disables the READ operation

15 of con~roller memory 170 and releases the ?olling coun~er 52~1.
,he foregoing action causes signal RDY to i~e asserted so as to close the second stage and open the first stage of the transfer lin~. ~ore specifically, further communications bet~een the controller and the port buffer are shut off and 20 communications between the port bufler and the external subsi~stem are enabled.
Since the subsequent transfer of data from the port buffer to the external subsystem may occur asynchronously, the data read out from the controller memory into the port 2~ buffer memory during the first portion of 1:he READ operation ~.
is held in the port buffer memory until such time as it is read out upon the initiative of the ex-ternal subsystem.
Such readout occurs by way of bidixectiona]. s~itch 194 and data bus 188, ~Jhenever signal LD3 is asserted by the 30 external subsystem. Thus, on each rising edge of an LD3 pulse a data byte is placed on the data bus to the ex.ernal ~
subsystem. I~hile LD3 is held lli~h, the ext:ernal subsystem ææ
may read the cata byte. Upon each falling edge of the LD3 ,:
pulse transfer byte counter 212 is incremerlted. Upon the 35 rising edge Or ~he ne.~t LD3 pulse the subsequent byte ~ill L

.

1~949SB

be read out.
It ~ill be clear from the foregoing explanation, that ~_ the readout or ~ata bytes from the controller memory occurs in synchronism ~;ith the controller cloc~. ~lowever, the 5 subsequent readout from the port buffer memory into the external subsystem is cletermined by the timing of the LD3 pulse provided by the external subsystem. Since the external subsystem originally ~rovidea the nu~ber count r defined by control byte PC-l for the READ operation, a 10 count of the data bytes transferred from port buffer memory 208 to the external subsystem is not made. Accordingly no BTEQ si~nal is ~enerated at the conclusion of the REA
operation.
The READ operation discussed above further evidences 15 the closel~ lin~ed operational relationship between the port buffer and the controller. The controller memory clock is used to read d~ta bytes out of the controller memory and into the ~ort buffer and it thus determines the timing of ~-this operation. The clock also controls port address 20 memory counter 524 which sequentially polls successive port '~
buffers and which stops at a given port buffer address to permit a da~a transfer to be completed. However, the -controller does not keep track of the number of data bytes _ read out of the controller memory and it depends on the port ~~
buffer, specifically on transfer byte counter 212 and comparator 214, to do so.
i~hen the signal derived at -the output of EXCLUSIVE OR
gate 390 is high, i.e. when LD3X ~ PMCS, a low signal is ;~
applied to port buffer memory chip select input CS which 30 serves to enable ~emory 208. The l`lRD input of port buffer memory 208 imposes a further condition on the operation of this memory. Specifically, the output of EXCLU.SIV~ OR gates 390 and 336 must both be high before memory 208 is enabled. The additional condition thus requires that ~he inputs of gate 386 35 not be the same, i.e. R~W ~ XFR. Since XFR is high only for -4~S8 a transfer in the second stage of the transfer link, i.e. between the port buffer and the controller memory, (modes (1) and (4) above), the application of a signal to input MRD assures that the port buffer is not simultaneously involved in a data transfer in bot}l stages, i.e. with both the controller and the subsystem.
Transfer request latch 306, (Fig. 5D), toge-ther with ready latch 284 (Fig. 5A), prepares the port buffer for synchronization wi-th the controller so that a data transfer may properly take place. Both oE these latches constitute positive edge triggered flip flops in the preferred embodiment of the invention. This means that when the clock input C of either latch goes from ZERO to ONE, the Q output will be forced to correspond to the D input, in this case a high signal level.
In order for ready latch 284 to be latched, the conditions set forth below, which follow from the previous discussion, must be present:
LD2(1`) RDY R/W + BTEQ(l~) XF~' R/W
If either of the conditions above is present, transfer request latch ,06 and signal TREQ can be triggered by ready latch 284 via NAND gate 300 and inverting buffer 304.
Such triggering will occur only if the controller is not currently addressing the port buffer, as determined 25 by signal PADR in Fig. 5A. Both the ready latch 284 and the transfer request latch 306 are reset at the completion of a data transfer, i.e. when all data bytes have been transferred, at which time signal BTEQ is generated.
As already discussed, transfer request signal 30 TREQ will be generated by latch 306 only if RDY is disabled and the port buffer address i5 not present.
This is an important requirement since is provides adequate time for transfer signal XFR to stop port address counter 524, (Fig. 6B), X

~4~

at the address of the particular port buf.fer that is to be addressed. Signal XFR, in turn, goes true ~Jhen the appropriate port address PADR comes up only if all conditions for a data transfer between the con-troller memory S and the addressed port buffer have been previously met. _ ~ ~
In a preferred embodiment of the inven~ion a maximum of ff`
sixteen substantially identical port buffers are connected to the common node bus of each node. T~e respective port buffers differ from each other only in the decoding circuitry 10 associated with each port buffer, which decodes the port buffer's unique address from signals PA~ - PA3 to obtain signal PADR.
As discussed above, controller 18 includes a clock ~
oscillator 495 and a connected timing circuit 507, which ~h 15 act to synchronize the various functions of the controller, as well as the data transfers to and from the controller memory. The wa~reforms generated by thPse circuits are best explained with reference to Fig. 8. As shown, clock signal CLK, which is derived at the outout of oscillator 495, has 20 a frequency twice that of signal HAC~K, which is obtained ~2 at the Q output of flip flop 508 of timing circui~ 507.
The latter flip flop can change states only when the clock signal changes from logic O~E to logic ZERO, or on the fal~ing edge of the CLK waveform applied to the C input of 3 25 flip flop 508. As shown, a slight delay is introduced at this point so that the rising edge of the HACLK waveform trails sli~htly behind the corresponding falling edge of CLK. ~s the HACLK sisnal is applied to clock input C of port address counter 524, the latter counts continuously from 0 - 15 to 30 poll every port bufrer on node bus 15. If a port buffer is ready to transfer, (as indicated by signal TREQ, Fig. 5D), ~`;
counter 524 will continue to count until that port buffer's ~Q
address is reached. At that time the port buffer generates a si~nal SXF~, (Figs. 5D and 8), which will force port address counter 524 to stcp at that address and enable flip flop 512, !~

s~ i (Fig. 6~), to cn2nge states on the next rising pulse edge ;~
of signal HACL~. ~he Q output of flip flop 512 remains high until sisnal SXFR again qoes high and resets this flip flo?.
The hish signal sta~e of output Q oE flip flop 512 ~ ~ ~i enables fli flop 514 to change state on the next risingL_ pulse edge of tne ~CLK signal. As is apparent from Fig. 8, the time difCerence between the change of state of flip flops 512 and 51~ i5 the pulse interval for signal LADR
which is derivec at the output of NA~D gal-e 516. This pulse loads the ini~ial 10-bit data address into counter units 450, 452 and 4-~ o~ memory address counter 172. When flip ~lop 51~ changes states, its Q output goes high. This ~
action enables fli? _lop 510, due to the connection of its ~R
reset input R to the Q output of Clip flop 514. Thus, flip flo? 5~0 now changes state with every falling pulse edge o- the CL:~ sisnal.
The Q ou.?u, of flip flop 510 generates signal CS, shown in Fig. 8, ~Jhich is applied to the appropriately designated inpu~s of the respecti~e memory chips of controller me-.ory 170. The corresponding signal PCMS
in Fig. 5C is ap?lied to chip select input CS of port buffer memory 208, by ~la~ of EXCLUSIVE OR gate 3'30 and inverting buffer 378. ~~
As explained in connection with the discussion of Fig.
5C, signal P~SCS is also used to pulse port buffer rnemory , inputs ,"RD on a ~ITE instruction. The 52 output of flip flop S10 is combined with signal CLK in ~A~D gate 518 to provide signal C~ RT at its output, shown as signal MWRT and WRT
in Fig. 8. One functio3l of signal Ci~lr~RT is to clock controller memorv address counter 172 on a rising pu:Lse edge, as best shown b~r the 2~rc?~iatel~ desisna~ed ~.emory input signal waveforms o' Fic. 8. ~ further func.ion of this signal is to clock input ~ o$ ?ort buffer me~ory 508 on a READ command.
Signal ~ is a~plied to input R/W of the res~ective memory L

~9 3L~

chips of controller memory 170, which are enabled by the application of each WRT pulse.
Controller ~emory address counter 172 comprises three synchronous 4-bit binary counter units 450, 452 5 and 454 in the preferred embodiment of th,e invention, _ - _ which are cascade-connected for a 10-bit output signal.
When input GD goes to logic ZERO, signals SA0 - SA9 load these counter units with the initial data address, i.e. the starting address originally provided by c:ontrol bytes 10 PC-l and PC-2. Thereafter, the output of each of these counter units is incremented whenever input +l of counter unit 450 sees a positive going transition of signal CMWRT.
The output of the respective address counter units is applied to the eight memory chi~s of controller memory 170.
15 In tr.is wai, the bytes er.~ered consecutively on lines SD~ -SD9 will be stored at consecutive addresses i.n the respective memory chips. The latter form a 1024 byt:e random access memory. The sa~e 10-bit address is placed on the address input A~ - A9 of each chip by controlle~ memory address 20 counter 172. I~hen chip select signal CS goes low, the ~
input address is latched into each memory chip. The output ~-DO of each chip is enabled if R/~ remains in a high state, representative of a READ operation. If signal R/W goes to ~-ZERO, chip output ~0 is disabled and data can then be written 25 into the chip during a ~RITE operation.
The time relationships of the respective signals that control the operation of memory 170 will become clear from a consideration of Fig. 9, which illustrates in greater detail some of the waveforms shown in Fis. 8. l`he various values 4 30 of specific time intervals callea out in these Figures refer to design margins adopted for a s?ecific implementation of ~i the invention and are beyond the scope of the present discussion. It is noted that signal CS has a period of 2t, t~here t = l/foSC. Although so~e waveforms appear in both of 35 these Figures, they are not drawn to the same time scale. To 1, provide a frame of reference, point A is indicated in both L
~ .

- 52 ~

Figures and marks the instant when the address is latched into controller memory 170.
Assuming that a valid address is applied to memory chips 460 - 474 of controller memory 170, the memory chip select signal CS is seen to latch this address into the memory on the falling edge of the waveform. As indicated in Fig. 9, valid data is available from the port buffer at this time for readout from the latter. This data is written into the addressed memory location upon the next-occurring rising edge of WRT. Thereafter the address is incremented by address counter 172, as schematically indicated by the zero point crossover of waveforms A~ - A9. Upon the occurrence of -the next falling edge of signal CS, the incremented address is latched into controller memory 170. Subsequent valid data which is read out of the port buffer can be written into the newly addressed memory locations.
During the readout of controller memory 170, the address of the particular memory location which is to be read out, is again latched into this memory on the falling edge of waveform CS, i.e. at point A. Shortly thereafter, data from the addressed location becomes available and it is read out on the next falling edge of clock pulse CLK and transferred to the port buffer.
From the foregoing explanation of a preferred embodi-ment, it will be clear that the invention lends itselfto different variations, changes and substitutions. For example, the invention is not limited to the use of 16 port buffers per communication node. Thus, counter 524 may be modified to provide expanded port addressing which could accommodate more than 16 port buffers on the common node bus. It is also feasible to assign more than one address -to a given port buffer in order to enhance its priority with respect to other port buffers regarding access to the controller. In such a case, the decoder of the port buffer in question will provide a PADR signal whenever any 35~

- 52 ~ 18MT-0013 Figures and marks the instan-t when the address is latched into controller memory 170.
Assuming that a valid address is applied to memory chips 460 - 474 of controller memory 170, the memory chip select signal CS is seen to latch this address into the memory on the falling edge of the waveform. As indicated in Fig. 9, valid data is available from the port buf-fer at this time for readout from the latter. This data is written into the addressed memory location upon the next-occurring rising edge of WRT. Thereafter the address is incremented by address counter 172, as schematically indicated by the zero point cxossover of waveforms A0 - A9. ~pon the occurrence of the next falling edge of signal CS, the incremented address is latched into controller memory 170. Subsequent valid data which is read out of the port buffer can be written into the newly addressed memory locations.
During the readout of controller memory 170, the address of the particular memory location which is to be read out, is again latched into this memory on the falling edge of waveform CS, i.e. at point A. Shortly thereafter, data from the addressed location becomes available and it is read out on the next falling edge of clock pulse CLK and transferred to the port buffer.
From the foregoing explanation of a preferred embodi-ment, it will be clear that the inven-tion lends itself to different variations, changes and substitutions. For e~ample, the invention is not limited to the use of 16 port buffers per communication node. Thus, coun-ter 524 may be modified to provide expanded port addressing which could accommodate more than 16 port bufEers on the common node bus. It is also feasible to assign more than one address to a given port buffer in order to enhance its priority with respect to other port bufEers regarding access to the controller. In such a case, the decoder of the port buffer in question will provide a PADR signal whenever any 9~

- 5~ - 18MT-0013 It will be clear from the discussion above that the communication system disclosed herein provides an economical, simple and flexible arrangement for dealing with the problem of enabling the respeclive componen-ts of a distributed control system to communicate with each o-ther without any interruption of the ongoing operations.
As discussed above, prior art systems of this type are forced to establish multiple priority levels to deal with in-terruptions of ongoing operativns, which increases the complexity and cost of implementing, operating and maintaining such systems. Moreover, the present invention avoids contention between competing subsystems for access to the communication lines and it can readily accommodate additions and deletions with respect to the distributed control arrangement with which it is associated.
From the foregoing discussion of the comrnunication system which forms the subject matter of. the present invention, it will be apparent that numerous substitutions, variations, changes and equivalents will now occur to those skilled in the art, all of which fall within the true spirit and scope embraced by the inventi.on. Accordingly, it is intended that the invention be limited only by the scope o-E the appended claims.

Claims (30)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. In a communication system for a distributed control arrangement adapted to control the operation of a plurality of operating units of a common installation, each of said operating units being under the control of a set of subsystems adapted to perform specific control functions relative to the corresponding operating unit;
a plurality of communication nodes each corres-ponding to a separate one of said operating units, each of said nodes being coupled to the set of subsystems that exercise control over the corresponding operating unit;
a separate secondary station coupled to each of said nodes;
each of said nodes including a common node bus;
the secondary station and respective ones of the set of subsystems associated with a node individually constituting separate circuits external to said node, each of said external circuits including a local data processor and being adapted to communicate through said node bus;
a data link interconnecting respective nodes through the secondary station associated with each node;
and a primary station coupled to said data link and including a data processor, said primary station being adapted to address respective ones of said secondary stations through said data link in accordance with a predetermined protocol and a sequence determined by said primary station;
whereby said primary station upon its own command is capable of communicating with respective ones of a selectively variable number of nodes coupled to said data link to transmit or receive information with respect to selected subsystems associated with each of said nodes, said primary station being adapted to prevent contention between competing nodes for access to said data link.

2. A system in accordance with claim 1 wherein each of said nodes further comprises:
a controller coupled to said common node bus;
a plurality of port buffers each coupled to said bus and to a separate one of said external circuits, each of said port buffers being adapted to establish a 2-stage bidirectional transfer link between its coupled external circuit and said controller wherein said port buffer is present in both stages to provide intermediate data storage and to translate between the protocol of the external circuit and the protocol of said node; and said controller including means for sequentially polling said port buffers;
whereby said controller periodically sets the conditions for each port buffer to establish its transfer link.

3. A system in accordance with claim 2 wherein one stage of each of said transfer links comprises means for providing bidirectional data transfers between the coupled external circuit and its corresponding port buffer timed by said external circuit; and wherein the second stage of each of said transfer links comprises means for providing bidirectional data transfers between said port buffer and said controller by way of said bus timed by said controller.

4. A system in accordance with claim 3 wherein said one stage of each of said transfer links is further adapted to perform data transfers from the coupled external circuit to its corresponding port buffer under port buffer control.

5. A system in accordance with claim 4 wherein said controller includes means for generating clock pulses;
said means for providing data transfers in said second stage of each of said transfer links timed by said controller including means for transferring said information in clock pulse synchronism; and wherein data transfers in said one stage of each of said transfer links may be performed asynchronously with respect to said clock pulses.

6. A system in accordance with claim 4 wherein said intermediate data storage in each of said port buffers comprises a port buffer memory;
each of said port buffers further comprising:
first bidirectional switch means connected between said port buffer memory and the corresponding external circuit;
second bidirectional switch means connected between said port buffer memory and said controller; and means for enabling said first and second switch means during mutually exclusive time intervals to stagger the data transfer operations in the respective stages of said transfer link.

7. A system in accordance with claim 6 wherein data and control information is organized into bytes, each data transfer between an external circuit and said controller being preceded by a pair of control bytes generated by said subsystem;
each of said port buffers further comprising:
latch means for temporarily storing said control bytes; and means operative during each data transfer for directing said control bytes into said latch means and for directing said data bytes into said port buffer memory through one of said switch means.

8. A system in accordance with claim 7 wherein said control bytes define at least the direction of the data transfer and the number count of data bytes to be transferred;
each of said port buffers further comprising:
means responsive to said defined direction of data transfer to determine the order in which said first and second switch means are enabled;

means operative during data transfers performed under port buffer control for counting the number of data bytes transferred;
means for comparing the count of transferred data bytes with said number count entered by said control bytes; and means for terminating the transfer of data bytes when equality of the compared counts is reached.

9. A system in accordance with claim 8 wherein said control bytes further define a starting address;
said controller comprising:
means for generating clock pulses;
a controller memory;
said means timed by said controller including a controller address counter for sequentially addressing successive controller memory locations in clock pulse synchronism, said controller address counter being respon-sive to said control bytes to begin said sequential addressing at said starting address; and means responsive to said defined direction of data transfer to write said data bytes into, or to read said data bytes out from, said addressed controller memory locations.

10. A system in accordance with claim 4 wherein said control bytes are loaded into each port buffer by control signals generated by the corresponding external circuit;
each of said port buffers comprising means responsive to said control signals and to said defined direction of data transfer to generate a transfer request;
said sequential polling means comprising a port address counter for generating signals adapted to address successive port buffers of said node;
means for initiating the requested data transfer if a transfer request generated by a port buffer is pending when said port buffer is addressed in sequence by said port address counter; and means for interrupting said sequential addressing of said port buffers for the duration of each data transfer;
whereby contention between competing port buffers for access to said common node bus is effectively prevented by said controller.

11. A system in accordance with claim 9 wherein said control bytes are loaded into each port buffer by control signals generated by the corresponding external circuit;
each of said port buffers comprising means responsive to said control signals and to said defined direction of data transfer to generate a transfer request;
said sequential polling means comprising a port address counter for generating signals adapted to address successive port buffers of said node;
means for initiating the requested data transfer if a transfer request generated by a port buffer is pending when said port buffer is addressed in sequence by said port address counter; and means for interrupting said sequential addressing of said port buffers for the duration of each data transfer;
whereby contention between competing port buffers for access to said common node bus is effectively prevented by said controller.

12. A system in accordance with claim 10 wherein said external circuits of at least one of said nodes further include at least one peripheral station adapted to communicate through said node;
said last-recited node further comprising a port buffer corresponding to said peripheral station; and each of said port buffers including means for decoding the count of said port address counter, said port buffers being substantially identical to each other except for said decoding means.

13. A system in accordance with claim 11 wherein said external circuits of at least one of said nodes further include at least one peripheral station adapted to com-municate through said node;
said last-recited node further comprising a port buffer corresponding to said peripheral station; and each of said port buffers including means for decoding the count of said port address counter, said port buffers being substantially identical to each other except for said decoding means.

14. A communication node for enabling a set of subsystems external to said node to communicate through the latter, each of said subsystems comprising a circuit including local data processing means for performing a specific control function relative to an operating unit responsive to said set of subsystems;
said communication node comprising:
a common node bus;
a controller coupled to said bus;
a plurality of port buffers each coupled to said bus and to a corresponding one of said subsystems, each of said port buffers being adapted to establish a 2-stage bidirectional transfer link between its corresponding subsystem and said controller wherein said port buffer is present in both stages to provide intermediate data storage and to translate between the subsystem protocol and the protocol of said node; and said controller including means for sequentially polling said port buffers;
whereby said controller periodically sets the conditions for each port buffer to establish its transfer link.

15. A communication node in accordance with claim 14 wherein one stage of each of said transfer links comprises means for providing bidirectional data transfers between the coupled subsystem and its corresponding port buffer timed by said subsystem; and wherein the second stage of each of said transfer links comprises means for providing bidirectional data transfers between said port buffer and said controller by way of said bus timed by said controller.

16. A communication node in accordance with claim 15 wherein said one stage of each of said transfer links is further adapted to perform data transfers from the coupled subsystem to its corresponding port buffer under port buffer control.

17. A communication node in accordance with claim 16 wherein said controller includes means for generating clock pulses;
said means for providing data transfers in said second stage of each of said transfer links timed by said controller including means for transferring said information in clock pulse synchronism; and wherein data transfers in said one stage of each of said transfer links may be performed asynchronously with respect to said clock pulses.

18. A communication node in accordance with claim 16 wherein said intermediate data storage in each of said port buffers comprises a port buffer memory;
each of said port buffers further comprising:
first bidirectional switch means connected between said port buffer memory and the corresponding subsystem;
second bidirectional switch means connected between said port buffer memory and said controller; and means for enabling said first and second switch means during mutually exclusive time intervals to stagger the data transfer operations in the respective stages of said transfer link.

19. A communication node in accordance with claim 18 wherein data and control information is organized into bytes, each data transfer between a subsystem and said controller being preceded by a pair of control bytes generated by said subsystem;
each of said port buffers further comprising:
latch means for temporarily storing said control bytes; and means operative in conjunction with each data transfer for directing said control bytes into said latch means and for directing said data bytes into said port buffer memory through one of said switch means.

20. A communication node in accordance with claim 19 wherein said control bytes define at least the direction of the data transfer and the number count of data bytes to be transferred;
each of said port buffers further comprising:
means responsive to said defined direction of data transfer to determine the order in which said first and second switch means are enabled;
means operative during data transfers performed under port buffer control for counting the number of data bytes transferred;
means for comparing the count of transferred data bytes with said number count entered by said control bytes;
and means for terminating the transfer of data bytes when equality of the compared counts is reached.

21. A communication node in accordance with claim 20 wherein said control bytes further define a starting address;
said controller comprising:
means for generating clock pulses;
a controller memory;
said means timed by said controller including a controller address counter for sequentially addressing successive controller memory locations in clock pulse synchronism, said controller address counter being responsive to said control bytes to begin said sequential addressing at said starting address; and means responsive to said defined direction of data transfer to write said data bytes into, or to read said data bytes out from, said addressed controlled memory locations.

22. A communication node in accordance with claim 16 wherein said control bytes are loaded into each port buffer by control signals generated by the corresponding subsystem;
each of said port buffers comprising means responsive to said control signals and to said defined direction of data transfer to generate a transfer request;
said sequential polling means comprising a port address counter for generating signals adapted to address successive port buffers of said node;
means for initiating the requested data transfer if a transfer request generated by a port buffer is pend-ing when said port buffer is addressed in sequence by said port address counter; and means for interrupting said sequential addressing of said port buffers for the duration of each data trans-fer;
whereby contention between com.peting port buffers for access to said common node bus is effectively prevented by said controller.

23. A communication node in accordance with claim 21 wherein said control bytes are loaded into each port buffer by control signals generated by the correspond-ing subsystem;
each of said port buffers comprising means responsive to said control signals and to said defined direction of data transfer to generate a transfer request;
said sequential polling means comprising a port address counter for generating signals adapted to address successive port buffers of said node;
means for initiating the requested data transfer if transfer request generated by a port buffer is pending when said port buffer is addressed in sequence by said port address counter; and means for interrupting said sequential addressing of said port buffers for the duration of each data transfer;
whereby contention between competing port buffers for access to said common node bus is effectively prevented by said controller.

24. A communication node in accordance with claim 22 wherein at least one peripheral station external to said node is adapted to communicate through said node;
said node further comprising a port buffer coupled between said bus and said peripheral station; and each of said port buffers including means for decoding the count of said port address counter, said port buffers being substantially identical to each other except for said decoding means.

25. A communication node in accordance with claim 23 wherein at least one peripheral station external to said node is adapted to communicate through said node, said node further comprising a port buffer coupled between said bus and said peripheral station;
and each of said port buffers including means for decoding the count of said port address counter, said port buffers being substantially identical to each other except for said decoding means.

26. In a communication node:
a common node bus;
a controller coupled to said bus;
a plurality of port buffers each coupled to said bus and to an external circuit, each of said port buffers being adapted to established a 2-stage bidirectional transfer link between its coupled external circuit and said controller wherein said port buffer is present in both stages to provide intermediate data storage and to translate between the protocol of said external circuit and the protocol of said node;
a first stage of each of said transfer links comprising means timed by said external circuit for providing bidirectional data transfers between said external circuit and its corresponding port buffer;
the second stage of each of said transfer links comprising means timed by said controller for providing bidirectional data transfers between said controller and said port buffer;
said controller comprising:
means for sequentially polling said port buffers including a port address counter for generating a count adapted to address successive port buffers of said node;
and means operative during each data transfer for holding said port address counter at the count of the addressed port buffer for the duration of said transfer;
whereby said controller periodically sets the conditions for successive port buffers to establish a transfer link.

27. Apparatus in accordance with claim 26 wherein said controller includes means for generating clock pulses;
said means timed by said controller including means for carrying out said data transfers in said second stage in clock pulse synchronism; and means for carrying out said data transfers in said first stage asynchronously with respect to said clock pulses.
28. Apparatus in accordance with claim 27 wherein data and control information is organized into bytes, each data transfer through said transfer link being preceded by first and second control bytes provided by said external circuit and defining at least the direction of data transfer by means of a read/write bit and the number count of data bytes to be transferred;

Claim 28 continued:
each of said port buffers further comprising:
a port buffer memory adapted to provide said intermediate data storage;
an information bus coupled to the corresponding external circuit and adapted to pass said control and data bytes therethrough;
first and second latch means coupled to said information bus;
means responsive to first and second control signals generated by said external circuit for loading said control bytes into said first and second latch means respectively;
first switch means coupled between said port buffer memory and said information bus;
second switch means coupled between said port buffer memory and said controller;
a transfer tyte counter coupled to said port buffer memory for addressing the latter and for counting data bytes transferred thereto;
a comparator coupled to said first latch means and to said transfer byte counter, said comparator being adapted to generate a byte count equal signal when the count of data bytes actually transferred equals said number count;
third latch means for generating a transfer request signal;
means responsive when said transfer request signal is high for providing a transfer signal when the address of said port buffer is next generated in sequence by said port address counter;
a ready circuit adapted to provide a ready signal indicative of the state of readiness of said transfer link to transfer data;
means for setting said ready circuit when said byte count equal signal and said transfer signal are both high;

said third latch means being adapted to provide said high transfer signal only when said ready signal is low;
means for enabling said second switch means when said transfer signal is high; and means responsive to a third control signal generated by said external circuit for enabling said first switch means when said transfer signal is concurrently low;
whereby said first and second switch means are enabled at mutually exclusive time intervals to stagger the transfer of data in said first and second stages.

29. Apparatus in accordance with claim 28 and further including means for terminating the transfer of data bytes, said last-recited means comprising:
means for resetting said ready circuit when said second control signal, said ready signal and a read/write signal responsive to said read/write bit are concurrently high, or when said byte count equal signal in high while said transfer signal and said read/write signal are concurrently low;
means for resetting said third latch means when said byte count equal signal and said transfer signal are concurrently high; and means for resetting and for initializing said transfer byte counter when said byte count equal signal is high or when said second control signal and said ready signal are concurrently high.
30. Apparatus in accordance with claim 29, wherein said control bytes further define a starting address and wherein said controller further comprises:
a controller memory;
a controller address counter for sequentially addressing successive controller memory locations in clock pulse synchronism, said controller address counter being coupled to said first and second latch means and being responsive to the control byte information stored therein to begin said sequantial addressing at said starting

Claim 30 continued:
address; and means responsive when said transfer signal is high for writing data bytes into said addressed controller memory locations when said read/write signal concurrently assumes one of its two states, and for reading said data bytes out of said addressed memory locations when said read/write signal concurrently assumes the opposite state.