CA1196423A - Synchronous clock stopper for microprocessor - Google Patents
Synchronous clock stopper for microprocessorInfo
- Publication number
- CA1196423A CA1196423A CA000437871A CA437871A CA1196423A CA 1196423 A CA1196423 A CA 1196423A CA 000437871 A CA000437871 A CA 000437871A CA 437871 A CA437871 A CA 437871A CA 1196423 A CA1196423 A CA 1196423A
- Authority
- CA
- Canada
- Prior art keywords
- microprocessor
- phase
- clocking
- request signal
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
- A61N1/00—Electrotherapy; Circuits therefor
- A61N1/18—Applying electric currents by contact electrodes
- A61N1/32—Applying electric currents by contact electrodes alternating or intermittent currents
- A61N1/36—Applying electric currents by contact electrodes alternating or intermittent currents for stimulation
- A61N1/372—Arrangements in connection with the implantation of stimulators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
Abstract
Synchronous Clock Stopper For Microprocessor Abstract A synchronous clock stopper circuit for inhibiting clock pulses to a microprocessor in response to a stop request signal, and for reinstating the clock pulses in response to a start request signal thereby to conserve power consumption of the micro-processor when used in an environment of limited power. The stopping and starting of the microprocessor is synchronized, by a phase tracker, with the occurrences of a predetermined phase in the instruction cycle of the microprocessor in which the I/O data and address lines of the microprocessor are of high impedance so that a shared memory connected to the I/O lines may be accessed by other peripheral devices. The starting and stopping occur when the microprocessor initiates and completes, respectively, an instruction, as well as before and after transferring data with a memory.
Also, the phase tracker transmits phase information signals over a bus to other peripheral devices which signals identify the current operational phase of the microprocessor.
Also, the phase tracker transmits phase information signals over a bus to other peripheral devices which signals identify the current operational phase of the microprocessor.
Description
~ca6~3 Synchronous Clock Stop~er For Microprocessor This invention relates to microprocessor systems, and more specifically, to a clocking control circuit for controlling ~he operation of a microprocessor used in a pswer-limited environment, such as in a medical implanted device.
Among many uses of miniature electronic data processors, more commoxlly known as microprocessors, is to control moni-toring and diagnosing circuits in implanted medical devices. They are particularly desixable because of their relatively small weight and size. In each application, however, the micro-processor requixes a certain amount of power and thepower demand varies according to ~he amount of "process-ing" activity performed by the microprocessor. By "processing" activity, it is meant data transfers into and out of various registers in the microprocessor and computations or logic operations performed by the processor. For use in medically implanted devices, a storage battery usually provides the source of power for the microprocessor operation, but if the battery becomes exhausted, then it becomes necessary to surgically replace the battery to maintain the electrical functions performed by the microprocessor.
One obvious approach for minimixing the foregoing difficulties is to employ microprocessor logic requiring a minimum amount of power and/or to employ extended-life, durable batteries. The advantages gained by these techniques are limited by the state-of the-art in solid state logic and battery design.
.~, i 69~
~nother rather obvious approach for extending the useful life of the microprocessor power source is -to turn off power to non~essential circuits at certain time periods that do not require the afec-ted electronic circuit, but in the case of a microprocessor controlled device, such as a data acquisition device, this may not always be possible since internal housekeeping functions re~uire continuous operation for timekeeping, data logging, and other monitoring and con-trol operations.
Also, some ty~es of logic circuits essential to the operation of the processor unit, such as an active memory, require repetitive refreshing cycles in order to retain the validity of their data content. Refresh-ing cycles require continuous power which cannot be temporarily suspended. A significant amount of power, however, could be conserved by deactivating the processor during idle periods, such as be-tween transfers of memory data or executions of instructions.
But since the microprocessor itself is usually the sole unit within a data processing system that controls all other devices (such as peripherals and memories), it is not ordinarily powered down as synchronism in operation with the other devices could ~e lost.
In view of the foregoing, an objective of the present invention is to provide a clockin~ control circuit for reducing power requirement of a micro-processor operated in a power~limited environment.
A more specific objective of the present invention is to provide a clocking control circuit for starting and stopping a microprocessor cloc~ of an optimum phase during its instruction cycle, thereby to reduce power drain during idle periods and to preserve its synchronism with other devices when restarted.
.
~6~Z3 A further objective of the present invention is to provide a clocking control circuit for use in a microprocessor system that includes a random access memory which circuit enables the use of the memory by other peripheral devices in the system when the microprocessor is idle.
Other objects of this invention will becorne apparent upon review o~ the succeeding description of an illustrative embodiment.
According to the present invention there is provided a clocking control circuit Eor a microprocessor system including a microprocessor that is responsive to clocking pulses for processing instructions in a plurality of successive stages in each instruction cycle, said clocking control circuit comprising:
a clock source for generating clocking pulses;
phase tracking means responsive to said clocking pulses and a predeterrnined phase in each instruction cycle of said micropxocessor for producing a phase pulse signal;
receiving means for receiving a stop request signal and a start request signal, said stop request signal being generated when said microprocessor completes an instruction sequence and said start request signal being generated when said processor initiates an instruction sequence; and synchronous logic means responsive to said phase pulse signal and said stop request signal for disabling the transfer of said clocking pulses to said microprocessor, and responsive to said phase pulse signal and said start request signal for enabling the transEer of said clocking p~lses to said microprocessor.
Preferably, the clocking control circuit coupled to the microprocessor system includes (1) a phase tracker for generating a phase pulse in response to an instruction cycle sync signal from the microprocessor, each sync pulse identifying a predetermined phase in the operational cycle of execution oE
an instruction by the microprocessor, and (2) a start/stop logic circuit responsive to the phase pulse Erom the phase tracker and a stop/start request signal from various devices in the microprocessor system for enabling or disabling, respectively, the flow of clock pulses from a clock source to the microprocessor. In one instance, the stop and start requests signals occur be!ween direct memory accesses by the microprocessor. In another instance, a stop request is made ~C~16~3 after the microprocessor completes an instruction cycle and a start request is made when the microprocessor initiates an instruction cycle. Starting and stopping of the microprocessor occur only with the occurrences of the phase pulse, that is, at a time when the microprocessor's I/O data lines are logically disconnected from an external peeipheral buss having a device, such as a memory, connected thereto.
Advantageously, other peripheral devices may gain access to the memory while the microprocessor is disconnected. Further, the phase tracker also generates phase information signals and transmits them over a data bus lthereby to inform peripheral devices connec-ted to the data bus of the current phase of the microprocessor's instruction cycle so that the peripheral devices may ready themselves for an I/O data transfer with the shared memory.
The invention, though, is pointed out with particularity in~the appended claims. The above and further objects and advantages of ~this invention may be better understood by referring -to the following d~scription of an illustrative embodiment of the ,invention taken in conjunction with the accompanying drawings.
Fi~lre 1 is a block diagram of a clocking control circuit embodying the concepts of this invention.
Figure 2 is a timing diagram of the clocking control circuit of Figure 1.
Figure 3 is a detailed circuit diagram of the circuit of Figure 1.
As previously stated, this invention is useful for conserving power consumed by a microprocessor being operated in an environment of limited power, such as, for example, in a medical implanted device.
In developing this invention, it was recognized that ~ ~, there exists a rather significant difference in power dissipatiQn between the static and dynamic modes of operation of a microprocessor, especially a micro-processor employing CMOS logic circuitry, such as, for example, an 1802 microprocessor manufa,ctured by RCA.
Figures 1 and 2 depict a block diagram circuit -together wi-th its timing diagram in which the concept of this invention may be implemented. As shown, a synchronous stop logic circuit 12 asserts a CLK EN signal on line 30 during the active, dynamic mode of operation of a microprocessor 15 and deasserts the CLK EN signal during the static inactive mode of operation. The assertion of the CLK EN signal enables an AND gate 14 which allows clocking signals to pass from a clock source 17 directly to the CK input of the microprocessor 15. While being clocked by these clocking signals, microprocessor 15 processes data transferred among the microprocessor 15, memory 11, and peripherals 21. A processor bus 13 couples the memory 11 and peripheral bus ~0 couples the peripheral devices to the processor bus 13. Memory 11 typically is a random access memory having both address and data lines. It could also be another type of s-torage device. Peripheral bus 20 normally carries signals from data acquisition probes.
For its contemplated use in a medical implanted device about ninety percent of the micro-processor 15 activity, usually is consumed in making memory references and transfers among devices connected to the buses 13 and 20. At times, however, the microprocessor 15 is not involved in a data processing or da-ta transfer operation and thus does not require 6~23 opera-ting power to sequence its internal registers and arithmetic units. These circumstances could be occasioned by the performance of data acquisition by one of the peripheral devices 21 which would place in the memory ll sampled data for later use by the microprocessor 15. In the preferred embodiment, such transfer occurs while the data lines of the processor are logically disconnected from the bus 13 so that the address and data lines of the memory 13 are free.
In operation, a phase tracker 10 keeps track of the curren-t phase of operation of the micro-processor during its instruction cycle. In the preferred 1802 microprocessor, each instruction cycle has eight stages, or phases, that run the duration of eight clocking pulses from the clock source 17. The phase tracker 10 monitors clocking pulses 16 from the clock source 17 and a sync signal 18 from the micro~
processor 15. The sync signal occurs at a predetermined one of the eight phases in the operational cycle of the microprocessor 15. In synchronism with the clocking pulses and the sync pulses, the phase tracker 10 produces a series of information signals on the bus 20. These information signals inform the peripheral devices of the current instruction cycle in which of the microprocesscr 15 is undergoing The phase tracker 10 also produces a start/stop phase pulse (SSPP pulse) on conductor 22 and supplies it to the synchronous start/stop logic 12. The SSPP pulse occurs at a predetermined one of the phases in the instruction cycle of the microprocessor 15, also in synchronism with the clock pulses from source 17.
During assertion of the SSPP pulse, the data lines of the microprocessor are in a high impedence state so that, if necessary, -the peripheral devices can gain 6~Z~
access to the memory bus while the microprocessor is dormant, as previously explained.
Also, during assertion of the SSPP pulse, the synchronous start/stop logic 12 can respond to a stop request (STOP) or a start request (START) signal appearing on conductors 24 and 26. The START or STOP
signals may emanate from the microprocessor 15, such as when it initiates an interrupt or completes a memory transfer. If the circui-t 12 receives a STOP
signal, the CLK E~ signal appearing on line 30 will become deasserted at the occurrence of the next SSPP
pulse. Likewise, if the processor is dormant, the logic circuit 12 will assert the CLK EN signal in response to a START signal on line 24 upon the occur-rence of the next SSPP pulse from the phase tracker22. Thus, the phase tracker 10 assures that the microprocessor always goes dormant, or becomes active, in synchronism with the desired phase in the instruc-tion cycle of the microprocessor 15, e.g., when the microprocessor 15 is logically decoupled from the bus 13.
A RESET signal initializes all latches and gates in the synchxonous star-t/stop logic 12 prior to opera-tion of the circuit 12. This provides for placing -the circuit 12 in operating condition when the microprocessing system is first powered up.
Figure 2 shows a detail circuit diagram of the synchronous clock stopper circuit 12 and the phase tracker circuit 10 just described with reference to Figure 1. The phase tracker 10 contains an octal counter (e.g., ring coun-ter) and decoder circuit 34 which indexes one bit position in response to receipt of each clocking pulse from the clock source 17 (Figure 1). In response to the clocking pulses, the d~coder circuit 34 produces the SSPP pulse each time ': ' 6~Z3 it counts eight pulses, or each -time a count bit recirculates to position "one" in the ring countex 34. At phase "one" the I/O address and data lines of the microprocessor reside in a high impedence state.
A SYNC signal, timing pulse "~" ~TPB), from the microprocessor 15 enables one input of an AND gate 36 so that the decoder 34 is initialized (i.e., reset) at the beginning of each instruc-tion cycle of the microprocessor 15 in synchronism with clocking pulses f.om the clock source 17 which also couples the other enabling input of the AND gate 36.
To initiate a start request on line 24, the synchronous start/stop logic 12 includes an OR gate 38 which responds to various control signals such as an interrupt signal "INT", and direct memory access signals "DMA IN" and "DMA OUT". These signals initiate and terminate the transfer of memory data with random access memory 11. Also, the logic circuit 12 includes an AND gate 46 which, to initiate a stop request of the processor 15 on line 26, responds to various peripheral device completion signals such as a CPU
DONE, a DMA IN DONE or a DMA OUT DONE signal. These signals indicate that the processor has completed an instruction se~uence or that a memory transfer operation is complete, and therefore, the processor may be stopped.
To stop the microprocessor, a flip-flop 54 is set in response to the assertion of a STOP request signal on conductor 26, assuming no START reguest signal is presen-t on line 24. The "Q" ou-tput of the flip-flop 54 and the SSPP pulse on conductor 22 energize an AND gate 56 thereby to set a second flip-flop 58. The flip-flop 58 is also set upon the occurrence of the SSPP pulse. Thereafter, at its Q
output, the flip-flop 58 disables an enabling signal g on conductor 30 to disable the A~ ga-te 14 thereby blocking the transfer over line 16 of the clocking pulses from the clock source 17 -to the microprocessor 15. Also, flip-flop 58 asserts an enabling signal at its "Q" outpu-t which resets the flip-flop 54 through an OR gate 62, and holds itself in a set condition by virtue of an OR gate 60 connected in a feedback path of the flip-flop 58 until a STAR~ request on line 24 is made.
To restart the microprocessor 15, that is, to permit passage of the clocking signals through the AND gate 14, a START signal on conductor 24 sets the flip-flop 58 upon the occurrence of an SSPP pulse on conductor 22. When set, the "Q" output of flip-flop 58 asserts an enabling signal to enable the AND gate 14 thereby -to permi-t passage of the clocking pulses from the clock source 17 to the microprocessor 15.
The above description illus-trates a preferred embodiment of implemen-ting the concepts of this invention, and is by no means intended to restrict the scope of the invention to that which is shown and described. It will be apparent, however, that various modifications can be made to this specific embodiment while at-taining some or all of the advantages and objectives of this invention. Therefore, it is the objective of the appended claims to cover all such modifications and alternate embodiments as come within the true scope of -this invention.
Among many uses of miniature electronic data processors, more commoxlly known as microprocessors, is to control moni-toring and diagnosing circuits in implanted medical devices. They are particularly desixable because of their relatively small weight and size. In each application, however, the micro-processor requixes a certain amount of power and thepower demand varies according to ~he amount of "process-ing" activity performed by the microprocessor. By "processing" activity, it is meant data transfers into and out of various registers in the microprocessor and computations or logic operations performed by the processor. For use in medically implanted devices, a storage battery usually provides the source of power for the microprocessor operation, but if the battery becomes exhausted, then it becomes necessary to surgically replace the battery to maintain the electrical functions performed by the microprocessor.
One obvious approach for minimixing the foregoing difficulties is to employ microprocessor logic requiring a minimum amount of power and/or to employ extended-life, durable batteries. The advantages gained by these techniques are limited by the state-of the-art in solid state logic and battery design.
.~, i 69~
~nother rather obvious approach for extending the useful life of the microprocessor power source is -to turn off power to non~essential circuits at certain time periods that do not require the afec-ted electronic circuit, but in the case of a microprocessor controlled device, such as a data acquisition device, this may not always be possible since internal housekeeping functions re~uire continuous operation for timekeeping, data logging, and other monitoring and con-trol operations.
Also, some ty~es of logic circuits essential to the operation of the processor unit, such as an active memory, require repetitive refreshing cycles in order to retain the validity of their data content. Refresh-ing cycles require continuous power which cannot be temporarily suspended. A significant amount of power, however, could be conserved by deactivating the processor during idle periods, such as be-tween transfers of memory data or executions of instructions.
But since the microprocessor itself is usually the sole unit within a data processing system that controls all other devices (such as peripherals and memories), it is not ordinarily powered down as synchronism in operation with the other devices could ~e lost.
In view of the foregoing, an objective of the present invention is to provide a clockin~ control circuit for reducing power requirement of a micro-processor operated in a power~limited environment.
A more specific objective of the present invention is to provide a clocking control circuit for starting and stopping a microprocessor cloc~ of an optimum phase during its instruction cycle, thereby to reduce power drain during idle periods and to preserve its synchronism with other devices when restarted.
.
~6~Z3 A further objective of the present invention is to provide a clocking control circuit for use in a microprocessor system that includes a random access memory which circuit enables the use of the memory by other peripheral devices in the system when the microprocessor is idle.
Other objects of this invention will becorne apparent upon review o~ the succeeding description of an illustrative embodiment.
According to the present invention there is provided a clocking control circuit Eor a microprocessor system including a microprocessor that is responsive to clocking pulses for processing instructions in a plurality of successive stages in each instruction cycle, said clocking control circuit comprising:
a clock source for generating clocking pulses;
phase tracking means responsive to said clocking pulses and a predeterrnined phase in each instruction cycle of said micropxocessor for producing a phase pulse signal;
receiving means for receiving a stop request signal and a start request signal, said stop request signal being generated when said microprocessor completes an instruction sequence and said start request signal being generated when said processor initiates an instruction sequence; and synchronous logic means responsive to said phase pulse signal and said stop request signal for disabling the transfer of said clocking pulses to said microprocessor, and responsive to said phase pulse signal and said start request signal for enabling the transEer of said clocking p~lses to said microprocessor.
Preferably, the clocking control circuit coupled to the microprocessor system includes (1) a phase tracker for generating a phase pulse in response to an instruction cycle sync signal from the microprocessor, each sync pulse identifying a predetermined phase in the operational cycle of execution oE
an instruction by the microprocessor, and (2) a start/stop logic circuit responsive to the phase pulse Erom the phase tracker and a stop/start request signal from various devices in the microprocessor system for enabling or disabling, respectively, the flow of clock pulses from a clock source to the microprocessor. In one instance, the stop and start requests signals occur be!ween direct memory accesses by the microprocessor. In another instance, a stop request is made ~C~16~3 after the microprocessor completes an instruction cycle and a start request is made when the microprocessor initiates an instruction cycle. Starting and stopping of the microprocessor occur only with the occurrences of the phase pulse, that is, at a time when the microprocessor's I/O data lines are logically disconnected from an external peeipheral buss having a device, such as a memory, connected thereto.
Advantageously, other peripheral devices may gain access to the memory while the microprocessor is disconnected. Further, the phase tracker also generates phase information signals and transmits them over a data bus lthereby to inform peripheral devices connec-ted to the data bus of the current phase of the microprocessor's instruction cycle so that the peripheral devices may ready themselves for an I/O data transfer with the shared memory.
The invention, though, is pointed out with particularity in~the appended claims. The above and further objects and advantages of ~this invention may be better understood by referring -to the following d~scription of an illustrative embodiment of the ,invention taken in conjunction with the accompanying drawings.
Fi~lre 1 is a block diagram of a clocking control circuit embodying the concepts of this invention.
Figure 2 is a timing diagram of the clocking control circuit of Figure 1.
Figure 3 is a detailed circuit diagram of the circuit of Figure 1.
As previously stated, this invention is useful for conserving power consumed by a microprocessor being operated in an environment of limited power, such as, for example, in a medical implanted device.
In developing this invention, it was recognized that ~ ~, there exists a rather significant difference in power dissipatiQn between the static and dynamic modes of operation of a microprocessor, especially a micro-processor employing CMOS logic circuitry, such as, for example, an 1802 microprocessor manufa,ctured by RCA.
Figures 1 and 2 depict a block diagram circuit -together wi-th its timing diagram in which the concept of this invention may be implemented. As shown, a synchronous stop logic circuit 12 asserts a CLK EN signal on line 30 during the active, dynamic mode of operation of a microprocessor 15 and deasserts the CLK EN signal during the static inactive mode of operation. The assertion of the CLK EN signal enables an AND gate 14 which allows clocking signals to pass from a clock source 17 directly to the CK input of the microprocessor 15. While being clocked by these clocking signals, microprocessor 15 processes data transferred among the microprocessor 15, memory 11, and peripherals 21. A processor bus 13 couples the memory 11 and peripheral bus ~0 couples the peripheral devices to the processor bus 13. Memory 11 typically is a random access memory having both address and data lines. It could also be another type of s-torage device. Peripheral bus 20 normally carries signals from data acquisition probes.
For its contemplated use in a medical implanted device about ninety percent of the micro-processor 15 activity, usually is consumed in making memory references and transfers among devices connected to the buses 13 and 20. At times, however, the microprocessor 15 is not involved in a data processing or da-ta transfer operation and thus does not require 6~23 opera-ting power to sequence its internal registers and arithmetic units. These circumstances could be occasioned by the performance of data acquisition by one of the peripheral devices 21 which would place in the memory ll sampled data for later use by the microprocessor 15. In the preferred embodiment, such transfer occurs while the data lines of the processor are logically disconnected from the bus 13 so that the address and data lines of the memory 13 are free.
In operation, a phase tracker 10 keeps track of the curren-t phase of operation of the micro-processor during its instruction cycle. In the preferred 1802 microprocessor, each instruction cycle has eight stages, or phases, that run the duration of eight clocking pulses from the clock source 17. The phase tracker 10 monitors clocking pulses 16 from the clock source 17 and a sync signal 18 from the micro~
processor 15. The sync signal occurs at a predetermined one of the eight phases in the operational cycle of the microprocessor 15. In synchronism with the clocking pulses and the sync pulses, the phase tracker 10 produces a series of information signals on the bus 20. These information signals inform the peripheral devices of the current instruction cycle in which of the microprocesscr 15 is undergoing The phase tracker 10 also produces a start/stop phase pulse (SSPP pulse) on conductor 22 and supplies it to the synchronous start/stop logic 12. The SSPP pulse occurs at a predetermined one of the phases in the instruction cycle of the microprocessor 15, also in synchronism with the clock pulses from source 17.
During assertion of the SSPP pulse, the data lines of the microprocessor are in a high impedence state so that, if necessary, -the peripheral devices can gain 6~Z~
access to the memory bus while the microprocessor is dormant, as previously explained.
Also, during assertion of the SSPP pulse, the synchronous start/stop logic 12 can respond to a stop request (STOP) or a start request (START) signal appearing on conductors 24 and 26. The START or STOP
signals may emanate from the microprocessor 15, such as when it initiates an interrupt or completes a memory transfer. If the circui-t 12 receives a STOP
signal, the CLK E~ signal appearing on line 30 will become deasserted at the occurrence of the next SSPP
pulse. Likewise, if the processor is dormant, the logic circuit 12 will assert the CLK EN signal in response to a START signal on line 24 upon the occur-rence of the next SSPP pulse from the phase tracker22. Thus, the phase tracker 10 assures that the microprocessor always goes dormant, or becomes active, in synchronism with the desired phase in the instruc-tion cycle of the microprocessor 15, e.g., when the microprocessor 15 is logically decoupled from the bus 13.
A RESET signal initializes all latches and gates in the synchxonous star-t/stop logic 12 prior to opera-tion of the circuit 12. This provides for placing -the circuit 12 in operating condition when the microprocessing system is first powered up.
Figure 2 shows a detail circuit diagram of the synchronous clock stopper circuit 12 and the phase tracker circuit 10 just described with reference to Figure 1. The phase tracker 10 contains an octal counter (e.g., ring coun-ter) and decoder circuit 34 which indexes one bit position in response to receipt of each clocking pulse from the clock source 17 (Figure 1). In response to the clocking pulses, the d~coder circuit 34 produces the SSPP pulse each time ': ' 6~Z3 it counts eight pulses, or each -time a count bit recirculates to position "one" in the ring countex 34. At phase "one" the I/O address and data lines of the microprocessor reside in a high impedence state.
A SYNC signal, timing pulse "~" ~TPB), from the microprocessor 15 enables one input of an AND gate 36 so that the decoder 34 is initialized (i.e., reset) at the beginning of each instruc-tion cycle of the microprocessor 15 in synchronism with clocking pulses f.om the clock source 17 which also couples the other enabling input of the AND gate 36.
To initiate a start request on line 24, the synchronous start/stop logic 12 includes an OR gate 38 which responds to various control signals such as an interrupt signal "INT", and direct memory access signals "DMA IN" and "DMA OUT". These signals initiate and terminate the transfer of memory data with random access memory 11. Also, the logic circuit 12 includes an AND gate 46 which, to initiate a stop request of the processor 15 on line 26, responds to various peripheral device completion signals such as a CPU
DONE, a DMA IN DONE or a DMA OUT DONE signal. These signals indicate that the processor has completed an instruction se~uence or that a memory transfer operation is complete, and therefore, the processor may be stopped.
To stop the microprocessor, a flip-flop 54 is set in response to the assertion of a STOP request signal on conductor 26, assuming no START reguest signal is presen-t on line 24. The "Q" ou-tput of the flip-flop 54 and the SSPP pulse on conductor 22 energize an AND gate 56 thereby to set a second flip-flop 58. The flip-flop 58 is also set upon the occurrence of the SSPP pulse. Thereafter, at its Q
output, the flip-flop 58 disables an enabling signal g on conductor 30 to disable the A~ ga-te 14 thereby blocking the transfer over line 16 of the clocking pulses from the clock source 17 -to the microprocessor 15. Also, flip-flop 58 asserts an enabling signal at its "Q" outpu-t which resets the flip-flop 54 through an OR gate 62, and holds itself in a set condition by virtue of an OR gate 60 connected in a feedback path of the flip-flop 58 until a STAR~ request on line 24 is made.
To restart the microprocessor 15, that is, to permit passage of the clocking signals through the AND gate 14, a START signal on conductor 24 sets the flip-flop 58 upon the occurrence of an SSPP pulse on conductor 22. When set, the "Q" output of flip-flop 58 asserts an enabling signal to enable the AND gate 14 thereby -to permi-t passage of the clocking pulses from the clock source 17 to the microprocessor 15.
The above description illus-trates a preferred embodiment of implemen-ting the concepts of this invention, and is by no means intended to restrict the scope of the invention to that which is shown and described. It will be apparent, however, that various modifications can be made to this specific embodiment while at-taining some or all of the advantages and objectives of this invention. Therefore, it is the objective of the appended claims to cover all such modifications and alternate embodiments as come within the true scope of -this invention.
Claims (8)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A clocking control circuit for a micro-processor system including a microprocessor that is responsive to clocking pulses for processing instruc-tions in a plurality of successive stages in each instruction cycle, said clocking control circuit comprising:
a clock source for generating clocking pulses;
phase tracking means responsive to said clock-ing pulses and a predetermined phase in each instruc-tion cycle of said microprocessor for producing a phase pulse signal;
receiving means for receiving a stop request signal and a start request signal, said stop request signal being generated when said microprocessor com-pletes an instruction sequence and said start request signal being generated when said processor initiates an instruction sequence; and synchronous logic means responsive to said phase pulse signal and said stop request signal for disabling the transfer of said clocking pulses to said microprocessor, and responsive to said phase pulse signal and said start request signal for enabling the transfer of said clocking pulses to said microprocessor.
a clock source for generating clocking pulses;
phase tracking means responsive to said clock-ing pulses and a predetermined phase in each instruc-tion cycle of said microprocessor for producing a phase pulse signal;
receiving means for receiving a stop request signal and a start request signal, said stop request signal being generated when said microprocessor com-pletes an instruction sequence and said start request signal being generated when said processor initiates an instruction sequence; and synchronous logic means responsive to said phase pulse signal and said stop request signal for disabling the transfer of said clocking pulses to said microprocessor, and responsive to said phase pulse signal and said start request signal for enabling the transfer of said clocking pulses to said microprocessor.
2. A clocking control circuit as recited in claim 1 wherein said microprocessor system includes peripheral devices interconnected by data bus means and said synchronous logic means includes means for generating and transmitting over said data bus means phase information signals identifying the current phase of the instruction cycle of said microprocessor.
3. A clocking control circuit as recited in claim 1 wherein said microprossor includes input/output data lines and said predetermined phase of said phase tracking means corresponds with the phase of high impedence of input/output data lines of said microprocessor.
4. A clocking control circuit as recited in claim 2 wherein said microprocessor includes input/output data lines and said predetermined phase of said phase tracking means corresponds with the phase of high impedence of input/output data lines of said microprocessor.
5. A clocking control circuit as recited in claim 3 or claim 4 wherein said microprocessor system includes memory means having address and data lines, and said stop request signal is generated upon completion of a data transfer between said microprocessor and memory means and said start request signal is generated in response to the initation of a data transfer with said memory means.
6. A clocking control circuit for receiving an external start request signal for a microprocessor system including a microprocessor that is responsive to clocking pulses for processing instructions in a plurality of successive stages in each instruction cycle, said microprocessor having input/output data and address lines, said clocking control circuit comprising:
a clock source for generating clocking pulses, phase tracking means coupled to said input/output data and address lines, said phase tracking means made operative by, said clocking pulses for producing a phase pulse signal at a predetermined phase in each instruction cycle of said microprocessor, said predetermined phase of said phase tracking means occurring when said input/output data and address lines of said microprocessor are operating at high impedance;
means for generating a start signal based upon said external start request signal;
receiving means for receiving a stop request signal from said microprocessor system, said stop request signal being generated when said microprocessor completes an instruction sequence: and synchronous logic means responsive to said phase pulse signal and said stop request signal for preventing the transfer of said clocking pulses from said clock source to said microprocessor, and responsive to said phase pulse signal and said start signal for permitting the transfer of said clocking pulses from said clock source to said microprocessor.
a clock source for generating clocking pulses, phase tracking means coupled to said input/output data and address lines, said phase tracking means made operative by, said clocking pulses for producing a phase pulse signal at a predetermined phase in each instruction cycle of said microprocessor, said predetermined phase of said phase tracking means occurring when said input/output data and address lines of said microprocessor are operating at high impedance;
means for generating a start signal based upon said external start request signal;
receiving means for receiving a stop request signal from said microprocessor system, said stop request signal being generated when said microprocessor completes an instruction sequence: and synchronous logic means responsive to said phase pulse signal and said stop request signal for preventing the transfer of said clocking pulses from said clock source to said microprocessor, and responsive to said phase pulse signal and said start signal for permitting the transfer of said clocking pulses from said clock source to said microprocessor.
7. A clocking control circuit as recited in claim 6 wherein said microprocessor system includes peripheral devices, the clocking control circuit including means for transmitting to said peripheral devices said phase pulse signals identifying the current phase of the instruction cycle of said microprocessor and indicating access to said input/output data and address lines.
8. A clocking control circuit as recited in claim 7 wherein said microprocessor system includes memory means common to both said microprocessor and said peripheral devices, said phase pulse signals indicating permission for data transfers to occur between said microprocessor and said memory and between said peripheral devices and said memory when said microprocessor is being clocked and between said peripheral devices and said memory means when said microprocessor is not being clocked.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/425,668 US4545030A (en) | 1982-09-28 | 1982-09-28 | Synchronous clock stopper for microprocessor |
| US425,668 | 1989-10-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1196423A true CA1196423A (en) | 1985-11-05 |
Family
ID=23687539
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000437871A Expired CA1196423A (en) | 1982-09-28 | 1983-09-28 | Synchronous clock stopper for microprocessor |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US4545030A (en) |
| JP (1) | JPS5981720A (en) |
| AU (1) | AU557250B2 (en) |
| CA (1) | CA1196423A (en) |
| DE (1) | DE3335145A1 (en) |
| FR (1) | FR2533719A1 (en) |
| GB (1) | GB2127999B (en) |
| IL (1) | IL69865A (en) |
| NL (1) | NL8303313A (en) |
Families Citing this family (69)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59200327A (en) * | 1983-04-26 | 1984-11-13 | Nec Corp | Control system of peripheral device |
| US4698748A (en) * | 1983-10-07 | 1987-10-06 | Essex Group, Inc. | Power-conserving control system for turning-off the power and the clocking for data transactions upon certain system inactivity |
| US4631702A (en) * | 1984-02-28 | 1986-12-23 | Canadian Patents and Deveopment Limited--Societe Canadienne des Brevets et d'Exploitation Limitee | Computer speed control |
| US4825407A (en) * | 1984-07-26 | 1989-04-25 | Miles Inc. | Method and circuit for controlling single chip microcomputer |
| US4625730A (en) * | 1985-04-09 | 1986-12-02 | The Johns Hopkins University | Patient ECG recording control for an automatic implantable defibrillator |
| JPS61262827A (en) * | 1985-05-15 | 1986-11-20 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JPS6227813A (en) * | 1985-07-29 | 1987-02-05 | Hitachi Ltd | Phase synchronization system |
| US4851987A (en) * | 1986-01-17 | 1989-07-25 | International Business Machines Corporation | System for reducing processor power consumption by stopping processor clock supply if a desired event does not occur |
| JPS63163912A (en) * | 1986-12-26 | 1988-07-07 | Toshiba Corp | Microcomputer system |
| JPH01241636A (en) * | 1988-03-17 | 1989-09-26 | Internatl Business Mach Corp <Ibm> | Data processing system |
| US5032982A (en) * | 1988-05-18 | 1991-07-16 | Zilog, Inc. | Device for timing interrupt acknowledge cycles |
| JPH0719211B2 (en) * | 1988-10-08 | 1995-03-06 | 日本電気株式会社 | Clock control system |
| US4980836A (en) * | 1988-10-14 | 1990-12-25 | Compaq Computer Corporation | Apparatus for reducing computer system power consumption |
| JPH02201516A (en) * | 1989-01-31 | 1990-08-09 | Toshiba Corp | Power save system |
| JPH02250191A (en) * | 1989-03-23 | 1990-10-05 | Mitsubishi Electric Corp | Microcomputer |
| US7537167B1 (en) * | 1993-08-31 | 2009-05-26 | Broadcom Corporation | Modular, portable data processing terminal for use in a radio frequency communication network |
| JPH0328911A (en) * | 1989-06-26 | 1991-02-07 | Mitsubishi Electric Corp | Microprocessor |
| CA2063413C (en) * | 1989-06-30 | 2000-08-15 | Leroy D. Harper | Computer power management system |
| JPH03111960A (en) * | 1989-09-26 | 1991-05-13 | Mitsubishi Electric Corp | One-chip microcomputer |
| JPH03231320A (en) * | 1990-02-06 | 1991-10-15 | Mitsubishi Electric Corp | Microcomputer system |
| JP2676966B2 (en) * | 1990-03-16 | 1997-11-17 | 日本電気株式会社 | Single chip microcomputer |
| US5396635A (en) | 1990-06-01 | 1995-03-07 | Vadem Corporation | Power conservation apparatus having multiple power reduction levels dependent upon the activity of the computer system |
| JPH04107623A (en) * | 1990-08-28 | 1992-04-09 | Seiko Epson Corp | Display device |
| JPH04236682A (en) * | 1991-01-18 | 1992-08-25 | Mitsubishi Electric Corp | Microcomputer system |
| US5333300A (en) * | 1991-02-11 | 1994-07-26 | Intel Corporation | Timing circuitry and method for controlling automated programming and erasing of a non-volatile semiconductor memory |
| US5546561A (en) * | 1991-02-11 | 1996-08-13 | Intel Corporation | Circuitry and method for selectively protecting the integrity of data stored within a range of addresses within a non-volatile semiconductor memory |
| FI88657C (en) * | 1991-02-12 | 1993-06-10 | Nokia Mobile Phones Ltd | Foerfarande Foer att minska stroemfoerbrukningen i en mobil telefon |
| US5203003A (en) * | 1991-03-28 | 1993-04-13 | Echelon Corporation | Computer architecture for conserving power by using shared resources and method for suspending processor execution in pipeline |
| US5935253A (en) * | 1991-10-17 | 1999-08-10 | Intel Corporation | Method and apparatus for powering down an integrated circuit having a core that operates at a speed greater than the bus frequency |
| WO1993016883A1 (en) * | 1992-02-26 | 1993-09-02 | Seiko Epson Corporation | Additional electronic device and electronic system |
| JP3529805B2 (en) * | 1992-03-27 | 2004-05-24 | ナショナル・セミコンダクター・コーポレイション | Microprocessor with hardware controlled power management function and selectable input / output control pins |
| US6343363B1 (en) | 1994-09-22 | 2002-01-29 | National Semiconductor Corporation | Method of invoking a low power mode in a computer system using a halt instruction |
| US8213431B2 (en) * | 2008-01-18 | 2012-07-03 | The Boeing Company | System and method for enabling wireless real time applications over a wide area network in high signal intermittence environments |
| WO1993023825A1 (en) * | 1992-05-20 | 1993-11-25 | Seiko Epson Corporation | Cartridge for electronic apparatus |
| EP0645030A4 (en) * | 1992-06-12 | 1996-04-10 | Norand Corp | Portable data processor which selectively activates and deactivates internal modular units and application processor to conserve power. |
| US5404459A (en) * | 1992-07-21 | 1995-04-04 | Advanced Micro Devices | Serial interface module and method in which the clock is only activated to send a predetermined number of data bits |
| US5473767A (en) * | 1992-11-03 | 1995-12-05 | Intel Corporation | Method and apparatus for asynchronously stopping the clock in a processor |
| KR0138973B1 (en) * | 1992-11-23 | 1998-06-15 | 죤 에이취.무어 | Electric circuit |
| US5457781A (en) * | 1993-01-04 | 1995-10-10 | Amdahl Corporation | System having main unit for shutting off clocks to memory upon completion of writing data into memory and information supervising unit to read the data |
| US5603036A (en) * | 1993-02-19 | 1997-02-11 | Intel Corporation | Power management system for components used in battery powered applications |
| US5586332A (en) * | 1993-03-24 | 1996-12-17 | Intel Corporation | Power management for low power processors through the use of auto clock-throttling |
| CA2092854A1 (en) * | 1993-03-29 | 1994-09-30 | Richard C. Madter | Apparatus and method for enhancing the performance of personal computers |
| US5428765A (en) * | 1993-08-12 | 1995-06-27 | Databook Incorporated | Method and apparatus for disabling and restarting clocks |
| US5600839A (en) * | 1993-10-01 | 1997-02-04 | Advanced Micro Devices, Inc. | System and method for controlling assertion of a peripheral bus clock signal through a slave device |
| DE69522595T2 (en) * | 1994-02-04 | 2002-07-11 | Intel Corp | Method and device for power consumption control in a computer system |
| US5721934A (en) * | 1994-06-29 | 1998-02-24 | Intel Corporation | Retrofit external power saving system and method for use |
| EP0703521A1 (en) * | 1994-09-23 | 1996-03-27 | International Business Machines Corporation | Control logic for very fast clock speeds |
| US5606704A (en) * | 1994-10-26 | 1997-02-25 | Intel Corporation | Active power down for PC card I/O applications |
| US5724592A (en) * | 1995-03-31 | 1998-03-03 | Intel Corporation | Method and apparatus for managing active power consumption in a microprocessor controlled storage device |
| JP2974950B2 (en) * | 1995-10-26 | 1999-11-10 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Information processing system |
| JP3676882B2 (en) * | 1996-06-12 | 2005-07-27 | 株式会社リコー | Microprocessor and its peripheral devices |
| US5832243A (en) * | 1996-12-31 | 1998-11-03 | Compaq Computer Corporation | Computer system implementing a stop clock acknowledge special cycle |
| US5987614A (en) * | 1997-06-17 | 1999-11-16 | Vadem | Distributed power management system and method for computer |
| US6115823A (en) * | 1997-06-17 | 2000-09-05 | Amphus, Inc. | System and method for task performance based dynamic distributed power management in a computer system and design method therefor |
| US7032119B2 (en) | 2000-09-27 | 2006-04-18 | Amphus, Inc. | Dynamic power and workload management for multi-server system |
| US7228441B2 (en) * | 2000-09-27 | 2007-06-05 | Huron Ip Llc | Multi-server and multi-CPU power management system and method |
| US20070245165A1 (en) * | 2000-09-27 | 2007-10-18 | Amphus, Inc. | System and method for activity or event based dynamic energy conserving server reconfiguration |
| USRE40866E1 (en) | 2000-09-27 | 2009-08-04 | Huron Ip Llc | System, method, and architecture for dynamic server power management and dynamic workload management for multiserver environment |
| US7822967B2 (en) * | 2000-09-27 | 2010-10-26 | Huron Ip Llc | Apparatus, architecture, and method for integrated modular server system providing dynamically power-managed and work-load managed network devices |
| US20030196126A1 (en) | 2002-04-11 | 2003-10-16 | Fung Henry T. | System, method, and architecture for dynamic server power management and dynamic workload management for multi-server environment |
| US20060248360A1 (en) * | 2001-05-18 | 2006-11-02 | Fung Henry T | Multi-server and multi-CPU power management system and method |
| US7085952B2 (en) * | 2001-09-14 | 2006-08-01 | Medtronic, Inc. | Method and apparatus for writing data between fast and slow clock domains |
| FR2833448B1 (en) * | 2001-12-06 | 2004-02-27 | Cit Alcatel | OPTIMIZATION OF THE CONSUMPTION OF A MULTIMEDIA AUXILIARY CHIP IN A MOBILE RADIO COMMUNICATION TERMINAL |
| JP3919740B2 (en) * | 2003-07-30 | 2007-05-30 | 株式会社ソニー・コンピュータエンタテインメント | Circuit operation control device and information processing device |
| US7388248B2 (en) * | 2004-09-01 | 2008-06-17 | Micron Technology, Inc. | Dielectric relaxation memory |
| DE102006004346A1 (en) * | 2006-01-30 | 2007-10-18 | Deutsche Thomson-Brandt Gmbh | Data bus interface with switch-off clock |
| FR2914562B1 (en) * | 2007-04-05 | 2009-05-29 | Univ Grenoble 1 | ORAL PROSTHESIS SYSTEM COMPRISING AN ELECTROSTIMULATION DEVICE ASSOCIATED WITH A WIRELESS TRANSCEIVER DEVICE |
| US8909961B2 (en) | 2011-11-29 | 2014-12-09 | Ati Technologies Ulc | Method and apparatus for adjusting power consumption level of an integrated circuit |
| CN105388963B (en) * | 2015-11-17 | 2018-07-27 | 西安紫光国芯半导体有限公司 | A kind of gated clock control method based on DFI interfaces |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3535560A (en) * | 1967-06-09 | 1970-10-20 | Nasa | Data processor having multiple sections activated at different times by selective power coupling to the sections |
| US3941989A (en) * | 1974-12-13 | 1976-03-02 | Mos Technology, Inc. | Reducing power consumption in calculators |
| JPS5178656A (en) * | 1974-12-29 | 1976-07-08 | Fujitsu Ltd | KUROTSUKUSEIGYO SOCHI |
| JPS5348638A (en) * | 1976-10-15 | 1978-05-02 | Sharp Corp | Electronic apparatus |
| US4080659A (en) * | 1977-02-28 | 1978-03-21 | Francini Joseph P | Multi-mode file storage calculator |
| US4171539A (en) * | 1977-12-19 | 1979-10-16 | The Bendix Corporation | Power strobed digital computer system |
| US4279020A (en) * | 1978-08-18 | 1981-07-14 | Bell Telephone Laboratories, Incorporated | Power supply circuit for a data processor |
| JPS5545246A (en) * | 1978-09-25 | 1980-03-29 | Matsushita Electric Ind Co Ltd | Information receiving unit |
| JPS5547549A (en) * | 1978-09-28 | 1980-04-04 | Nippon Texas Instr Kk | Low power consumption microcomputer |
| DE2911998C2 (en) * | 1979-03-27 | 1985-11-07 | Robert Bosch Gmbh, 7000 Stuttgart | Power supply for a microprocessor that controls electrical devices, in particular a motor vehicle |
| JPS5654529A (en) * | 1979-10-08 | 1981-05-14 | Nec Corp | Data processor |
| AU6606881A (en) * | 1980-01-16 | 1981-07-23 | Medtronic, Inc. | Pacemaker |
| GB2080585B (en) * | 1980-07-22 | 1984-07-04 | Tokyo Shibaura Electric Co | Semiconductor integrated circuit with reduced power consumption |
-
1982
- 1982-09-28 US US06/425,668 patent/US4545030A/en not_active Expired - Fee Related
-
1983
- 1983-09-20 AU AU19311/83A patent/AU557250B2/en not_active Ceased
- 1983-09-22 GB GB08325417A patent/GB2127999B/en not_active Expired
- 1983-09-27 NL NL8303313A patent/NL8303313A/en not_active Application Discontinuation
- 1983-09-27 FR FR8315304A patent/FR2533719A1/en active Pending
- 1983-09-28 JP JP58180100A patent/JPS5981720A/en active Granted
- 1983-09-28 DE DE19833335145 patent/DE3335145A1/en active Granted
- 1983-09-28 IL IL69865A patent/IL69865A/en unknown
- 1983-09-28 CA CA000437871A patent/CA1196423A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0214723B2 (en) | 1990-04-09 |
| GB8325417D0 (en) | 1983-10-26 |
| JPS5981720A (en) | 1984-05-11 |
| US4545030A (en) | 1985-10-01 |
| NL8303313A (en) | 1984-04-16 |
| AU557250B2 (en) | 1986-12-11 |
| IL69865A (en) | 1987-09-16 |
| AU1931183A (en) | 1984-04-05 |
| GB2127999A (en) | 1984-04-18 |
| DE3335145C2 (en) | 1987-10-08 |
| GB2127999B (en) | 1986-04-30 |
| IL69865A0 (en) | 1983-12-30 |
| DE3335145A1 (en) | 1984-03-29 |
| FR2533719A1 (en) | 1984-03-30 |
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