CA1200858A - Delay circuit - Google Patents
Delay circuitInfo
- Publication number
- CA1200858A CA1200858A CA000433835A CA433835A CA1200858A CA 1200858 A CA1200858 A CA 1200858A CA 000433835 A CA000433835 A CA 000433835A CA 433835 A CA433835 A CA 433835A CA 1200858 A CA1200858 A CA 1200858A
- Authority
- CA
- Canada
- Prior art keywords
- signal
- output
- delayed
- demodulating
- demodulated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/20—Circuitry for controlling amplitude response
- H04N5/205—Circuitry for controlling amplitude response for correcting amplitude versus frequency characteristic
- H04N5/208—Circuitry for controlling amplitude response for correcting amplitude versus frequency characteristic for compensating for attenuation of high frequency components, e.g. crispening, aperture distortion correction
Abstract
ABSTRACT OF THE DISCLOSURE
A delay circuit, which comprises a modulator for effecting contour modulation of signal using a signal from a carrier oscillator as a carrier, a delay for delaying the modulation output of the modulator, a variable phase shifter for phase shifting the carrier oscillator output signal, a demodulator for effecting demodulation by synchronous detection using the output of the variable phase shifter as a synchronizing signal, an adder for superimposing a reference signal on a first demodulation of signal from the demodulator corresponding to a first input signal to the modulator and supplying the resultant signal as a second input signal to the modulator, and a control for controlling the amount of phase shift by the variable phase shifter according to the reference signal demodulated by the demodulator, wherein the demodulator produces a first demodulated signal delayed behind the first input signal supplied to the modulator by an amount provided by the delay and a second demodulated signal delayed behind the first input signal by double the amount.
A delay circuit, which comprises a modulator for effecting contour modulation of signal using a signal from a carrier oscillator as a carrier, a delay for delaying the modulation output of the modulator, a variable phase shifter for phase shifting the carrier oscillator output signal, a demodulator for effecting demodulation by synchronous detection using the output of the variable phase shifter as a synchronizing signal, an adder for superimposing a reference signal on a first demodulation of signal from the demodulator corresponding to a first input signal to the modulator and supplying the resultant signal as a second input signal to the modulator, and a control for controlling the amount of phase shift by the variable phase shifter according to the reference signal demodulated by the demodulator, wherein the demodulator produces a first demodulated signal delayed behind the first input signal supplied to the modulator by an amount provided by the delay and a second demodulated signal delayed behind the first input signal by double the amount.
Description
~ ;~ O () ~3 5 ~
DELAY CI~CUIT
BACKGROUND OF THE INVENTION
Field of the Invention:
This invention relates a delay circuit used for such purpose as contour compensation.processing on video signals dealt with ln video systems such as television receivers and television cameras and, more particular~y, to a delay circuit which can produce delayed output signals delayed by two differen.t amounts by a single delay line.
Description of the Prior Art:
.~ideo signals .in video systems such as television receivers and television cameras pass through various electric circuits and signal transmission lines having finite operation frequency ranges. Therefore, high frequency component attenuation occurs to result in a so-called reduction of resolution. By way of example, if the luminance signal contains a 3.58-MHz color subcarrier, a 35.8-MHz beat brilliance variations result in the image reproduction. To eliminate such beat interference, the video amplifier circuit in a color television receiver has frequency characteristics such that the color subcarrier is attenuated by more than 15 to 16 d3. Therefore, through such a video ~ ? ~
amplifier circuit high frequency components of the video ~ignal are attenuated t~ result in the reduction of the resolution of ~he image reproduction. In a shadow-mask type cathoderay tube, the brilliance modulation efficiency turns to be reduced when the frequency exceeds 2 M~z. The reduction of the brilliance modulation efficiency reduces the contrast to reduce the resolution.
~ compensate for s~ch reduction of the resolution, it has bee~ in practice to effect cont~ur ~ompensation processing on portions of the lumlnance signal waveform corresponding to the contour of the Lmage with an ~ ,-~overshoot or undershoot of 20 to 30%. This processing has an effect of increasing the ~h~rpness of the contour portions of the Lmage, ~hus- ~proving~the resolutisn.
DESCRIPTION OF T~E DRAWINGS
Fig. 1 is a block diagram showing the general circuit construction of a vertical contour ~ompensation circuit;
Pig. 2 is a time chart explanatory of the operation of the prior art example;
Fig. 3 is a block diagram showing an embodiment of the invention;
Fig. 4 is a vector diagram ~xplanatory of a first and second amplitude modulator;
Fig. ~ is a wave form diagram showing an input signal to the second amplitude modulator; and ~ igs. 6 and 7 are vector diagrams explanatory of the operation of voltage controlled variable phase shifter i~ the ~ame embodiment.
Heretofore, a vertical contour compensation circuit 10 as shown in Fig. 1 has been broadly used for improving the resolution of the image in the vertical dire~tion thereof.
In the vertical contour compensation circuit 10 shown in Fig. 1, an input luminance sisnal Yin which has ~een contour compensated is coupled to a ~ignal inputtermi~all to be fed to a delay line 2 and a first adder 3. The input luminance signal Yin has a waveform as shown, for instance, in A in Fig. 2.
The delay line 2 produces a first delayed luminance ~ign 1 YDLl having a waveform as ~hown ~ 8 in Fig. 2, which is delayed after the input luminance signal Yin by one horizontal scanning period 1 ~, and ~ second delayed luminance signal YDL2 having a waveform as shown in C in Fig. 2, which is delayed after the input luminance signal Yin by 2 ~. The first delayed luminance signal YDLl obtained form the del~y line 2 is fed to a subtracter 5 and a second adder 7. The second delayed luminance signal YDL2 on the other hand, is fed to the first adder 3 noted above. The first adder 3 adds the input luminance signal Yin and second delayed luminance signal YD~2 and feed~ the resultant sisnal YA (having a waveform as shown in D in Fig. 2) through an attenuator 4 to the ~ubtracter 5.. The subtracter 5 3ubtracts ~he~resultant~signal ~ from the first delayed luminance signal YDLl to obtain a contour compensation signal SAc having a waveform as shown in E in Fig. 2. This contour compensation signal SAc is fed through a level controller 6 to the second ~dder 7. The second adder 7 superLmposes the contour compensation signal SAC on the first delayed luminance signal YDLl a~d produces an ou~put luminance signal Yout as sho~n in F in Fig. 2. The signal ~out appears at an output terminal 8. It has a vertical contour compensated waveform with an oversheet and an undershoot given as a r~sult of the uper~mposition of the contour compensation ~ignal SAc on the luminance change portions, i.e., contour portions in the vertical direction of the image.
The delay-line 2 in the vertical contour compensation circuit 10 usually uses two 1 ~ delay lines 22 and 25 each providing a delay time equal to 1 H. Referring to Fig. 1, the input luminance signal Yin coupled to the input terminal 1 is fed to a modulator 21 in ~he delay line 2 for amplitude modulation; The output of the modulator 21 is fed to the first delay line 22. The delayed output signal from the first delay line 22 is fed thr,ough a firs~
gain controlled amplifier 23 to a first demodulator 24. The first gain controlled.amplifier 23 is gain controlled by the output of the first demodulator 24.
5~
The delayed output signal from ~he firqt delay line 22 is fed through the first gain controlled amplifier 23 to the second delay line 25. The delayed output signal from the second delay line 25 is fed through a ~econd gain controlled amplifier 26 to a second .
demodulator 27.
When the input luminance siqnal Yin as shown in A in Fig. 2 is fed to the amplitude modulator 21, the first demodulator 24 demodulates the 1 ~ delayed luminance signal from the first delay line 22 and produces the first delayed luminance signal YDLl delayed by 1 ~ behind the input luminance signal Yin a3 shown in B in Fig. 2. The second demodulator 27 demodulates the luminance signal that has been delayed by 1 ~ through each of the first and second delay lines 22 and 25 and produces the ~econd delayed luminance signal YDL2 delayed by 2 ~ behind the input luminance signal YDL2 as shown in C in Fig. 2.
As has been shown, the delay line 2 in the vertical cOntour compensation circuit 10 uses two 10 delay lines 22 and 25 in order to obtain the first and second delayed luminance signals YDLl and YDL2 delayed by 1 ~ and 2 ~ behind the input,luminance signal Yi~, respectively. ~owever, the delay line is generally expensive. Especially, the vertical contour compens~tion circuit 10; which used two hi~h performance 5~
1 ~ delay lines which are required to provide a comparatively long delay time alnd nevertheless have wide frequency band characteristics is inevitably very expensive. Actually, a major propQrtion of the price is occupied by the delay lines ~2 and 25. Besides, the signal level attenuation and temperature characteistics vary with individual delay lines even o~ the same ratings and specifications. Therefore, where the two delay lines 22 and 25 are used as in the above case, the delayed output signals must be passed through the gain controlled amplifiers 23 and 26 for the AG~
level controlO
SUMMARY OF THE INVE~TION
The invention has been intended in the light of the above affairs, and its object is tG provide a delay circuit having a novel construction, which can provide two different delay times with a single delay line.
Another object of the invention is to provide delay circuit, which permits steady demodulation of a orthogonal modulated signal transmitted through a single delay line.
~' A f urther object of the invention is to provide delay circuit, which permits a vertical contour compensation processing,suit~d to the image'reproduction 5~
by forming a vertical contour compensation signal from delayed luminance signals obtained from a single 1 ~ delay line and delayed 1 ~ and 2 H behind an input luminance signal respectively;
To attain the above objects of the invention, there is provided a delay circuit, which comprises modulating means for effecting orthogonal modulation of signal using ~ signal from a carrier oscillator as a carrier, del~ying means for delaying ~he modulation output of the modulating means, variable phase shifting means for phase shifting the carrier o~cillator output signal, demodulating means for effecting demodulation for effecting demodulation by synchronous detection using the output of the variable phase shifting means as a synchronizing signal, adding means for superposing a reference signal on a first demodulation of signal from the demodulating means corresponding to a first input signal to the modulating mRans and supplying the resultant signal as a second input signal to the moduiating means, and control means for controlling the amount of phase shift by the variable phase shifting means according to the reference signal demodulated by the demodulating means, wherein the demodulating means pro uces a first demodulated signal d~layed behind the first input signal cupplied to the modulating ~eans by an amount provïded Sy the delay means and a second demodulated signal delayed ~ehind the first input signal by double the amountO
DETAILED ~ESCRIPTION OF TKE INVEN$ION
Fig. 3 is a block diagr~m showing an embodLment of the invention applied to a vertical contour compensation circuit.
The illustrated vertical contour compensation circui~ 100 incorporates a delay circuit 40! which employs a ~ingle 1 ~ delay-l~ne 43 which can provide a first and second delayed luminance signal YDLl and YDL2 respectively delayed 1 ~ and 2 ~ behind an input luminance signal Yin. A first adder 60 addes the input luminance signal Yin which is coupled to an input terminal 30 and the second delayed luminance signal YDL2. A subtracter 70 produces a contour compensation signal SAc from the first delayed luminance signal YDLl and the 5Um signal from the first adder 60.
A ~econd adder 80 superimposes the contoux compensation signal SAc on the first delayed luminance qignal YDLl to obtain a vertical contour compensated output luminance s~
signal Yout' The delay circuit 40 also includes a first and second amplitude moduiator 41A and 41B for effecting commonly termed orthogonal modulation of a carrier from a carrier socillator 50. The input luminance signal coupled to the input terminal 30 is fed to the first amplitude modulator 41A. The carrier output signal from the carrier oscillator 50 is supplied directly to the first amplitude modulator 41A, while it is supplied to the second amplitude modulator 41B
through a phase shifter 51 for shifting the phase by 90~. The orthogonal modulation thus is done with carriers 90 out of phase with each other to produce a first and second amplitude modulation Sl and S2 90 out of phase with each other as shown in the vector diagram of ~'ig. 4, these modulations being fed to an adder 42 to be added together. The resultant sum signal SA from the adder 42 is fed through the l delay line 43 to a voltage controlled variable gain amplifler 44. The l H delay line 43 delays the sum signal SA by l H. The voltage controlled variable gain amplifier 44 effects insertion loss temperature compensation of l H delay line, and it is gain controlled by the output of a reference signal detector 49 to be described later. The output of the voltage controlled variable gain amplifier 44 is fed to a first and second demodulator 45A and 45~. The carrier output signal from the carrier oscilLator 50 is coupled as synchro-nizing signal through a voltage controlled variable phase shifter 52 to the first and second demodulators 45A and 45B for demodulating -the sum signal output form the voltage controlled variable gain amplifier 44 by synchronous detection. A phase shifter 53 provides a phase difference of 90 between synchronizing signals supplied to the modulators 45A and 45B. The amount of phase shift by the boltage controlled variable phase shifter 52 is controlled by the output of a level comparator 55 to be described later.
The first demodulator 45A demodulates only a component of the sum signal output of the voltage controlled variable gain amplifier 44 corresponding to the first amplitude modulation Sl by synchronous detection of the sum signal output. It recovers the first delayed luminance signal YDLl delayed 1 H behind the input luminance signal Yin, because the sum signal output fed to it from the variable gain amplifier 44 has been delayed 1 ~ through the 1 ~ delay line 43 and the first amplitude modulation Sl in the sum signal SA
is the amplitude modulation of the input luminance signal Yin on the carrier.
The first delayed luminance signal YDLl from the first demodulator 45A is fed to the subtracter 70 v~
and second adder ~0 as mentioned earlier. It is further fed through a clamp circuit 46 in the delay circuit40 to a sample/hold circuit 54 and an adder 47. A reference signal S~ coupled to a reference signal input terminal 48 is fed to the adder 47 to be superimposed on the first delayed luminance signal YDLl at a position corresponding to the ~lanking period as shown in Fig. 5.- The output of the adder 47, consisting of the reference signal S~ and first delayed luminance signal YDLl superimposed on each other, is fed to the second amplitude modulator 41B~
The second demodulator 4SB that corresponds to the second amplitude modulator 41B, demodulates only a component of the sum signal output of the voltage controlled variable gain amplifier 44 corresponding to the second amplitude modulation S2 by synchronous detection of the sum signal output. It recovers the second delayed luminance signal YDLl, which is delayed 1 H behind the first delayed luminance signal YDLl, i.e., delayed 2 H behind the input luminance signal Yin, under the control of the reference signal S~, because the second amplitude modulation S2 is the amplitudes modulation of the output consisting of the reference signal S~ and first delayed luminance signal YDLl superimposed on each other on the carrier and has been delayed 1 H through the 1 H delay line 43 before ~eing fet to it.
The second delayed luminance signal YDLl is fed to the first adder 60 for addition to the input luminance signal Yin. The sum signal YA from the first adder 60 is fed through an attenuator 65 to the subtracter 70. The subtracter 70 subtracts the first delayed luminance signal YDLl and sum signal YA one from the other to obtain the contour compensation signal SAc: The second adder 80 superimposes the contour sompensation signal SAc on the first delayed luminance signal YDLl, whereby the vertical contour compensated output luminance signal Yout is produced from the output terminal.
In this embodiment, the reference signal detector 49 detects the reference signal S~ demodulated by the second demodulator 45B and controls the gain of the voltage controlled variable gain amplifier 44 to make the signal level of the reference signal S
constant. By this automatic gain control (A~C) function, the insertion loss temperature compensation of 1 ~
delay line 43 is done in the voltage controlled variable grain amplifier 41 on the sum signal input thereto, i.e., the first and second amplitude modulations Sl and S2, having been delayed through the l ~ delay line 43. The first and second demodulators 45A and 45B, 0a~5~
to which the sum signal SA is fed through the voltage controlled variable gain amp:Llfier 44, demodulate the first delayed luminance signal YDLl perfectly free from the reference signal S~ and the perfect referenced signal S~ respectively so long as the phase relation of the synchronous detection, i.e., the phase relation between the synchronizing signals, is rightO
In this embodiment, the output signal of the carrier oscillator 50 is supplied as synchronizing signal through the voltage controlled variable phase shifter 52 to the first and second demodulators 45A
and 45B. The amount of phase shift by the voltage controlled variable phase shifter 52 is controlled according to the output of the level comparator 55.
More specifically, the level comparator 55 compares a reference voltage VREF supplied to one input terminal of it and a hold voltage VsH supplied from the sample/hold circuit 54. The output representing the result of comparison of fed through a signal selection swhich 56 to the voltage controlled variable phase shifter 52. The sample/hold circuit 54 samples and holds the output of the clamp circuit 46 at a position corresponding to the reference signal S~
superimposed on the first delayed luminance signal ~'DLl The level comparator 55 compares the levels of the reference voltage VREF, which is equal in level to the clamp voltage of the clamp circuit 46, i.e., the first delayed luminance signal YD11, and the hold voltage VsH. The first delayed luminance signal YDLl, demodulated hy the first demodulator does not contain any component corresponding to the second modulation S2 by the second amplitude modulator 41B so long as the phase of synchronous detection by the first demodulator 45A is right. In other words, with the right phase of synchronous detection by the first demodulator 45A
the first delayed luminance signal TDLl fed to the sample/hold circuit 54 does not contain the reference single S~ noted above. II1 this case, the clamp level is sampled and held by the sample/hold circuit 54.
It is to be understood that by controlling the amount o~ phase shift by the voltage controlled variable phase shifter 52 according to the output of the level comparator SS, which compares the hold voltage VsH
from the dample/hold circuit 54 and the reference voltage VREF equal to the clamped voltage, the correct phase of the synchronizing signal supplied to the first demodulator 45A can be maintained. Also, by feeding the synchronizing signal noted above through the 90 phase shifter 53 to the second demodulator 45B, the correct phase of the synchronous detection by the second demodulator 4SB maintained. In other words, through automatic phase control of the synchro-nizing signals using the voltage controlled variable phase shifter 52, the correc1_ phases of synchronous detection by the demodulators 45A and 45B can be maintained stably and reliably irrespective of variations of the delay characteristics of the l H
delay line 43 due to temperature changes or long use.
It is unknown the control state, in which the automatic phase control loop described is established at the time of the closure of power source. If the phase of the synchronous detection is deviated by 180 or more at the time of the establishment of the loop, stable pull-in cannot be obtained. For example, if the phase of the synchronous detection of the first demodulator 45~ is in a range indicated by ~ in Fig.
6, where the phase range of the voltage controlled variable phase shifter 52 is indicated at 30, ~he automatic phase control is stopped at one limit of the range ~0, so that the phase can no longer be locked at the correct phase. In this embodiment, the amount of phase shift by the voltage controlled variable phase shifter 52 is -tentatively fixed at the center 3c of the phase range as shown in Fig. 7 at the time of the closure of the power source. By so doing, reliable pull-in to the correct phase can be obtained. More specifically, at the time of the closure of the power source the control vol-tage selection which 56 is tentatively switched to the side of a ~ixed t5b~
power supply 57 by a time constant circuit 58, which detects the rising of the power source voltage.
The voltage of the fixed power supply 57, which is supplied as the control voltage to the voltage controlled variable phase shifter 52, is set to fix the phase amount to the center ~c The control voltage selection switch 56 is switched to the side of thr level comparator 55 after the lapse of a predetermined period of time determined by the time constant circuit 58.
With the switching of control vol.tage as described, the voltage controlled variable phase shifter 52 in the phase control loop starts the pull-in of phase.
from the cPnter 9c noted above. The synchronous detection phase thus can be automatically and reliably locked to the correct phase.
As has been shown, in the above embodiment the delayed luminance signals YDLl and YDL2 respectively delayed l H and 2 H behind the input luminance signal Yin for effecting the vertical contour compensation can be obtained with a single l H delay line 43, and the insertion loss temperature compensation of 1 H delay line 43 is obtained through the ACG function or the variable gain amplifier 44, so that the levels of the delayed luminance signals YDLl and YDL2 can be automatically controlled to obtain stable regular vertical contour compensation processing.
As has been described in the foregoing, according to the invention two delayed signals delayed by different amounts can be obtained with a simple construction utilizing a single delay line and orthogonal modulation/demodulation means. Also, the orthogonal modulations of signal can be reliably demodulated for steady recovery of the delayed signals throug~
synchronous detection using the phase controlled c~rrier from the variable phase shi~ter as synchronizing signal.
DELAY CI~CUIT
BACKGROUND OF THE INVENTION
Field of the Invention:
This invention relates a delay circuit used for such purpose as contour compensation.processing on video signals dealt with ln video systems such as television receivers and television cameras and, more particular~y, to a delay circuit which can produce delayed output signals delayed by two differen.t amounts by a single delay line.
Description of the Prior Art:
.~ideo signals .in video systems such as television receivers and television cameras pass through various electric circuits and signal transmission lines having finite operation frequency ranges. Therefore, high frequency component attenuation occurs to result in a so-called reduction of resolution. By way of example, if the luminance signal contains a 3.58-MHz color subcarrier, a 35.8-MHz beat brilliance variations result in the image reproduction. To eliminate such beat interference, the video amplifier circuit in a color television receiver has frequency characteristics such that the color subcarrier is attenuated by more than 15 to 16 d3. Therefore, through such a video ~ ? ~
amplifier circuit high frequency components of the video ~ignal are attenuated t~ result in the reduction of the resolution of ~he image reproduction. In a shadow-mask type cathoderay tube, the brilliance modulation efficiency turns to be reduced when the frequency exceeds 2 M~z. The reduction of the brilliance modulation efficiency reduces the contrast to reduce the resolution.
~ compensate for s~ch reduction of the resolution, it has bee~ in practice to effect cont~ur ~ompensation processing on portions of the lumlnance signal waveform corresponding to the contour of the Lmage with an ~ ,-~overshoot or undershoot of 20 to 30%. This processing has an effect of increasing the ~h~rpness of the contour portions of the Lmage, ~hus- ~proving~the resolutisn.
DESCRIPTION OF T~E DRAWINGS
Fig. 1 is a block diagram showing the general circuit construction of a vertical contour ~ompensation circuit;
Pig. 2 is a time chart explanatory of the operation of the prior art example;
Fig. 3 is a block diagram showing an embodiment of the invention;
Fig. 4 is a vector diagram ~xplanatory of a first and second amplitude modulator;
Fig. ~ is a wave form diagram showing an input signal to the second amplitude modulator; and ~ igs. 6 and 7 are vector diagrams explanatory of the operation of voltage controlled variable phase shifter i~ the ~ame embodiment.
Heretofore, a vertical contour compensation circuit 10 as shown in Fig. 1 has been broadly used for improving the resolution of the image in the vertical dire~tion thereof.
In the vertical contour compensation circuit 10 shown in Fig. 1, an input luminance sisnal Yin which has ~een contour compensated is coupled to a ~ignal inputtermi~all to be fed to a delay line 2 and a first adder 3. The input luminance signal Yin has a waveform as shown, for instance, in A in Fig. 2.
The delay line 2 produces a first delayed luminance ~ign 1 YDLl having a waveform as ~hown ~ 8 in Fig. 2, which is delayed after the input luminance signal Yin by one horizontal scanning period 1 ~, and ~ second delayed luminance signal YDL2 having a waveform as shown in C in Fig. 2, which is delayed after the input luminance signal Yin by 2 ~. The first delayed luminance signal YDLl obtained form the del~y line 2 is fed to a subtracter 5 and a second adder 7. The second delayed luminance signal YDL2 on the other hand, is fed to the first adder 3 noted above. The first adder 3 adds the input luminance signal Yin and second delayed luminance signal YD~2 and feed~ the resultant sisnal YA (having a waveform as shown in D in Fig. 2) through an attenuator 4 to the ~ubtracter 5.. The subtracter 5 3ubtracts ~he~resultant~signal ~ from the first delayed luminance signal YDLl to obtain a contour compensation signal SAc having a waveform as shown in E in Fig. 2. This contour compensation signal SAc is fed through a level controller 6 to the second ~dder 7. The second adder 7 superLmposes the contour compensation signal SAC on the first delayed luminance signal YDLl a~d produces an ou~put luminance signal Yout as sho~n in F in Fig. 2. The signal ~out appears at an output terminal 8. It has a vertical contour compensated waveform with an oversheet and an undershoot given as a r~sult of the uper~mposition of the contour compensation ~ignal SAc on the luminance change portions, i.e., contour portions in the vertical direction of the image.
The delay-line 2 in the vertical contour compensation circuit 10 usually uses two 1 ~ delay lines 22 and 25 each providing a delay time equal to 1 H. Referring to Fig. 1, the input luminance signal Yin coupled to the input terminal 1 is fed to a modulator 21 in ~he delay line 2 for amplitude modulation; The output of the modulator 21 is fed to the first delay line 22. The delayed output signal from the first delay line 22 is fed thr,ough a firs~
gain controlled amplifier 23 to a first demodulator 24. The first gain controlled.amplifier 23 is gain controlled by the output of the first demodulator 24.
5~
The delayed output signal from ~he firqt delay line 22 is fed through the first gain controlled amplifier 23 to the second delay line 25. The delayed output signal from the second delay line 25 is fed through a ~econd gain controlled amplifier 26 to a second .
demodulator 27.
When the input luminance siqnal Yin as shown in A in Fig. 2 is fed to the amplitude modulator 21, the first demodulator 24 demodulates the 1 ~ delayed luminance signal from the first delay line 22 and produces the first delayed luminance signal YDLl delayed by 1 ~ behind the input luminance signal Yin a3 shown in B in Fig. 2. The second demodulator 27 demodulates the luminance signal that has been delayed by 1 ~ through each of the first and second delay lines 22 and 25 and produces the ~econd delayed luminance signal YDL2 delayed by 2 ~ behind the input luminance signal YDL2 as shown in C in Fig. 2.
As has been shown, the delay line 2 in the vertical cOntour compensation circuit 10 uses two 10 delay lines 22 and 25 in order to obtain the first and second delayed luminance signals YDLl and YDL2 delayed by 1 ~ and 2 ~ behind the input,luminance signal Yi~, respectively. ~owever, the delay line is generally expensive. Especially, the vertical contour compens~tion circuit 10; which used two hi~h performance 5~
1 ~ delay lines which are required to provide a comparatively long delay time alnd nevertheless have wide frequency band characteristics is inevitably very expensive. Actually, a major propQrtion of the price is occupied by the delay lines ~2 and 25. Besides, the signal level attenuation and temperature characteistics vary with individual delay lines even o~ the same ratings and specifications. Therefore, where the two delay lines 22 and 25 are used as in the above case, the delayed output signals must be passed through the gain controlled amplifiers 23 and 26 for the AG~
level controlO
SUMMARY OF THE INVE~TION
The invention has been intended in the light of the above affairs, and its object is tG provide a delay circuit having a novel construction, which can provide two different delay times with a single delay line.
Another object of the invention is to provide delay circuit, which permits steady demodulation of a orthogonal modulated signal transmitted through a single delay line.
~' A f urther object of the invention is to provide delay circuit, which permits a vertical contour compensation processing,suit~d to the image'reproduction 5~
by forming a vertical contour compensation signal from delayed luminance signals obtained from a single 1 ~ delay line and delayed 1 ~ and 2 H behind an input luminance signal respectively;
To attain the above objects of the invention, there is provided a delay circuit, which comprises modulating means for effecting orthogonal modulation of signal using ~ signal from a carrier oscillator as a carrier, del~ying means for delaying ~he modulation output of the modulating means, variable phase shifting means for phase shifting the carrier o~cillator output signal, demodulating means for effecting demodulation for effecting demodulation by synchronous detection using the output of the variable phase shifting means as a synchronizing signal, adding means for superposing a reference signal on a first demodulation of signal from the demodulating means corresponding to a first input signal to the modulating mRans and supplying the resultant signal as a second input signal to the moduiating means, and control means for controlling the amount of phase shift by the variable phase shifting means according to the reference signal demodulated by the demodulating means, wherein the demodulating means pro uces a first demodulated signal d~layed behind the first input signal cupplied to the modulating ~eans by an amount provïded Sy the delay means and a second demodulated signal delayed ~ehind the first input signal by double the amountO
DETAILED ~ESCRIPTION OF TKE INVEN$ION
Fig. 3 is a block diagr~m showing an embodLment of the invention applied to a vertical contour compensation circuit.
The illustrated vertical contour compensation circui~ 100 incorporates a delay circuit 40! which employs a ~ingle 1 ~ delay-l~ne 43 which can provide a first and second delayed luminance signal YDLl and YDL2 respectively delayed 1 ~ and 2 ~ behind an input luminance signal Yin. A first adder 60 addes the input luminance signal Yin which is coupled to an input terminal 30 and the second delayed luminance signal YDL2. A subtracter 70 produces a contour compensation signal SAc from the first delayed luminance signal YDLl and the 5Um signal from the first adder 60.
A ~econd adder 80 superimposes the contoux compensation signal SAc on the first delayed luminance qignal YDLl to obtain a vertical contour compensated output luminance s~
signal Yout' The delay circuit 40 also includes a first and second amplitude moduiator 41A and 41B for effecting commonly termed orthogonal modulation of a carrier from a carrier socillator 50. The input luminance signal coupled to the input terminal 30 is fed to the first amplitude modulator 41A. The carrier output signal from the carrier oscillator 50 is supplied directly to the first amplitude modulator 41A, while it is supplied to the second amplitude modulator 41B
through a phase shifter 51 for shifting the phase by 90~. The orthogonal modulation thus is done with carriers 90 out of phase with each other to produce a first and second amplitude modulation Sl and S2 90 out of phase with each other as shown in the vector diagram of ~'ig. 4, these modulations being fed to an adder 42 to be added together. The resultant sum signal SA from the adder 42 is fed through the l delay line 43 to a voltage controlled variable gain amplifler 44. The l H delay line 43 delays the sum signal SA by l H. The voltage controlled variable gain amplifier 44 effects insertion loss temperature compensation of l H delay line, and it is gain controlled by the output of a reference signal detector 49 to be described later. The output of the voltage controlled variable gain amplifier 44 is fed to a first and second demodulator 45A and 45~. The carrier output signal from the carrier oscilLator 50 is coupled as synchro-nizing signal through a voltage controlled variable phase shifter 52 to the first and second demodulators 45A and 45B for demodulating -the sum signal output form the voltage controlled variable gain amplifier 44 by synchronous detection. A phase shifter 53 provides a phase difference of 90 between synchronizing signals supplied to the modulators 45A and 45B. The amount of phase shift by the boltage controlled variable phase shifter 52 is controlled by the output of a level comparator 55 to be described later.
The first demodulator 45A demodulates only a component of the sum signal output of the voltage controlled variable gain amplifier 44 corresponding to the first amplitude modulation Sl by synchronous detection of the sum signal output. It recovers the first delayed luminance signal YDLl delayed 1 H behind the input luminance signal Yin, because the sum signal output fed to it from the variable gain amplifier 44 has been delayed 1 ~ through the 1 ~ delay line 43 and the first amplitude modulation Sl in the sum signal SA
is the amplitude modulation of the input luminance signal Yin on the carrier.
The first delayed luminance signal YDLl from the first demodulator 45A is fed to the subtracter 70 v~
and second adder ~0 as mentioned earlier. It is further fed through a clamp circuit 46 in the delay circuit40 to a sample/hold circuit 54 and an adder 47. A reference signal S~ coupled to a reference signal input terminal 48 is fed to the adder 47 to be superimposed on the first delayed luminance signal YDLl at a position corresponding to the ~lanking period as shown in Fig. 5.- The output of the adder 47, consisting of the reference signal S~ and first delayed luminance signal YDLl superimposed on each other, is fed to the second amplitude modulator 41B~
The second demodulator 4SB that corresponds to the second amplitude modulator 41B, demodulates only a component of the sum signal output of the voltage controlled variable gain amplifier 44 corresponding to the second amplitude modulation S2 by synchronous detection of the sum signal output. It recovers the second delayed luminance signal YDLl, which is delayed 1 H behind the first delayed luminance signal YDLl, i.e., delayed 2 H behind the input luminance signal Yin, under the control of the reference signal S~, because the second amplitude modulation S2 is the amplitudes modulation of the output consisting of the reference signal S~ and first delayed luminance signal YDLl superimposed on each other on the carrier and has been delayed 1 H through the 1 H delay line 43 before ~eing fet to it.
The second delayed luminance signal YDLl is fed to the first adder 60 for addition to the input luminance signal Yin. The sum signal YA from the first adder 60 is fed through an attenuator 65 to the subtracter 70. The subtracter 70 subtracts the first delayed luminance signal YDLl and sum signal YA one from the other to obtain the contour compensation signal SAc: The second adder 80 superimposes the contour sompensation signal SAc on the first delayed luminance signal YDLl, whereby the vertical contour compensated output luminance signal Yout is produced from the output terminal.
In this embodiment, the reference signal detector 49 detects the reference signal S~ demodulated by the second demodulator 45B and controls the gain of the voltage controlled variable gain amplifier 44 to make the signal level of the reference signal S
constant. By this automatic gain control (A~C) function, the insertion loss temperature compensation of 1 ~
delay line 43 is done in the voltage controlled variable grain amplifier 41 on the sum signal input thereto, i.e., the first and second amplitude modulations Sl and S2, having been delayed through the l ~ delay line 43. The first and second demodulators 45A and 45B, 0a~5~
to which the sum signal SA is fed through the voltage controlled variable gain amp:Llfier 44, demodulate the first delayed luminance signal YDLl perfectly free from the reference signal S~ and the perfect referenced signal S~ respectively so long as the phase relation of the synchronous detection, i.e., the phase relation between the synchronizing signals, is rightO
In this embodiment, the output signal of the carrier oscillator 50 is supplied as synchronizing signal through the voltage controlled variable phase shifter 52 to the first and second demodulators 45A
and 45B. The amount of phase shift by the voltage controlled variable phase shifter 52 is controlled according to the output of the level comparator 55.
More specifically, the level comparator 55 compares a reference voltage VREF supplied to one input terminal of it and a hold voltage VsH supplied from the sample/hold circuit 54. The output representing the result of comparison of fed through a signal selection swhich 56 to the voltage controlled variable phase shifter 52. The sample/hold circuit 54 samples and holds the output of the clamp circuit 46 at a position corresponding to the reference signal S~
superimposed on the first delayed luminance signal ~'DLl The level comparator 55 compares the levels of the reference voltage VREF, which is equal in level to the clamp voltage of the clamp circuit 46, i.e., the first delayed luminance signal YD11, and the hold voltage VsH. The first delayed luminance signal YDLl, demodulated hy the first demodulator does not contain any component corresponding to the second modulation S2 by the second amplitude modulator 41B so long as the phase of synchronous detection by the first demodulator 45A is right. In other words, with the right phase of synchronous detection by the first demodulator 45A
the first delayed luminance signal TDLl fed to the sample/hold circuit 54 does not contain the reference single S~ noted above. II1 this case, the clamp level is sampled and held by the sample/hold circuit 54.
It is to be understood that by controlling the amount o~ phase shift by the voltage controlled variable phase shifter 52 according to the output of the level comparator SS, which compares the hold voltage VsH
from the dample/hold circuit 54 and the reference voltage VREF equal to the clamped voltage, the correct phase of the synchronizing signal supplied to the first demodulator 45A can be maintained. Also, by feeding the synchronizing signal noted above through the 90 phase shifter 53 to the second demodulator 45B, the correct phase of the synchronous detection by the second demodulator 4SB maintained. In other words, through automatic phase control of the synchro-nizing signals using the voltage controlled variable phase shifter 52, the correc1_ phases of synchronous detection by the demodulators 45A and 45B can be maintained stably and reliably irrespective of variations of the delay characteristics of the l H
delay line 43 due to temperature changes or long use.
It is unknown the control state, in which the automatic phase control loop described is established at the time of the closure of power source. If the phase of the synchronous detection is deviated by 180 or more at the time of the establishment of the loop, stable pull-in cannot be obtained. For example, if the phase of the synchronous detection of the first demodulator 45~ is in a range indicated by ~ in Fig.
6, where the phase range of the voltage controlled variable phase shifter 52 is indicated at 30, ~he automatic phase control is stopped at one limit of the range ~0, so that the phase can no longer be locked at the correct phase. In this embodiment, the amount of phase shift by the voltage controlled variable phase shifter 52 is -tentatively fixed at the center 3c of the phase range as shown in Fig. 7 at the time of the closure of the power source. By so doing, reliable pull-in to the correct phase can be obtained. More specifically, at the time of the closure of the power source the control vol-tage selection which 56 is tentatively switched to the side of a ~ixed t5b~
power supply 57 by a time constant circuit 58, which detects the rising of the power source voltage.
The voltage of the fixed power supply 57, which is supplied as the control voltage to the voltage controlled variable phase shifter 52, is set to fix the phase amount to the center ~c The control voltage selection switch 56 is switched to the side of thr level comparator 55 after the lapse of a predetermined period of time determined by the time constant circuit 58.
With the switching of control vol.tage as described, the voltage controlled variable phase shifter 52 in the phase control loop starts the pull-in of phase.
from the cPnter 9c noted above. The synchronous detection phase thus can be automatically and reliably locked to the correct phase.
As has been shown, in the above embodiment the delayed luminance signals YDLl and YDL2 respectively delayed l H and 2 H behind the input luminance signal Yin for effecting the vertical contour compensation can be obtained with a single l H delay line 43, and the insertion loss temperature compensation of 1 H delay line 43 is obtained through the ACG function or the variable gain amplifier 44, so that the levels of the delayed luminance signals YDLl and YDL2 can be automatically controlled to obtain stable regular vertical contour compensation processing.
As has been described in the foregoing, according to the invention two delayed signals delayed by different amounts can be obtained with a simple construction utilizing a single delay line and orthogonal modulation/demodulation means. Also, the orthogonal modulations of signal can be reliably demodulated for steady recovery of the delayed signals throug~
synchronous detection using the phase controlled c~rrier from the variable phase shi~ter as synchronizing signal.
Claims (6)
1. A delay circuit comprising:
oscillator means;
modulating means for effecting contour modulation of first and second input signals using outputs of said oscillator means as carriers;
delaying means for delaying a modulation output of said modulating means;
variable phase shifting means for phase shifting said carriers;
demodulating means for effecting demodulation of the delayed modulation output by synchronous detection using the phase shifted carriers as synchronizing signals;
adding means for superimposing a reference signal on a first demodulated signal from said demodulating means corres-ponding to said first input signal to said modulating means and supplying the resultant signal as said second input signal to said modulating means; and control means for controlling the amount of phase shift by said variable phase shifting means according to the reference signal included in a second demodulated signal demodulated by said demodulating means;
said first demodulated signal being delayed behind said first input signal supplied to said modulating means by an amount provided by said delaying means and said second de-modulated signal being delayed behind said first input signal by double said amount.
oscillator means;
modulating means for effecting contour modulation of first and second input signals using outputs of said oscillator means as carriers;
delaying means for delaying a modulation output of said modulating means;
variable phase shifting means for phase shifting said carriers;
demodulating means for effecting demodulation of the delayed modulation output by synchronous detection using the phase shifted carriers as synchronizing signals;
adding means for superimposing a reference signal on a first demodulated signal from said demodulating means corres-ponding to said first input signal to said modulating means and supplying the resultant signal as said second input signal to said modulating means; and control means for controlling the amount of phase shift by said variable phase shifting means according to the reference signal included in a second demodulated signal demodulated by said demodulating means;
said first demodulated signal being delayed behind said first input signal supplied to said modulating means by an amount provided by said delaying means and said second de-modulated signal being delayed behind said first input signal by double said amount.
2. The delay circuit according to claim 1, further comprising a gain controlled amplifier with the gain thereof controlled according to the output of said demodulating means, the delayed modulating output from said delaying means being supplied to said demodulating means through said gain con-trolled amplifier.
3. The delay circuit according to claim 2, wherein the gain of said gain controlled amplifier is controlled according to said reference signal included in said second demodulated signal.
4. A delay circuit comprising:
oscillator means;
first modulating means for effecting contour modulation of an input video signal using an output of said oscillator means as a first carrier for providing a first modulated signal;
delaying means for delaying said first modulated signal;
variable phase shifting means for phase shifting said output of said oscillator means;
first demodulating means receiving the output of said variable phase shifting means as a syncrhonizing signal and effecting demodulation of the delayed first modulated signal to provide a first demodulated signal;
second modulating means for effecting contour modulation of a second input signal using said output of said oscillator means, phase shifted relative to said first carrier, as a second carrier;
adding means for superimposing a reference signal on said first demodulating signal and supplying the resultant signal as said second input signal to said second modulating means for providing a second modulated signal from the latter;
means for also applying said second modulated signal to said delaying means;
second demodulating means receiving the output of said variable phase shifting means, phase shifted similarly to said second carrier, as a syncrhronizing signal and effecting demodulation of the delayed second modulated signal to provide a second demodulated signal;
control means for controlling the amount of phase shift by said variable phase shifting means according to the reference signal demodulated by said second demodulating means;
and said delay circuit producing a first demodulating signal delayed behind said input video signal by an amount provided by said delaying means and a second demodulated signal delayed behind said input video signal by double the amount provided by said same delaying means.
oscillator means;
first modulating means for effecting contour modulation of an input video signal using an output of said oscillator means as a first carrier for providing a first modulated signal;
delaying means for delaying said first modulated signal;
variable phase shifting means for phase shifting said output of said oscillator means;
first demodulating means receiving the output of said variable phase shifting means as a syncrhonizing signal and effecting demodulation of the delayed first modulated signal to provide a first demodulated signal;
second modulating means for effecting contour modulation of a second input signal using said output of said oscillator means, phase shifted relative to said first carrier, as a second carrier;
adding means for superimposing a reference signal on said first demodulating signal and supplying the resultant signal as said second input signal to said second modulating means for providing a second modulated signal from the latter;
means for also applying said second modulated signal to said delaying means;
second demodulating means receiving the output of said variable phase shifting means, phase shifted similarly to said second carrier, as a syncrhronizing signal and effecting demodulation of the delayed second modulated signal to provide a second demodulated signal;
control means for controlling the amount of phase shift by said variable phase shifting means according to the reference signal demodulated by said second demodulating means;
and said delay circuit producing a first demodulating signal delayed behind said input video signal by an amount provided by said delaying means and a second demodulated signal delayed behind said input video signal by double the amount provided by said same delaying means.
5. The delay circuit according to claim 4; further comprising:
gain controlled amplifier means through which said delayed signal from said delaying means are supplied to said first and second demodulating means; and means for controlling the gain of said controlled amplifier means including detecting means for detection of said reference signal, which is part of the output of said second demodulating means,
gain controlled amplifier means through which said delayed signal from said delaying means are supplied to said first and second demodulating means; and means for controlling the gain of said controlled amplifier means including detecting means for detection of said reference signal, which is part of the output of said second demodulating means,
6. The delay circuit according to claim 4; in which said variable phase shifting means is voltage controlled; and said control means includes clamp means receiving said first demodulated signal, sample/hold means sampling an output of said clamp means, and level comparator means comparing a voltage from said sample/hold means with a reference voltage to provide a comparison voltage by which said variable phase shifting means is controlled.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57137863A JPS5928766A (en) | 1982-08-10 | 1982-08-10 | Delay circuit |
| JP137863/82 | 1982-08-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1200858A true CA1200858A (en) | 1986-02-18 |
Family
ID=15208505
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000433835A Expired CA1200858A (en) | 1982-08-10 | 1983-08-03 | Delay circuit |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4558354A (en) |
| EP (1) | EP0102773B1 (en) |
| JP (1) | JPS5928766A (en) |
| AT (1) | ATE42436T1 (en) |
| AU (1) | AU551114B2 (en) |
| CA (1) | CA1200858A (en) |
| DE (1) | DE3379709D1 (en) |
Families Citing this family (34)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60114090A (en) * | 1983-11-26 | 1985-06-20 | Toshiba Corp | Vertical contour correction device |
| GB2151429B (en) * | 1983-11-26 | 1987-03-18 | Toshiba Kk | Vertical contour correction device |
| KR920004441Y1 (en) * | 1989-12-30 | 1992-06-29 | 삼성전자 주식회사 | Aperture edge amount compensation circuit of video monitor |
| US5585007A (en) * | 1994-12-07 | 1996-12-17 | Plasmaseal Corporation | Plasma concentrate and tissue sealant methods and apparatuses for making concentrated plasma and/or tissue sealant |
| JP2004502267A (en) * | 2000-07-07 | 2004-01-22 | モサイド・テクノロジーズ・インコーポレイテッド | High-speed DRAM architecture with uniform access latency |
| US7179391B2 (en) | 2002-05-24 | 2007-02-20 | Biomet Manufacturing Corp. | Apparatus and method for separating and concentrating fluids containing multiple components |
| US20030205538A1 (en) | 2002-05-03 | 2003-11-06 | Randel Dorian | Methods and apparatus for isolating platelets from blood |
| US7992725B2 (en) | 2002-05-03 | 2011-08-09 | Biomet Biologics, Llc | Buoy suspension fractionation system |
| US7832566B2 (en) | 2002-05-24 | 2010-11-16 | Biomet Biologics, Llc | Method and apparatus for separating and concentrating a component from a multi-component material including macroparticles |
| US7845499B2 (en) | 2002-05-24 | 2010-12-07 | Biomet Biologics, Llc | Apparatus and method for separating and concentrating fluids containing multiple components |
| US20060278588A1 (en) | 2002-05-24 | 2006-12-14 | Woodell-May Jennifer E | Apparatus and method for separating and concentrating fluids containing multiple components |
| JP4423157B2 (en) * | 2004-10-06 | 2010-03-03 | キヤノン株式会社 | Power line communication apparatus and control method thereof |
| US7866485B2 (en) | 2005-02-07 | 2011-01-11 | Hanuman, Llc | Apparatus and method for preparing platelet rich plasma and concentrates thereof |
| US7708152B2 (en) | 2005-02-07 | 2010-05-04 | Hanuman Llc | Method and apparatus for preparing platelet rich plasma and concentrates thereof |
| JP4961354B2 (en) | 2005-02-07 | 2012-06-27 | ハヌマン リミテッド ライアビリティ カンパニー | Platelet rich plasma concentration apparatus and method |
| US8567609B2 (en) | 2006-05-25 | 2013-10-29 | Biomet Biologics, Llc | Apparatus and method for separating and concentrating fluids containing multiple components |
| US8328024B2 (en) | 2007-04-12 | 2012-12-11 | Hanuman, Llc | Buoy suspension fractionation system |
| JP5479319B2 (en) | 2007-04-12 | 2014-04-23 | バイオメット・バイオロジックス・リミテッド・ライアビリティ・カンパニー | Buoy suspension fractionation system |
| EP2567692B1 (en) | 2008-02-27 | 2016-04-06 | Biomet Biologics, LLC | Use of a device for obtaining interleukin-1 receptor antagonist rich solutions |
| WO2009111338A1 (en) | 2008-02-29 | 2009-09-11 | Biomet Manufacturing Corp. | A system and process for separating a material |
| US8012077B2 (en) | 2008-05-23 | 2011-09-06 | Biomet Biologics, Llc | Blood separating device |
| US8187475B2 (en) | 2009-03-06 | 2012-05-29 | Biomet Biologics, Llc | Method and apparatus for producing autologous thrombin |
| US8313954B2 (en) | 2009-04-03 | 2012-11-20 | Biomet Biologics, Llc | All-in-one means of separating blood components |
| US9011800B2 (en) | 2009-07-16 | 2015-04-21 | Biomet Biologics, Llc | Method and apparatus for separating biological materials |
| US8591391B2 (en) | 2010-04-12 | 2013-11-26 | Biomet Biologics, Llc | Method and apparatus for separating a material |
| US9642956B2 (en) | 2012-08-27 | 2017-05-09 | Biomet Biologics, Llc | Apparatus and method for separating and concentrating fluids containing multiple components |
| US9895418B2 (en) | 2013-03-15 | 2018-02-20 | Biomet Biologics, Llc | Treatment of peripheral vascular disease using protein solutions |
| US10143725B2 (en) | 2013-03-15 | 2018-12-04 | Biomet Biologics, Llc | Treatment of pain using protein solutions |
| US9950035B2 (en) | 2013-03-15 | 2018-04-24 | Biomet Biologics, Llc | Methods and non-immunogenic compositions for treating inflammatory disorders |
| US10208095B2 (en) | 2013-03-15 | 2019-02-19 | Biomet Manufacturing, Llc | Methods for making cytokine compositions from tissues using non-centrifugal methods |
| US20140271589A1 (en) | 2013-03-15 | 2014-09-18 | Biomet Biologics, Llc | Treatment of collagen defects using protein solutions |
| US9713810B2 (en) | 2015-03-30 | 2017-07-25 | Biomet Biologics, Llc | Cell washing plunger using centrifugal force |
| US9757721B2 (en) | 2015-05-11 | 2017-09-12 | Biomet Biologics, Llc | Cell washing plunger using centrifugal force |
| US10171282B1 (en) * | 2017-11-09 | 2019-01-01 | Sprint Communications Company L.P. | Dynamic optimization of amplitude weights |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL6604020A (en) * | 1966-03-26 | 1967-09-27 | ||
| JPS5141297B1 (en) * | 1969-11-24 | 1976-11-09 | ||
| GB1353618A (en) * | 1970-08-29 | 1974-05-22 | Marconi Co Ltd | Colour television camera equipments |
| JPS54143021A (en) * | 1978-04-28 | 1979-11-07 | Sony Corp | Processing circuit of video signal |
| CA1187167A (en) * | 1981-07-09 | 1985-05-14 | Sadaaki Tanaka | Video signal processing circuit |
| JPH0230943U (en) * | 1988-08-19 | 1990-02-27 |
-
1982
- 1982-08-10 JP JP57137863A patent/JPS5928766A/en active Granted
-
1983
- 1983-08-02 AU AU17503/83A patent/AU551114B2/en not_active Ceased
- 1983-08-03 CA CA000433835A patent/CA1200858A/en not_active Expired
- 1983-08-08 US US06/521,363 patent/US4558354A/en not_active Expired - Fee Related
- 1983-08-09 EP EP83304600A patent/EP0102773B1/en not_active Expired
- 1983-08-09 DE DE8383304600T patent/DE3379709D1/en not_active Expired
- 1983-08-09 AT AT83304600T patent/ATE42436T1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5928766A (en) | 1984-02-15 |
| AU1750383A (en) | 1984-02-16 |
| EP0102773B1 (en) | 1989-04-19 |
| EP0102773A2 (en) | 1984-03-14 |
| EP0102773A3 (en) | 1985-07-03 |
| AU551114B2 (en) | 1986-04-17 |
| JPH0430230B2 (en) | 1992-05-21 |
| ATE42436T1 (en) | 1989-05-15 |
| US4558354A (en) | 1985-12-10 |
| DE3379709D1 (en) | 1989-05-24 |
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