CA1204879A - Universal coupling means - Google Patents
Universal coupling meansInfo
- Publication number
- CA1204879A CA1204879A CA000433842A CA433842A CA1204879A CA 1204879 A CA1204879 A CA 1204879A CA 000433842 A CA000433842 A CA 000433842A CA 433842 A CA433842 A CA 433842A CA 1204879 A CA1204879 A CA 1204879A
- Authority
- CA
- Canada
- Prior art keywords
- bus
- local bus
- peripheral unit
- data
- exchange
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
Abstract
A B S T R A C T
The invention relates to a universal coupling means for linking processing systems incorporating at least computers or processors with at least one peripheral unit.
Each processing system comprises at least one processor and an exchange bus for exchanging information with the peripheral unit.
Coupling means comprise bus controllers connected respectively to the exchange buses and to a local bus, itself connected to the peripheral unit by means for controlling exchanges of data and for processing control and state information. The bus controllers are able to manage the access protocols to the exchange buses, the information exchanges on the exchange buses and on the local bus, as well as any request made by a processor for access to the local bus. The control means comprise a microprocessor for managing the priorities of the access requests of the processors and the processing of controls and states contained in the information exchanged on the local bus. Selection means are connected to the bus controllers and controlled by the management microprocessor for selecting, as a function of the priorities, the controller able to ensure a data exchange on the local bus. An input and output buffer register is connected to the local bus and to the peripheral unit for receiving the data to be transmitted to the peripheral unit or for receiving the data to be transmitted to one of the processors.
The invention relates to a universal coupling means for linking processing systems incorporating at least computers or processors with at least one peripheral unit.
Each processing system comprises at least one processor and an exchange bus for exchanging information with the peripheral unit.
Coupling means comprise bus controllers connected respectively to the exchange buses and to a local bus, itself connected to the peripheral unit by means for controlling exchanges of data and for processing control and state information. The bus controllers are able to manage the access protocols to the exchange buses, the information exchanges on the exchange buses and on the local bus, as well as any request made by a processor for access to the local bus. The control means comprise a microprocessor for managing the priorities of the access requests of the processors and the processing of controls and states contained in the information exchanged on the local bus. Selection means are connected to the bus controllers and controlled by the management microprocessor for selecting, as a function of the priorities, the controller able to ensure a data exchange on the local bus. An input and output buffer register is connected to the local bus and to the peripheral unit for receiving the data to be transmitted to the peripheral unit or for receiving the data to be transmitted to one of the processors.
Description
~2~7g UNIVERSAL COUPLING MEANS
-BACKGROUND OF TllE INVENTION
The present invention relates to a universal coupling means for linking processing systems incorporating at least computers or processors, with at least one peripheral unit. It applies more particularly to multicomputer systems in which it is necessary to exchange information between the memories of several processing systems and one or more peripheral units, such as e.g. magnetic tape unreeling devices or disks.
In general terms, a processing system is a logic processing unit, which can have one or more processors or computers, optionally realized with the aid of microprocessors and input - output units and optionally peripheral units.
Coupling means are known making it possible to manage information exchanges between several processing systems and at least one peripheral unit. In general, these coupling means are designed as a function of` each type of` peripheral unit to be lin~ed with several processing systems.
Thus, the connection of ar.other type of peripheral unit makes it necessary for the user to have a new coupling device adapted to the new peripheral unit ; chosen. This impossibility of rendering common place the connection of random peripheral unit types in a multicomputer system leads to very long connect-ion delays, high costs for each coupling of a new 3D peripheral unit, a number of different coupling devices for the same multicomputer system and dif~icult choices with respect to the peripheral unit.
. ~
~, ~2~4~
SUMMARY OF THE INVENTION
The object of the present invention is to obviate these disadvantages and more particularly to provide a coupling means between several processing systems, e.g. computers, and at least one peripheral unit making it possible in simple manner, to connect a random type of peripheral unit to several processors or computers~ even if said unit and said processors have operating specifications or narrowly making their operations difficultly compatible. This coupling means, apart from the fact that it permits and simplifies the connection of any random peripheral unit to processing systems, also makes it possible to easily manage conflicts regarding access requests of the processing systems to each peripheral unit.
Moreover, the invention also aims at increasing the access availability between the processing systems and a peripheral unit by offering an access by two basically separate buses.
The invention relates to a universal coupling means for linking information processing systems and at least one peripheral unit J each processing sys-tem comprising at least one processor and an exchange bus for exchanging information with the peripheral unit. The means comprise bus controllers connected respectively to the exchange buses and to a local bus 9 itself connected to the peripheral unit by means for controlling exchanges of data and for processing control and state information, the bus controllers~ being able to manage the access proto-cols to the exchange buses, the information exchanges on the exchange buses and on the local bus 9 as well as any request made by a processor for access to the local bus.
~2~1~87~
According to another feature of the invention, the control means comprise a microprocessor for managing the priorities of the access requests of the processors and the processing of controls and states contained in the information exchanged on the local bus, selection means connected to the bus controllers and controlled by the manage-ment microprocessor for selecting, as a function o~ the priorities, the con~roller able to ensure a data exchange on the local bus, and an input and output buffer register connected to the local bus and to the peripheral unit for receiving the data to be transmitted to the peripheral unit or for receiving the data to be transmitted to one of the processors.
According to another feature 5 the selection means comprise a data code control circuit connect-ing the local bus to the input and output bu~fer register~
Finally, according to another feature~ the control circuit comprises a buffer store connected to the local bus and to the input and output buffer register9 and a device connected to said store for controlling a cyclic data code.
DESCRIPTION OF THE DRAWING AND PREFERRED EMBODIMENTS
The invention is described in greater detail hereina~ter relative to non limitative embodiments and the attached drawing showing diagrammatically the coupling system according to -the invention.
The coupling system 1 diagrammatically shown in the drawing makes it possible to link processing systems 4 and 5, with at least one peripheral unit 6, such as e.g. a magnetic tape unreeling device or ~o~
a disk. The processors 2, 3 of these processing systems are respectively connected to bus controllers 7, 8 permitting the exchange of information between the processing systems and the peripheral unit 6.
These information exchanges take place across exchange buses 9, 10, each of these buses being associated with the processors of each processing system. In per se known manner said information contains data, controls and states, expressed in binary form. The controls or commands ore instruct-ions given to the processing systems or to the peripheral unit for the performance of an action.
The states make it possible to express in binary form, the situations in which the peripheral unit is before, during or after performing an action.
The exchange buses 9, 10, diagrammatically shown in the drawing, are well known in the art and can e.g. be buses as defined by IEEE standard 4B8.
In the considered embodiment, the number of periph-eral units has been limited to one and the numberof exchange buses 9, 10 to 2. However, it is obvious that these numbers can differ. For example, peripheral unit 6 could be replaced by a row of peripheral units, connected in series or in parallel.
The coupling system 1 has, for each exchange bus 9, 10, a bus controller. rrhese bus controllers 18, 19 are connected to a local bus 17 and ensure the management of the access protocols to the corresponding specific buses 9, 10. These bus controllers are known and can e.g. be controllers of type TMS 9914 defined in IEEE standard 4R8. In per se known manner, the protocols are conventions ~LZ~
defining the performance of information exchanges between specific buses 9, 10 and bus controllers 189 19.
The means also comprises control means 21 5 incorporating a microprocessor 22, associated with a memory 23. This microprocessor manages the priorities of access requests from processors 2, 3 and processing systems 4, 5, whilst also ~aking it possible to process commands and states 10 contained in the information exchanged on local bus 17 and which are supplied or received by the management microprocessor 22 on a command bus 24 and on a state bus 25. The command or control means also comprise selection means 26 connected 15 to bus controllers 18, 19 and contro~ed by manage-ment processor 22 in order to select, as a function of the priorities, whichever of these controllers can ensure a data exchange at a given time.
The control means also comprise an input and 20 output re~ister 27 connected to local bus 17 and to peripheral unit 6, for receiving the data to be transmitted to this peripheral unit, or for receiving the data to be -transmitted to one of the processors 2, 3. Control means 21 also comprise a 25 circuit 30 controlling the code of the data exchanged on local bus 17 and connecting said bus to input and output register 27. This control circuit can be constituted in per se known manner by a buffer store 29 connected to local bus 17 and to register s 30 27, as well as a device 30 connected to bu~fer store 29, in order to control the cyclic code of the data exchanged on bus 17.
...
87~
For each exchange bus controller, the selection means 26 comprise a writing or reading control circuit, associated with the management microprocessor, in order to control, via the corresponding controller, the reading or writing of information on exchange buses 9, 10.
The selection means 26 also comprise a reading or writing control circuit, connected to management microprocessor 22 and to input and output register 27, for controlling the reading of data supplied by peripheral unit 6 and contained in register 27, or for controlling the writing into this register of data from local bus 17 and which are supplied by one of the processing systems 2, 3. Selection means 26 are well known in the art and do not have to be described in detail here.
The system described hereinbefore functions in the following way. For example, if the processing system 4 wishes to have access to the peripheral unit 6, it supplies a data blockj called the command or control block, to the management microprocessor 22. As a function of the avail-ability of peripheral unit 6, compared with that of requests other than that of e.g. processing system 5, manage~ent microprocessor 22 replies by issuing a data block, ca],led acknowledgement of receipt and controls and positions the controls necessary for peripheral unit 6 on control bus 24 with, i~ necessary, the control of the states of ' - the peripheral unit on state bus 25. Then when e.g. processing system 4 wishes to write data into peripheral unit 6, it supplies its data block on ~2~
bus 9 for buffer store 29. Under the control o~
microprocessor 22, cvntrol device 30 checks the absence of errors in the data block, which i5 then transmitted from the buffer store 29 ko peripheral unit 6 by input and output register 27.
After reading state bus 25, microprocessor 22 supplies to processing system 4, a data block, called performance report, indicating whether the overall transfer of data has been correctly performed up to peripheral unit 6.
Hereinbefore, the elementary exchange of information has taken place in the following way.
When e.g. processing system 4 wishes to supply elementary data to coupling system 1, bus controller 18 supplies a request REQ by selection means 26.
The latter supplies a request acceptance signal ACQ and transfers the elementary data, into buffer store 29 by means of local bus 17, by supplying a reading control signal R to bus controller 18.
In the same way, selection means 26 also supplies the input or output register 27 with a data writing control signal W. The data are transferred into this register, after being rerecorded in buffer store 29, in such a way that device 30 controls the cyclic code of said data.
The other information, such as commands or states, which are transmitted by the specific bus 9 and which come -_ from processing system 49 transit vn local bus 17. They are processed by the manage-ment microprocessor 22 for supply to peripheralunit 6. The same operations are per~ormed i~ per-ipheral unit 6 issues a request for obtaining access ~2~ 379 to processing system 4, or to processing system 5.
It is obvious that in the system described hereinbefore, the means used could have been replaced by equivalent means, without passing beyond the scope of the invention.
-BACKGROUND OF TllE INVENTION
The present invention relates to a universal coupling means for linking processing systems incorporating at least computers or processors, with at least one peripheral unit. It applies more particularly to multicomputer systems in which it is necessary to exchange information between the memories of several processing systems and one or more peripheral units, such as e.g. magnetic tape unreeling devices or disks.
In general terms, a processing system is a logic processing unit, which can have one or more processors or computers, optionally realized with the aid of microprocessors and input - output units and optionally peripheral units.
Coupling means are known making it possible to manage information exchanges between several processing systems and at least one peripheral unit. In general, these coupling means are designed as a function of` each type of` peripheral unit to be lin~ed with several processing systems.
Thus, the connection of ar.other type of peripheral unit makes it necessary for the user to have a new coupling device adapted to the new peripheral unit ; chosen. This impossibility of rendering common place the connection of random peripheral unit types in a multicomputer system leads to very long connect-ion delays, high costs for each coupling of a new 3D peripheral unit, a number of different coupling devices for the same multicomputer system and dif~icult choices with respect to the peripheral unit.
. ~
~, ~2~4~
SUMMARY OF THE INVENTION
The object of the present invention is to obviate these disadvantages and more particularly to provide a coupling means between several processing systems, e.g. computers, and at least one peripheral unit making it possible in simple manner, to connect a random type of peripheral unit to several processors or computers~ even if said unit and said processors have operating specifications or narrowly making their operations difficultly compatible. This coupling means, apart from the fact that it permits and simplifies the connection of any random peripheral unit to processing systems, also makes it possible to easily manage conflicts regarding access requests of the processing systems to each peripheral unit.
Moreover, the invention also aims at increasing the access availability between the processing systems and a peripheral unit by offering an access by two basically separate buses.
The invention relates to a universal coupling means for linking information processing systems and at least one peripheral unit J each processing sys-tem comprising at least one processor and an exchange bus for exchanging information with the peripheral unit. The means comprise bus controllers connected respectively to the exchange buses and to a local bus 9 itself connected to the peripheral unit by means for controlling exchanges of data and for processing control and state information, the bus controllers~ being able to manage the access proto-cols to the exchange buses, the information exchanges on the exchange buses and on the local bus 9 as well as any request made by a processor for access to the local bus.
~2~1~87~
According to another feature of the invention, the control means comprise a microprocessor for managing the priorities of the access requests of the processors and the processing of controls and states contained in the information exchanged on the local bus, selection means connected to the bus controllers and controlled by the manage-ment microprocessor for selecting, as a function o~ the priorities, the con~roller able to ensure a data exchange on the local bus, and an input and output buffer register connected to the local bus and to the peripheral unit for receiving the data to be transmitted to the peripheral unit or for receiving the data to be transmitted to one of the processors.
According to another feature 5 the selection means comprise a data code control circuit connect-ing the local bus to the input and output bu~fer register~
Finally, according to another feature~ the control circuit comprises a buffer store connected to the local bus and to the input and output buffer register9 and a device connected to said store for controlling a cyclic data code.
DESCRIPTION OF THE DRAWING AND PREFERRED EMBODIMENTS
The invention is described in greater detail hereina~ter relative to non limitative embodiments and the attached drawing showing diagrammatically the coupling system according to -the invention.
The coupling system 1 diagrammatically shown in the drawing makes it possible to link processing systems 4 and 5, with at least one peripheral unit 6, such as e.g. a magnetic tape unreeling device or ~o~
a disk. The processors 2, 3 of these processing systems are respectively connected to bus controllers 7, 8 permitting the exchange of information between the processing systems and the peripheral unit 6.
These information exchanges take place across exchange buses 9, 10, each of these buses being associated with the processors of each processing system. In per se known manner said information contains data, controls and states, expressed in binary form. The controls or commands ore instruct-ions given to the processing systems or to the peripheral unit for the performance of an action.
The states make it possible to express in binary form, the situations in which the peripheral unit is before, during or after performing an action.
The exchange buses 9, 10, diagrammatically shown in the drawing, are well known in the art and can e.g. be buses as defined by IEEE standard 4B8.
In the considered embodiment, the number of periph-eral units has been limited to one and the numberof exchange buses 9, 10 to 2. However, it is obvious that these numbers can differ. For example, peripheral unit 6 could be replaced by a row of peripheral units, connected in series or in parallel.
The coupling system 1 has, for each exchange bus 9, 10, a bus controller. rrhese bus controllers 18, 19 are connected to a local bus 17 and ensure the management of the access protocols to the corresponding specific buses 9, 10. These bus controllers are known and can e.g. be controllers of type TMS 9914 defined in IEEE standard 4R8. In per se known manner, the protocols are conventions ~LZ~
defining the performance of information exchanges between specific buses 9, 10 and bus controllers 189 19.
The means also comprises control means 21 5 incorporating a microprocessor 22, associated with a memory 23. This microprocessor manages the priorities of access requests from processors 2, 3 and processing systems 4, 5, whilst also ~aking it possible to process commands and states 10 contained in the information exchanged on local bus 17 and which are supplied or received by the management microprocessor 22 on a command bus 24 and on a state bus 25. The command or control means also comprise selection means 26 connected 15 to bus controllers 18, 19 and contro~ed by manage-ment processor 22 in order to select, as a function of the priorities, whichever of these controllers can ensure a data exchange at a given time.
The control means also comprise an input and 20 output re~ister 27 connected to local bus 17 and to peripheral unit 6, for receiving the data to be transmitted to this peripheral unit, or for receiving the data to be -transmitted to one of the processors 2, 3. Control means 21 also comprise a 25 circuit 30 controlling the code of the data exchanged on local bus 17 and connecting said bus to input and output register 27. This control circuit can be constituted in per se known manner by a buffer store 29 connected to local bus 17 and to register s 30 27, as well as a device 30 connected to bu~fer store 29, in order to control the cyclic code of the data exchanged on bus 17.
...
87~
For each exchange bus controller, the selection means 26 comprise a writing or reading control circuit, associated with the management microprocessor, in order to control, via the corresponding controller, the reading or writing of information on exchange buses 9, 10.
The selection means 26 also comprise a reading or writing control circuit, connected to management microprocessor 22 and to input and output register 27, for controlling the reading of data supplied by peripheral unit 6 and contained in register 27, or for controlling the writing into this register of data from local bus 17 and which are supplied by one of the processing systems 2, 3. Selection means 26 are well known in the art and do not have to be described in detail here.
The system described hereinbefore functions in the following way. For example, if the processing system 4 wishes to have access to the peripheral unit 6, it supplies a data blockj called the command or control block, to the management microprocessor 22. As a function of the avail-ability of peripheral unit 6, compared with that of requests other than that of e.g. processing system 5, manage~ent microprocessor 22 replies by issuing a data block, ca],led acknowledgement of receipt and controls and positions the controls necessary for peripheral unit 6 on control bus 24 with, i~ necessary, the control of the states of ' - the peripheral unit on state bus 25. Then when e.g. processing system 4 wishes to write data into peripheral unit 6, it supplies its data block on ~2~
bus 9 for buffer store 29. Under the control o~
microprocessor 22, cvntrol device 30 checks the absence of errors in the data block, which i5 then transmitted from the buffer store 29 ko peripheral unit 6 by input and output register 27.
After reading state bus 25, microprocessor 22 supplies to processing system 4, a data block, called performance report, indicating whether the overall transfer of data has been correctly performed up to peripheral unit 6.
Hereinbefore, the elementary exchange of information has taken place in the following way.
When e.g. processing system 4 wishes to supply elementary data to coupling system 1, bus controller 18 supplies a request REQ by selection means 26.
The latter supplies a request acceptance signal ACQ and transfers the elementary data, into buffer store 29 by means of local bus 17, by supplying a reading control signal R to bus controller 18.
In the same way, selection means 26 also supplies the input or output register 27 with a data writing control signal W. The data are transferred into this register, after being rerecorded in buffer store 29, in such a way that device 30 controls the cyclic code of said data.
The other information, such as commands or states, which are transmitted by the specific bus 9 and which come -_ from processing system 49 transit vn local bus 17. They are processed by the manage-ment microprocessor 22 for supply to peripheralunit 6. The same operations are per~ormed i~ per-ipheral unit 6 issues a request for obtaining access ~2~ 379 to processing system 4, or to processing system 5.
It is obvious that in the system described hereinbefore, the means used could have been replaced by equivalent means, without passing beyond the scope of the invention.
Claims (3)
1. A universal coupling means for linking information processing systems and at least one peripheral unit, each processing system comprising at least one processor and an exchange bus for exchanging information with the peripheral unit, said coupling means comprising bus controllers connected respectively to the exchange buses and to a local bus, itself connected to the peripheral unit by means for controlling exchanges of data and for processing control and state information, the bus controllers being able to manage the access protocols to the exchange buses, the information exchanges on the exchange buses and on the local bus, as well as any request made by a processor for access to the local bus, wherein the control means comprise a microprocessor for managing the priorities of the access requests of the processors and the processing of controls and states contained in the information exchanged on the local bus, selection means connected to the bus controllers and controlled by the manage-ment microprocessor for selecting, as a function of the priorities, the controller able to ensure a data exchange on the local bus, and an input and output buffer register connected to the local bus and to the peripheral unit for receiving the data to be transmitted to the peripheral unit or for receiving the data to be transmitted to one of the processors.
2. A coupling system according to claim 1, wherein the control or command means also comprise a data code control circuit, connecting the local bus to the input and output buffer register.
3. A coupling means according to claim 2, wherein the control circuit comprises a buffer store connected to the local bus and to the input and output buffer store, as well as a device connected to said store for controlling a cyclic data code.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR8213765A FR2531550B1 (en) | 1982-08-06 | 1982-08-06 | UNIVERSAL COUPLING DEVICE FOR THE COMMUNICATION OF INFORMATION PROCESSING ASSEMBLIES AND AT LEAST ONE PERIPHERAL UNIT |
| FREN8213765 | 1982-08-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1204879A true CA1204879A (en) | 1986-05-20 |
Family
ID=9276700
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000433842A Expired CA1204879A (en) | 1982-08-06 | 1983-08-04 | Universal coupling means |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4682285A (en) |
| EP (1) | EP0102278B1 (en) |
| JP (1) | JPS5945528A (en) |
| CA (1) | CA1204879A (en) |
| DE (1) | DE3374463D1 (en) |
| FR (1) | FR2531550B1 (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2177824A (en) * | 1985-07-02 | 1987-01-28 | Director Computer Products Lim | Computer peripheral controller system |
| US5003508A (en) * | 1985-10-31 | 1991-03-26 | Floating Point Systems, Inc. | Linear nearest neighbor interconnect bus system |
| US5297260A (en) * | 1986-03-12 | 1994-03-22 | Hitachi, Ltd. | Processor having a plurality of CPUS with one CPU being normally connected to common bus |
| US6379998B1 (en) | 1986-03-12 | 2002-04-30 | Hitachi, Ltd. | Semiconductor device and method for fabricating the same |
| US4932040A (en) * | 1987-12-07 | 1990-06-05 | Bull Hn Information Systems Inc. | Bidirectional control signalling bus interface apparatus for transmitting signals between two bus systems |
| DD266436B3 (en) * | 1987-12-11 | 1993-02-04 | Jenoptik Jena Gmbh | SYSTEMBUSER EXPANSION FOR COUPLING MULTIMASTER-AFFORDABLE MULTI-SYSTEMS |
| US5278974A (en) * | 1989-12-04 | 1994-01-11 | Digital Equipment Corporation | Method and apparatus for the dynamic adjustment of data transfer timing to equalize the bandwidths of two buses in a computer system having different bandwidths |
| CA2044022A1 (en) * | 1990-06-28 | 1991-12-29 | Miriam A. Nihart | Common agent computer management system and method |
| US5664142A (en) * | 1990-10-01 | 1997-09-02 | International Business Machines Corporation | Chained DMA devices for crossing common buses |
| JPH04118382U (en) * | 1991-01-31 | 1992-10-22 | 太陽誘電株式会社 | Electronic parts packaging |
| KR940001593B1 (en) * | 1991-09-20 | 1994-02-25 | 삼성전자 주식회사 | Bus-controller operating system with main controller |
| NL9301093A (en) * | 1993-06-23 | 1995-01-16 | Nederland Ptt | Processor circuit comprising a first processor, a memory and a peripheral circuit, and a system comprising the processor circuit and a second processor. |
| US5598542A (en) * | 1994-08-08 | 1997-01-28 | International Business Machines Corporation | Method and apparatus for bus arbitration in a multiple bus information handling system using time slot assignment values |
| FR2791203A1 (en) * | 1999-03-17 | 2000-09-22 | Schlumberger Systems & Service | DEVICE FOR AUTHENTICATING A MESSAGE DURING A CRYPTOGRAPHIC PROCESSING OPERATION OF SAID MESSAGE |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3810105A (en) * | 1967-10-26 | 1974-05-07 | Xerox Corp | Computer input-output system |
| US4007448A (en) * | 1974-08-15 | 1977-02-08 | Digital Equipment Corporation | Drive for connection to multiple controllers in a digital data secondary storage facility |
| US4228496A (en) * | 1976-09-07 | 1980-10-14 | Tandem Computers Incorporated | Multiprocessor system |
| JPS5588116A (en) * | 1978-12-27 | 1980-07-03 | Fujitsu Ltd | Input-output subsystem |
| JPS55124830A (en) * | 1979-03-19 | 1980-09-26 | Toshiba Corp | Input and output control system |
| JPS5679332A (en) * | 1979-11-30 | 1981-06-29 | Casio Comput Co Ltd | Printing system of electronic register |
| JPS5748127A (en) * | 1980-09-04 | 1982-03-19 | Nec Corp | Data processor |
| JPS57105021A (en) * | 1980-12-23 | 1982-06-30 | Fujitsu Ltd | Input/output device |
-
1982
- 1982-08-06 FR FR8213765A patent/FR2531550B1/en not_active Expired
-
1983
- 1983-07-29 DE DE8383401573T patent/DE3374463D1/en not_active Expired
- 1983-07-29 EP EP83401573A patent/EP0102278B1/en not_active Expired
- 1983-08-04 CA CA000433842A patent/CA1204879A/en not_active Expired
- 1983-08-05 JP JP58142626A patent/JPS5945528A/en active Pending
-
1986
- 1986-08-29 US US06/902,110 patent/US4682285A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| FR2531550A1 (en) | 1984-02-10 |
| DE3374463D1 (en) | 1987-12-17 |
| JPS5945528A (en) | 1984-03-14 |
| US4682285A (en) | 1987-07-21 |
| FR2531550B1 (en) | 1987-09-25 |
| EP0102278B1 (en) | 1987-11-11 |
| EP0102278A1 (en) | 1984-03-07 |
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