CA1206531A - Transmitter and receiver for controlling remote elements - Google Patents

Transmitter and receiver for controlling remote elements

Info

Publication number
CA1206531A
CA1206531A CA000434482A CA434482A CA1206531A CA 1206531 A CA1206531 A CA 1206531A CA 000434482 A CA000434482 A CA 000434482A CA 434482 A CA434482 A CA 434482A CA 1206531 A CA1206531 A CA 1206531A
Authority
CA
Canada
Prior art keywords
receiver
transmitter
address code
radio frequency
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000434482A
Other languages
French (fr)
Inventor
Joseph W. Twardowski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chamberlain Manufacturing Corp
Original Assignee
Chamberlain Manufacturing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chamberlain Manufacturing Corp filed Critical Chamberlain Manufacturing Corp
Application granted granted Critical
Publication of CA1206531A publication Critical patent/CA1206531A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G08SIGNALLING
    • G08CTRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
    • G08C19/00Electric signal transmission systems
    • G08C19/16Electric signal transmission systems in which transmission is by pulses
    • G08C19/28Electric signal transmission systems in which transmission is by pulses using pulse code
    • GPHYSICS
    • G07CHECKING-DEVICES
    • G07CTIME OR ATTENDANCE REGISTERS; REGISTERING OR INDICATING THE WORKING OF MACHINES; GENERATING RANDOM NUMBERS; VOTING OR LOTTERY APPARATUS; ARRANGEMENTS, SYSTEMS OR APPARATUS FOR CHECKING NOT PROVIDED FOR ELSEWHERE
    • G07C9/00Individual registration on entry or exit
    • G07C9/00174Electronically operated locks; Circuits therefor; Nonmechanical keys therefor, e.g. passive or active electrical keys or other data carriers without mechanical keys
    • G07C9/00817Electronically operated locks; Circuits therefor; Nonmechanical keys therefor, e.g. passive or active electrical keys or other data carriers without mechanical keys where the code of the lock can be programmed
    • GPHYSICS
    • G07CHECKING-DEVICES
    • G07CTIME OR ATTENDANCE REGISTERS; REGISTERING OR INDICATING THE WORKING OF MACHINES; GENERATING RANDOM NUMBERS; VOTING OR LOTTERY APPARATUS; ARRANGEMENTS, SYSTEMS OR APPARATUS FOR CHECKING NOT PROVIDED FOR ELSEWHERE
    • G07C9/00Individual registration on entry or exit
    • G07C9/00174Electronically operated locks; Circuits therefor; Nonmechanical keys therefor, e.g. passive or active electrical keys or other data carriers without mechanical keys
    • G07C9/00857Electronically operated locks; Circuits therefor; Nonmechanical keys therefor, e.g. passive or active electrical keys or other data carriers without mechanical keys where the code of the data carrier can be programmed

Abstract

ABSTRACT
Transmitters and receivers for controlling remote elements which use a synchronous serial transmission format and which allows changes in coding to be automatically made between the receiver and transmitter and wherein the code is stored in memories of the transmitter and receiver and wherein the receiver can generate and transmit a new code with a light emitting diode so as to change the code in the transmitter. The transmitter and the receiver use micro-computers which are suitably programmed and include non-volatile memories.

Description

~2~ S3~

SPECIFICATION
This invention rela~es in general to control transmitters and receivers and in particular to a novel control system.
Remote control transmitters ~nd receivers are known as, for example, for garage door openers and other devices. Initially, a different carrier frequency was utilized for each pair of transmitters and receivers ; 80 as to isolate them from other units. Also, various coding schemes have been utilized to encode data into binary form. Certain of such transmitters and receivers include a plurality of two position switches which control the coding for the transmitter and receiver and in such systems the codes can be changed by manually changing the positions of the switches to different positions to assure that the po~ltion of the switches in the transmitter and receiver are the same.
The present invention comprise6 a novel multi-channel transmitter and receiver for controllin~
a plurality of functions and includes the feature of changing the code in the receiver and transmitter to one of a large number of codes in an automatic manner. A
pulse length binary code i~ utilized.
When it is desixed to change the identification code, a program mode switch is closed in the receiver and the micro-computer recalls from the non-volatile memory the la6t 6tored code. Using this code as a start~ it performs a random number generation algorithm and stores the newly generated cote in the non-volatile memory and immediately transmit6 the new code through a light emitting diode. The transmission format with the . ~

12~S31 light emitting diode at the receiver continues until the pro-gram mode switch is turned off. During the energization of the light emitting diode in the receiver, the transmitter is placed in close proximity to the receiver so that it detects the code from the light emitting diode and the new code is then stored in the memory of the transmitter which then produces a flashing ready signal to indicate to the operator that the programming cycle has been completed.
It is seen that the present invention provides an improved remote control system that can be used for a number of channels and allows for automatic change of the address coding between the transmitter and receiver.
In summary, the invention provides apparatus for con-trolling a receiver with a remote radio frequency transmitter comprising a first micro-processor and a first memory means in said receiver for storing at least one address code, non-radio frequency transmitting means in said receiver, switch means for energizing said non-radio frequency transmitting means to transmit an address code, a non-radio frequency receiving means in said transmitter for receiving said address code, a second microprocessor and second memory means in said transmitter for storing said address code, radio frequency radiating means in said transmitter for radiating said address code, receiving means in said receiver for receiving said radio frequency radia-ted address code, said first microprocessor in said receiver comparing the received address code with the address code stored in said first memory, an output circuit energized by said comparing means when said addresses are the same, wherein said first memory means comprises a non-volatile memory and a programmable read only memory and said second memory means com-prises a non-volatile memory and a programmable read only memory.

12a~S31 Another object of the invention is to provide trans-mitters and receivers which have a large number of possible codes so as to eliminate interference between closely spaced transmitters and receiver systems.
Yet another object of the invention is to provide an improved transmitter and receiver system for a remote con-trol device.
Other objects, features and advantages of the inven-tion will be readily apparent from the following description of certain preferred embodiments thereof taken in conjunction with the accompanying drawings although variations and modifica-tions may be effected without departing from the spirit and scope of the novel concepts of the disclosure and in which:

-2a-- 12¢1 ~531 ON THE DRAWINGS
Figure 1 comprises a block diagram of the transmitter;
~igure 2 comprises a flow chart for the transmitter;
Figure 3 comprises a block diagram for the receiver;
Figure 4 comprises a flow chart for the receiver;
Figure 5 illustrates a transmission signal format;
Figure 6A illustrates a 6ync header waveform;
~igure 6B illustrates a terminating header waveform;
~igures 7A and 7B comprise a schematic diagram of the transmitter;
Figures 8A and 8B compriRe a schematic diagram of the receiver; and Figure 9 illustrates a typical pulse train.
Figure 1 illustrates in block form the transmitter of the invention which comprises an antenna 10, an RF transmitter section 11 connected to the antenna and a micro-computer 12 supplying an input signal to the RF transmitter 11. The micro-computer is connected to a memory 13 which may be a non-volatile type memory and A number of channel 6elect inputs 1~, 17, 18 ~nd 19 are connected to a channel selector unit 14 and supply inputs to the micro-computer 12. A
power supplg Gomprise6 a battery E and a transmit switch 22 6uch that when the transmit switch 22 i6 closed ~;2~53~

the transmitter is energized by applying power to the various units of th~ tr~nsmitter. A programming signal receiver 21 is connected to the micro-computer and provides means for selecting the code in the transmitter.
Fi~ule 2 comprises the transmitter flow chart and when power is turned cn the micro-computer 12 detenmines whether a valid programming signal is present.
Figure 3 is a block diagram of the receiver 30 which comprises an antenna 31 for receiving radiation from the transmitter 9. The receiver 30 includes an RF
section 32 which is connected to the output of the antenna 31 and the RF receiver ~ection 32 supplies an input to a micro-computer 33. A memory 34 such as a non-volatile type is connected to the micro-computer 33.
A program mode switch 41 i8 connected to the micro-computer and output channel leads 37, 38, 39 and 40 supply operating signals for various apparatus or functions which are to be controlled as, for example, channel l might comprise a garage door opener. Channel 2 might comprise a security control channel, A programming signal transmitter 36 i8 connected to the micro-computer 33 for programming the transmitter 9.
Figure 4 comprises a flow chart for the receiver.
The transmitter and receiver of the lnvention eliminate the dip switches for code selection which are required in prior art devices and allows the expansion of channels so that a number of channels can be utilized to control different functions. Faster response times are obtained than prior art control transmitters and receivers. A specific embodiment of ~4--i ~ ~6 5 3 1 the invention was c~nstructed wherein a four-bit single chip micro-computer was utilized rather than custom discrete logic integrated circui~ for performing the encoding and decoding of the algorithm. In addition, a non-~o1atile memory is used rather than a multiple three p~sit~on switch for storing the custom code for each transmitter and receiver system.
The use of a single chip micro-computer !~ rather than a discrete logic integrated circuit allows system flexibility for additional expansion and for various other radio controlled applications in addition to garage door opener 6ystems without the requirement of ma;or and exhaustive redesign efforts or cu~tom integrated circuits. For such subsequent changes, a simple micro-program change in the self-contained mask ROM is all that is required and thus only software changes are necessary.
By using non-volatile memorie~ rather than the dip switches used in the transmitters and receivers of the prior art devices requires that the randomly selected code be ~upplied from the receiver to the transmitter. Because of ~ederal Communication Commission rules and regulations, the transmission of radio frequency signals for this purpose cannot be used since the transmifision of a coding signal for defining the code in the transmitter would not be within the Rules for actuating a garage door opener. This would comprise the transmission of a message containing information.
This means that 1) during the programming mode transfer of code information from the receiver to the transmitter, the transmitter and receiver would have 12;~ 531 to be hard wired together or 2) the transfer of such data occurs by using infrared transmitters and receivers.
The use of infrared tranRmitting and receiving means requires no physical contact between the systems.
In the present invention a cynchronous serial transmissi~n data format is utilized because 1~ the equivalent replacement of the prior art nine pole three-position switch with a non-volatile memory requires that the electrical inputs be binary and 2) the present design ~llows additional channel expansion and identification.
In a particular embodiment constructed according to the invention, the maximum number of channels was selected to be sixteen and allow 215 possible code combination6 or 65,536.
The trangmi~sion format used in the invention utilizes security and privacy and is binary and uses pulse position modulation a6 the tecoding format for data transmission. Figures 5 and 6A ~nd 6B illustrate the data format used. As shown in ~igure 5, a synchronization header frame of two blts is used for ~y~chronization at the receiver. The first word 1 is a channel identification block of four-bits in length which contains the binary coded information that identifies the transmitting channel and this selection limits the maximum number of channels to sixteen.
Words 2 through 5 are data blocks and comprise four words each of four-bits containing binary coded information that can represent the code for a particular channel (216 pos~ible code combinations or 65,536).

12~53~

Alternatively, other forms of digital information as, f~r example, the output of a transducer can be included in the~e ~ords.
Word 6 iB a checksum block and i~ an error checking format which is derived by the binary addition of the identification block ~ith data blocks 1 through 4 and eliminates any carry bits. For example:

Ch~ ~ denti~icat~on Block ~- lt 3 _Blt ~ 1 Data Block 1 1 1 0 Data Block 2 1 0 0 Data Block 3 1 1 1 0 Data Block 4 1 1 0 Checksum Block e 0 binary 6um of all blocks less any carry bits Then a termination header which is two-bits in length indicate~ to the receiver that the current information transmission train has terminated. Then there i8 a blanking period of 28 bits which in a speciflc embodiment comprises 28m~ec and then the data format i8 repeated ~gain.
An example of word 1 is shown in exploded form in Figure 5 comprising four-bits of a typical word and a logic 1 comprises a pulse of 0.75 msec and a 0.25 period of no signal. A logic 0 compri6es a signal of 0.25 and then no signal for 0.75msec.
Figure 3 illustrates the receiver block diagram and the software flow chart for the receiver is illustrated in Figure 4. When the power is turned on, the receiver software first turns on the complete hardware system. It first interrogates the program mode switch input. If 1 2 ~ S3 i the program mode switch 41 is closed, the micr~-computer 33 proceeds to access the non-volatile memory 34 to recall the last stored cGde. Using this code as a start, it then performs a random number generation ~lgorithm - 5 and stores the ne~ly generated code in the non-volatile memory and immediately transmits this new code through the light emitting diode 36. The tr~nsmitter 9 is placed in close proximity to ~he receiver 30 such that the programming signal receiver 21 receives the information from the light emitting diode 36. The transmisgion signal format of the receiver is as shown in Figure 5 except that lt does not need the channel identification block and uses a shorter blanking time equal to Smsec. The receiver continues tv transmit the code until the program mode switch 41 is opened after which the receiver monitors the receiver input port from the RF section and antenna.
The receiver algorithm contains a software phase lock loop to lock it on the receiver sync header.
All timing information required to perform the remainder of the algorithm i6 contained in the pulse width of the sync pulse. A software tlming loop times out the pulse and stores this value in the memory.
For each consecutive negative to positlve transition, the micro-computer 6amples the input at the time interval it calculated from the sync pulse, as illustrated in Figure 9. After all of the bits are sampled and stored in the memory, a comparison is made with the code stored in the non-volatile memory for a valid match.
If a match is found, the appropriate channel output is identified by an appropriate light emit~ing diode to :~2~6531 identify that particular channel.
Figure 1 comprises a block diagram of the transmitter and ~igure 2 illustrates the software flow chart of the transmitter. The transmitter upon power up - 5 interrogates the input photo-transistor 21 for a perioh of about l~msec for indication of a valid programming signal. If no programming ~ignal is available within the first ten milliseconds, the transmitter ~oftware assumes that the presently stored code is accurate and the transmitter proceeds to transmi~ such code. lt accesses the stored code from the non-volatile memory, reads the channel identification number, computes the check~um and then transmit~
all the information using the format illustrated and described.
If a programming signal is received, the transmitter decodes the incoming information and if the checksum is correct stores the new code in its non-volatile memory 13 and output~ a flashing ready ~ignal to indicate that the programming cycle has been compl ted.
All output transmission timing is based on an ideal instruction execution time of 20msec, Since the software is fixed, the only parameters that affect output timing are the reslstor capacitor tolerances and any input tolerance variations between different micro-computers.
A software pseudorandom number generator is utilized at the receiver to generate the different codes.
The use of software to generate random values results in a paradox. The fact that an algorithm exists " lZ¢~653i for a process implies that the process ~utputs are not truly random because the algorithm can be u~ed t~ predict the output sequence. True random values can only be generated by the use of ~ystems such as "memory garbage"
or "human reacti~n time". The use of human reaction time requires additional hardware and expense which is undesirable in the high volume electronic industry. In the present invention, the use of "memory garbage" to tart the sy6tem "initiation" or ~tarting value is used on a one time basis.
In the algorithm used every time a random number is required a new ~ixteen bit configuration will result from the ~eed or initiation value u~ed.
Continuous recall for sufficient number of times will result in all the possible sixteen bit configurations.
However, the outputs will appear random if the sequence of outputs are considered and it i8 impossible to prove that the program is not producing true random numbers.
The distribut~on of outputs i6 uniform over the range of possible outputs although all possible sixteen bit values appear before any repetition occurs. In the present invention 65,536 output6 will occur before any repetition occurs.
The algorithm used works as follows. The random code is stored in four blocks of memory each four-bits wide for a sixteen bit word. This allows a binary representation of 65,536 discrete numbers.
However, for the random number generator algorithm to work, the all zero state must not be used therefore there are only 65,53~ numbers that can be ufied.

lZ~S31 ¦ ~L~ LK 2 ¦ ~LK 3¦ ~LK 4 ~ B - B, B2~-B;¦
.

Whenever the program calls for random number, the previous value or "seed" is recalled. Each bit is shifted left one position. Bits 14 and 15 are exclusive or-ed and the result is shifted into the first position of block 4. In this manner, all possible 65,535 combinations will result before the pattern repeats.
The program for the transmitter micro-processor 12 and the program for the receiver micro-processor 33 are attached.
Figures 7A and 7B illustrate the electrical ~chematic of the ~ransmitter 9, the antenna 10 is connected to the RF transmitter 11 which receives an output on lead 50 from output terminal SO of the micro-computer 12. The micro-computer 12 may be a National type 404LP, for example. The non-volatile memory 13 may be a XICOR
type X-2210 and is connected by leads Sl through 57 to the micro-processor 12 as illustrated. An octal latch 26 is,connected to the micro-computer 12 by leads 58 through 65 and might be a type 74C373. A EPROM 27 might be a type 2716 available from INIEL and is connected by leads 58 through 69 to the micro-computer 12 and is further connected to the octal latch 26 by leads 70 through 77. The power supply E and transmit 12C~6S3~
switch 22 are connected to a regulator 23 which produces the drive voltage +Vcc. Infrared ~ensor 90 is connected by lead 91 to the micro-computer 12.
A ready indicator 92 is connected by lead 93 to the micro-computer ~2. Channel selector 6witches 94 through 97 are connected to channel selector leads 16, 17, 18 and 19 which are connected to the micro-computer 12. A lead 101 is connected from the memory 13 to the reset terminal of the micro-computer 12.
Figure 8 illustrates the receiver in schematic form. The micro-computer 33 may be a type 404LP available from National Corporation. The antenna 31 is connected to the R~ receiver 32 and by lead 105 to the micro-computer 33. The programming LED 36 i8 connected through a resistor and a transistor Tl to lead 107 which i8 connected to the micro-computer 33. A non-volatile memory 34 which might be a type X2210 available from XICOR ls connected by leads 110 through 119 to the micro-computer 33. A reset circuit 121 i8 connected by leads 122 and 123 to the reset of the micxo-computer 33 and the memory 34. An octal latch 8 which might be type 74C373 i8 connected by leadc 125 through 133 to the micro-computer 33. An EPROM 7 which may be a type 2715 i8 connected to the octal latch 8 and to the c~mputer 33 by leads 125 through 136. The EPROM 7 and octal latch 8 are connected together by leads 137 through 144. The program ~witch 41 i8 connected to the micro-computer 33 by lead 200. The channel indicator lights 250, 251 and 252 are connected to the micro-computer by 12~S31 leads 150, 151 and 152 and illustrate which channel is energized~
Although the invention has been described with respect to preferred embodiments, it is not to be 5 80 limited as chan~es and modifications can be made which are within the full intended scope of the inventiDn as defined by the appended claims.

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~94 OC9 70 ~TII O ~
195 0~ OE Ll~l 0,15 ;TU~ OFF lNDlCATDh .
2~

120~S31 i97 OCD ~9B. JSR TI~IER
198 OCf B~ ~P a~J8 1~9 ;START TR~;11IT SEQUENCE
200 ODO 3387 STR~X: LEI 0,7 ;l~iTITUTE A~ Y KCdLL
201 OD2 333E aE~ ; CYC~ TO N~
202 ~W OE ~1 O. 15 203 0~5 333E ~IBD
2U OD? OE LBI FU~GI ;SEl READ FRal INh~ FLA~
20S GD8 ~D ~IB O
20~ OD~ 39 Ul CNTka ;STOFE C~NT~OL 110~1 20~ ODA 77 STII 7 ao~ ODB 69~3 JSR 1~ ;

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209 ODD 19 II~J IDNUI ;~AD CI~L JD ~EER
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211 ~LATE CHEDKSll~ Cf DATA ~L~KS AND ID IPMEER

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~217 t~ 2 218 tlE6 31 ADD
219 0E7 lC LBI BLI~
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221 OE9 lD LBI

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22~ X t) 2~5 ;TRA~IIT SYI~ FULSE
226 OED 3B JNITX: LB1 alt9Pl ;IIIITILJZE l:alPAhE hEGlSIEh 22 OEF OO ~LRA
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232 OF~ 21 SKE ; F~ ~ USEC.
233 OF5 F3 ~P Bhl~
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23~ OF9 7D ~11 13 ~F0R 1.5 ~ISEG
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239 ~C 51 BR20: AISC I

241 OFE 21 SI~E

242 OFF 60FC J~P BR~

2~14 102 ~4 1101~
245 ;TR~1T DATa eLOCI;
246 tO3 3C LBI BDPNT ; INlTlALlZE BD F~lNTER TO

% ~ ' 12~S3~
24E 10~ 3A L81 COMP2 ;D~TA TO EE T~NSnlTTED
249 10~ 70 STJ~ 0 25v 10' 3C I~XEYTE lBJ ~NT
251 ~0~ 25 Ill 2 25. ~0~ 50 Cq~
253 IOA ~1 LEI I ;5~7 EN~.S~O
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260 113 3 Ul SCRATC i 1~ USEC DELAY
262 114 Æ STIJ 14 262 115 3 LBI ~ATC
263 116 0~ X 0 2U 117 51 511SC t 2~5 118 D7 JP . -1 2S~

12~6S31 2N I~A 3C L~l BDFHI
2~ IIB 25 LD 2 2~9 l~C 50 aB
270 IID 3~t LEI I iS~ EN3~.Sl~=O
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274 122' E~ R E~4 23 22 ~R2~ S~
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282 12B EA .P . -I
283 ~2C 44 ~,IOP
284 12D 3B 1~1 BDF~

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2B7 13û 3~61 LEI I i~ET EH~O,S~O
2~ 132 11 SKMBZ I ;CIECK LOGIC STATl~ 0~ BIT I
289 1~ F6 R BR25 ;P~Il Blt I
290 ~3~ 32 ~ ;~1 5 t~P 8R2b 292 1~i6 22 ~2~: SC
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306 1~6 C9 JP ~IR27 iRAI~ PO=I
307 147 32 RD ;RIU1 P~Pb 4S ~ JP 73R~
3~ 149 ~ 8R27: SC
310 I'~A 69CB B~6~ TX~7T

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315~006 XO
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317152 ~q LBI COMP2 JUST ~ ORY L06ATION

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324 ISE OQ CLR~

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3 2 162 3E LBI CO~lPI
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335 1~ 2I SI~E
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337 168 33~1 LEI I ;SET El~O,SO=O
3~ iTRANSMl;T BL~l( Tl~IE 0~ 28 MSE~.
339 16A ~q L~ 1P2 ilNlTlALl'E C~PA~E REGISTERS
340 16~ 72 STII 2 341 16C 7~ STII 6 342 16D 2C L~l COUNII ;RESET ClPJNTEk ~GISTERS
3~3 16E 7~ STII O

3~5 170 ~9B2 J~ TlnER
3~172 4~D ~lP INITX ;~ETRAN~IIT OATA
347 ; ~WTINES
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350 175 00 CLRA ;S~UP SAMPLING VALUE

12~S31 ~P
353 17E 21 Sl~'E
354 179 F~
355 t-,A ~3tN St:OEZ O ;REAr~ lNPUT
35~ 17C 61gl ~P S~L
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330 19~ 33b5 LEJ 5 iEHAeLE L 5RIVERS
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395 IP.B 06 X O ;S~E NEII VALUE FOR
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3~

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27 IC~ ~3 STII 3 CD oo n~

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439 ID9 3~ LBI C~1Pl UO IDA 00 CLhA
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. . .

~2~6S3i CO\~ CROæ ASSEMELE~ PAGE: tO
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101PJ~1 OO)A INCI 0ID2 IHC2 01bD 1~3 OIES
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NDUSE 003~ IIU~AIl 01~ lelB~ 0107 IIEPEAI 005B
S~E Q174 S~C 003F STA~T 000E SThTX OOD~
5U81 017~ 2 01BI SU~ 018~ 0h4 019B
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0~ECT FILE OEI~JSER ~ Ln lZ~6531 cop cRnss QSSElgE:LER PAGE:
p~

I I RECEIVER SOFT~ARE LISTINC

~ t UCOPVRIGHT 1982 S ~ CHAMPERL41N MANUFACTURINB CORPOR~TtON
ALL RI BHTS RESERVED

B
OOlF CKSUM ~ 1 15 ~CHECKSUM
tI OOlE 3LK4 - 1 14 ~INFOR~ATION BLOC~ 4 12 OOlD BLK3 - 1.13 INFOR~ATION BLOCK 3 13 OOIC BLK2 ~ 1.12 INFORMATION BLOC1~ 2 t4 OOIB : BLKl ~ I.ll tJNFOR~ATlON BLOCK I
IS OOlA J3NUM - I-tO ~J. ~. NUnEER
l6 002F JRIN ~ 2-IS IJNFRARED INPUT COUNTER
t7 002E COUNTO ~ 2-14 ~GP COUNTER O
18 002D COUNTI ~ 2-13 ~GP COUNTER I
t9 002C COUN~2 - 2-12 ~GP COUNTER 2 003F SCkATC ~ 3 95 ~SCkATC~ PAD kEGlSTER
21 003E BRPNT - 3.14 . ~h~ ~EMDRV PO~NTEk 22 003~ BDPNT - 8.t3 BD MEMOkV POINTER
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42 009 33~0 LEI O ~TRISTATE L ~ORT
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47 OOF 4~ SME O ISET REA~ FROM N~RAM FLA6 48 010 39 LLI CNTROL N ORE CONTROL WOR~I
49 011 77 sTIi 7 50 012 3387 LPI 0 7 ~INSTITUTE AN ARRAY RECALL
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100 04C 3F LBI NOUSE ~ IN';TJTUTE A 8TORE COM1~1AND
101 04D 7i~ TI I 13 102 04E 3F LBI NOllSE
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114 ose lc L~ eL~

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119 0~0 Ob X O
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142 078 78 ~TII 11 ~tlRST AND LAST LOCATlOI~ OF
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, , 12~ S31 , I r~P cRnss ASSEM~LER PAGE: 4 MAJNP~

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173 09B 7E ~,T 11 14 I 74 09C 3E L81 8CkATC
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216 OC:k 3:~.1 LFI t 217 OCD 3E L~J COMPI

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238 OE2 70 ~711 0 2~9 OE~ 7b ~TII O
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241 OE~ 3F LBI ~DUSE ;CHECI: FOR PRnBRaM
242 OE7 ~32E ~NL J$~ITr;~ CLOSURE243 OE9 13 6K~k7 ~
244 OE~ Fl .~ EFr~lN ~SWITC~ ~DT CLOSED
245 OEB OB L~l FLABI JSWJTCH CLOSED
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24B OEF ~02l JMP N~E~ ~ Nr~ GF~FR~TE NFW RAN~O~ N~IMF:F
249 OFI OB BEriJN l.t.l FLAr 25b OF2 4'. RME~ I
251 nF3 33~ LEI 2 252 OF5 3C LEI knP~T ;INITI~ E RECEJvFr.~ n~TA
253 bFh 7~ STJJ ~0 ~F~rlky POI~TEk 254 OF7 2n L~J t:Ol ltJTt~ ; RFSET COUNTEh~ Ikl~
255 OF8 7b STII O
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257 OFA 09 L~l RIDNUM
258 OFB 70 ~Tll O

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.-.

S~3 ' ~i2~ 3~

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2~ In6 70 STI~ O
267 107 70 S~l I O
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273 IOF ~il Al5C
274 110 3~ Bk~,: SKGEZ O ; JS INPLI~ STILL A LOCilc:
275 112 D5 JP I~R4 ~ ~'E5 276 t 1:3 6bF1 JMP ~EGIN ~ NO
277 IIS 51 ~ BR4: AISC 1 271B 116 DO JP E~RS
275' ~17 06 X C~
2go l~e 51 I~IS~: I
2E I l l Sl 06 X O
2E2 t IA 05 Lll:l o 2B3 llB S~ ~ISC 10 4 IIC 610E JMP LOU~1 .
285 ~lE 2E Lrrll IR;N ~ VALID 10 MSEC. ELANN~ ~IME
;!86 ~1, F 1)0 CLF~A
ZB7 ~20 33nl f;I~riBZ O . I IS ~NPUT ~ I OGJC; O ?
. , .. . .,, . . _ . .... . .. . . .

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.

?~5~ ~2~ T.SC I ~E~
2so 124 .~3t 1 ~n8x o 17S ;NPUT ~;TlLL A lOriJC O 7 291 1~ S ~P ~k7 ~NO, RJ.SJNri T6~Nz:ITJotJ DETF~:TI
~9? 127 E3 JP æfi6 IYEC, 293 12E Q6 ~7: ~ O ;S~RE r:OllNT 7N IkJN
294 12~ oe, LD O ISlIr;TkACT CORkECTlCIN FACTOP
295 ~2A 5E AJSC 14 ~FOR ~A~PLE VALUE
296 12~ 44 NnP
297 ~2B 2C LBI COUNTI ISTORE ~AMPLE YALUE
29B i2~ ~6 X O ilN LOUNTER I
2ff' 12E 2E ~E1 IRJN ~CHEBK FOR CIV~R~LrlW

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302 1~1 F4 JP REPEAT ~NO OVERFLOW
303 1-~2 6bl8 ~P ST~RT ~n~ERFLOW EX~ST5 304 134 3301 REPEAT: SKCiEi O ;OHFr:I' FOR F~LLJNri TRPNSJTJON
305 136 F4 JP .-~ ;INPIIT ~.TILL HlCiH
3t6 ~37 6$rr:F: JSR ~MPLE ;FAI.LINCi TRaNSlTInN DETEC;TE~
307 135' 3C LEI EnP~T ' iPnlNT TO RECEIYE rIRTA POJNTE
~06 ~ 3~ L~ 3 30Ç' 138 50 C~E
~10 13C 2~ 'C
311 l~D 6t40 , ~MP ~Re 312 13F 4B 8~ 3 ,.._ .... ... . .
.

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.

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214 ~42 C4 P RR~ JINPIIT ~TILL HJGH
~I 31S i43 CO JP ~P8 IlNPUT ~iTlLL LOW
3i~ 144 330~ BR9: 5~tiBZ O
317 14~ C4 JP .-2 ~INPUT STILL ~ICH
31~ i47 b9C~ JSk SAMPLE ;F~LLJNri TRAN51TION IlrTE~TErl 31~ 149 ~C L~l EnPNT ;P~IJNT Tb REOFIVE nATA PCIINTE;

321 14E SO cAr~
322 a4c 20 ~C
323 I~D ~F JP kR1t 324 14E 4~ ~Mr: 2 325 14F 33;~ BRlC): ~ BZ O l Lnnl~ FOk FALLIN~i TRANSITION
32~ iSI D3 JP ~Rt1 ~lNPUT STlLL HI~H
327 152 tF JP BRIQ ;lNPLlT STILL L~W
323 153 3301 BRII: 3KtiRZ O
329 555 D3 JP .-~ . tINPUT STILL HJGH
230 156 ~9r~ JSR SA~PLF ~F~LLlNGi TRaNSlTIoN rlETEcTErJ
3~1 158 30 LBI Br~PNT tPOINT TO REr:EIvE DATA POINTF

233 ~ SO CAr: .
334 lSB 20 8KC
-335 a50 ~E JP BR12 33~, 15D 47 1~
337 ~5E 3301 ~R12: ~KfiiRZ 0 i LD0~ EOR FALLI~Ci TRANSITION
338 1~0 E2 JP ~R~3 ;lNPIJT STJII Hl~iH
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`

310 1~2 3~;1s ~kl;'i~
341 lh4 E2 JP . 2 ~1NPUT ~TILL Hl~iH
342 lb~ hgC~ J~R ~4MPLE ~FALLIN~i T~AN~;JTJDN rJETÆCTEl:
343 1~7 3C LBl ~DPNT ~Pn~T ~CI ~ErEJVE rJATA FnJtJt 344 I~R 35 L~
345 ~69 50 C~E
~i4~ 1~A 20 S~C
347 16~i ErJ JP ~R14 ~46 I~C 4D S~E O
349 1~D 3C BRt4: L~1 ~inPNT ~INCRE~ENT ~rJ PDINTFR
350 1 ~Æ 05 LD G
3Si 9hF S1 AJSC 1 ~LAST ~E~n~Y i.tiCAT1CIN FlL.l.t' . 352 170 F2 ~ P~R15 ~o ~i53 171 FE JP ~R16 ~YES
354 a 72 Oh ~ik15 X O
355 973 3~ R17: SI~'rEZ O ;LOnl~ FOk FALL1NCi TRA~.IT1~Ii, 35~ 175 ~134 .J~P REPEAT ilNPlIT STILL HJ8H
357 177 F3 JP BR17 ;JNPUT STILL LO~J
~5~ ~CALCULATÆ RFr:EIVErI DATA C~EC~SU~
359 178 00 BR1h: ~LkA
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3~1 ~7A 31 Anrl 3~2 17E OA LB1 RELK1 363 17C 31 ~bb 364 1~ OB L~1 RBLI'2 3~.5 17E 31 AnrI
3hh 17F OC LEil kEl.1~3i .

.. _ . _ .... . ... . . . _ .

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- coP cRnss ~8sF~r:l~ER F~P~GE: 8 ~A J NPR

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368 ISI Orl LP,I RFsLK4 3~ 1,E12 31 ADD
370 ~i83 OE LE:I kCl'SUM
371 1~4 21 ~KE CHFCI~SIJlq cnF~REcT
37~ leF~ ~bl~ 1p ST~fiT i cHFrK8llM lNrnF~RFcT
373 IF.:7 08 I.P.I FLAr.i~
374 ~ e8 4n SMF~ SF:T kEAr FF.'rlM NVfiA-~1 FLAri 375 1~.9 39 LBJ CNT~nl. i ~TnRF cne~lTkrll- ~nfir~
37* 18A 77 STJ I 7 377 18r~ 3387 LE:I 0, 7 i IN';TITIJTE AN ARRAY F~ECALL
378 13D 333E oBr~ ; CYCLE
37Sl 18F OE LE~ , 15 380 19C) 33E OED
~iF: I 19~ ~9D7 JSR NV~AM
3~ 194 IA LEtI E:LKI ~ C~ECK FOR RANrJcM
3E~3i 15l~i 15 L~ I NIIMr~ER 11ATC.~I

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391 19F a~ LD I
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396 1 A5 21 ~:1;E
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401 1;~ 40 CO~1P
402 1~C :~33C S:;AMt~
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406, Ik2 7F STTI 15 407 IE:-: 2F LBJ IR7N

4-.-5' 1135 2C ~1Tl LF:J t`.n1JNT1 ; I~7TIALIZE CO1JNTFF~ kF~il5TEk':
410 IB6 70 STlI O
411 îE:7 70 ~iTI7 0 41? lB~ 6A06 J5k TlffER
413 11~ 2E LBI IRIN

415 IBC ~!il AISC I
416 a~ 61CI JMP JT2 ~,~

53~

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417 IBF ~104 JMP JT3 41B lCI 06 JT2: X O
419 ~C2 ~lB5 ~MP JTl 420 'IC4 33bO JT:3: LE-I O
421 lC6 ~OlB J~P ~TAkT
422 ;SIlBRnilTlNE'i 4~3 1 ~iLIP.~nllTINE ~PlE
424 Ir,B ~C SAMPLF: L~il CCIUNTI
425 1t~ OO r,LRA ~ETLIP SAMPLJNC VALIlE
426 lC~ ~,i SU~ lFiC
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43b I SLI~ROL~lNE NV~M
437 lD7 3e ~VRAM: L~J CO~F~ INITIALIZE BD ~E~ORY PCIINTER
~3B 1~8 7F STIl lS ~ANrl COMP~RE REGISTFR
439 1~9 79 ~iTlI ll 440 lDA 3C fiUBb LBI BDPUT
441 ln~ 2~i L~ 2 ~OUTPl~ ~DDRE'iiS POINTED TO
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458 ~FO 25 Ln 2 45~ IFI 5CI CA~
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442 IF5 3F ~UBe, LEI Nt1UC;E iYNITIATE A DEfiELECT
443 IF~ 7F S~II 15 ~4 lF7 3F L~I ~nlJ8E
445 IF8 333~ O~G
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t~A I NPR

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47~ 2~0 45 LD O ~ErORY P01NTEk 472 201 3R L~ COMPI ~LAST ~EMOkV LOCATlON
478 202 ~I BKF ;ACCESSE~7 474 203 ~ JMP ~U~6 ~NO
4 X. 20' 4E RET ~YES
476 ~ ~U~ROUTINE TlMEk 477 206 2n ~JMER: L~l COUNT~
4~R 207 00 Cl.. h~A
479 20~ S~ ~Ise I
480 20P CE JP . - t . 1 ~40 IISEC. DELAV LOOP
4E1 20~ 0~, LD O ~ cnuN~o CONTENTS TO ACC;U.
~E2 20~ Sl A~SC I ~ADD t ~0 ACCU.
20C n1 , Jp l~
4B4 20D 07 xns ~TORE 2EkO IN COUNTO
~85 20E OS LD O ~nFcREMFNT Tn cnllN
4B6 20F SJ ~JSC 1 ~ ADn 1 TO t:nuNT~
487 2tO 44 NtlP
E;8 ;~1 t 06 LPI: X 0 ~' 489 2i2 3A LF;I t:t~MP2 ~ COMP~ E COllNTFRS TO
~90 213 OS L~ O ~COMP~E REGISTEkS
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502 22( 73 ~7~ 3 503 221 00 ~LR~
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512 22E 3k l ~ OMPl 5~3 2~C 74 ~ 7 4 514 22D 33 LP.J COMF~I

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S27 23E F9 ~P TNC3 52~ ~3C 4~ ~ET
529 ~RANnOM NU~EFk ~ENERATrJk S30 ~sEEr~ cnNTAJNErl ~N 11.11) T~kN ~1.14) lS USECl AS A k~SJC;
531 ~FOk ~ NF~ R~Nnot1 Nut~r:ER GENFRAT~n IN ANn STnREr~ IN
532 (0-11) T~RU ~0.14) 533 23D 3C RaNDoM: LBI ~nPNT

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55~ 251 ~ S

553 2~S~ 3t L~l 13n~NT
~54 2~4 2~ X 2 555 2S5 50 c~r~
55~ 2~5b 13 !6KMEZ 3~
S57 257 ~25E ' ~lP SUE10 S5S ZS9 1&1 SUEI 1: LRJ 1, 1 I 3 XOR OPER~TION ~ tl 559 2SA :~33E ORrJ ~FoRr.~ LEAC.T SIGN. BJT ON
sf~n 25C 6~61 uMr sur~ S~JFT REGISTE~ TO O
5~1 25E lE SUR~O: LE:I 1- 15 ~ %OR OPER~TION ~ I
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5~8 267 ~8 ~ ,6UB14: RET i TERMI~TE ~sOCFSS

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.-.

.

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574 1 ~LL RJ~HTS RESERVED"

577 .EN~

.

..... , ........ .. _.. . .

', ', ,' ' ''' '.

5~ .

Claims (12)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. Apparatus for controlling a receiver with a remote radio frequency transmitter comprising a first micro-processor and a first memory means in said receiver for storing at least one address code, non-radio frequency transmitting means in said receiver, switch means for energizing said non-radio frequency transmitting means to transmit an address code, a non-radio frequency receiving means in said transmitter for receiving said address code, a second microprocessor and second memory means in said transmitter for storing said address code, radio frequency radiating means in said transmitter for radiating said address code, receiving means in said receiver for receiving said radio frequency radiated address code, said first microprocessor in said receiver comparing the received address code with the address code stored in said first memory, an output circuit energized by said comparing means when said addresses are the same, wherein said first memory means com-prises a non-volatile memory and a programmable read only memory and said second memory means comprises a non-volatile memory and a programmable read only memory.
2. Apparatus according to claim 1 wherein said first micro-processor is programmed to operate as a pseudo random number generator to generate a plurality of different address codes to allow the address codes in said transmitter and receiver to be changed.
3. Apparatus according to claim 2 wherein said non-radio frequency transmitting means is a light radiator.
4. Apparatus according to claim 3 wherein said non-radio frequency receiving means in said transmitter is a light detector.
5. Apparatus according to claim 2 wherein said non-radio frequency transmitting means in said receiver is an electrical conductor.
6. Apparatus according to claim 4 wherein said address code comprises a serial binary code of pulse length modulated form of a plurality of word lengths.
7. Apparatus according to claim 6 wherein said address code contains a binary check block for indicating whether a correct signal has been received.
8. Apparatus according to claim 6 wherein said address code contains a binary synchronizing block for synchronizing the transmitter and receiver.
9. Apparatus according to claim 6 wherein said address code contains a terminating block.
10. Apparatus according to claim 6 wherein said address code is repeated and each address code is separated by a blanking period.
11. Apparatus according to claim 2 including a first octal latch in said receiver which is connected to said first micro-processor.
12. Apparatus according to claim 2 including a second octal latch in said transmitter.
CA000434482A 1982-09-23 1983-08-12 Transmitter and receiver for controlling remote elements Expired CA1206531A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US422,452 1982-09-23
US06/422,452 US4535333A (en) 1982-09-23 1982-09-23 Transmitter and receiver for controlling remote elements

Publications (1)

Publication Number Publication Date
CA1206531A true CA1206531A (en) 1986-06-24

Family

ID=23674950

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000434482A Expired CA1206531A (en) 1982-09-23 1983-08-12 Transmitter and receiver for controlling remote elements

Country Status (4)

Country Link
US (1) US4535333A (en)
JP (1) JPS59160399A (en)
CA (1) CA1206531A (en)
DE (1) DE3332761A1 (en)

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DE3332761A1 (en) 1984-04-05
JPS59160399A (en) 1984-09-11
US4535333A (en) 1985-08-13
JPH0249600B2 (en) 1990-10-30
DE3332761C2 (en) 1987-12-03

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