CA1209280A - Process of making dual well cmos semiconductor structure with aligned field-dopings using single masking step - Google Patents

Process of making dual well cmos semiconductor structure with aligned field-dopings using single masking step

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Publication number
CA1209280A
CA1209280A CA000485177A CA485177A CA1209280A CA 1209280 A CA1209280 A CA 1209280A CA 000485177 A CA000485177 A CA 000485177A CA 485177 A CA485177 A CA 485177A CA 1209280 A CA1209280 A CA 1209280A
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Prior art keywords
regions
well regions
field
insulating layer
over
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CA000485177A
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French (fr)
Inventor
Wayne I. Kinney
Charles W. Koburger, Iii
Jerome B. Lasky
Larry A. Nesbit
Ronald R. Troutman
Francis R. White
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H01L21/76218—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers introducing both types of electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers, e.g. for isolation of complementary doped regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/053—Field effect transistors fets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/10—Lift-off masking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/157—Special diffusion and profiles

Abstract

PROCESS OF MAKING DUAL WELL CMOS
SEMICONDUCTOR STRUCTURE WITH ALIGNED
FIELD-DOPINGS USING SINGLE MASKING STEP

ABSTRACT OF THE DISCLOSURE

A process for making a CMOS dual-well semi-conductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells to each other and also of the field isolation doping regions to the wells. The lithographic masking step forms a well mask and defines an oxidation barrier which acts as: an implant mask (absorber) during the ion-implantation of a field dopant of one type; an oxidation barrier over one well during the oxidation of the opposite-type well to form over the one well a sacrificial oxide layer which forms the alignment marks for subsequent formation of the field-doping regions; and a dopant-transmitter during the ion-implanation of an opposite-type field dopant which is simultaneously absorbed by the sacrificial oxide. As a result, there are formed field-doped oxide layers self-aligned to the wells so that, with a subsequent masking step, oxide field isolations are defined over the doped oxide layers. A heat cycle is then used to drive the field dopants into the cor-responding field-doping regions.

Description

IBM Docket No. BU 9-83-013 PROCESS OF MAKING DUAL WELL CMOS
SEMICONDUCTOR STRUCTURE WIT~ ALIGNED
FIELD-DOPINGS USING SINGLE MASKING STEP

BACKGROUND 0~ THE INVENTION
s This i~vention relates generally to the field of CMOS (complementary metal oxide semiconductor) tech nology and, more particularly, to a process which uses a single masking step to form self-aligned dual wells (tubs) and self-aligned field-doping regions in a CMOS
lo structure forming a part of a semiconductor device, such as a field effect transistorO
In dual-well ttwin-tub) CMOS technology, it is highly .desirable to utilize as much of the semicon-ductor chip area as possible. In the past~ several lithographic masking steps were required for makin~
integrated circuit chips having densely packed elements and devices thereon, but each masking step inherently re~uires the dedication of chip areas which otherwise could be occupied by the devices ultimately formed in the chip. Also, in the past, the doping concentration o the dual wells and als~ of the field regions were dependent upon each other, and/or both P
and N field isolation regions were doped with a conductivity-determining impurity of a first t~pe, one region masked, and the other region doped with a conductivity-determining impurity of the opposite type to form khe reguired P-doped and N-doped field isolation regions.
In forming field isolation regions between devices on a chip, it is necessary to provide field-doping beneath these isolation regions to provide electrical isolation between adjacent devices or active regions on the same substrate which is, typically, a lightly doped silicon waer. The fabrication step or steps that produce these isolation i~
,~.

:~2~2~3~

IBM Docket No. BU 9-83-013 regions affects the spacing between devices (i.e. the device packing density) on the chip, as well as the electrical characteristics of the device. The field-doping beneath the isolation regions is often referred s to as a "parasitic channel stopper" doping, and it is used to contxol the parasitic ~OS threshold voltages outside vf the active region of a device, such as an FET, and to eliminate unwanted conduction due to inversion under the field isolation when lightly doped suhstrates are employed. There are many prior art techniques for aligning the field-doping to the field isolation. One technique is to use an extra litho-graphic masking step; however, the disadvantages of~
such an extra masking step have already been dis-cussed. In order to form a recessed isolation oxide with a self-aligned field-doping, it is also known to provide an oxidation barrier layer, such as silicon nitride, for delineating the device regions. Thin silicon dioxide layers may be provided on either side o~ the silicon nitride layer to aid in its delineation and to prevent damage to the underlying silicon substra~e. The photoresist pattern used to define the device regions also serves as the implantation mask, and the resist regions are locat~d over the future device areas.
U.S. Patent No. 4,144,101 - Rideout discloses the broad concept o~ providing a self-aligned field-doping using only one lithographic masking step. It is important to employ as few masking steps as possible sinc~ the li~hographic masking steps involved in pxeparing integrated circuits are among the most critical. Lithographic masking st~ps require high precision and registration and extreme care in exe-cu~ion. Each additional lithographic masking step in a process in~roduces possible masking defects and increases mask-to-mask registration problems that ~2~8~

IBM Docket No. BU 9-83-013 decrease the processing yield and, accordingly, significantly increases the fabrication cost. Al-though other factors affect the yield and cost, such as, for example, the number of high temperature heat treatments, a basic objective in FET integrated circuit fabrication is to minimize the number of basic lithographic masking steps required to produce a particular integrated circuit array of desired device structuresO U.S. Patent No. 4,144,101 dis-closes a process wherein the incorporation of the doping beneath the preselected isolation regions and the fabrication of the isolation regions require only a single lithographic mas~ing step. More specifi-cally, ~his patent discloses a process for providing ion-implanted doped regions in a substrate beneath preselected regions of an existing layer on the substrate, wherein the doped regions are self-aligned to preselected subsequently abricated regions of the e2isting layer. The process includes providing a first layer o silicon dioxide on a silicon su~strate.
Ion-implanted doped regions are tc be later formed beneath preselected portions of the oxide layer. A
resist masking layer is formed on the oxide layer, and active impurities ar~ ion-implanted through ~he oxide ~5 layer in those regions not covered by the resist masking material in order to provide ion-implanted regions beneath the oxide layer, whereby the resist and o~ide layers act as a mask to prevent the implanted ions from pene~rating ~herethrough. A lift-of~ material, such as aluminum, is deposited over the oxide layer and resist l~yer, and then the resist layer is removed, taking with i~ the lift-off material deposited on it. Then, the portion of the oxide layer which was beneath this layer is removed by etching, using the remaining lift-off material as a mask.
Then, the ~emaining lift-off material is remov~d from ~$.Z~3~

IBM Docket No. BU 9-83-013 the oxide layer beneath it, whereby there are obtained impl~nted regions in the substrate which are self-aligned at the edges to the boundaries of preselected fabrica~ted regions of the oxide layer located above S the ion-implanted regions. In other words, by the use of this lift-off technique, the masking pattern is actually reversed from over the device region before implantation, to over the field isolation region after implantation. After the fonmation of the field-doping regions which are self-aligned at the edges to the overlying isolation field oxide regions, further lithographic and ionimplantation steps are used to ~orm the oxides, device-doping and conductors~
. required to complete the fabrication of an FET having gate, source and drain regions. This lift-off technique is used in one embodiment of the present invention.
U.S. Pat. No. 4,435,8~6 - Parrillo et al discloses a dual-well or twin-tub CMOS process using only a single lithographic masking step for forming self-aligned contiguous P- and N-wells. A silicon nitride layer and a silicon dioxide layer of different thicknesses are used to achieve this self-alignment of the wells; however, this patent does not address the problem of forming field-doping beneath field isolation regions.
U.S. Pat. No. 4,280,272 - Egawa et al discloses a process of making a twin-well CMOS FE~ by using the conventional method of employing two masking steps to form spaced N- and P-wells.
U.S. Pat. ~o. 4,244,752 - ~enderson, Sr. et al discloses a process for making CMOS FET integrated circuits having both ~-channel and N-cha~nel struc-tures, and in which only a P-channel well is formed.
Both silicon dioxide and silicon nitride layers are formed on a P-type wafer to produce a silicon dioxide-silicon nitride sandwich, and a first masking step is 121~

IBM ~ocket No. BU 9-83-013 used to etch away this sandwich to define the acti~e areas of both the P-channel a~d N-channel devices to be formed later in those areas covered by the sand-wich. ~ second masking step is used to form a photoresist pattern to enable ion-implantation to form a P-channel well. With the oxide-nitride sandwich serving as a mask, field-doping regions are formed by ion-implantation of a P-type dopant (boron). This implant goes into the field regions of both the N-channel well, where it is required, and the P-channel well where it is not de~ired. Field isolation oxides are then formed over the field doping regions, using the silicon nitride layer as a mask to prevent oxi-dation of the active areas of the P channel and N-channel devices.
SUMMARY OF l~ INVENTION
The primary object of the i~vention is to provide an improved process for making a CMOS dual-well semiconductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells to each other and also of the field isolation doping regions to the wells.
Another obj~ct is to provide such a process wherein the slower-diffusing N-well dopant may be driven-in independently of the P-well dopant.
A~other object is to provide such a proces~ which enables independent control of both the well and field-dopan~ profiles.
In summary, the invention achieves ~he above objects by the use of a single lithographic masking step to form a well mask and define an oxidation barrier which, then, acts as: an implant mask (absorber) during the ion-implantation of a field dopant of one type; an oxidation barrier over one well during the oxida~ion of the opposite-~ype well to form ~2~

IBM Docket No. BU 9-83-013 over the one well a sacrificial oxide layer which forms the alignment marks for subsequent formation of the field-doping regions; and a dopant-transmitter during the ion-implantation of an opposite-type field s - dopant which is simultaneously absorbed by the sacrificial oxide.
More specifically, in a preferred embodiment the invention involves depositing a silicon nitride layer over a silicon dioxide layer which is disposed over an lo epitaxial silicon layer. ~ photoxesist mask deines on the silicon nitride layer the positions of ~he N-wells and the P-wells, leaving the N well areas exposed, and the silicon nitride layer is removed from~
those areas. An N-type conductivity-determining impurity is implanted through the exposed silicon dioxide layer and into the epi-layer, using the photoresist as a mask for the P-wells. A lift-off material, which may be chosen to withstand high temperatures, is deposited over the struc.tuLe through lift-off techniques, and the photoresist with its lift-off material is lifted or removed from the P-wells. The N-well dopants may then be independently driven into the epi-layer to form the N-wells. A
P-type dopant is then implanted into the structure for the formation of the P-well regions, using the lift-off material as a mask to keep the P-dopants out of the N-well regions. The lift-off material is then removed from the N-well regions, and an a~neallng step is used fur~her to drive in the dopants to complete ~he formation of the profiles of both well regionsO
During the same step, a relatively thin sacrifi~ial silicon dioxide layer is grown over the N-well region not covered by the silicon nitride layer. This grown oxide layer provides an alignment mark for subsequent processing steps. P-type field dopants are then implanted into the thin original silicon dioxide ~2~28~

IBM Docket No. BU 9-83-013 layer, which is over the P-well regions and underneath the nitride layer, and into the thicker grown silicon dioxide layer over the N-well regions. The silicon dioxide layer over the N-wells is removed, using the nitride layer as a mask to protect the silicon dioxide layer over the P-wells, and a new silicon dioxide layer is grown in its place. An N-type dopant is implanted into the new silicon dioxide layer over the N-well region, with the nitride layer no~ absorbing and preventing any N-type ions from xeaching the silicon dioxide layer over the P-wells.
Then, the already established alignment mark can be used in subsequent lithographic masking steps to form a complete device. For example, a thick oxide layer is deposited and defined by a lithographic masking step to provide field isolation regions around the well regions. During the definition of the field isolation oxide regions, the previously doped oxide layers in the active device re~ions of both type wells are removed, theraby leaving the remaining doped layers over only the defined isolation regions; a subsequent heat cycle drives the N and P type dopants out o their respective remaining oxide layers and into ~he selected epi-regions to form the field-dopings beneath the oxide ~ield isolatio~s.
BRIEF DESCRIPTION OF T~ DRAWlNG
Figures 1-11 diagrammatically illustrate the essential process steps of the preferred embodiment of the invention.
Figures 12-14 diagrammatically illustrate additional process ~teps for completing the field isolation regions using the alignment mark established in the ~teps of Figures 1-9.
DETAILED DESCRIPTION OF THE PREFERRED EMBODI~ENT
In the preferred embodiment of the process for forming, with a single lithographic mas~ing step, a -~P$Z8~

IBM Docket No. BU 9-83-013 CMOS semiconductor structure having twin wells, which are self-aligned to each other, and an alignment feature self-aligned to the wells for use in subse-quent lithographic masking steps for forming, for example, field isolation regions, the following sequential steps are employed.
(1) As shown in Fig. 1, in the initial step, a relatively thin (approximately 25 nm) silicon dioxide layer 10 is grown on an appropriate substrate 12, such as lightly doped epitaxial silicon on a heavily doped substrate. A relati~ely thin (10-20 nm) layer 14 of silicon nitride (Si3N4) is deposited over the oxide layer 10.
~2) As shown in Fig. 2, a relatively thick photoresist layer 16 (~ig. 2) is deposited over layer 14, and, then a lithographic masking step is employed to define in the photoresist layer 16 twin~
well regions. The areas over regions which are to become N-type wells are removed, ~ogether with the 2Q underlying silicon nitride layer 14, ko form areas 18 which are exposed to the oxide layer 10 ~see Fig. 3).
The photoresist layer 16 should be thick enough to stop the implantation of N-type impurities in a sub-seguent step, and should be of a material which is compatible wi~h the lift-off material used in a s-~bse~
guent step, as disclosed in U.S. Patent No. 4,244,752.
(3~ N-type impurities (donor species), such as phosphorus or arsenic, are ion-implanted ~hrough the oxide layer 10 in the area 18 and into the substrate 12 to orm N-~ype well regions 20. The implantation energy and the thickness of the photo-resist layer 16 are chosen such that the desired implant~tions of the N-type well regions are achieved while the implant is prevented from reaching the P-type well regions by the thick photoresist layer 16 in combination with the layers 14 and 10. (See Fig. 4)-81~

IBM Docket No. BU 9-83-013 g (4) Deposit a layer 22 of lift-off material, such as Al, Mo, W, etcO, which is compatible with the photoresist material in layer 16. (See Fig. 5). The layer 22 should be of sufficient thickness to stop the boron implanted in a subsequent step for forming the P-well regions.
~5) Lift-off the photoresist 16 and the over-lying layer 22 from the layer 14 over the regions that are to become P-wells. These P regions are now exposed (beneath the nitride film 14 and the oxide film 10). (See Fig. 6).
(6) This is ~n optional step in which, if desired, the N-well regions can now be driven or~
diffused into the substrate 12 by heating if the material of the lift-off layer ~2 has been chosen to be capable of withstanding elevated te~perature exposure. Such materials are metal (molybdenum, tungsten, etc.) or oxides. Such an optional step permits the N~well regions to be driven or diffused independently of the P-well regions.
(7) Implant P~type impurities (boron) to form the P-well regions 24, using the lift-off layer 22 as a mask to pr~vent implantation of the N-well regions 20. (See Fig. 7).
(8) Remove the lift-off layer 22 from the N-well regions 20, and anneal both wells 26 and 28 until their diffusion profiles are near the final desired conditions. At the same time, grow a layer 29 of moderate thickness (approximately 50 nm) of silicon dioxide over the N-wells ~ in order to provide in the substrate 1~ an alignment st~p 30 for use in subse quent masking operations. (See Fig. 8).
(9) Implant P-type field-dopant impurities into the relatively thin oxide layer 10 over the P-type well 28. The thicker oxide 29 over the N-well region 26 will also be doped with P-type impurities, -~$~

I~M Docket No. BU 9-83-013 but the thickness of the oxide layer 29 will prevent these impurities from reaching the N-wells 26. (See Fig. 8).
(10) Etch away the doped oxide sacrificial S layer 29 rom the N-wells 26. The doped oxide layer 10 over the P-wells 28 will be protected by the existing silicon nitride layer 14 over these wells. ~See~ Fig. 9).
(11) Regrow a relatively thin (approximately 25-40 nm) silicon dioxide layer 32 over the N-wells 26;
the existing silicon nitride layer 14 will prevent oxidation over ~he P~wells 28. Implant N-type impuri-ties, such as arsenic, into the relatively thin oxide~
. layer 32 over the N-well regions 26. The implant voltage is chosen such that the silicon nitride layer 14 over the P-well regions 26 absorbs substan tially all of this implant. ~See Fig. 10).
(12) Strip from the P-well regions 28 the nitride layer 14 which has been doped with the N-type impuri-ties in the preceeding step. (See Fig. 11).
At this point, the process has produced, with only a single lithographic masking step, twin-well s~ructure in which the P-and N-wells 26 and 28 are aligned to each other and in which there has been formed an alignment step 30 at the boundaries of the P and N-wells, together with the oxide layers 32 and 10 over the respective wells and already doped with an impurity of the conductivity type necessary to produce the field doping for each of the wells.
These oxide layers are s~lf aligned to the step 30 which is self-aligned to the wells.
To complete the for~ation of the field isola-tions, the following additional steps are carried out in sequence.
~13) Deposit a relatively thick oxide layer 34 ~Fig. 12) to be used as field isolation and, using a ~Z~$~

IBM Docket No. BU 9-83-013 lithographic masking step, define ~le field isolations by etching away the thick field oxide layer 34 except in those areas 36 and 38 which define the field isolation regions (Fig. 13). That is, during this etching process, the previously doped oxide layers 32 and 10 are removed from the active device regions of the respective wells 26 and 38.
(14) Using an appropriate heat cycle, drive (diffuse) the N-type and P-type dopants from their respective doped oxide layers 32 and 10 and into the substrate to form the field dopings 40 and 42 under ~he field isolations 36 and 38, respectively. ~See ~ig. 14).
(15) Regrow dielectrics, deposit conductors, etc.
to fabricate a device, such as an FET.
If desired, the lift-off steps may be eliminated so that only N-wells are formed in a P type substrate.
Otherwise the same steps are employed, but the photo-resist masking layer 16 is removed in a separate step between the implant step ~7) and the anneal step in step (8).

Claims (7)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:
1. A process of fabricating an integrated circuit having both P-well and N-well regions in a single semiconductor body, which process uses only a single lithographic masking step to define the posi-tions of both of said well regions and also the position of doped field regions for controlling the parasitic threshold voltages of portions of said body, comprising:
a) forming a first electrically insulating layer on a surface of said semiconductor body;
b) forming on said first layer a second electrically insulating layer from a material pre-selected to be impervious to oxygen diffusion therethrough;
c) lithographically forming a mask over said second electrically insulating layer to define the position of said N-well regions by exposed areas in the mask, and removing said second electrically insulating layer from said exposed areas;
d) implanting N-type conductivity-determining impurities in said semiconductor body, using said mask as an implantation mask to prevent implantation of said P-well regions;
e) forming on said first insulating layer over said N-well regions and on the mask over said P-well regions a layer of lift-off material, and then removing said mask over the P-well regions together with the lift-off material-thereon;
f) implanting into said body P-type conductivity determining impurities using said lift-off material as an implantation mask to prevent P-type impurities from reaching into said N-well regions;
g) removing the remaining lift-off material from said N-well regions. and annealing said semiconductor body to form the desired doping profiles in said P and N-well regions, and oxidizing said body to convert only the body portion in said N-well regions into an electrically insulating grown oxide layer, thus forming a step in said body for use as an alignment mark;
h) implanting said first insulating layer with P-type conductivity determining impurities, using the grown oxide layer over the N-well regions as a mask; and using said second electrically insulating layer over said P-well regions as an etching mask for removing the insulating and oxide layers from over said N-well regions; and i) forming a new electrically insulating layer over said N-well regions, and implanting N-type conductivity determining impurities in said new electrically insulating layer over said N-well regions using said second electrically insulating layer over said P-wells as a masking layer to prevent said N-type conductivity determining impurities from reaching said first insulating layer portion posi-tioned over said P-well regions;
thereby producing N- and P-well regions in said body with alignment marks on the surface of said body indicating the separation of said regions and with corresponding field-doped insulating layers over said regions, wherein the doped insulating layer over said N-well regions is doped with predominantly N-type impurities, and the doped insulation layer over said P-well regions is doped- with predominantly P-type impurities.
2. The process claimed in claim 1 wherein said body is silicon, said first insulating layer is silicon dioxide, and said second insulating layer is silicon nitride.
3. The process claimed in claim 1 further a) depositing a field isolation oxide layer over said body;
b) using said step as an alignment mark, defining field isolations in the isolation oxide layer over said well regions and removing the field-doped insulation layers from the active device regions of said well regions; and c) driving the dopants from the remaining doped insulating layers into said body to form corres-ponding field dopings under the field isolations of said well regions.
4. The process claimed in claim 1 further comprising, between steps (e) and (f), annealing said semiconductor body to drive the N-type impurities into the N-well regions.
5. A process of fabricating an integrated circuit having both P-regions and N-well regions in a single P-type semiconductor body, which process uses only a single lithographic masking step to define the positions of both of said P-regions and N-well regions and also the position of doped field regions for controlling the parasitic threshold voltages of por-tions of said body, comprising:
a) forming a first electrically insulating layer on a surface of said semiconductor body;
b) forming on said first layer a second electrically insulating layer from a material pre-selected to be impervious to oxygen diffusion therethrough;
c) lithographically forming a mask over said second electrically insulating layer to define the position of said N-well regions by exposed areas in the mask, and removing said second electrically insulating layer from said exposed areas;
d) implanting N-type conductivity-determining impurities in said semiconductor body.

using said mask as an implantation mask to prevent implantation of said P-regions;
e) removing the mask;
f) annealing said semiconductor body to form the desired doping profiles in said N-well regions, and oxidizing said body to convert only the body portion in said N-well regions into an elec-trically insulating grown oxide layer, thus forming a step in said body for use as an alignment mark;
g) implanting said first insulating layer with P-type conductivity determining impurities, using the grown oxide layer over the N-well regions as a mask; and using said second electrically insulating layer over said P-regions as an etching mask for removing the insulating and oxide layers from over said N-well regions; and h) forming a new electrically insulating layer over said N-well regions, and implanting N-type conductivity determining impurities in said new electrically insulating layer over said N-well regions using said second electrically insulating layer over said P-regions as a masking layer to prevent said N-type conductivity determining impuri-ties from reaching said first insulating layer portion positioned over said P-regions;
thereby producing N-well regions and P-regions in said body with alignment marks on the surface of said body indicating the separation of said regions and with corresponding field-doped insu-lating layers over said-regions, wherein the doped insulating layer over said N-well regions is doped with predominantly N-type impurities, and the doped insulation layer over said P-regions is doped with predominantly P-type impurities.
6. The process claimed in claim 5 wherein said body is silicon, said first insulating layer is silicon dioxide, and said second insulating layer is silicon nitride.
7. The process claimed in claim 5 further comprising:
a) depositing a field isolation oxide layer over said body;
b) using said step as an alignment mark, defining field isolations in the isolation oxide layer over said P-regions and N-well regions and removing the field-doped insulation layers from the active device regions of said P-regions and N-well regions;
and c) driving the dopants from the remaining doped insulating layers into said body to form corres-ponding field dopings under the field isolations of said P-regions and N-well regions.
CA000485177A 1984-10-15 1985-06-25 Process of making dual well cmos semiconductor structure with aligned field-dopings using single masking step Expired CA1209280A (en)

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DE3584757D1 (en) 1992-01-09
JPH0244155B2 (en) 1990-10-02
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US4558508A (en) 1985-12-17
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EP0178440A3 (en) 1988-01-27

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