CA1215471A - Redundant rows in integrated circuit memories - Google Patents
Redundant rows in integrated circuit memoriesInfo
- Publication number
- CA1215471A CA1215471A CA000445251A CA445251A CA1215471A CA 1215471 A CA1215471 A CA 1215471A CA 000445251 A CA000445251 A CA 000445251A CA 445251 A CA445251 A CA 445251A CA 1215471 A CA1215471 A CA 1215471A
- Authority
- CA
- Canada
- Prior art keywords
- address
- row
- rows
- redundant
- receive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/781—Masking faults in memories by using spares or by reconfiguring using programmable devices combined in a redundant decoder
Abstract
REDUNDANT ROWS IN INTEGRATED CIRCUIT MEMORIES
Abstract of the disclosure Decoding apparatus for an integrated circuit memory having normal rows of memory cells and at least one selectively connectable redundant second row of memory cells for being connected in place of one of the first rows, said apparatus including: a redundant decoder connected to each of the at least one redundant row, the redundant decoder including a plurality of selectable connections for creating an address for each of the at least one redundant row; a control signal generating circuit for generating a control signal of a first state until an address is supplied to the memory and of a second state if any of the at least one redundant row is selected by the address;
and, another decoder connected to receive the control signal from the generating circuit for controlling the normal rows in response thereto.
Abstract of the disclosure Decoding apparatus for an integrated circuit memory having normal rows of memory cells and at least one selectively connectable redundant second row of memory cells for being connected in place of one of the first rows, said apparatus including: a redundant decoder connected to each of the at least one redundant row, the redundant decoder including a plurality of selectable connections for creating an address for each of the at least one redundant row; a control signal generating circuit for generating a control signal of a first state until an address is supplied to the memory and of a second state if any of the at least one redundant row is selected by the address;
and, another decoder connected to receive the control signal from the generating circuit for controlling the normal rows in response thereto.
Description
'7~ ' 50.4196/8332-54/FAIR02H
REDUNDANT ROWS IN INTEGRATED CIRCUIT ~MORIES
Back round of the Invention _ g. _ _ Field of the Invention This invenkion relates to integrated circuit memories, and in particular, to an apparatus .for pro-viding redundant rows in such memories when other po~tions of the memory are found defective.
Descri~tion of the Prior Art In integrated circuit memories, a single de~ect in any portion of the array of memory cells may render the entire memQry useless. As impr~vements in the design and abrication of i~tegrated Ci~CUl*s are made, greater nu~bers c~ memor~ c~lls are bei~g pl~ced on a single chip. Furthermore, ~enerally -.physic 1 ~y larger integrated circui~s are being manufacture~.
E~ch ~act~r t~nds .to ~cr~ase ~e like}ihQod of defect:L~ one or mo~e ~ells which may render an e~tir~
chip useless.
V~e prior:art solution to this prohlem has been-to desi~n a~d fabri~ate i~tegrated circ~it . memories using more ~ault tolerant designs a~d processes. ~his approach, ~y i~self, does nat always suffice. Conse~uently, another solution which has received increasing attention i~ the fabric~tion of redundant components on the same chip. At a suita~le stage in the fabrication process, the non-fu~ctional portions of the circuit are replaced with the redundant portions, typically by using redundant wiring tech-niques, fuses, discretionary metal masks, or ot~.er technigues. The usual prior art approach, however, has been to re~lace an entire relatively large block in the memory with a new block. For example, in a 64k memory divided into 16 sections, each.of 4k bits, a defective $~
bit in a single section will result in the replacement of the entire 4k section. ~nfortunately, this approach requires a considerable amount of extra logic and extra space on the integrated circuit.
While redundant rows improve yield, and are relatively simple to implement, the addressing scheme for redundant rows is critical because it lies along the critical signal path. The added decoding circuits for the redundant rows, when selected by laser fusing or other techni~ues, must select the redundant row and at the same time de-select all the other redundant rows and normal rows of memory cells. At the same time, the operating speed of the overall memory must not be affected by the added circuitry.
Summary of the Inve_tion One feature of the present invention is directed to a decoding apparatus for an integrated circuit memory having first rows of memory cells, each first row being selectable by a row address, including at least one address bit, and having at leas-t one second row selectively connectable in place of one of the first rows, the apparatus comprising:
at least one redundant decoder means, each redundant decoder means being connected to a second row, including a plurality of selectable connections for creating an address for the connected second row, and including means for producing an address signal of a first level if the row address corresponds to the created address and of a second level if the row address does not correspond to the reated address;
logic means for generating a control signal of a first state until an address bit is supplied to the memory and of a second state i.f at least one address signal from the at least one second row is of the first level; and deeoder means conneeted to each first row to reeeive the control slgnal from the logie means for controlling the first row in response thereto.
-2a-Brief Description of the Drawin~s Figure 1 is an electrical schematic illustra-ting an addressing circuit for a normal row of an integrated circuit memory.
Figure 2 is a circuit schematic of a decoder for a redundant row of a me~ory.
Fi~ure 3 is a schematic of the circuit used to generate the control siDal s~plied to Figures 1 and 2.
Detai}ed Descri~tion of t~e Preferred Embodiments ~ igure 1 is a circuit schematic illustrating ~ypical decoding apparatus for a normal-row of memory ' cells connected to line 10~ Xhe apparatus includes transistors ll, 12, and 13 to which address signals A8, Ag, and Alo ~re supplied. ~he combined sisnals of these three transistors are applled to the gate of transistor 14 to selectively connect line lO to poten-tial Vcc, assuming certain other transistors are on.
The address signals from transistors 11, 12, and 13 are also supplied, after being inverted by inverter 15, to the gate of transistor 16. As also shown address signal A6 controls transistor 17, address signal A7 controls transistor 18, address A11 controls trar.sistor l9, and address signal A12 controls transistor 20. In a similar fashion address A4 controls transistor 21, address A5 transistor 22, and a control sisnal ~C
transistor 23. The combined address signals of tran-slstors 21, 22, and 23 control transistor 24 as shown.
The same combined address signals lnverted by inverter 25 also control transistor 26.
In operation if the row connected to line 10 is to be addressed, address sign~l A~ + Ag + Alo will be low turning on transistor 14 and pulling row line lO
to potential Vcc during reading of the memory cells attached to line lO. Alternatively, line 1~ may be pulled to potential Vpp during programming ~y applica-tion of a signal ~o the node designated PGM. ~n additio~, to address row 10 transistors,17, 18, 19, an~
20 must be off. If any of these transistors are on then line 10 will be pulled to ground. The signal supplied to transistor 16 is complementary to that supplied to transistor 14.
~ he potential of line 10 i5 also controlled by a smaller d~coder connected to recei~e addresses A4 and A~, and contr~1 sign~ . These si~nals are suppl~ed to transistors 21,.~2, a~d ~3 respecti~ely, and thereby control transistors 24 and 26. O~ course, if transistor 26 is o~, ~hen line 10 will ~e pulled to .ground, because transistor.~g will ~e o~f~ ~he control .signal ~ supplied to transistor 23 is generated using the apparatus shown i~ Figure 3, ~nd will be dis~ussed in-conj~nction with that Fig~re.
Figure 2 illustrates t~e decoding apparatus associated with the redundant row. A chip enable signal CE is supplied to transistor 30 to connect the redundant row associated with line 31 to potential Vcc unless one of t~e decoding transistors 32, 33,...n is turned on to pull line 31 to ground. Each of these decoding transistors is serially connected with a fuse Fl, F2,...Fn, which, in the preferred embodiment, may be "blown" using a laser. Fuses such as these are well-known in the semiconductor arts. If any of these fuses are blown, then the address signals supplied to the gate of the corresponding transistor will have no effect upon the addressing of row 31. If none of the fuses are blown, then when any address is supplied, the redundant row coupled to line 31 will be pulled tv ground~ and the presence of the redundant row will not affect the remainder of the memory.
If the redundant row i~ desired, then 11 fuses are ~lown e~cept for those correspanding to the desired address of the xedundant row. In this manner the redundant row will be pulled to groulld cnly when one or more o~ its address bits having intact fuses are high. If aIl the connected address bits are low, then redundan~ row 31 will be selected. -~ igure 3 illustrates the manner in which the control ~ is generated for application to transistor .23. As shown in Figure 3, .a plurality of redun-dant IOW a~dresses ~ , ~ ~ Rn~ (whose ~rigins are as shown i:~ Figure 2 ) are applied to an OR gate 35 .
Adaress ~rLputs A4 a~ A4 are applied to the terminals c~ cclusiv~ OR gate 46. l~e ou~put signal~ from ~ates a~ .and 4~ a~e supplied to inp~t termInal~ of NAND gate ~7 $o ~here~ generat~ a control sign21-~.c, which afte~
being invert~d, .is used to control transistor 23.
F~r th~ ~ircuit sho~ in Figures 1, 2, and 3 when the chip containing the memory ~ell~.is enahled, signal ~C stays low. All rows, including-any redundant rows, are pulled hiyh,because all addresses are low unconditionally when the chip is deselected until the ou~puts of the address buffers are valid. Once address signals A4 and A4 are valid, exclusive OR gate 46 supplies a sisnal to NAND gate 47. If a redundant row has been selected, OR gate 45 will also supply a signal and ~C will go low ~nd ~C high to deselect all normal rows. Thu~ for every redundant row only the selected fuses need be ~lown to provide the necessary address signals. If no fuses are blown, then the redundant row will not be selected by any address.
Although ~ne embodiment of this inYention has been described above, this embodiment is intended .tD
o illustrate the invention, rather than limit it. The scope of the invention may be determined from the following claims.
REDUNDANT ROWS IN INTEGRATED CIRCUIT ~MORIES
Back round of the Invention _ g. _ _ Field of the Invention This invenkion relates to integrated circuit memories, and in particular, to an apparatus .for pro-viding redundant rows in such memories when other po~tions of the memory are found defective.
Descri~tion of the Prior Art In integrated circuit memories, a single de~ect in any portion of the array of memory cells may render the entire memQry useless. As impr~vements in the design and abrication of i~tegrated Ci~CUl*s are made, greater nu~bers c~ memor~ c~lls are bei~g pl~ced on a single chip. Furthermore, ~enerally -.physic 1 ~y larger integrated circui~s are being manufacture~.
E~ch ~act~r t~nds .to ~cr~ase ~e like}ihQod of defect:L~ one or mo~e ~ells which may render an e~tir~
chip useless.
V~e prior:art solution to this prohlem has been-to desi~n a~d fabri~ate i~tegrated circ~it . memories using more ~ault tolerant designs a~d processes. ~his approach, ~y i~self, does nat always suffice. Conse~uently, another solution which has received increasing attention i~ the fabric~tion of redundant components on the same chip. At a suita~le stage in the fabrication process, the non-fu~ctional portions of the circuit are replaced with the redundant portions, typically by using redundant wiring tech-niques, fuses, discretionary metal masks, or ot~.er technigues. The usual prior art approach, however, has been to re~lace an entire relatively large block in the memory with a new block. For example, in a 64k memory divided into 16 sections, each.of 4k bits, a defective $~
bit in a single section will result in the replacement of the entire 4k section. ~nfortunately, this approach requires a considerable amount of extra logic and extra space on the integrated circuit.
While redundant rows improve yield, and are relatively simple to implement, the addressing scheme for redundant rows is critical because it lies along the critical signal path. The added decoding circuits for the redundant rows, when selected by laser fusing or other techni~ues, must select the redundant row and at the same time de-select all the other redundant rows and normal rows of memory cells. At the same time, the operating speed of the overall memory must not be affected by the added circuitry.
Summary of the Inve_tion One feature of the present invention is directed to a decoding apparatus for an integrated circuit memory having first rows of memory cells, each first row being selectable by a row address, including at least one address bit, and having at leas-t one second row selectively connectable in place of one of the first rows, the apparatus comprising:
at least one redundant decoder means, each redundant decoder means being connected to a second row, including a plurality of selectable connections for creating an address for the connected second row, and including means for producing an address signal of a first level if the row address corresponds to the created address and of a second level if the row address does not correspond to the reated address;
logic means for generating a control signal of a first state until an address bit is supplied to the memory and of a second state i.f at least one address signal from the at least one second row is of the first level; and deeoder means conneeted to each first row to reeeive the control slgnal from the logie means for controlling the first row in response thereto.
-2a-Brief Description of the Drawin~s Figure 1 is an electrical schematic illustra-ting an addressing circuit for a normal row of an integrated circuit memory.
Figure 2 is a circuit schematic of a decoder for a redundant row of a me~ory.
Fi~ure 3 is a schematic of the circuit used to generate the control siDal s~plied to Figures 1 and 2.
Detai}ed Descri~tion of t~e Preferred Embodiments ~ igure 1 is a circuit schematic illustrating ~ypical decoding apparatus for a normal-row of memory ' cells connected to line 10~ Xhe apparatus includes transistors ll, 12, and 13 to which address signals A8, Ag, and Alo ~re supplied. ~he combined sisnals of these three transistors are applled to the gate of transistor 14 to selectively connect line lO to poten-tial Vcc, assuming certain other transistors are on.
The address signals from transistors 11, 12, and 13 are also supplied, after being inverted by inverter 15, to the gate of transistor 16. As also shown address signal A6 controls transistor 17, address signal A7 controls transistor 18, address A11 controls trar.sistor l9, and address signal A12 controls transistor 20. In a similar fashion address A4 controls transistor 21, address A5 transistor 22, and a control sisnal ~C
transistor 23. The combined address signals of tran-slstors 21, 22, and 23 control transistor 24 as shown.
The same combined address signals lnverted by inverter 25 also control transistor 26.
In operation if the row connected to line 10 is to be addressed, address sign~l A~ + Ag + Alo will be low turning on transistor 14 and pulling row line lO
to potential Vcc during reading of the memory cells attached to line lO. Alternatively, line 1~ may be pulled to potential Vpp during programming ~y applica-tion of a signal ~o the node designated PGM. ~n additio~, to address row 10 transistors,17, 18, 19, an~
20 must be off. If any of these transistors are on then line 10 will be pulled to ground. The signal supplied to transistor 16 is complementary to that supplied to transistor 14.
~ he potential of line 10 i5 also controlled by a smaller d~coder connected to recei~e addresses A4 and A~, and contr~1 sign~ . These si~nals are suppl~ed to transistors 21,.~2, a~d ~3 respecti~ely, and thereby control transistors 24 and 26. O~ course, if transistor 26 is o~, ~hen line 10 will ~e pulled to .ground, because transistor.~g will ~e o~f~ ~he control .signal ~ supplied to transistor 23 is generated using the apparatus shown i~ Figure 3, ~nd will be dis~ussed in-conj~nction with that Fig~re.
Figure 2 illustrates t~e decoding apparatus associated with the redundant row. A chip enable signal CE is supplied to transistor 30 to connect the redundant row associated with line 31 to potential Vcc unless one of t~e decoding transistors 32, 33,...n is turned on to pull line 31 to ground. Each of these decoding transistors is serially connected with a fuse Fl, F2,...Fn, which, in the preferred embodiment, may be "blown" using a laser. Fuses such as these are well-known in the semiconductor arts. If any of these fuses are blown, then the address signals supplied to the gate of the corresponding transistor will have no effect upon the addressing of row 31. If none of the fuses are blown, then when any address is supplied, the redundant row coupled to line 31 will be pulled tv ground~ and the presence of the redundant row will not affect the remainder of the memory.
If the redundant row i~ desired, then 11 fuses are ~lown e~cept for those correspanding to the desired address of the xedundant row. In this manner the redundant row will be pulled to groulld cnly when one or more o~ its address bits having intact fuses are high. If aIl the connected address bits are low, then redundan~ row 31 will be selected. -~ igure 3 illustrates the manner in which the control ~ is generated for application to transistor .23. As shown in Figure 3, .a plurality of redun-dant IOW a~dresses ~ , ~ ~ Rn~ (whose ~rigins are as shown i:~ Figure 2 ) are applied to an OR gate 35 .
Adaress ~rLputs A4 a~ A4 are applied to the terminals c~ cclusiv~ OR gate 46. l~e ou~put signal~ from ~ates a~ .and 4~ a~e supplied to inp~t termInal~ of NAND gate ~7 $o ~here~ generat~ a control sign21-~.c, which afte~
being invert~d, .is used to control transistor 23.
F~r th~ ~ircuit sho~ in Figures 1, 2, and 3 when the chip containing the memory ~ell~.is enahled, signal ~C stays low. All rows, including-any redundant rows, are pulled hiyh,because all addresses are low unconditionally when the chip is deselected until the ou~puts of the address buffers are valid. Once address signals A4 and A4 are valid, exclusive OR gate 46 supplies a sisnal to NAND gate 47. If a redundant row has been selected, OR gate 45 will also supply a signal and ~C will go low ~nd ~C high to deselect all normal rows. Thu~ for every redundant row only the selected fuses need be ~lown to provide the necessary address signals. If no fuses are blown, then the redundant row will not be selected by any address.
Although ~ne embodiment of this inYention has been described above, this embodiment is intended .tD
o illustrate the invention, rather than limit it. The scope of the invention may be determined from the following claims.
Claims (18)
1. Decoding apparatus for an integrated circuit memory having first rows of memory cells, each first row being selectable by a row address, including at least one address bit, and having at least one second row selectively connectable in place of one of the first rows, the apparatus comprising:
at least one redundant decoder means, each redundant decoder means being connected to a second row, including a plurality of selectable connections for creating an address for the connected second row, and including means for producing an address signal of a first level if the row address corresponds to the created address and of a second level if the row address does not correspond to the created address;
logic means for generating a control signal of a first state until an address bit is supplied to the memory and of a second state if at least one address signal from the at least one second row is of the first level; and decoder means connected to each first row to receive the control signal from the logic means for controlling the first rows in response thereto.
at least one redundant decoder means, each redundant decoder means being connected to a second row, including a plurality of selectable connections for creating an address for the connected second row, and including means for producing an address signal of a first level if the row address corresponds to the created address and of a second level if the row address does not correspond to the created address;
logic means for generating a control signal of a first state until an address bit is supplied to the memory and of a second state if at least one address signal from the at least one second row is of the first level; and decoder means connected to each first row to receive the control signal from the logic means for controlling the first rows in response thereto.
2. The apparatus of Claim 1 wherein the logic means comprises:
first means connected to receive the address signal from each of the at least one second row; and second means connected to receive a selected address bit.
first means connected to receive the address signal from each of the at least one second row; and second means connected to receive a selected address bit.
3. The apparatus of Claim 2 wherein the first means supplies a first output signal if any of the address signals for the at least one second row is of the first level.
4. The apparatus of Claim 3 wherein the first means comprises an OR
gate.
gate.
5. The apparatus of Claim 3 wherein the second means is connected o receive a complement of the address bit and supply a second output signal.
6. The apparatus of Claim 5 wherein the second means comprises an exclusive OR gate.
7. The apparatus of Claim 7 wherein both of the first and second output signals are connected as input to a logic gate.
8. The apparatus of Claim 7 wherein the logic gate comprises a NAND
gate.
gate.
9. The apparatus of Claim 7 wherein the logic gate output is the control signal.
10. The apparatus of Claim 1 wherein each redundant decoder comprises a plurality of transistors each adapted to receive an address bit.
11. The apparatus of Claim 10 wherein each transistor is connected to the second row and a fusing means is serially connected between each transistor and ground.
12. The apparatus of Claim 11 wherein each fusing means comprises a laser destructible electrical connection.
13. The apparatus of Claim 11 wherein each transistor includes a .
control electrode connected to receive and address bit.
control electrode connected to receive and address bit.
14. The apparatus of Claim 1 having at least two second rows.
15. The apparatus of Claim 3 having at least two second rows.
16. The apparatus of Claim 6 having at least two second rows.
17. The apparatus of Claim 9 having at least two second rows.
18. The apparatus of Claim 13 having at least two second rows.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/457,999 US4538247A (en) | 1983-01-14 | 1983-01-14 | Redundant rows in integrated circuit memories |
| US457,999 | 1990-01-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1215471A true CA1215471A (en) | 1986-12-16 |
Family
ID=23818943
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000445251A Expired CA1215471A (en) | 1983-01-14 | 1984-01-13 | Redundant rows in integrated circuit memories |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4538247A (en) |
| EP (1) | EP0114763A3 (en) |
| JP (1) | JPS59140700A (en) |
| CA (1) | CA1215471A (en) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60130000A (en) * | 1983-12-15 | 1985-07-11 | Mitsubishi Electric Corp | Semiconductor storage device |
| JPS60191500A (en) * | 1984-03-08 | 1985-09-28 | Sharp Corp | Redundancy circuit |
| US4618784A (en) * | 1985-01-28 | 1986-10-21 | International Business Machines Corporation | High-performance, high-density CMOS decoder/driver circuit |
| KR890001847B1 (en) * | 1986-05-07 | 1989-05-25 | 삼성전자 주식회사 | Semiconductor memory devices |
| US4758744A (en) * | 1986-11-26 | 1988-07-19 | Rca Corporation | Decoder circuitry with reduced number of inverters and bus lines |
| EP0327861B1 (en) * | 1988-02-10 | 1993-03-31 | Siemens Aktiengesellschaft | Redundancy decoder for an integrated semiconductor memory |
| DE3934303C2 (en) * | 1988-10-15 | 2001-01-25 | Sony Corp | Address decoder for non-volatile memories |
| JP2575919B2 (en) * | 1990-03-22 | 1997-01-29 | 株式会社東芝 | Redundancy circuit of semiconductor memory device |
| DE69128746T2 (en) * | 1990-06-19 | 1998-07-16 | Texas Instruments Inc | Laser path decoder for DRAM redundancy scheme |
| US5257228A (en) * | 1991-05-16 | 1993-10-26 | Texas Instruments Incorporated | Efficiency improved DRAM row redundancy circuit |
| KR100248165B1 (en) * | 1992-04-16 | 2000-03-15 | 칼 하인쯔 호르닝어 | Integrated semiconductor memory with redundancy arrangement |
| GB9223226D0 (en) * | 1992-11-05 | 1992-12-16 | Algotronix Ltd | Improved configurable cellular array (cal ii) |
| US5551004A (en) * | 1993-05-28 | 1996-08-27 | Sgs-Thomson Microelectronics, Inc. | Structure which renders faulty data of a cache memory uncacheable in order that a partially functional cache memory may be utilized |
| US5369314A (en) * | 1994-02-22 | 1994-11-29 | Altera Corporation | Programmable logic device with redundant circuitry |
| EP0675436B1 (en) * | 1994-03-31 | 1999-10-27 | STMicroelectronics, Inc. | Recoverable set associative cache |
| US6091258A (en) * | 1997-02-05 | 2000-07-18 | Altera Corporation | Redundancy circuitry for logic circuits |
| US6034536A (en) * | 1997-02-05 | 2000-03-07 | Altera Corporation | Redundancy circuitry for logic circuits |
| JP3865789B2 (en) * | 1997-05-23 | 2007-01-10 | アルテラ コーポレイション | Redundant circuit for programmable logic device with interleaved input circuit |
| US6201404B1 (en) | 1998-07-14 | 2001-03-13 | Altera Corporation | Programmable logic device with redundant circuitry |
| JP2002064145A (en) * | 2000-06-09 | 2002-02-28 | Fujitsu Ltd | Integrated circuit chip having redundancy element, multiprocessor and method of manufacturing the same |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4250570B1 (en) * | 1976-07-15 | 1996-01-02 | Intel Corp | Redundant memory circuit |
| US4059231A (en) * | 1976-07-16 | 1977-11-22 | Grefco, Inc. | Method and apparatus for selectively comminuting particles of a frangible material |
| JPS56174200U (en) * | 1980-05-27 | 1981-12-22 | ||
| US4358833A (en) * | 1980-09-30 | 1982-11-09 | Intel Corporation | Memory redundancy apparatus for single chip memories |
-
1983
- 1983-01-14 US US06/457,999 patent/US4538247A/en not_active Expired - Lifetime
-
1984
- 1984-01-13 JP JP59003712A patent/JPS59140700A/en active Granted
- 1984-01-13 CA CA000445251A patent/CA1215471A/en not_active Expired
- 1984-01-13 EP EP84400068A patent/EP0114763A3/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| EP0114763A3 (en) | 1988-07-27 |
| US4538247A (en) | 1985-08-27 |
| JPH0444359B2 (en) | 1992-07-21 |
| EP0114763A2 (en) | 1984-08-01 |
| JPS59140700A (en) | 1984-08-13 |
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