CA1216630A - Method and apparatus for testing of electrical interconnection networks - Google Patents
Method and apparatus for testing of electrical interconnection networksInfo
- Publication number
- CA1216630A CA1216630A CA000449003A CA449003A CA1216630A CA 1216630 A CA1216630 A CA 1216630A CA 000449003 A CA000449003 A CA 000449003A CA 449003 A CA449003 A CA 449003A CA 1216630 A CA1216630 A CA 1216630A
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- network
- interconnection
- impedance
- terminal
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- 238000012360 testing method Methods 0.000 title claims abstract description 69
- 238000000034 method Methods 0.000 title claims abstract description 55
- 238000005259 measurement Methods 0.000 claims abstract description 82
- 239000000523 sample Substances 0.000 claims abstract description 82
- 238000002847 impedance measurement Methods 0.000 claims abstract description 9
- 239000004020 conductor Substances 0.000 claims description 61
- 230000007547 defect Effects 0.000 claims description 12
- 238000010998 test method Methods 0.000 claims description 2
- 230000003213 activating effect Effects 0.000 claims 2
- 238000001514 detection method Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 22
- 238000010586 diagram Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 230000006870 function Effects 0.000 description 5
- 238000013459 approach Methods 0.000 description 4
- 230000002950 deficient Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000037361 pathway Effects 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 241000282320 Panthera leo Species 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 210000003371 toe Anatomy 0.000 description 2
- 241000282322 Panthera Species 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000005686 electrostatic field Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000013101 initial test Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- PXHVJJICTQNCMI-BJUDXGSMSA-N nickel-58 Chemical compound [58Ni] PXHVJJICTQNCMI-BJUDXGSMSA-N 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000012883 sequential measurement Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/08—Locating faults in cables, transmission lines, or networks
- G01R31/088—Aspects of digital computing
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2805—Bare printed circuit boards
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/302—Contactless testing
- G01R31/312—Contactless testing by capacitive methods
Abstract
Abstract A method and apparatus for testing circuit boards using two or a small number of probes for making resistive and radio frequency impedance measurements e.g. capacitive measurements. The combination of resistive and impedance measurements substantially reduces the number of tests required to verify the integrity of a circuit board. The impedance or capacitive "norm" values used in testing the circuit boards can be obtained by operating the system in a learning mode.
Analysis of the data provides not only fault detection but also can indicate approximate fault location.
Analysis of the data provides not only fault detection but also can indicate approximate fault location.
Description
36:~
This invention relates to electrical interconnection networks, and more particularly, to methods and apparatus for testing the integrity of rigid or flexible interconnection networks.
Background of the Invention:
-Interconnection networks (hereinafter also referred toes interconnection boards) are used for mounting and interconnections electronic components in most commercial electronic equipment. The interconnection boards are generally made by either of two commonly used methods.
The most kimono method of manufacture is based on graphics technology wherein an image of the desired pattern is produced by mechanical or photographic printing techniques on the board surface and the actual conductors are made by 2 plating or an etching process, or a combination of such processes providing conductive paths.
The second type of Interconnection board is made by one of the so-called discrete wiring processes. In these methods insulated wire is lazed down on the board surface, usually by a point to point computer controlled program" to form the conductive pathways. The connections between terminal points and the conductive pathways may be made by mechanical deformation, soldering, or a metal plating process.
.
.~., i , . . .
l l Interconnection boards may display one an more of the
This invention relates to electrical interconnection networks, and more particularly, to methods and apparatus for testing the integrity of rigid or flexible interconnection networks.
Background of the Invention:
-Interconnection networks (hereinafter also referred toes interconnection boards) are used for mounting and interconnections electronic components in most commercial electronic equipment. The interconnection boards are generally made by either of two commonly used methods.
The most kimono method of manufacture is based on graphics technology wherein an image of the desired pattern is produced by mechanical or photographic printing techniques on the board surface and the actual conductors are made by 2 plating or an etching process, or a combination of such processes providing conductive paths.
The second type of Interconnection board is made by one of the so-called discrete wiring processes. In these methods insulated wire is lazed down on the board surface, usually by a point to point computer controlled program" to form the conductive pathways. The connections between terminal points and the conductive pathways may be made by mechanical deformation, soldering, or a metal plating process.
.
.~., i , . . .
l l Interconnection boards may display one an more of the
2 following defects:
a. Points of a conductor network which should be connected together have one (or more) discontinuities in the Al conductor path(s). This results in an "open circuit" condition 6 with substantially infinite resistance between certain sections ¦
7 of the network.
Al b. Two independent conductor networks or conductor I areas which are intended to have no electrical connection, and 1nl, therefore, substantially infinite resistance between them, in ill' fact, display an unacceptable, low value of resistance between the two networks commonly referred to as a 'short circuit".
13 c. A conductive pathway is defective because it 14 ¦ displays one or more sections having a resistance exceeding the 15 I acceptable level. This defect is referred to as a "resistive 16 I fault.
lo I In an acceptable interconnection board the resistance 18 , between terminals of a common conductor network is normally in lug I the range of from a few milliohms to a few ohms depending on 20l the length and cross-section of the conductors. The resistance 21 between independent networks should approach infinity, ego, 22 ¦ typically exceed l00 megohms.
23 I The most common technique presently used for testing 24 ' interconnection boards involves making resistance measurements 25 , between each terminal pair of each network of the board to 26 verify the existence of a proper conductive path and, in I addition, resistance measurements between a terminal of each ,, I network and a terminal of all the other networks to insure the 29~ absence of short circuits or unacceptable low resistance paths - 30 between networks. One of the disadvantages of this board , .
I 3~3 I testing concept is that it requires a very large number of 2 individual measurements. For example, a board having 1000 I networks and an average of 3 terminal points per network Al requires 499,500 tests for shorts and additional 2000 tests for Al opens and thus a total of 501,500 tests Sequential 6 measurements using moving probes are impractical with this 7' technique because of the time needed for this large number of Al the test measurements and the complexity of the necessary probe ., ill movement control. Resistive measurements therefore are 10l~ generally made using a special multi contact probe (known as a 11 "bed of nails") providing contacts to each terminal point of I the interconnection board being tested. with parallel contact 13 1 of all of the terminals on the board at the same time, rapid 14 electronic switching can be used to accomplish the individual measurements thereby substantially reducing the time required 16 ¦ for testing an individual board. Such multi contact probes have 17 I to be custom made to match the terminal pattern of the 18 I interconnection board to be tested (e.g. the hole pattern in 19¦1 the case of boards with plated through holes) and, as such, are 20 I relatively time consuming to make and expensive. "Universal"
211l bed of nails multi contact probes are also in use; such probes 22l~ are not only very expensive, but require special adaptation 23 Al tooling for each terminal pattern. Furthermore, with the trend Al toward interconnection board designs with increased terminal 25l point densities, another disadvantage of the "bed of nails 26l concept consists in the high pressure that has to be applied to 27' the multi contact probe fixture in order to achieve adequate I individual contact pressure at each terminal point. For a 29 contact force of only two ounces per contact, for example, a total force of 1250 pounds is required for testing an 1 interconnection board with 10,000 terminals.
I Another interconnection board testing technique which I has been suggested in the past utilizes a movable probe for measuring capacitance between each terminal point and a common S conductor plate. this technique is described in "Continuity 6, Testing by Capacitance" by Robert W. Wed wick, published in Circuits Manufacturing, November AYE, pages 60 and 61 and in I U.S. Patent No. 3,975,680 issued to Larry JO Webb. This type 9 I of measurement, however, does not detect resistive faults in the conductor paths, and, therefore, does not provide complete 11ll test results suitable for assuring electrical integrity of the 12~ interconnection board being tested.
13l An object of the present invention is to provide a method and apparatus capable of completely testing an interconnection board which does not require a "bed of nails"
16 I or similar type multi contact probe 17 Another object of the invention is to provide a method 18 I and apparatus for testing an interconnection board employing 19 ¦ moving probes and sequential measurements and requiring only a 20 I limited number of test measurements.
21 1 Another object of the invention is to provide a method 22¦l and apparatus which can operate on a "self learning" mode to 23 Al' develop criteria for accepting and rejecting boards.
24 , Another object of the invention is to provide an 25 Al apparatus and testing method capable of determining the signal 26 transmission characteristics of the network interconnections.
271 Still another object of the invention is to provide a 28l board testing method and apparatus which not oriole detects 29 faults, but which is also capable of giving the location of faults on the board.
31~ , l .
I Summary of the Invention i, 2 Applicants have found that by using two, or a small ill number, of moving probes, the combination of resistance measurements with radio frequency impedance measurements, e.g., Al capacitance measurements in accordance with the present Al invention, an unexpected and substantial reduction of Al sequential measuring operations or tests is achieved for Al assuring electrical integrity of the interconnection board 4 I tested; the concept of the present invention allows at the same 10l time to test the board completely and for all types or defects 11 described herein before. Furthermore, the concept of this 12¦l invention avoids the necessity of individual test fixtures.
13!l With the invention only two probes need be in contact 14 with terminal points on the board under test any given 15 , time. Thus, the invention provides adequate contact pressure 16 ¦ without exposing the interconnection board to the excessive 17 forces necessary for testing boards with high terminal density 18 when using the bed of nails method.
19¦ In a preferred embodiment of the present invention, 20l each segment of a network is tested for continuity integrity by 21 if a resistance measurement test which detects open faults and 22 resistance faults. A single impedance, e.g. a capacitance 23 it test, it any point in a selected network, taken with respect to 2~1 a common reference plane establishes whether the network is 25jl shorted to any other network. As a result, the number of 26 fill required test operations is greatly reduced.
27~ For the test method of the prior art employing byway, resistance measurement tests and a bed of nails or moving 29l probes the number of tests is given as follows:
, For N = number of networks of the interconnection board;
; P/N = the average number of terminals per network.
The number of tests required to determine whether any ! network is shorted to any other network it:
5 ¦ I No _ N
6 Al ; and, ill the number of tests required to verify continuity 8 I integrity of each network is l (P/N-l)N.
9 I Using the method of the present invention in its 101l preferred embodiment, the number of tests required with respect to possibly existing shorts is only N, namely one impedance, l e.g. capacitance test, per network; and, the number of tests to 13 ', verify continuity within each of the networks is, as before, lo Using the previously mentioned example of an 16 interconnection board having 1000 network with an average of 17 ¦ three terminal points per network, the prior art methods (bed 18 of nails or movable probes for resistance measurements require 19 Lowe - 1000 + (3 - 1)1000 = 499 500 + 2 000 = 501 ~00 201l 2 21¦, tests for testing the board for shorts, opens and resistive 22i faults.
23¦l The method of the present invention in the above 241~ described, preferred embodiment requires only 1 000 tests for 25~l shorts and ~3-1)1000 = 2,000 tests for opens and resistive 26~l faults or a total of 3,00Q tests for completely testing the 27 11 interconnection board of the example. The number of tests is Al thus reduced by a ratio of 160 to 1.
29 Al The system according to this invention can be operated 30 in a " learning mode" by evaluating a sample board or sample I I Us 6 I
it 1 quantities of boards of the kind to be tested to derive 2 information for establishing the parameters for subsequent testing of the same type of board. Moreover, the invention in one of its embodiments provides for the generation of information for giving locations of defects present on a board.
6 according to a preferred embodiment of this invention Al at least two, preferably independently movable probes are I employed which follow a sequence contacting terminal points.
9 The capacitance is measured between the terminals and a Al conductive reference plane either adjacent the interconnection 11' board or forming part of the interconnection hoard. The I measured capacitance is a function of the length and width of 13~ the conductors connected to the terminal and serves to detect 14¦l the open circuit" and "short circuit" defects as previously ¦ defined. A resistance measurement is then made between 16 I terminals within the network to detect any "resistance faults".
17~¦ The correct capacitance values for a good 811 interconnection board without faults are, in general, difficult 19~l to calculate since, in addition to the effect of the conductor 20 11 length, the capacitance value is also affected by fringe 21ll effects, variations in conductor width, and variations in 22 distance between the conductor and the conductive reference 231~ plane. To eliminate the need for such calculations, as 24¦ mentioned before, the system according to the invention may be 25l used in a self learning mode. Capacitance measurements are 26l~ first made on several boards. Measurements falling outside one 27l' mean deviation from the "norm" for a particular terminal are Al eliminated and the "norm" is then recalculated. In this manner I a set of measured values is derived which can be used in further measurements of boards of the same type to detect "open lo of.) I circuits" and "short circuits Al, In a preferred embodiment according to the concept of Al the invention the location of the defects in the board can be I indicated. The resistance measurement of each segment of each 5 l network will indicate the location of each "open" or Eli resistance faulted" segment. In the case of an "open circuit"
defect, use may be made under certain conditions of the 811 capacitive measurements which indicate the length o' conductor lo connected to each terminal. By comparing the measurements of a 10l faulty interconnection board with the correct values for fault 11l free board, the approximate length of the conductor from each terminal to the location of the "open circuit" may be 13~¦ determined and thus, the location of the defect established.
it In the case of a "short circuit" condition, the capacitive measurements can be examined to determine which two 16 ¦ independent networks are in contact with each other and thus 17 I shorted together. Both networks will have abnormally high 18 capacitive measurements if compared to the norm capacitance 19 ¦ values for the respective intact networks and will show about 201l the same value. In accordance with one embodiment, resistance 21 ¦¦ measurements between terminals of the two shorted networks 22 ¦¦ provides sufficient data to determine the conductor distance 231 from each terminal to the point of the short, thus, 24 Al establishing the locus of the defect.
25ll !
26 ! Brief Description of the Drawings:
27 I The foregoing an other objects of the invention will I l' become apparent from the following detailed specification which 29 ! sets forth illustrative embodiments of the invention. The it 1, I drawings form part of this specification wherein:
I Figure l is a schematic block diagram showing the 2 apparatus according to the invention;
I Figures AUDI are flow diagrams illustrating the Al method by which tests are made according to the invention;
511 Figure 3 is a diagram illustrating fault location Eli using resistance measurements; and 7¦1 Figure 4 is an exploded view showing an 8 Al interconnection board with an internal reference plane ill connected for capacitive measurements.
10 If, Al Detailed Description of the Invention 121l Apparatus according to the invention is shown 13~ diagrammatically in Fig. l. A circuit board 10, to be tester lo I is placed on a dielectric layer if which overlies a conductive 15 Al plate 12. The circuit board includes various terminal holes at 16~¦ locations 14 and interconnecting conductors 16. The terminal 17¦¦ points can be in the form of holes with plated walls and lands 18¦ surrounding the holes on the board surface or can be in the lg¦l form of plated pads or other known forms. The terminal points I are interconnected by conductors to form separate conductor 211l nitric 22 I The apparatus of this embodiment includes at least two 23 l independently movable probes 20 and 22, as shown in Fig. l.
24 I Each probe includes a shaped contact portion which can be raised and lowered by conventional apparatus, e.g., pneumatic 26~ or solenoid actuators. When in the lowered position a downward 27 if force is applied to the contact area, such as supplied by a 28 compression spring, to thereby insure good contact. between 29 probe and terminal. The locations of probes 20 and 22 with 30l respect to the board being tested are controlled, respectively, 1 by x-y positioning systems 24 and 26. These positioning 2,' systems ore capable of moving the probes to any desired x-y coordinate so that, when lowered, a probe can contact any desired terminal point on the board.
I The probes are electrically connected sequentially to I a resistance measuring device 30 and a capacitive measuring 7 I device 32. When activated, the resistive measuring device ¦ measures the resistance between probes 20 and 22 and the ill capacitive measurement device, measures the capacitance between 10 l the activated probe(s) and plate 12.
These measured resistance values vary according to the I, l conductor length. For most boards of normal configuration the 13 if resistance of a conductive pathway is bottle a few milliohms 14 I and a few ohms.
15 I The capacitive measurements indicate the capacitance 16 1 between the conductor(s) (if any) connected to the respective 171 terminal arid the conductive plate 12. The measured value is a 18 I function of the total length and width of conductors connected 19 ¦ to the terminal. All terminals connected to the same conductor network will show very nearly the same capacitance value. In 21 I the case of an "open circuit" condition, one or more of the 22~¦ terminals will show a capacitance value below the "norm" for 23l the network thus indicating a conductor connected thereto which 24l is shorter than it should be. "Short circuit" conditions i.e., 25~l a connection between two independent networks, result in 26l abnormally high capacitance values appearing at all terminals 27~ belonging to the shorted networks.
28ll Suitable resistance and capacitance measurement 29l devices may be designed by persons skilled in the art and are available commercially, e.g., from the Hewlett-Packard Company 1 (Model AYE CRY Meter 2 Operation of the apparatus is preferably controlled by Al; a computer 40. The computer supplies the x and y coordinate 4 I positions to positioning systems 24 and 26 to bring the probes 5 l into contact with desired terminal hole pairs. The computer 6 l l also activates measuring instruments 30 and 32 when ill measurements are desired and records the measured values.
ill The computer is suppled with data giving the o' coordinates of all terminal holes on the board and is further supplied with information indicating which groups of the 11 terminal holes connect to specific conductor networks.
ill The computer can be supplied with the specific 13 I sequence of measurements, or, preferably, can develop a 14 I sequence on the basis of the coordinates information.
The board 10 under test is aligned on the board 16 ! support of the tester which includes dielectric layer 11 and 17 ¦¦ plate 12 so that the rows of terminal points, are parallel to 18 1¦ the x and y axes as much as possible. The data base 9 I! controlling probe positioning is presorted to position probe 20 if number 20 to the first terminal point of the first row and then 21~ to each adjacent terminal point.
221 Probe 20 is lowered into contact with the hole, and the capacitance of this terminal point, with respect to 24¦l reference plate 12 is measured and recorded by the computer.
25l Probe 22 is then moved into position over the point 26~l corresponding to an end of the same network. After probe 20 27l has measured the capacitance as described above, probe 22 is 28 lowered into contact. Probe 20 is electrically switched from 2~j the capacitance measuring mode to the resistance (or 3Q conductance measuring mode and the two probes are now used to I
Al determine the end to end resistance of the network or the 2 lo terminal to end resistance if the terminal connected to probe 31 20 is not at the end. This value is also recorded by the 4 I computer.
So` Probe 20 is then switched back to the capacitance 6jl measuring mode and moved into position over the next terminal 71; point of the first row and the process is repeated. This 8 I procedure is followed terminal point by terminal point and line Al by line with probe 20 progressing from the first row to the 101l second, third, etc. and probe 22 positioning itself over network end points. The design of the probes is such as to 1~1 permit simultaneous probing of two adjacent terminal points 13 Al (holes) in the same row, thus, providing for the testing of two it ¦ adjacent terminal points (e.g. plated through holes or pairs) lo I in the same row.
16 I Within the concept of the present invention the probes 17 ¦ may be programmed in a variety of different ways for performing 18 ¦ static and dynamic testing of the interconnection boards. One 19 ¦ of the probes may be programmed to measure capacitance with 20 I respect to the reference plane. Alternatively both probes may 21 I be programmed to measure capacitance thus increasing the 22 I throughput. A common probe may measure capacitance and then be 23 I switched in function to read resistance in cooperation with 24 I another probe, or separate probes can be used for the capacitance and the resistance measurements. Other testing 26 I techniques can also be combined. For example, one probe may be 27l programmed to inject a burst of high voltage, radio frequency 2Bj; energy into a network while other probes monitor the resultant 29l current to thereby test for high stress breakdown. As another example, one probe may be pulsed with a steeply rising waveform I .
i of voltage which is injected into the end point of a network 2 and the same probe can be connected to apparatus which can be used to measure the magnitude of the reflected wave indicating the characteristic impedance of the network.
Capacitive values fur a circuit board may in principle 6 be calculated. The capacitance is principally a function of I the area of the conductor run. It is also affected by other I factors such as the distance between the conductor and the Al conductive plate employed as reference plane, the effect of other conductors in the electrostatic field of the measurement, 11 ' and various fringing effects due to conductor configuration.
I Actual calculation of capacitance values is, therefore, 13j, obviously difficult. Rather than require the operator to I¦ determine the capacitive values for a board without defects, it is preferable to use a self learning approach where the correct 16 value is derived from actual measurements. The method of the 17 I invention can be carried out manually, but is preferably done 181 automatically by a control system which can be either a 191~ dedicated digital control system or a programmed general purpose digital computer 21 I The following section describes the "Learn Mode" in 22~l detail for an interconnection board having terminal holes with 23'l metalized walls to form terminal points.
24 I Figure pa is a flow diagram for acquiring information 25~l in a learning mode called "LEARN I which information is 26 I subsequently used to determine the normal capacitive values for 27l the interconnection board. In step 101 the computer is loaded 28 ! with information indicating the x and y coordinates of all the 29l terminal holes on the board as well as data indicating which terminal points are interconnected in network combinations.
I
Al An interconnection boar is then loaded Leo placed 2 in position above conductive plate 12 forming the reference plane and dielectric 11 fig. AL) in step 102. Thereafter the lo computer supplies the x and y coordinate information to the 5~1 probe positioning apparatus in step 103. In the learning mode Al the system is only required to make capacitive measurements 7j¦ and, hence, only one probe need be used. However, the data can 8 I be acquired more quickly using both probes and, hence, the use ill of two probes is preferable. Once the probes are positioned 10¦¦ the are lowered into contact with the terminal holes or lands 11l and the capacitive measurements are made to determine the "C"
12 ¦ values in step 104. The "C" values are stored in the computer , !
13 ¦ memory in step 105. In decision 106 the computer determines if 14 I it has measured capacitance of the last hole and, if not, the lo I computer returns to step 103 to advance to the next hole pair 16 ¦ and another set of measurements. Operation continues in this 17 I fashion until the last hole has been measured at which point 18 the computer advances from decision 106 to decision 107.
19¦ The computer next determines if it has sufficient data 20!l for determination of the "norm" values. If the same capacitive 21 ¦ value for a particular terminal point appears in measurements 22 ¦ on a number of boards, it can be assumed that this is the 23 correct capacitive value for a board free from defects.
24 I Usually data from 3 to 10 boards is sufficient to determine the 25 Al "norm" values. When sufficient data has been obtained the 26l~ memory disc array is closed in step 108 and the system proceeds I I to determine the "norm" values according to the flow diagram in Bill figure 2b called "LEARN #2".
29l First, as indicated in step 110 of figure 2b, the computer is supplied with additional information indicating the 1 "percent deviation" for the norm value which should be slagged 2 as an error. For most boards a value of 10% deviation from the norm is sufficiently wide to pass all good boards and, at the Al same time, detect and reject all defective boards. For less Al critical applications a 20~ deviation may be appropriate. In 6 some cases the value can be as high as 30%.
Al In processing the data according to the learning mode, 8 ¦ the computer in step 111 calls up from memory all the data for Al a particular terminal hole and then calculates the mean and no' standard deviation for these values in step 112. In step 113 11 values that fall more than one standard deviation either side I of the mean value are discarded and a new mean value is 13 I calculated and stored as the "norm". In decision 116 the 14~ computer determines whether or not the data for all of the 15¦ terminal holes have been evaluated and, if not, the sequence 16 returns to step 111 for evaluation of data on the next terminal 17 hole.
18 Data points which are above and below values permitted 19 within the designated "percent deviation" are flagged by the computer as faults. As previously mentioned the "percent 21lll deviation" value is assigned and not fixed because the 22¦' tolerance should be a function of the type of board being 23 I tested. As an example, discrete wiring boards, using constant 24 Al diameter wire for forming conductors may be assigned tighter US if tolerance than a dense multi layer board with very fine 26 I conductor lines (e.g., five mills wide) and subject to much 27'l larger percentage variations due to the etching or plating 28 process variations.
29 Tables 1 and 2 illustrates the type of data collected 30 ! in the learning mode which may be used in establishing of the 12 'c :;30 if inform values. A simple example of how the learn mode data 2 I might appear for one four-hole network in a sample lot of five boards wherein one of the boards does contain an open circuit ill is shown in Table l. Table 2 shows the data for a simple 5 Al three-hole network containing a board with a suspected short I circuit-I
9..
11 1., 14 :
I
lo I
I
1 TABLE 1 - Data of Nitric I NET HOLE- Bordello BYRD BYRD BYRD BOARDS
2;! ~~-Gil 3 140.1* 39~5 39.9 40.2 40.0
a. Points of a conductor network which should be connected together have one (or more) discontinuities in the Al conductor path(s). This results in an "open circuit" condition 6 with substantially infinite resistance between certain sections ¦
7 of the network.
Al b. Two independent conductor networks or conductor I areas which are intended to have no electrical connection, and 1nl, therefore, substantially infinite resistance between them, in ill' fact, display an unacceptable, low value of resistance between the two networks commonly referred to as a 'short circuit".
13 c. A conductive pathway is defective because it 14 ¦ displays one or more sections having a resistance exceeding the 15 I acceptable level. This defect is referred to as a "resistive 16 I fault.
lo I In an acceptable interconnection board the resistance 18 , between terminals of a common conductor network is normally in lug I the range of from a few milliohms to a few ohms depending on 20l the length and cross-section of the conductors. The resistance 21 between independent networks should approach infinity, ego, 22 ¦ typically exceed l00 megohms.
23 I The most common technique presently used for testing 24 ' interconnection boards involves making resistance measurements 25 , between each terminal pair of each network of the board to 26 verify the existence of a proper conductive path and, in I addition, resistance measurements between a terminal of each ,, I network and a terminal of all the other networks to insure the 29~ absence of short circuits or unacceptable low resistance paths - 30 between networks. One of the disadvantages of this board , .
I 3~3 I testing concept is that it requires a very large number of 2 individual measurements. For example, a board having 1000 I networks and an average of 3 terminal points per network Al requires 499,500 tests for shorts and additional 2000 tests for Al opens and thus a total of 501,500 tests Sequential 6 measurements using moving probes are impractical with this 7' technique because of the time needed for this large number of Al the test measurements and the complexity of the necessary probe ., ill movement control. Resistive measurements therefore are 10l~ generally made using a special multi contact probe (known as a 11 "bed of nails") providing contacts to each terminal point of I the interconnection board being tested. with parallel contact 13 1 of all of the terminals on the board at the same time, rapid 14 electronic switching can be used to accomplish the individual measurements thereby substantially reducing the time required 16 ¦ for testing an individual board. Such multi contact probes have 17 I to be custom made to match the terminal pattern of the 18 I interconnection board to be tested (e.g. the hole pattern in 19¦1 the case of boards with plated through holes) and, as such, are 20 I relatively time consuming to make and expensive. "Universal"
211l bed of nails multi contact probes are also in use; such probes 22l~ are not only very expensive, but require special adaptation 23 Al tooling for each terminal pattern. Furthermore, with the trend Al toward interconnection board designs with increased terminal 25l point densities, another disadvantage of the "bed of nails 26l concept consists in the high pressure that has to be applied to 27' the multi contact probe fixture in order to achieve adequate I individual contact pressure at each terminal point. For a 29 contact force of only two ounces per contact, for example, a total force of 1250 pounds is required for testing an 1 interconnection board with 10,000 terminals.
I Another interconnection board testing technique which I has been suggested in the past utilizes a movable probe for measuring capacitance between each terminal point and a common S conductor plate. this technique is described in "Continuity 6, Testing by Capacitance" by Robert W. Wed wick, published in Circuits Manufacturing, November AYE, pages 60 and 61 and in I U.S. Patent No. 3,975,680 issued to Larry JO Webb. This type 9 I of measurement, however, does not detect resistive faults in the conductor paths, and, therefore, does not provide complete 11ll test results suitable for assuring electrical integrity of the 12~ interconnection board being tested.
13l An object of the present invention is to provide a method and apparatus capable of completely testing an interconnection board which does not require a "bed of nails"
16 I or similar type multi contact probe 17 Another object of the invention is to provide a method 18 I and apparatus for testing an interconnection board employing 19 ¦ moving probes and sequential measurements and requiring only a 20 I limited number of test measurements.
21 1 Another object of the invention is to provide a method 22¦l and apparatus which can operate on a "self learning" mode to 23 Al' develop criteria for accepting and rejecting boards.
24 , Another object of the invention is to provide an 25 Al apparatus and testing method capable of determining the signal 26 transmission characteristics of the network interconnections.
271 Still another object of the invention is to provide a 28l board testing method and apparatus which not oriole detects 29 faults, but which is also capable of giving the location of faults on the board.
31~ , l .
I Summary of the Invention i, 2 Applicants have found that by using two, or a small ill number, of moving probes, the combination of resistance measurements with radio frequency impedance measurements, e.g., Al capacitance measurements in accordance with the present Al invention, an unexpected and substantial reduction of Al sequential measuring operations or tests is achieved for Al assuring electrical integrity of the interconnection board 4 I tested; the concept of the present invention allows at the same 10l time to test the board completely and for all types or defects 11 described herein before. Furthermore, the concept of this 12¦l invention avoids the necessity of individual test fixtures.
13!l With the invention only two probes need be in contact 14 with terminal points on the board under test any given 15 , time. Thus, the invention provides adequate contact pressure 16 ¦ without exposing the interconnection board to the excessive 17 forces necessary for testing boards with high terminal density 18 when using the bed of nails method.
19¦ In a preferred embodiment of the present invention, 20l each segment of a network is tested for continuity integrity by 21 if a resistance measurement test which detects open faults and 22 resistance faults. A single impedance, e.g. a capacitance 23 it test, it any point in a selected network, taken with respect to 2~1 a common reference plane establishes whether the network is 25jl shorted to any other network. As a result, the number of 26 fill required test operations is greatly reduced.
27~ For the test method of the prior art employing byway, resistance measurement tests and a bed of nails or moving 29l probes the number of tests is given as follows:
, For N = number of networks of the interconnection board;
; P/N = the average number of terminals per network.
The number of tests required to determine whether any ! network is shorted to any other network it:
5 ¦ I No _ N
6 Al ; and, ill the number of tests required to verify continuity 8 I integrity of each network is l (P/N-l)N.
9 I Using the method of the present invention in its 101l preferred embodiment, the number of tests required with respect to possibly existing shorts is only N, namely one impedance, l e.g. capacitance test, per network; and, the number of tests to 13 ', verify continuity within each of the networks is, as before, lo Using the previously mentioned example of an 16 interconnection board having 1000 network with an average of 17 ¦ three terminal points per network, the prior art methods (bed 18 of nails or movable probes for resistance measurements require 19 Lowe - 1000 + (3 - 1)1000 = 499 500 + 2 000 = 501 ~00 201l 2 21¦, tests for testing the board for shorts, opens and resistive 22i faults.
23¦l The method of the present invention in the above 241~ described, preferred embodiment requires only 1 000 tests for 25~l shorts and ~3-1)1000 = 2,000 tests for opens and resistive 26~l faults or a total of 3,00Q tests for completely testing the 27 11 interconnection board of the example. The number of tests is Al thus reduced by a ratio of 160 to 1.
29 Al The system according to this invention can be operated 30 in a " learning mode" by evaluating a sample board or sample I I Us 6 I
it 1 quantities of boards of the kind to be tested to derive 2 information for establishing the parameters for subsequent testing of the same type of board. Moreover, the invention in one of its embodiments provides for the generation of information for giving locations of defects present on a board.
6 according to a preferred embodiment of this invention Al at least two, preferably independently movable probes are I employed which follow a sequence contacting terminal points.
9 The capacitance is measured between the terminals and a Al conductive reference plane either adjacent the interconnection 11' board or forming part of the interconnection hoard. The I measured capacitance is a function of the length and width of 13~ the conductors connected to the terminal and serves to detect 14¦l the open circuit" and "short circuit" defects as previously ¦ defined. A resistance measurement is then made between 16 I terminals within the network to detect any "resistance faults".
17~¦ The correct capacitance values for a good 811 interconnection board without faults are, in general, difficult 19~l to calculate since, in addition to the effect of the conductor 20 11 length, the capacitance value is also affected by fringe 21ll effects, variations in conductor width, and variations in 22 distance between the conductor and the conductive reference 231~ plane. To eliminate the need for such calculations, as 24¦ mentioned before, the system according to the invention may be 25l used in a self learning mode. Capacitance measurements are 26l~ first made on several boards. Measurements falling outside one 27l' mean deviation from the "norm" for a particular terminal are Al eliminated and the "norm" is then recalculated. In this manner I a set of measured values is derived which can be used in further measurements of boards of the same type to detect "open lo of.) I circuits" and "short circuits Al, In a preferred embodiment according to the concept of Al the invention the location of the defects in the board can be I indicated. The resistance measurement of each segment of each 5 l network will indicate the location of each "open" or Eli resistance faulted" segment. In the case of an "open circuit"
defect, use may be made under certain conditions of the 811 capacitive measurements which indicate the length o' conductor lo connected to each terminal. By comparing the measurements of a 10l faulty interconnection board with the correct values for fault 11l free board, the approximate length of the conductor from each terminal to the location of the "open circuit" may be 13~¦ determined and thus, the location of the defect established.
it In the case of a "short circuit" condition, the capacitive measurements can be examined to determine which two 16 ¦ independent networks are in contact with each other and thus 17 I shorted together. Both networks will have abnormally high 18 capacitive measurements if compared to the norm capacitance 19 ¦ values for the respective intact networks and will show about 201l the same value. In accordance with one embodiment, resistance 21 ¦¦ measurements between terminals of the two shorted networks 22 ¦¦ provides sufficient data to determine the conductor distance 231 from each terminal to the point of the short, thus, 24 Al establishing the locus of the defect.
25ll !
26 ! Brief Description of the Drawings:
27 I The foregoing an other objects of the invention will I l' become apparent from the following detailed specification which 29 ! sets forth illustrative embodiments of the invention. The it 1, I drawings form part of this specification wherein:
I Figure l is a schematic block diagram showing the 2 apparatus according to the invention;
I Figures AUDI are flow diagrams illustrating the Al method by which tests are made according to the invention;
511 Figure 3 is a diagram illustrating fault location Eli using resistance measurements; and 7¦1 Figure 4 is an exploded view showing an 8 Al interconnection board with an internal reference plane ill connected for capacitive measurements.
10 If, Al Detailed Description of the Invention 121l Apparatus according to the invention is shown 13~ diagrammatically in Fig. l. A circuit board 10, to be tester lo I is placed on a dielectric layer if which overlies a conductive 15 Al plate 12. The circuit board includes various terminal holes at 16~¦ locations 14 and interconnecting conductors 16. The terminal 17¦¦ points can be in the form of holes with plated walls and lands 18¦ surrounding the holes on the board surface or can be in the lg¦l form of plated pads or other known forms. The terminal points I are interconnected by conductors to form separate conductor 211l nitric 22 I The apparatus of this embodiment includes at least two 23 l independently movable probes 20 and 22, as shown in Fig. l.
24 I Each probe includes a shaped contact portion which can be raised and lowered by conventional apparatus, e.g., pneumatic 26~ or solenoid actuators. When in the lowered position a downward 27 if force is applied to the contact area, such as supplied by a 28 compression spring, to thereby insure good contact. between 29 probe and terminal. The locations of probes 20 and 22 with 30l respect to the board being tested are controlled, respectively, 1 by x-y positioning systems 24 and 26. These positioning 2,' systems ore capable of moving the probes to any desired x-y coordinate so that, when lowered, a probe can contact any desired terminal point on the board.
I The probes are electrically connected sequentially to I a resistance measuring device 30 and a capacitive measuring 7 I device 32. When activated, the resistive measuring device ¦ measures the resistance between probes 20 and 22 and the ill capacitive measurement device, measures the capacitance between 10 l the activated probe(s) and plate 12.
These measured resistance values vary according to the I, l conductor length. For most boards of normal configuration the 13 if resistance of a conductive pathway is bottle a few milliohms 14 I and a few ohms.
15 I The capacitive measurements indicate the capacitance 16 1 between the conductor(s) (if any) connected to the respective 171 terminal arid the conductive plate 12. The measured value is a 18 I function of the total length and width of conductors connected 19 ¦ to the terminal. All terminals connected to the same conductor network will show very nearly the same capacitance value. In 21 I the case of an "open circuit" condition, one or more of the 22~¦ terminals will show a capacitance value below the "norm" for 23l the network thus indicating a conductor connected thereto which 24l is shorter than it should be. "Short circuit" conditions i.e., 25~l a connection between two independent networks, result in 26l abnormally high capacitance values appearing at all terminals 27~ belonging to the shorted networks.
28ll Suitable resistance and capacitance measurement 29l devices may be designed by persons skilled in the art and are available commercially, e.g., from the Hewlett-Packard Company 1 (Model AYE CRY Meter 2 Operation of the apparatus is preferably controlled by Al; a computer 40. The computer supplies the x and y coordinate 4 I positions to positioning systems 24 and 26 to bring the probes 5 l into contact with desired terminal hole pairs. The computer 6 l l also activates measuring instruments 30 and 32 when ill measurements are desired and records the measured values.
ill The computer is suppled with data giving the o' coordinates of all terminal holes on the board and is further supplied with information indicating which groups of the 11 terminal holes connect to specific conductor networks.
ill The computer can be supplied with the specific 13 I sequence of measurements, or, preferably, can develop a 14 I sequence on the basis of the coordinates information.
The board 10 under test is aligned on the board 16 ! support of the tester which includes dielectric layer 11 and 17 ¦¦ plate 12 so that the rows of terminal points, are parallel to 18 1¦ the x and y axes as much as possible. The data base 9 I! controlling probe positioning is presorted to position probe 20 if number 20 to the first terminal point of the first row and then 21~ to each adjacent terminal point.
221 Probe 20 is lowered into contact with the hole, and the capacitance of this terminal point, with respect to 24¦l reference plate 12 is measured and recorded by the computer.
25l Probe 22 is then moved into position over the point 26~l corresponding to an end of the same network. After probe 20 27l has measured the capacitance as described above, probe 22 is 28 lowered into contact. Probe 20 is electrically switched from 2~j the capacitance measuring mode to the resistance (or 3Q conductance measuring mode and the two probes are now used to I
Al determine the end to end resistance of the network or the 2 lo terminal to end resistance if the terminal connected to probe 31 20 is not at the end. This value is also recorded by the 4 I computer.
So` Probe 20 is then switched back to the capacitance 6jl measuring mode and moved into position over the next terminal 71; point of the first row and the process is repeated. This 8 I procedure is followed terminal point by terminal point and line Al by line with probe 20 progressing from the first row to the 101l second, third, etc. and probe 22 positioning itself over network end points. The design of the probes is such as to 1~1 permit simultaneous probing of two adjacent terminal points 13 Al (holes) in the same row, thus, providing for the testing of two it ¦ adjacent terminal points (e.g. plated through holes or pairs) lo I in the same row.
16 I Within the concept of the present invention the probes 17 ¦ may be programmed in a variety of different ways for performing 18 ¦ static and dynamic testing of the interconnection boards. One 19 ¦ of the probes may be programmed to measure capacitance with 20 I respect to the reference plane. Alternatively both probes may 21 I be programmed to measure capacitance thus increasing the 22 I throughput. A common probe may measure capacitance and then be 23 I switched in function to read resistance in cooperation with 24 I another probe, or separate probes can be used for the capacitance and the resistance measurements. Other testing 26 I techniques can also be combined. For example, one probe may be 27l programmed to inject a burst of high voltage, radio frequency 2Bj; energy into a network while other probes monitor the resultant 29l current to thereby test for high stress breakdown. As another example, one probe may be pulsed with a steeply rising waveform I .
i of voltage which is injected into the end point of a network 2 and the same probe can be connected to apparatus which can be used to measure the magnitude of the reflected wave indicating the characteristic impedance of the network.
Capacitive values fur a circuit board may in principle 6 be calculated. The capacitance is principally a function of I the area of the conductor run. It is also affected by other I factors such as the distance between the conductor and the Al conductive plate employed as reference plane, the effect of other conductors in the electrostatic field of the measurement, 11 ' and various fringing effects due to conductor configuration.
I Actual calculation of capacitance values is, therefore, 13j, obviously difficult. Rather than require the operator to I¦ determine the capacitive values for a board without defects, it is preferable to use a self learning approach where the correct 16 value is derived from actual measurements. The method of the 17 I invention can be carried out manually, but is preferably done 181 automatically by a control system which can be either a 191~ dedicated digital control system or a programmed general purpose digital computer 21 I The following section describes the "Learn Mode" in 22~l detail for an interconnection board having terminal holes with 23'l metalized walls to form terminal points.
24 I Figure pa is a flow diagram for acquiring information 25~l in a learning mode called "LEARN I which information is 26 I subsequently used to determine the normal capacitive values for 27l the interconnection board. In step 101 the computer is loaded 28 ! with information indicating the x and y coordinates of all the 29l terminal holes on the board as well as data indicating which terminal points are interconnected in network combinations.
I
Al An interconnection boar is then loaded Leo placed 2 in position above conductive plate 12 forming the reference plane and dielectric 11 fig. AL) in step 102. Thereafter the lo computer supplies the x and y coordinate information to the 5~1 probe positioning apparatus in step 103. In the learning mode Al the system is only required to make capacitive measurements 7j¦ and, hence, only one probe need be used. However, the data can 8 I be acquired more quickly using both probes and, hence, the use ill of two probes is preferable. Once the probes are positioned 10¦¦ the are lowered into contact with the terminal holes or lands 11l and the capacitive measurements are made to determine the "C"
12 ¦ values in step 104. The "C" values are stored in the computer , !
13 ¦ memory in step 105. In decision 106 the computer determines if 14 I it has measured capacitance of the last hole and, if not, the lo I computer returns to step 103 to advance to the next hole pair 16 ¦ and another set of measurements. Operation continues in this 17 I fashion until the last hole has been measured at which point 18 the computer advances from decision 106 to decision 107.
19¦ The computer next determines if it has sufficient data 20!l for determination of the "norm" values. If the same capacitive 21 ¦ value for a particular terminal point appears in measurements 22 ¦ on a number of boards, it can be assumed that this is the 23 correct capacitive value for a board free from defects.
24 I Usually data from 3 to 10 boards is sufficient to determine the 25 Al "norm" values. When sufficient data has been obtained the 26l~ memory disc array is closed in step 108 and the system proceeds I I to determine the "norm" values according to the flow diagram in Bill figure 2b called "LEARN #2".
29l First, as indicated in step 110 of figure 2b, the computer is supplied with additional information indicating the 1 "percent deviation" for the norm value which should be slagged 2 as an error. For most boards a value of 10% deviation from the norm is sufficiently wide to pass all good boards and, at the Al same time, detect and reject all defective boards. For less Al critical applications a 20~ deviation may be appropriate. In 6 some cases the value can be as high as 30%.
Al In processing the data according to the learning mode, 8 ¦ the computer in step 111 calls up from memory all the data for Al a particular terminal hole and then calculates the mean and no' standard deviation for these values in step 112. In step 113 11 values that fall more than one standard deviation either side I of the mean value are discarded and a new mean value is 13 I calculated and stored as the "norm". In decision 116 the 14~ computer determines whether or not the data for all of the 15¦ terminal holes have been evaluated and, if not, the sequence 16 returns to step 111 for evaluation of data on the next terminal 17 hole.
18 Data points which are above and below values permitted 19 within the designated "percent deviation" are flagged by the computer as faults. As previously mentioned the "percent 21lll deviation" value is assigned and not fixed because the 22¦' tolerance should be a function of the type of board being 23 I tested. As an example, discrete wiring boards, using constant 24 Al diameter wire for forming conductors may be assigned tighter US if tolerance than a dense multi layer board with very fine 26 I conductor lines (e.g., five mills wide) and subject to much 27'l larger percentage variations due to the etching or plating 28 process variations.
29 Tables 1 and 2 illustrates the type of data collected 30 ! in the learning mode which may be used in establishing of the 12 'c :;30 if inform values. A simple example of how the learn mode data 2 I might appear for one four-hole network in a sample lot of five boards wherein one of the boards does contain an open circuit ill is shown in Table l. Table 2 shows the data for a simple 5 Al three-hole network containing a board with a suspected short I circuit-I
9..
11 1., 14 :
I
lo I
I
1 TABLE 1 - Data of Nitric I NET HOLE- Bordello BYRD BYRD BYRD BOARDS
2;! ~~-Gil 3 140.1* 39~5 39.9 40.2 40.0
3 ~40.1 39.5 39.9 40.2 40.0 0.7 39.5 39.9 ~0.2 ~0.0 3 440.1 00.5 39.9 40.2 40.0 If Mean = 37.99 SOD. = ~.82 Mean - SOD. = 29.16 Mean SOD. =
6 Al 46.81 7 I The valves rejected from the second mean are: 0.5 8 11¦ Jew Mean = 39096 Al Allowable above new mean, 10~ or 43.95 I % Allowable below new mean, 10% or 35.95 If Readings of Board I Hole I with a reading of 0.5 pi 11' rejected, as suspected OPEN
1 ¦ I
Table 2 - Test of Network I
Readings:
I NET HOLE Bordello BYRD BORDEAUX BYRD BYRD
16 I 1 1 10.1* 10.0 9.9 20.1 10.3 17 1 2 10.1 10.0 9.9 20.1 10.3 1 3 10.1 10.0 9.9 20.1 10.3 18 Mean = 12.08 SOD. = 4.15 Mean - SOD. = 7.~2 Mean +
lug SOD. = 16.23 20 ! The values rejected from the second mean are: 20.1, 1 20.1, 20.1 21 New Mean = 10.075 I I Allowable above new mean, 10~ or 11.08 23 j Allowable below new mean, 10% or 9.08 24 ¦ Readings of 20.1 rejected as suspected SHORTS
25 Jo If I
26l * Readings in picofarads.
I 7_ I Al 11, The values associated with the faults are removed and 2 Al the "norm" is calculated on the basis of the consistent data.
3 ¦ Once the "norm" values have been established the system is then set up to test interconnection boards of the 5 I same type. The test sequence concept is exemplifies in Fig. 2c $1¦ and the sequence for diagnosing the data is described in Fig.
7 1 Ed.
8 To test a board in the sequence called "TEST" in 9 if Figure 2C, the first step, 120, is to load the board into the system i.e., to place the board upon dielectric layer 11 over lilt conductive plate 12. The control computer then moves the 1~¦1 probes to the locations for the first terminal hole pair in I step 121 as described herein before. once the probes are in I position over the terminal holes or lands, the probes are sequentially lowered and the capacitive measurement instrument 16 ¦ 32 is activated to measure the capacitance between the selected 17 ¦ probe and the conductive plate. The system then switches to 18 the resistance mode, the second probe is lowered and resistive 19 measurement instrument 30 is activated to measure the 20¦ resistance between the probes. The capacitive measurements are 21 then compared with the "norm`' values for the respective 22 ¦ terminal holes in step 123. If in decision 124 the computer 23 determines that the readings are within tolerance it goes on to 24 decision 126. If not, an error record is recorded in step 125 25~ recording the out of tolerance "C" readings indicative of a 26l, probable fault.
27~l In decision 126 the computer examines the resistance 28 I reading between the probes and determines whether or not the 29 reading is less than a specified value, for example, less than I 1 ohm. If the resistance reading is higher than the specified 63~3 1 . I
1 value, thus indicating a probable resistive fault, an error 2 message is recorded for the terminal pair in step 127 3 indicating the "R" resistive value actually measured.
6 Al 46.81 7 I The valves rejected from the second mean are: 0.5 8 11¦ Jew Mean = 39096 Al Allowable above new mean, 10~ or 43.95 I % Allowable below new mean, 10% or 35.95 If Readings of Board I Hole I with a reading of 0.5 pi 11' rejected, as suspected OPEN
1 ¦ I
Table 2 - Test of Network I
Readings:
I NET HOLE Bordello BYRD BORDEAUX BYRD BYRD
16 I 1 1 10.1* 10.0 9.9 20.1 10.3 17 1 2 10.1 10.0 9.9 20.1 10.3 1 3 10.1 10.0 9.9 20.1 10.3 18 Mean = 12.08 SOD. = 4.15 Mean - SOD. = 7.~2 Mean +
lug SOD. = 16.23 20 ! The values rejected from the second mean are: 20.1, 1 20.1, 20.1 21 New Mean = 10.075 I I Allowable above new mean, 10~ or 11.08 23 j Allowable below new mean, 10% or 9.08 24 ¦ Readings of 20.1 rejected as suspected SHORTS
25 Jo If I
26l * Readings in picofarads.
I 7_ I Al 11, The values associated with the faults are removed and 2 Al the "norm" is calculated on the basis of the consistent data.
3 ¦ Once the "norm" values have been established the system is then set up to test interconnection boards of the 5 I same type. The test sequence concept is exemplifies in Fig. 2c $1¦ and the sequence for diagnosing the data is described in Fig.
7 1 Ed.
8 To test a board in the sequence called "TEST" in 9 if Figure 2C, the first step, 120, is to load the board into the system i.e., to place the board upon dielectric layer 11 over lilt conductive plate 12. The control computer then moves the 1~¦1 probes to the locations for the first terminal hole pair in I step 121 as described herein before. once the probes are in I position over the terminal holes or lands, the probes are sequentially lowered and the capacitive measurement instrument 16 ¦ 32 is activated to measure the capacitance between the selected 17 ¦ probe and the conductive plate. The system then switches to 18 the resistance mode, the second probe is lowered and resistive 19 measurement instrument 30 is activated to measure the 20¦ resistance between the probes. The capacitive measurements are 21 then compared with the "norm`' values for the respective 22 ¦ terminal holes in step 123. If in decision 124 the computer 23 determines that the readings are within tolerance it goes on to 24 decision 126. If not, an error record is recorded in step 125 25~ recording the out of tolerance "C" readings indicative of a 26l, probable fault.
27~l In decision 126 the computer examines the resistance 28 I reading between the probes and determines whether or not the 29 reading is less than a specified value, for example, less than I 1 ohm. If the resistance reading is higher than the specified 63~3 1 . I
1 value, thus indicating a probable resistive fault, an error 2 message is recorded for the terminal pair in step 127 3 indicating the "R" resistive value actually measured.
4 The computer then proceeds to decision 128 which
5 ; determines if all hole pairs or land pairs have been measured.
6 If not, the computer goes to step 121 arid advances the probes Al to the next hole or land pair in step 121 and takes another set 8 if of readings. Eventually, when all hole or lank pairs have been ill measured the system progresses through step 129 to the next 10 l step as per the flow diagram in Fig. Ed called "DIAGNOSE" which 11' analyzes the data and prints out a record indicating faults.
In one embodiment of the invention the location of the faults 13 if is also indicated.
14 Al In the first step, 130, of the DIAGNOSE routine, the 15 ¦ computer calls up the error reports and recorded values. In 16 I the next step, 131, these reports are examined to reduce the 17 I error file to one report per fault. For example, a single 18 "short circuit" fault normally results in abnormally high 19 capacitive readings at all terminal holes of the particular 201 network in which the "short" occurs. Thus, when the computer 211l notes that all of the capacitive readings of a particular 22l network are above normal, these error messages are reduced to a 23 Al single fault report. Likewise, "open circuit" faults, if they 24~l occur at other than at the ends of a network, normally result 25l in several abnormally few capacitive readings in a network.
26 if These multiple indications can also be reduced to a single 27 fault record. Resistive faults, if other than at the ends of a 28l Norway, are also likely to result in several high resistive 29 readings in the network and, hence, this condition also can be reduced to a single fault record.
1lll Once the error file has been reduced to single fault ill records the computer routine proceeds to analyze each of the I, faults. The first step is to call up the pertinent data for a Al particular fault in step 132. In decisions 133 and 134 the 5 If computer determines the type of fault indicated by the record.
If the data corresponding to the fault includes abnormally high
In one embodiment of the invention the location of the faults 13 if is also indicated.
14 Al In the first step, 130, of the DIAGNOSE routine, the 15 ¦ computer calls up the error reports and recorded values. In 16 I the next step, 131, these reports are examined to reduce the 17 I error file to one report per fault. For example, a single 18 "short circuit" fault normally results in abnormally high 19 capacitive readings at all terminal holes of the particular 201 network in which the "short" occurs. Thus, when the computer 211l notes that all of the capacitive readings of a particular 22l network are above normal, these error messages are reduced to a 23 Al single fault report. Likewise, "open circuit" faults, if they 24~l occur at other than at the ends of a network, normally result 25l in several abnormally few capacitive readings in a network.
26 if These multiple indications can also be reduced to a single 27 fault record. Resistive faults, if other than at the ends of a 28l Norway, are also likely to result in several high resistive 29 readings in the network and, hence, this condition also can be reduced to a single fault record.
1lll Once the error file has been reduced to single fault ill records the computer routine proceeds to analyze each of the I, faults. The first step is to call up the pertinent data for a Al particular fault in step 132. In decisions 133 and 134 the 5 If computer determines the type of fault indicated by the record.
If the data corresponding to the fault includes abnormally high
7 11 capacitive readings the conditions are then analyzed as a
8 I "short circuit" fault (decision 133~. If the fault data Al includes abnormally low capacitive readings the data is I analyzed as an "open" circuit fault and if the capacitive 11l readings are within range the data is analyzed as a resistive Lowe! fault (decision 134).
13 ¦ The "short circuit" faults normally occur between two 14 ¦ networks. Therefore in analyzing a short circuit fault the 15 I computer first looks through the data file to locate other 16 networks which could be involved (step 140). If the computer 17 ¦ is supplied with information indicating where conductors cross 18 in the circuit board pattern, this information could be 19 utilized to determine possible candidates. Another possible approach is to determine where likely conductor crossings occur 21 based on the terminal hole locations of the different 22 networks. A third approach is to simply examine all other 23 networks having "short circuit" fault indications since 24l' generally a "short circuit" fault will involve two networks.
25 11 Once a list of candidates has been prepared by the 26 I computer, the next step, 141, is to determine if there are 27 I matching abnormally high capacitive values recorded in two 28 I different networks. Normally, if there is a "short circuit"
29!l between two conductor networks, all terminal holes in both conductive networks will show the same abnormally high 1¦, capacitive value, since this is the capacitive reading 2 corresponding to the combined conductor length of the two Al! conductive networks.
4 I In many applications identification of the networks Al interconnected by a "short circuit" condition is adequate 6' identification of the fault location since it would enable the Al operator to visually examine the particular networks on 8 Al interconnection board and determine the exact location of the ill fault In such cases, the DIAGNOSE routine would simply advance to step 144, and print out information indicating which 11 l networks appear to be interconnected by the "short" condition.
Al If more exacting fault location information is desired 13 l the DIAGNOSE routine can proceed through steps 142 and 143.
I ¦ First, in step 14~, the computer positions the probes to take 15I additional resistance readings including all terminal pairs 16jl~ within the shorted networks. These resistive readings provide 17 I sufficient data to determine the approximate distance of each 18 I terminal hole to the point of the short circuit as well as the 19 resistance of the short circuit connection between the networks.
20 I Figure 3 is the simplified illustration showing how 21 I resistive measurements can be utilized to determine the 22 ¦ distance from each terminal to the fault as well as the 23 I resistance of the short circuit connection between the 24l networks. In Fig. 3 crossing networks A and CUD are shown shorted together at their crossing point by a resistive 261 connection Rev Resistance Ray is the conductor resistance 27l from the terminal hole A to the point of the short circuit 28l, fault whereas resistance Rub represents the resistive value 29 from terminal B to the point of the fault. Likewise, resistance Arc is the conductor resistance from terminal C to I
l l l 1 the point of the fault and resistance Rod is the conductor 2 resistance from terminal D to the point of the fault.
3 If resistive measurements are made between each 4 terminal pair of the two networks interconnected by the short, S this results in six resistance readings RUB, RACY ROD, RBC, 6 ROD, ROD as indicated by the lines pa) through (f) in Fig. 3.
7, These resistive measurements correspond to the sum of the 8 resistive segments as indicated in Fig. 3. Inasmuch as there lo are six equations for five unknowns, the equations can be solved to derive the resistive values for each segment. prom 11 this information, since the resistance is approximately 12 proportional to the conductor run length, it is possible to 13'' determine the approximate distance from each terminal to the 14~l point of the fault. If the resistive measurements are made in 15l step 142 and analyzed in step 143, the information giving the I I approximate fault location in terms of distance from the 17 I respective terminals is printed out in step 144.
18 Al With shorted networks it may be desirable to make a 19ll further check to determine if an "open circuit" also exists.
20' If all terminal points in the shorted networks show abut the 211~ same abnormally high "C" values it can be assumed there are no 221 'lopes". However, if one or more values are lower than the 23 l rest, this indicates a probable 'lope" in addition to the I if "short" and is reported as such. The location of the "open"
fault can be determined in a routine like that in steps 150-153 '! !
26 described hereinafter.
27 If the fault is of the "open circuit" type, the first 28, step, 150, is to call up all of the capacitance readings for 29 terminal points in the defective network. Terminal points in the network having similar values of capacitance are 63~
it tentatively grouped together US belonging to either of the two 2 ; or more separated "islands" of the broken network as shown in I step 151. If the initial testing sequence does not include the I resistance testing of each wire segment of the networks, this Al operation is performed on the defective network, as in step I ;
Al, 152, to verify which segment(s) of the network are broken.
7 After the broken segments are verified, the clusters of Al connected holes or lands are reported in step 153.
go, Following steps 144 or 153, as the case may be, the 10ll computer determines, in decision 170, whether or not all faults 111 in the error file have been analyzed. If not, the routine goes I to step 132, calls up the next error record, and analyzes the 13'1 data. When all error records have been analyzed the system Lowe I advances to decision 171 and inquires if there is another board 15 I to be tested. If the answer is "yes" then the computer goes to 16 the beginning of the "TEST" sub-routine (step 120 in Fig. 2C) 17 ¦ and displays a cue to the operator indicating that a new board 18 I should be loaded. Otherwise, the computer provides a cue to 19l the operator indicating that the test work is completed.
20~ The operating mode according to the invention wherein 21¦ the probes are programmed to make a capacitive measurement at 22 I each terminal point and a resistance measurement from each 231~ terminal point to a network end point provide a complete test I Al of the board and a complete set of data for fault location.
25l~ Another operating mode within the scope of this invention is to 26 I program the probes to make a resistive measurement from each 27l' terminal point to one of the associated network end points and Al to make at least one capacitive measurement for each network.
29' With this arrangement the capacitive measurements can be used to detect short circuit conditions whereas the resistance if i 1. 3~3 ,, ', i I
lo measurements can detect open circuit conditions and resistance 2 faults. The advantage of this operating mode is a further I reduction in the number of required measurements without I sacrificing completeness of the test. With this operating mode, however, data available for determining fault locations 6 is less complete.
I Still another operating mode within the scope of this Al invention is to measure capacitance at each terminal point and c¦ to measure resistance between the ends of each network. The lo I capacitive measurements can detect the short circuit and open if circuit faults whereas the resistance measurements can detect lo ryes stance faults in the conductor run. This arrangement would 13 If not necessarily detect resistance faults between terminal I ¦ points and the conductor runs unless at the network ends) but 15~ in man types of interconnection boards, particularity those 16¦ made using graphics technology, faults of this type are most 17 unlikely.
18l Common to the various operating modes according to lull this invention are the requirements (l) that at least one 20 if measurement be made from each terminal point (2) that at least 21¦1 one capacitive measurement be made for each network and (3) 22 that the end to end resistance be measured for each network.
23 I The invention has thus far been described in 24 lo connection with testing a single layer board but, obviously, is 25~l equally as applicable to testing multi-layered boards which do 26~ not include interior ground planes or reference planes. The 27l invention is also applicable to testing individual layers prior 28" to lamination into multi-layered boards.
29, The invention is further applicable to interconnection boards including ground and reference planes. A example of ' ill such an interconnection board is illustrated in an exploded view Al' in Fig. 4. The upper layer 200 is the outer component pad ill layer and includes conductive pad areas along the edges for 4 1 ¦ inter system connections and conductive pad areas on the interior regions for connections to components mounted on the board.
Al The next layer 210 includes a high density signal 8 if wiring layer. This interior layer can be produced chemically q or by discrete wiring and includes the conductors for signal 10l connections between components and edge terminal pads. The 11 1 interconnection board may include one or more such interior layers containing the conductors for the signal connections.
13 if The third layer 220 includes power and ground 14 if distribution conductors 222 and 224 which cover most of the 15¦~ surface of the layer. The non conductive areas in layer 220 16 if are used to separate the power areas from the ground areas and 17~¦ to provide vacant land areas so that plated through hole 18¦l connections between upper layers 200 and 210 will not connect 19¦¦ to the ground and power conductors.
20l1 The bottom layer 230 acts as a support plane and can 21 I be made of a variety of known substrate materials which can be 22 lo dielectric or metallic. In high quality boards, for example, 231~ layer 230 could be "TOE matched" (temperature coefficient of 24 Al expansion matched) using a metal alloy such as 42~ nickel - 58 25l~ iron.
. ` , 26l, With interconnection boards of the type illustrated in 27 Fig. 4 it is not possible to make capacitive measurements 28,1 between the signal conductors and an outside reference plane as 29'~l illustrated in Fig. 1 because of conductive layers 220 and/or 230. For testing of such a board the power and ground I
I
i 1, , Al' distribution conductors and metallic substrate layer (if 2 ; present) are all connected together to form the reference plane for the capacitive measurements. Thus, as shown in Fig. 4, one side of the capacitive measuring device 32 is connected to moving probe 20 whereas the other side of the measuring device 6 is connected to power and ground conductors 222 and 224 of 7,, layer 220 as well as layer 230 if it is a metallic substrate.
Gil Although the connections sown in Fig. 4 are made directly to ill the power and ground distribution conductors, in a completed board the connections would more conveniently be made through 11;' the appropriate terminal points connected thereto from the upper layer.
it I While only a few illustrative embodiments have been 14 described in detail it should be apparent to those skilled in the art that there are other variations within the scope of 16 j this invention which is more particularly defined in the 17 ¦ appended claims 20 Al !
24~1 28 . .
291 i I
I
13 ¦ The "short circuit" faults normally occur between two 14 ¦ networks. Therefore in analyzing a short circuit fault the 15 I computer first looks through the data file to locate other 16 networks which could be involved (step 140). If the computer 17 ¦ is supplied with information indicating where conductors cross 18 in the circuit board pattern, this information could be 19 utilized to determine possible candidates. Another possible approach is to determine where likely conductor crossings occur 21 based on the terminal hole locations of the different 22 networks. A third approach is to simply examine all other 23 networks having "short circuit" fault indications since 24l' generally a "short circuit" fault will involve two networks.
25 11 Once a list of candidates has been prepared by the 26 I computer, the next step, 141, is to determine if there are 27 I matching abnormally high capacitive values recorded in two 28 I different networks. Normally, if there is a "short circuit"
29!l between two conductor networks, all terminal holes in both conductive networks will show the same abnormally high 1¦, capacitive value, since this is the capacitive reading 2 corresponding to the combined conductor length of the two Al! conductive networks.
4 I In many applications identification of the networks Al interconnected by a "short circuit" condition is adequate 6' identification of the fault location since it would enable the Al operator to visually examine the particular networks on 8 Al interconnection board and determine the exact location of the ill fault In such cases, the DIAGNOSE routine would simply advance to step 144, and print out information indicating which 11 l networks appear to be interconnected by the "short" condition.
Al If more exacting fault location information is desired 13 l the DIAGNOSE routine can proceed through steps 142 and 143.
I ¦ First, in step 14~, the computer positions the probes to take 15I additional resistance readings including all terminal pairs 16jl~ within the shorted networks. These resistive readings provide 17 I sufficient data to determine the approximate distance of each 18 I terminal hole to the point of the short circuit as well as the 19 resistance of the short circuit connection between the networks.
20 I Figure 3 is the simplified illustration showing how 21 I resistive measurements can be utilized to determine the 22 ¦ distance from each terminal to the fault as well as the 23 I resistance of the short circuit connection between the 24l networks. In Fig. 3 crossing networks A and CUD are shown shorted together at their crossing point by a resistive 261 connection Rev Resistance Ray is the conductor resistance 27l from the terminal hole A to the point of the short circuit 28l, fault whereas resistance Rub represents the resistive value 29 from terminal B to the point of the fault. Likewise, resistance Arc is the conductor resistance from terminal C to I
l l l 1 the point of the fault and resistance Rod is the conductor 2 resistance from terminal D to the point of the fault.
3 If resistive measurements are made between each 4 terminal pair of the two networks interconnected by the short, S this results in six resistance readings RUB, RACY ROD, RBC, 6 ROD, ROD as indicated by the lines pa) through (f) in Fig. 3.
7, These resistive measurements correspond to the sum of the 8 resistive segments as indicated in Fig. 3. Inasmuch as there lo are six equations for five unknowns, the equations can be solved to derive the resistive values for each segment. prom 11 this information, since the resistance is approximately 12 proportional to the conductor run length, it is possible to 13'' determine the approximate distance from each terminal to the 14~l point of the fault. If the resistive measurements are made in 15l step 142 and analyzed in step 143, the information giving the I I approximate fault location in terms of distance from the 17 I respective terminals is printed out in step 144.
18 Al With shorted networks it may be desirable to make a 19ll further check to determine if an "open circuit" also exists.
20' If all terminal points in the shorted networks show abut the 211~ same abnormally high "C" values it can be assumed there are no 221 'lopes". However, if one or more values are lower than the 23 l rest, this indicates a probable 'lope" in addition to the I if "short" and is reported as such. The location of the "open"
fault can be determined in a routine like that in steps 150-153 '! !
26 described hereinafter.
27 If the fault is of the "open circuit" type, the first 28, step, 150, is to call up all of the capacitance readings for 29 terminal points in the defective network. Terminal points in the network having similar values of capacitance are 63~
it tentatively grouped together US belonging to either of the two 2 ; or more separated "islands" of the broken network as shown in I step 151. If the initial testing sequence does not include the I resistance testing of each wire segment of the networks, this Al operation is performed on the defective network, as in step I ;
Al, 152, to verify which segment(s) of the network are broken.
7 After the broken segments are verified, the clusters of Al connected holes or lands are reported in step 153.
go, Following steps 144 or 153, as the case may be, the 10ll computer determines, in decision 170, whether or not all faults 111 in the error file have been analyzed. If not, the routine goes I to step 132, calls up the next error record, and analyzes the 13'1 data. When all error records have been analyzed the system Lowe I advances to decision 171 and inquires if there is another board 15 I to be tested. If the answer is "yes" then the computer goes to 16 the beginning of the "TEST" sub-routine (step 120 in Fig. 2C) 17 ¦ and displays a cue to the operator indicating that a new board 18 I should be loaded. Otherwise, the computer provides a cue to 19l the operator indicating that the test work is completed.
20~ The operating mode according to the invention wherein 21¦ the probes are programmed to make a capacitive measurement at 22 I each terminal point and a resistance measurement from each 231~ terminal point to a network end point provide a complete test I Al of the board and a complete set of data for fault location.
25l~ Another operating mode within the scope of this invention is to 26 I program the probes to make a resistive measurement from each 27l' terminal point to one of the associated network end points and Al to make at least one capacitive measurement for each network.
29' With this arrangement the capacitive measurements can be used to detect short circuit conditions whereas the resistance if i 1. 3~3 ,, ', i I
lo measurements can detect open circuit conditions and resistance 2 faults. The advantage of this operating mode is a further I reduction in the number of required measurements without I sacrificing completeness of the test. With this operating mode, however, data available for determining fault locations 6 is less complete.
I Still another operating mode within the scope of this Al invention is to measure capacitance at each terminal point and c¦ to measure resistance between the ends of each network. The lo I capacitive measurements can detect the short circuit and open if circuit faults whereas the resistance measurements can detect lo ryes stance faults in the conductor run. This arrangement would 13 If not necessarily detect resistance faults between terminal I ¦ points and the conductor runs unless at the network ends) but 15~ in man types of interconnection boards, particularity those 16¦ made using graphics technology, faults of this type are most 17 unlikely.
18l Common to the various operating modes according to lull this invention are the requirements (l) that at least one 20 if measurement be made from each terminal point (2) that at least 21¦1 one capacitive measurement be made for each network and (3) 22 that the end to end resistance be measured for each network.
23 I The invention has thus far been described in 24 lo connection with testing a single layer board but, obviously, is 25~l equally as applicable to testing multi-layered boards which do 26~ not include interior ground planes or reference planes. The 27l invention is also applicable to testing individual layers prior 28" to lamination into multi-layered boards.
29, The invention is further applicable to interconnection boards including ground and reference planes. A example of ' ill such an interconnection board is illustrated in an exploded view Al' in Fig. 4. The upper layer 200 is the outer component pad ill layer and includes conductive pad areas along the edges for 4 1 ¦ inter system connections and conductive pad areas on the interior regions for connections to components mounted on the board.
Al The next layer 210 includes a high density signal 8 if wiring layer. This interior layer can be produced chemically q or by discrete wiring and includes the conductors for signal 10l connections between components and edge terminal pads. The 11 1 interconnection board may include one or more such interior layers containing the conductors for the signal connections.
13 if The third layer 220 includes power and ground 14 if distribution conductors 222 and 224 which cover most of the 15¦~ surface of the layer. The non conductive areas in layer 220 16 if are used to separate the power areas from the ground areas and 17~¦ to provide vacant land areas so that plated through hole 18¦l connections between upper layers 200 and 210 will not connect 19¦¦ to the ground and power conductors.
20l1 The bottom layer 230 acts as a support plane and can 21 I be made of a variety of known substrate materials which can be 22 lo dielectric or metallic. In high quality boards, for example, 231~ layer 230 could be "TOE matched" (temperature coefficient of 24 Al expansion matched) using a metal alloy such as 42~ nickel - 58 25l~ iron.
. ` , 26l, With interconnection boards of the type illustrated in 27 Fig. 4 it is not possible to make capacitive measurements 28,1 between the signal conductors and an outside reference plane as 29'~l illustrated in Fig. 1 because of conductive layers 220 and/or 230. For testing of such a board the power and ground I
I
i 1, , Al' distribution conductors and metallic substrate layer (if 2 ; present) are all connected together to form the reference plane for the capacitive measurements. Thus, as shown in Fig. 4, one side of the capacitive measuring device 32 is connected to moving probe 20 whereas the other side of the measuring device 6 is connected to power and ground conductors 222 and 224 of 7,, layer 220 as well as layer 230 if it is a metallic substrate.
Gil Although the connections sown in Fig. 4 are made directly to ill the power and ground distribution conductors, in a completed board the connections would more conveniently be made through 11;' the appropriate terminal points connected thereto from the upper layer.
it I While only a few illustrative embodiments have been 14 described in detail it should be apparent to those skilled in the art that there are other variations within the scope of 16 j this invention which is more particularly defined in the 17 ¦ appended claims 20 Al !
24~1 28 . .
291 i I
I
Claims (34)
1. A method for testing rigid or flexible electrical interconnection network boards including at least two networks including terminal points and interconnecting conductors, said method comprising the steps of:
establishing an electrically conductive reference means in a predetermined electrical and geometrical position with respect to the surface containing the interconnecting conductors of the networks, and separated therefrom by a dielectric;
making measurements from terminal points of the interconnection board being tested including at least one impedance measurement from a terminal point of each network to said reference means, and at least a measurement of the end-to-end resistance of each network;
with either the impedance or the resistance measurement(s) being made first;
comparing said measured impedance and resistance values with the respective pre-established values for an interconnection board with no electrical faults;
and indicating faults when either (a) said impedance measurement value above said respective established value by more than a predetermined amount; and/or (b) said impedance measurement value is below said respective established value by more than a predetermined amount; and/or (c) said resistance measurement value departs from said respective predetermined value.
establishing an electrically conductive reference means in a predetermined electrical and geometrical position with respect to the surface containing the interconnecting conductors of the networks, and separated therefrom by a dielectric;
making measurements from terminal points of the interconnection board being tested including at least one impedance measurement from a terminal point of each network to said reference means, and at least a measurement of the end-to-end resistance of each network;
with either the impedance or the resistance measurement(s) being made first;
comparing said measured impedance and resistance values with the respective pre-established values for an interconnection board with no electrical faults;
and indicating faults when either (a) said impedance measurement value above said respective established value by more than a predetermined amount; and/or (b) said impedance measurement value is below said respective established value by more than a predetermined amount; and/or (c) said resistance measurement value departs from said respective predetermined value.
2. The method of claim 1, wherein the conductive reference means is a conductive reference plane substantially parallel to the plane of the interconnecting conductors of said networks.
3. The method of claim 1 or 2 including testing each segment of each network for its resistance value and each network for its impedance value.
4. The method of claims 1 or 2 including measuring the capacitive value of each network from each of its terminal points and the resistance value between the end terminal points of said network.
5. The method of claim 1 or 2 including measuring the impedance value of each network from each of its terminal points, and the resistance value from each terminal point to the end point of said network.
6. The method of claim 1 or 2 including measuring the impedance value for each network from one terminal point, and the resistance value from each terminal point to the end point of said network.
7. The method according to claim 1 wherein said pre-established impedance values of a board free of defects are determined by a learning sequence wherein said normal value is the mean of measured values on a plurality of interconnection boards of the respective kind which are within one standard deviation of each other.
8. The method of claim 7 wherein said normal values of impedance are obtained by:
obtaining a data set of impedance values for a terminal point on a sample lot of interconnection boards; and calculating the mean value and standard deviation for the initial data set for the terminal point; and discarding the values lying outside the standard deviation range; and then calculating said pre-established value as equal to the mean value of the remaining measurements.
obtaining a data set of impedance values for a terminal point on a sample lot of interconnection boards; and calculating the mean value and standard deviation for the initial data set for the terminal point; and discarding the values lying outside the standard deviation range; and then calculating said pre-established value as equal to the mean value of the remaining measurements.
9. The method of claim 1 wherein said impendance measurement is a capacitance measurement.
10. Apparatus for testing rigid or flexible electrical interconnection network boards including at least two networks and a plurality of terminal points interconnected by electrical conductors to form a predetermined pattern, comprising at least two independently movable probes for contacting selective terminal points of the said interconnection board being tested;
positioning means associated with at least one of said probes for positioning the same to contact selected terminal points on the interconnection board;
conductive reference means spaced from said conductor network of the interconnection board by a dielectric;
impedance measuring means connected to at least one of said probes to measure impedance between the probe connected thereto and said reference means;
resistance measuring means connected to said probes to measure electrical resistance between said probes; and control means for moving said probes and for activating said measuring means to obtain:
(a) at least one impedance measurement from a terminal point of each network to said reference means; an (b) at least a measurement of the end-to-end resistance of each network.
positioning means associated with at least one of said probes for positioning the same to contact selected terminal points on the interconnection board;
conductive reference means spaced from said conductor network of the interconnection board by a dielectric;
impedance measuring means connected to at least one of said probes to measure impedance between the probe connected thereto and said reference means;
resistance measuring means connected to said probes to measure electrical resistance between said probes; and control means for moving said probes and for activating said measuring means to obtain:
(a) at least one impedance measurement from a terminal point of each network to said reference means; an (b) at least a measurement of the end-to-end resistance of each network.
11. The apparatus of claim 10 wherein said electrically conductive reference means is a conductive plane arranged substantially parallel to the plane of the interconnect-ing conductors of the networks of the said interconnection board.
12. The apparatus of claim 10 or 11 wherein said conductive reference means is a means separate from the interconnection board to be tested.
13. The apparatus of claim 10 or 11 wherein said conductive reference means is an interior conductive means located within the interconnection board being tested.
14. The apparatus of claim 11 wherein said control means for moving said probes and for activating said measuring means is operable to obtain at least one impedance measurement for each terminal point of the interconnection board being tested.
15. The apparatus according to claim 11 wherein said control means for moving said measuring probes is operable to obtain at least one resistance measurement from each terminal point of the interconnection board being tested.
16. The apparatus of claim 11 wherein the impedance measuring means are capacitance measuring means.
17. A method of testing interconnection boards including at least two networks including terminal points and interconnecting conductors comprising the steps of:
establishing a conductive reference means in a predetermined electrical and geometrical position with respect to the surface containing the interconnecting conductors of the networks, and separated therefrom by a dielectric;
making at least one impedance measurement from a terminal point of each network and to said reference means for a plurality of interconnection boards in a sample lot;
determining the mean impedance value for each measured terminal point;
discarding measured impedance values which deviate from said average impedance values by more than a predetermined amount and determining the average impedance values for the remaining measurements to derive a respective reference value;
similarly measuring impedance values for other like inter-connection boards and rejecting as circuit faults any measurements higher than said reference valve by more than a predetermined amount, and rejecting as circuit faults any measurements lower than said respective reference value by more than a predetermined amount.
establishing a conductive reference means in a predetermined electrical and geometrical position with respect to the surface containing the interconnecting conductors of the networks, and separated therefrom by a dielectric;
making at least one impedance measurement from a terminal point of each network and to said reference means for a plurality of interconnection boards in a sample lot;
determining the mean impedance value for each measured terminal point;
discarding measured impedance values which deviate from said average impedance values by more than a predetermined amount and determining the average impedance values for the remaining measurements to derive a respective reference value;
similarly measuring impedance values for other like inter-connection boards and rejecting as circuit faults any measurements higher than said reference valve by more than a predetermined amount, and rejecting as circuit faults any measurements lower than said respective reference value by more than a predetermined amount.
18. The method according to claim 17 wherein measured impedance values are discarded which deviate by more than one standard deviation from said mean values.
19. The method according to claim 17 wherein the said impedance value is a capacitance value and measured between each terminal point and said reference means.
20. The method according to claim 19 wherein at least one capacitive measurement is made from a terminal point of each network of the interconnection board being tested.
21. The method according to claim 17 wherein said conductive reference means is an internal conductive layer of the interconnection board being tested.
22. The method according to claim 17 wherein said conductive reference means is a conductive plane exterior to the interconnection board being tested.
23. A method for testing interconnection boards including terminal points and interconnecting conductor networks and for indicating locations of faults therein comprising the steps of:
establishing a conductive reference plane parallel to the plane of the terminal points and interconnecting conductor networks, and separated therefrom by a dielectric;
measuring the capacitance between a particular terminal point and said reference plane;
comparing said measured capacitance value with the known correct value for an interconnection board with no faults present;
indicating an open circuit fault if said measured capacitance value is less than said known correct value by a predetermined amount; and determining the fault location for any such open circuit fault relative to said measuring point in accordance with the magnitude of deviation from said known correct value.
establishing a conductive reference plane parallel to the plane of the terminal points and interconnecting conductor networks, and separated therefrom by a dielectric;
measuring the capacitance between a particular terminal point and said reference plane;
comparing said measured capacitance value with the known correct value for an interconnection board with no faults present;
indicating an open circuit fault if said measured capacitance value is less than said known correct value by a predetermined amount; and determining the fault location for any such open circuit fault relative to said measuring point in accordance with the magnitude of deviation from said known correct value.
24. The method according to claim 23 wherein said known correct value is determined by making similar measurements on a sample plurality of like interconnection boards, determining the mean and standard deviation of said measurements, discarding measured values more than one standard deviation from said mean and determining the average value of the remaining measurements as said known correct value.
25. The method according to claim 23 further including at least one capacitive measurement from a terminal point of each network of the interconnection board being tested.
26. The method according to claim 25 further including a capacitive measurement at each terminal point of the interconnection board being tested.
27. The method according to claim 23 wherein said conductive reference plane is an interior conductive layer of the interconnection board being tested.
28. The method according to claim 23 where said conductive reference plane is a conductive plate outside the interconnection board being tested.
29. A method for testing interconnection boards including terminal points and interconnecting conductor networks and for indicating locations of faults therein comprising the steps of:
establishing a conductive reference plane parallel to the plane of the terminal points and interconnecting conductor networks and separated therefrom by a dielectric;
measuring the capacitance between at least one terminal point of each network and said reference plane;
comparing said measured capacitance value with the known correct value for interconnection boards with no faults therein indicating as a short circuit fault for any measured capacitance which is higher than the respective known correct value by more than a predetermined amount; and indicating as shorted together any networks showing similar high values.
establishing a conductive reference plane parallel to the plane of the terminal points and interconnecting conductor networks and separated therefrom by a dielectric;
measuring the capacitance between at least one terminal point of each network and said reference plane;
comparing said measured capacitance value with the known correct value for interconnection boards with no faults therein indicating as a short circuit fault for any measured capacitance which is higher than the respective known correct value by more than a predetermined amount; and indicating as shorted together any networks showing similar high values.
30. The method according to claim 29 wherein said known correct value is determined by making similar measurements on a sample plurality of like interconnection boards, determining the mean and standard deviation of said measurements, discarding measured values more than one standard deviation from said mean and determining the average value of the remaining measurements as said known correct value.
31. The method according to claim 29 further including at least one capacitive measurement from a terminal point of each network of the interconnection board being tested.
32, The method according to claim 31 further including a capacitive measurement at each terminal point of the interconnection board being tested.
33. The method according to claim 29 wherein said conductive reference plane is an interior conductive layer of the interconnection board being tested.
34. The method according to claim 29 where said conductive reference plane is a conductive plate outside the interconnection board being tested.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/473,590 US4565966A (en) | 1983-03-07 | 1983-03-07 | Method and apparatus for testing of electrical interconnection networks |
| US473,590 | 1990-02-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1216630A true CA1216630A (en) | 1987-01-13 |
Family
ID=23880189
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000449003A Expired CA1216630A (en) | 1983-03-07 | 1984-03-07 | Method and apparatus for testing of electrical interconnection networks |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4565966A (en) |
| EP (1) | EP0123828B1 (en) |
| JP (1) | JPS59168375A (en) |
| CA (1) | CA1216630A (en) |
| CH (1) | CH664020A5 (en) |
| DE (1) | DE3408704A1 (en) |
| GB (1) | GB2136138B (en) |
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-
1983
- 1983-03-07 US US06/473,590 patent/US4565966A/en not_active Expired - Lifetime
-
1984
- 1984-02-20 GB GB08404416A patent/GB2136138B/en not_active Expired
- 1984-03-02 EP EP84102217A patent/EP0123828B1/en not_active Expired
- 1984-03-07 CA CA000449003A patent/CA1216630A/en not_active Expired
- 1984-03-07 DE DE19843408704 patent/DE3408704A1/en active Granted
- 1984-03-07 JP JP59044808A patent/JPS59168375A/en active Granted
- 1984-03-07 CH CH1140/84A patent/CH664020A5/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| EP0123828A1 (en) | 1984-11-07 |
| US4565966A (en) | 1986-01-21 |
| EP0123828B1 (en) | 1987-09-16 |
| CH664020A5 (en) | 1988-01-29 |
| GB8404416D0 (en) | 1984-03-28 |
| DE3408704C2 (en) | 1987-04-30 |
| DE3408704A1 (en) | 1984-09-13 |
| GB2136138A (en) | 1984-09-12 |
| GB2136138B (en) | 1987-04-23 |
| JPH0417394B2 (en) | 1992-03-25 |
| JPS59168375A (en) | 1984-09-22 |
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