CA1226623A - Powered conservation system in battery powered keyboard device including a microprocessor - Google Patents
Powered conservation system in battery powered keyboard device including a microprocessorInfo
- Publication number
- CA1226623A CA1226623A CA000458355A CA458355A CA1226623A CA 1226623 A CA1226623 A CA 1226623A CA 000458355 A CA000458355 A CA 000458355A CA 458355 A CA458355 A CA 458355A CA 1226623 A CA1226623 A CA 1226623A
- Authority
- CA
- Canada
- Prior art keywords
- microprocessor
- input
- output
- coupled
- keyboard
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000000994 depressogenic effect Effects 0.000 claims description 9
- 239000011159 matrix material Substances 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/02—Input arrangements using manually operated switches, e.g. using keyboards or dials
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
- G06F1/3215—Monitoring of peripheral devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/02—Input arrangements using manually operated switches, e.g. using keyboards or dials
- G06F3/023—Arrangements for converting discrete items of information into a coded form, e.g. arrangements for interpreting keyboard generated codes as alphanumeric codes, operand codes or instruction codes
- G06F3/0231—Cordless keyboards
Abstract
POWER CONSERVATION SYSTEM IN BATTERY
.
POWERED KEYBOARD DEVICE INCLUDING MICROPROCESSOR
Abstract In a self-contained battery powered keyboard entry device, the keyboard is driven from a microprocessor and its output sensed by the microprocessor to generate drive signals for an infra-red transmitter. The sense lines are monitored so that, on a key depression, the microprocessor is switched to an operating mode from its low-power standby mode. When all sensed signals have been processed and outputted, the microprocessor is returned to the low-power standby mode.
.
POWERED KEYBOARD DEVICE INCLUDING MICROPROCESSOR
Abstract In a self-contained battery powered keyboard entry device, the keyboard is driven from a microprocessor and its output sensed by the microprocessor to generate drive signals for an infra-red transmitter. The sense lines are monitored so that, on a key depression, the microprocessor is switched to an operating mode from its low-power standby mode. When all sensed signals have been processed and outputted, the microprocessor is returned to the low-power standby mode.
Description
6~3 POWERED CONSERVATION SYSTEM IN
BATTERY POWERED KEYBOARD DEVICE
INCI,UDIN~ A MICROPROCESSOR
Description Technical Field .
10 The present invention relates to a power conservation system in a self contained battery powered keyboard device including a microprocessor.
Background Art Currently known battery powered key entry devices may be classified into two general groups.
The first group comprises calculators, extending from the simplest four function type through to the considerably more powerful programmable calculators as exemplified by the 600 and 700 series of calculators produced by Casino Corporation. All of these devices are not normally used continuously for any great length of time. The usual operational method is to switch the device on, perform one or more calculations, and then switch off. With such operations, and depending on the form of display employed, the batteries in calculators last from several months to years. In order to conserve the batteries in the event that a calculator is left on after operation, many such devices employ an arrangement in which, some minutes after a key operation, the microprocessor is switched to a standby mode, and the display is switched off.
Thereafter, the microprocessor and display are powered -' up by depression of a particular key, normally the CLEAR key.
The second group comprises remote control devices, for example television remote control units. In operation, these consume much more power than the average calculator as they employ some form of transmission device, such as an infrared generator.
Such control devices are normally used relatively infrequently and for short periods. Typically, a television remote control unit may generate a sequence of up to about ten control pulses during each of up to ten to twenty times a day. Between operations, these units are switched off completely. Consequently, battery drain offers no significant problem.
If, however, it is required to provide a remote self-contained, battery powered keyboard entry device for, for example, a microcomputer, battery life becomes a significant problem. Such a device may be in substantially continuous use throughout each day of a working week. With such operational conditions, without some form of battery conservation system, battery life may prove insufficient to ensure reliable operation without frequent battery changes.
It is, therefore, an object of the present invention to provide a power conservation system in such a keyboard entry device.
Disclosure of the Invention . . .
The present invention relates to a battery powered keyboard entry device in which a microprocessor of `f~3 processes key entry signals to produce coded output signals to drive an infrared light emitting device.
When the microprocessor has processed the received key entry signals, it is set into its low power standby mode and is not powered up until the next keystroke is detected. Accordingly, battery power is conserved as the microprocessor is for the majority of the time in its low power standby mode.
Brief Desert Figure 1 shows the circuit of a battery powered keyboard entry device.
Figure 2 is a timing diagram of keyboard drive and sense signals.
Best Mode for Carrying Out the Invention In Figure 1, a keyboard entry device includes a microprocessor 1 coupled to a matrix keyboard 2.
Microprocessor 1 may be the 80C48 microprocessor produced by Nippon Electric Company. For simplicity, only the inputs and outputs particularly relevant to the present invention have been shown. These are, the input data port lines, comprising 8 inputs DUO through DB7, the first output port lines, again 8 lines, P10 through P17, the address latch enable output ALE, which provides an output once during each processor cycle and is, therefore useful as a clock output, two lines P25 and P27 of the second output port, a NOT RESET input, and the low power standby input ODD.
The first output port lines P10 through Ply are ~Z~'6~ 3 coupled through eight inverting amplifiers 11-12 and eight diodes 13-14 to drive the matrix keyboard 2.
Eight sense lines from the keyboard 2 are fed back to the data input port DUO through DB7 of microprocessor l. Each matrix drive line is coupled through an associated one of eight resistors 15-16 to battery positive, and each matrix sense line is similarly coupled to the battery positive through an associated lo one of eight resistors 17-18.
Keyboard 2 is of the matrix contact type, in which depression of a key connects the single drive and sense lines which cross at the key position. Suitable keyboard technologies for the present system include the full travel contact membrane system or a carbon contact/rubber dome system.
Figure 2 shows the signals on the keyboard drive and sense lines in a typical operation of the Figure 1 system. As an example, let us look at the signals on the drive line from P10 and the resulting sense signals applied to DUO. With none of the eight keys coupled to the sense line depressed, this sense line is held high through resistor 17, as substantially no current flows through the resistor into the sense line. Similarly when none of the keys coupled to the P10 drive line is depressed, the input to inverting amplifiers 11 is high, its output is, therefore, low, but no current flows through diode 13 as the drive line is not connected within matrix 2. When the key coupling these lines is depressed, current flows through resistor 17, the associated keyboard contacts, and then through diode 13, as the output of amplifiers 11 is still low.
Thus, the voltage level on the DUO sense line is ~26~i23 lowered. Subsequently, when microprocessor 1 emits a drive pulse on P10, resistor 15 conducts, lowering the input to amplifier 11. The output of this amplifier is thereby raised, cutting off current through diode 13, so, for the period of the P10 pulse, -the DUO line goes high. In a scan cycle the P10 pulse is followed in turn by the Pit through P17 pulses to drive each of the drive lines, and outputs are provided on each sense lo line corresponding to a depressed key. Figure 2 shows the timing of the arrangement. Lines Al and K3 show the depression time of two keys corresponding respectively to drive P10/sense DUO and drive P12/sense DB2. Line K2 shows the depression time of a single key, which is depressed subsequent to the above -mentioned pair, and corresponds to drive Pleasance DBl.
To give some idea of the actual times involved, each key depression time shown may occupy 60 m seas, of which the useful time is the central 30 m seas, the hatched areas indicating times of possible contact bounce or noise. As shown, the drive pulses at P10 through Ply take a total period of 16 m seas. The arrows indicate that for the Al and K3 key depressions appropriate sense signals appears on the DUO and DB2 sense lines and for the K2 key-depression, on the DBl sense line.
In Figure 2, it is assumed that prior to any of the key depressions shown, microprocessor l is in its low power standby condition, and therefore no signals are generated on the Pro through Ply lines. Upon depression of a key, the P10 through Ply signals are initiated after a delay D. This is shown in Figure 2 as a delay of 15 m seas, but it may be of any length sufficient to allow the first cycle of the drive I ;Z3 signals (15 m seas. in Figure 2) to take placed within the 30 m seas. sense time for the first key depression.
This delay is to permit the microprocessor to power up from its low power standby condition.
Referring back to the details of Figure 1, an 8 input NOR gate 3 has each of its inputs coupled to an associated one of the DUO through DB7 sense lines.
With no key depressed, all of these lines are high, so the output on line 19 is low. Line 19 is coupled as a set input to a latch circuit comprising three RAND
gates 4, 5 and 6, which is reset by a signal on line 20 which will be described later. Assuming, for the present, that the latch circuit has been reset, the signal on line 19 sets it to raise output line 21 from a '0' condition to a '1' condition.
This '1' condition on line 21 is applied directly ; 20 to the S input of a D flip-flop 9, and after inversion by inventor 22, as a '0' input to a single shot 7 and the R input of a D flip-flop 8. Immediately prior to this time, flip flop 9 had no input to its clock line, the S input was '0', the D input was '0' and the R
input was '0', so the Q output was '0'. This Q output is applied, as shown, to the ODD input of microprocessor 1 and when in a '0' state, sets the microprocessor into its low power standby mode. Now, when the S input from line 21 changes to '1', flip-flop 9 switches to provide a '1' output at Q, thereby releasing the microprocessor from the standby mode. As mentioned above, the '0' input from inventor 22 is, at the same time, applied to a 16 m sec. single shot delay circuit 7 and to the R input of flip-flop 8. As can be seen, the D input of this flip-flop is always '1' and ~2;~66~3 the S input is always '0'. Prior to arrival of the '1' signal from inventor 22, the R input is '1' so the Q
output is '0' thereby placing microcomputer iII a reset state. The '0' signal from inventor 22 to the R input of flip flop 8 does not alter the Q output, but sets the flip flop in its synchronous mode to respond to a signal at the clock input. This clock input arrives 16 m. seas later from delay circuit 7 as a rising edge lo which sets flip-flop 8 to provide a '1' output. This takes microprocessor 1 out of its reset condition. It is noted that this output is also applied to the D
input of flip-flop 9, but at this time this flip-flop is operating in the asynchronous mode So so the D
input signal has no effect on the Q output.
Thus, what has happened so far is that a key has been depressed, flip-flop 9 has switched microprocessor 1 from its standby to its operating mode and, after a 16 m sec. delay, flip-flop 8 has removed reset from the microprocessor. The microprocessor now responds to keystroke inputs at inputs DUO through DB7, converts this data to a form suitable for transmission, and after buffering in an internal transmit buffer, sends the data in serial fashion to a line 23 from output P25 of the second output port. Line 23 is connected to a driver amplifier 10 which drives a light-emitting diode 24 to provide infrared pulses for transmission to a receiver device.
The microprocessor continuously monitors the content of the transmit buffer, and when it empties, generates a signal on output P27 of the second output port. This signal is applied to RAND gate 6 to switch the latch including this RAND gate and thereby return l~Z~iZ3 line 21 from the 'l' state back to the '0' state. This is transmitted through inverting amplifier 22 to the R
input of flip-flop 8 as a '1' signal. This resets this flip-flop to provide a '0' output to the NOT RESET
input of the microprocessor, thereby setting it into its reset state. This '0' output is also applied to the D input of flip-flop 9, setting it into the synchronous mode. In this mode, the next rising edge of a clock pulse from the microprocessor ALE output switches the flip flop to provide a '0' output. This is applied to the ODD input of the microprocessor which then reverts to its low power standby mode.
Thus, what has been described above is a keyboard entry device using battery power. The battery life is extended by placing the microprocessor in a standby, low power condition immediately it has processed and passed on the received keystroke data. In all but a very few exceptional cases, this condition is entered between each keystroke.
If we take an example of a system operating at 10000 keystrokes per eight hour day, with the electronics taking 0.1 sec. to process each keystroke and then power down to the standby condition, then the electronics are dynamic for 16.67 minutes, or 3.5~ of the day and at standby for the remaining 96.5% of the day. With a 6 m A dynamic current and a 1.5 A
standby current, this gives a battery drain of (1.5/106 x 96.5/100 x 8 + 6/103 x 3.5/100 x 8) x 103 = 1.6916 m A - hr. per day. This compares dramatically with the worst case in which the electronics remain in the dynamic state continuously. In this case the battery drain would be (6/103 x 8) x 103 = 48 m A - ho per day.
~2Z~623 With the prior art arrangements in which the standby condition is entered minutes after the last keystroke, it is quite probably that this worst case situation would be the normal situation with, possibly, standby entered only once or twice a day.
While the invention has been particularly described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention.
35m
BATTERY POWERED KEYBOARD DEVICE
INCI,UDIN~ A MICROPROCESSOR
Description Technical Field .
10 The present invention relates to a power conservation system in a self contained battery powered keyboard device including a microprocessor.
Background Art Currently known battery powered key entry devices may be classified into two general groups.
The first group comprises calculators, extending from the simplest four function type through to the considerably more powerful programmable calculators as exemplified by the 600 and 700 series of calculators produced by Casino Corporation. All of these devices are not normally used continuously for any great length of time. The usual operational method is to switch the device on, perform one or more calculations, and then switch off. With such operations, and depending on the form of display employed, the batteries in calculators last from several months to years. In order to conserve the batteries in the event that a calculator is left on after operation, many such devices employ an arrangement in which, some minutes after a key operation, the microprocessor is switched to a standby mode, and the display is switched off.
Thereafter, the microprocessor and display are powered -' up by depression of a particular key, normally the CLEAR key.
The second group comprises remote control devices, for example television remote control units. In operation, these consume much more power than the average calculator as they employ some form of transmission device, such as an infrared generator.
Such control devices are normally used relatively infrequently and for short periods. Typically, a television remote control unit may generate a sequence of up to about ten control pulses during each of up to ten to twenty times a day. Between operations, these units are switched off completely. Consequently, battery drain offers no significant problem.
If, however, it is required to provide a remote self-contained, battery powered keyboard entry device for, for example, a microcomputer, battery life becomes a significant problem. Such a device may be in substantially continuous use throughout each day of a working week. With such operational conditions, without some form of battery conservation system, battery life may prove insufficient to ensure reliable operation without frequent battery changes.
It is, therefore, an object of the present invention to provide a power conservation system in such a keyboard entry device.
Disclosure of the Invention . . .
The present invention relates to a battery powered keyboard entry device in which a microprocessor of `f~3 processes key entry signals to produce coded output signals to drive an infrared light emitting device.
When the microprocessor has processed the received key entry signals, it is set into its low power standby mode and is not powered up until the next keystroke is detected. Accordingly, battery power is conserved as the microprocessor is for the majority of the time in its low power standby mode.
Brief Desert Figure 1 shows the circuit of a battery powered keyboard entry device.
Figure 2 is a timing diagram of keyboard drive and sense signals.
Best Mode for Carrying Out the Invention In Figure 1, a keyboard entry device includes a microprocessor 1 coupled to a matrix keyboard 2.
Microprocessor 1 may be the 80C48 microprocessor produced by Nippon Electric Company. For simplicity, only the inputs and outputs particularly relevant to the present invention have been shown. These are, the input data port lines, comprising 8 inputs DUO through DB7, the first output port lines, again 8 lines, P10 through P17, the address latch enable output ALE, which provides an output once during each processor cycle and is, therefore useful as a clock output, two lines P25 and P27 of the second output port, a NOT RESET input, and the low power standby input ODD.
The first output port lines P10 through Ply are ~Z~'6~ 3 coupled through eight inverting amplifiers 11-12 and eight diodes 13-14 to drive the matrix keyboard 2.
Eight sense lines from the keyboard 2 are fed back to the data input port DUO through DB7 of microprocessor l. Each matrix drive line is coupled through an associated one of eight resistors 15-16 to battery positive, and each matrix sense line is similarly coupled to the battery positive through an associated lo one of eight resistors 17-18.
Keyboard 2 is of the matrix contact type, in which depression of a key connects the single drive and sense lines which cross at the key position. Suitable keyboard technologies for the present system include the full travel contact membrane system or a carbon contact/rubber dome system.
Figure 2 shows the signals on the keyboard drive and sense lines in a typical operation of the Figure 1 system. As an example, let us look at the signals on the drive line from P10 and the resulting sense signals applied to DUO. With none of the eight keys coupled to the sense line depressed, this sense line is held high through resistor 17, as substantially no current flows through the resistor into the sense line. Similarly when none of the keys coupled to the P10 drive line is depressed, the input to inverting amplifiers 11 is high, its output is, therefore, low, but no current flows through diode 13 as the drive line is not connected within matrix 2. When the key coupling these lines is depressed, current flows through resistor 17, the associated keyboard contacts, and then through diode 13, as the output of amplifiers 11 is still low.
Thus, the voltage level on the DUO sense line is ~26~i23 lowered. Subsequently, when microprocessor 1 emits a drive pulse on P10, resistor 15 conducts, lowering the input to amplifier 11. The output of this amplifier is thereby raised, cutting off current through diode 13, so, for the period of the P10 pulse, -the DUO line goes high. In a scan cycle the P10 pulse is followed in turn by the Pit through P17 pulses to drive each of the drive lines, and outputs are provided on each sense lo line corresponding to a depressed key. Figure 2 shows the timing of the arrangement. Lines Al and K3 show the depression time of two keys corresponding respectively to drive P10/sense DUO and drive P12/sense DB2. Line K2 shows the depression time of a single key, which is depressed subsequent to the above -mentioned pair, and corresponds to drive Pleasance DBl.
To give some idea of the actual times involved, each key depression time shown may occupy 60 m seas, of which the useful time is the central 30 m seas, the hatched areas indicating times of possible contact bounce or noise. As shown, the drive pulses at P10 through Ply take a total period of 16 m seas. The arrows indicate that for the Al and K3 key depressions appropriate sense signals appears on the DUO and DB2 sense lines and for the K2 key-depression, on the DBl sense line.
In Figure 2, it is assumed that prior to any of the key depressions shown, microprocessor l is in its low power standby condition, and therefore no signals are generated on the Pro through Ply lines. Upon depression of a key, the P10 through Ply signals are initiated after a delay D. This is shown in Figure 2 as a delay of 15 m seas, but it may be of any length sufficient to allow the first cycle of the drive I ;Z3 signals (15 m seas. in Figure 2) to take placed within the 30 m seas. sense time for the first key depression.
This delay is to permit the microprocessor to power up from its low power standby condition.
Referring back to the details of Figure 1, an 8 input NOR gate 3 has each of its inputs coupled to an associated one of the DUO through DB7 sense lines.
With no key depressed, all of these lines are high, so the output on line 19 is low. Line 19 is coupled as a set input to a latch circuit comprising three RAND
gates 4, 5 and 6, which is reset by a signal on line 20 which will be described later. Assuming, for the present, that the latch circuit has been reset, the signal on line 19 sets it to raise output line 21 from a '0' condition to a '1' condition.
This '1' condition on line 21 is applied directly ; 20 to the S input of a D flip-flop 9, and after inversion by inventor 22, as a '0' input to a single shot 7 and the R input of a D flip-flop 8. Immediately prior to this time, flip flop 9 had no input to its clock line, the S input was '0', the D input was '0' and the R
input was '0', so the Q output was '0'. This Q output is applied, as shown, to the ODD input of microprocessor 1 and when in a '0' state, sets the microprocessor into its low power standby mode. Now, when the S input from line 21 changes to '1', flip-flop 9 switches to provide a '1' output at Q, thereby releasing the microprocessor from the standby mode. As mentioned above, the '0' input from inventor 22 is, at the same time, applied to a 16 m sec. single shot delay circuit 7 and to the R input of flip-flop 8. As can be seen, the D input of this flip-flop is always '1' and ~2;~66~3 the S input is always '0'. Prior to arrival of the '1' signal from inventor 22, the R input is '1' so the Q
output is '0' thereby placing microcomputer iII a reset state. The '0' signal from inventor 22 to the R input of flip flop 8 does not alter the Q output, but sets the flip flop in its synchronous mode to respond to a signal at the clock input. This clock input arrives 16 m. seas later from delay circuit 7 as a rising edge lo which sets flip-flop 8 to provide a '1' output. This takes microprocessor 1 out of its reset condition. It is noted that this output is also applied to the D
input of flip-flop 9, but at this time this flip-flop is operating in the asynchronous mode So so the D
input signal has no effect on the Q output.
Thus, what has happened so far is that a key has been depressed, flip-flop 9 has switched microprocessor 1 from its standby to its operating mode and, after a 16 m sec. delay, flip-flop 8 has removed reset from the microprocessor. The microprocessor now responds to keystroke inputs at inputs DUO through DB7, converts this data to a form suitable for transmission, and after buffering in an internal transmit buffer, sends the data in serial fashion to a line 23 from output P25 of the second output port. Line 23 is connected to a driver amplifier 10 which drives a light-emitting diode 24 to provide infrared pulses for transmission to a receiver device.
The microprocessor continuously monitors the content of the transmit buffer, and when it empties, generates a signal on output P27 of the second output port. This signal is applied to RAND gate 6 to switch the latch including this RAND gate and thereby return l~Z~iZ3 line 21 from the 'l' state back to the '0' state. This is transmitted through inverting amplifier 22 to the R
input of flip-flop 8 as a '1' signal. This resets this flip-flop to provide a '0' output to the NOT RESET
input of the microprocessor, thereby setting it into its reset state. This '0' output is also applied to the D input of flip-flop 9, setting it into the synchronous mode. In this mode, the next rising edge of a clock pulse from the microprocessor ALE output switches the flip flop to provide a '0' output. This is applied to the ODD input of the microprocessor which then reverts to its low power standby mode.
Thus, what has been described above is a keyboard entry device using battery power. The battery life is extended by placing the microprocessor in a standby, low power condition immediately it has processed and passed on the received keystroke data. In all but a very few exceptional cases, this condition is entered between each keystroke.
If we take an example of a system operating at 10000 keystrokes per eight hour day, with the electronics taking 0.1 sec. to process each keystroke and then power down to the standby condition, then the electronics are dynamic for 16.67 minutes, or 3.5~ of the day and at standby for the remaining 96.5% of the day. With a 6 m A dynamic current and a 1.5 A
standby current, this gives a battery drain of (1.5/106 x 96.5/100 x 8 + 6/103 x 3.5/100 x 8) x 103 = 1.6916 m A - hr. per day. This compares dramatically with the worst case in which the electronics remain in the dynamic state continuously. In this case the battery drain would be (6/103 x 8) x 103 = 48 m A - ho per day.
~2Z~623 With the prior art arrangements in which the standby condition is entered minutes after the last keystroke, it is quite probably that this worst case situation would be the normal situation with, possibly, standby entered only once or twice a day.
While the invention has been particularly described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention.
35m
Claims (5)
- Claim 1. A battery powered keyboard device comprising a keyboard having drive and sense lines and coupled to the battery for providing a first potential on the sense lines with no key depressed and a second potential on a sense line coupled to a depressed key and a microprocessor having an output port coupled to the drive lines, an input port coupled to the sense lines and a low power standby mode input and to generate, in response to the sense line signals, coded output signals to drive an infra-red light emitting device, and including a power conservation system comprising first means responsive to a said second potential to energize the low power standby input of the microprocessor, and second means responsive to a microprocessor output signal indicating completion of processing of signals from the sense line to de-energize the low power standby input.
- Claim 2. A keyboard device according to claim 1 in which said first means comprises a NOR circuit having an associated input coupled to each of the sense lines.
- Claim 3. A keyboard device according to claim 2 in which the second means concludes a first latch circuit coupled to the output of the NOR circuit and to receive said microprocessor output signal for alternatively energizing and de-energizing said low power standby mode input.
- Claim 4. A keyboard entry device according to claim 3 including a second latch circuit having a first input coupled to the output of the first latch circuit and its output coupled to the microprocessor low power standby mode input.
- Claim 5. A keyboard entry device according to claim 4 including a delay circuit coupled between the output of said first latch circuit and an input of a third latch circuit having its output coupled to a resetting input of the microprocessor.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US522,061 | 1983-08-10 | ||
| US06/522,061 US4649373A (en) | 1983-08-10 | 1983-08-10 | Powered conservation system in battery powered keyboard device including a microprocessor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1226623A true CA1226623A (en) | 1987-09-08 |
Family
ID=24079302
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000458355A Expired CA1226623A (en) | 1983-08-10 | 1984-07-06 | Powered conservation system in battery powered keyboard device including a microprocessor |
Country Status (15)
| Country | Link |
|---|---|
| US (1) | US4649373A (en) |
| EP (1) | EP0134966B1 (en) |
| JP (1) | JPS60180036U (en) |
| KR (1) | KR890002322B1 (en) |
| AR (1) | AR241285A1 (en) |
| AT (1) | ATE31984T1 (en) |
| BR (1) | BR8403982A (en) |
| CA (1) | CA1226623A (en) |
| DE (1) | DE3468756D1 (en) |
| ES (1) | ES8507711A1 (en) |
| GB (1) | GB2144889A (en) |
| HK (1) | HK99489A (en) |
| MX (1) | MX155926A (en) |
| SG (1) | SG62189G (en) |
| ZA (1) | ZA845365B (en) |
Families Citing this family (50)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4905187A (en) * | 1986-01-31 | 1990-02-27 | Rca Lincensing Corporation | Time-keeping apparatus |
| USRE33229F1 (en) * | 1986-03-06 | 1999-11-16 | C L I C Electronics Internatio | Remote display device for a microcomputer with optical communication |
| US4763291A (en) * | 1986-03-06 | 1988-08-09 | Project Benjamin, Ltd. | Remote display device for a microcomputer |
| GB2194082A (en) * | 1986-08-18 | 1988-02-24 | Philips Nv | Data processing apparatus with energy saving clocking device |
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| JPS5330247A (en) * | 1976-09-02 | 1978-03-22 | Citizen Watch Co Ltd | Small-size electronic unit |
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| JPS5789119A (en) * | 1980-11-20 | 1982-06-03 | Nec Corp | Terminal device |
| JPS58129523A (en) * | 1982-01-28 | 1983-08-02 | Matsushita Electric Ind Co Ltd | Microcomputer device |
-
1983
- 1983-08-10 US US06/522,061 patent/US4649373A/en not_active Expired - Fee Related
-
1984
- 1984-04-28 KR KR1019840002299A patent/KR890002322B1/en not_active IP Right Cessation
- 1984-05-16 JP JP1984070474U patent/JPS60180036U/en active Granted
- 1984-07-03 GB GB08416920A patent/GB2144889A/en not_active Withdrawn
- 1984-07-05 AT AT84107801T patent/ATE31984T1/en active
- 1984-07-05 EP EP84107801A patent/EP0134966B1/en not_active Expired
- 1984-07-05 DE DE8484107801T patent/DE3468756D1/en not_active Expired
- 1984-07-06 CA CA000458355A patent/CA1226623A/en not_active Expired
- 1984-07-11 ZA ZA845365A patent/ZA845365B/en unknown
- 1984-08-01 AR AR84297420A patent/AR241285A1/en active
- 1984-08-07 MX MX202287A patent/MX155926A/en unknown
- 1984-08-09 ES ES535007A patent/ES8507711A1/en not_active Expired
- 1984-08-09 BR BR8403982A patent/BR8403982A/en not_active IP Right Cessation
-
1989
- 1989-09-09 SG SG621/89A patent/SG62189G/en unknown
- 1989-12-14 HK HK994/89A patent/HK99489A/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| KR890002322B1 (en) | 1989-06-30 |
| JPS60180036U (en) | 1985-11-29 |
| JPH0222734Y2 (en) | 1990-06-20 |
| MX155926A (en) | 1988-05-23 |
| EP0134966A2 (en) | 1985-03-27 |
| ZA845365B (en) | 1985-03-27 |
| ES535007A0 (en) | 1985-09-01 |
| DE3468756D1 (en) | 1988-02-18 |
| GB8416920D0 (en) | 1984-08-08 |
| GB2144889A (en) | 1985-03-13 |
| US4649373A (en) | 1987-03-10 |
| BR8403982A (en) | 1985-07-09 |
| EP0134966B1 (en) | 1988-01-13 |
| EP0134966A3 (en) | 1985-06-05 |
| HK99489A (en) | 1989-12-22 |
| ES8507711A1 (en) | 1985-09-01 |
| AR241285A1 (en) | 1992-04-30 |
| SG62189G (en) | 1990-01-26 |
| ATE31984T1 (en) | 1988-01-15 |
| KR850002613A (en) | 1985-05-15 |
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| Date | Code | Title | Description |
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| MKEX | Expiry |