CA1246158A - Sample-and-hold circuit arrangement - Google Patents
Sample-and-hold circuit arrangementInfo
- Publication number
- CA1246158A CA1246158A CA000509659A CA509659A CA1246158A CA 1246158 A CA1246158 A CA 1246158A CA 000509659 A CA000509659 A CA 000509659A CA 509659 A CA509659 A CA 509659A CA 1246158 A CA1246158 A CA 1246158A
- Authority
- CA
- Canada
- Prior art keywords
- amplifier
- capacitor
- output
- input
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/02—Sample-and-hold arrangements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/02—Sample-and-hold arrangements
- G11C27/024—Sample-and-hold arrangements using a capacitive memory element
- G11C27/026—Sample-and-hold arrangements using a capacitive memory element associated with an amplifier
Abstract
PHN.11.395 8 9.4.1986 ABSTRACT:
Sample-and-hold circuit arrangement.
The invention relates to a sample-and-hold circuit arrangement comprising a differential amplifier (5) followed by an inverting amplifier (8).
In accordance with the invention there is provided a third amplifier (12) and a capacitor (14) which connects an out-put of the third amplifier to its input. The inverting amplifier (68) ensures that the voltage on the output (16) of the arrange-ment is independent of the offset voltage of the differential amplifier (5). Moreover, the capacitor (14) maintains the voltage on the output (15) during a sampling interval at the value which it had in the directly preceding hold interval.
Fig. 1.
Sample-and-hold circuit arrangement.
The invention relates to a sample-and-hold circuit arrangement comprising a differential amplifier (5) followed by an inverting amplifier (8).
In accordance with the invention there is provided a third amplifier (12) and a capacitor (14) which connects an out-put of the third amplifier to its input. The inverting amplifier (68) ensures that the voltage on the output (16) of the arrange-ment is independent of the offset voltage of the differential amplifier (5). Moreover, the capacitor (14) maintains the voltage on the output (15) during a sampling interval at the value which it had in the directly preceding hold interval.
Fig. 1.
Description
~2~ 5~
PHN.11.395 l 904.1986 Sample and-hold circuit arrangement.
~ he invention relates to a sample-and-hold circuit arrangement comprising an input terminal, at least two switches, a capacitor, a aifferential amplifier and a second amplifier of an inverting type, said second amplifier having an input terminal connected to an output terminal of said differential amplifier, the inpvt terminal of the arrangement being connected to an in-put of -the differential amplifier via one of the switches and an output of the second amplifier being connected to an input of the differential amplifier via the second swi-tch.
Such a sample-and-hold circuit arrangement is known fxom United States Patent Specification 3,696,30~. During the hold intervals the output voltage of this circuit arrangement is hardly influenced by the offset voltage of the differential ampli-fier.
In this respect the offset voltage of the differential amplifier is to be understood to mean that voltage between the inputs of the differential amplifier which yields a zero signal on the output terminal of this amplifier.
Xowever, a disadvantage of the known circuit arrange-ment is that its output voltage decreases to substantially zerovolts during the sampling in-tervals. If such circuit arrangements are employed for example in combination with electrical memories for data processing equipment it is often desirable that the out-put voltage of the arrangement during a specific sampling inter-val remains substantially the same as in the directly precedinghold interval.
It is the object of the invention to provide a sample~
and-hold circuit arrangement of the type defined in the opening paragraph, in which the output voltage during a hold interval is not influenced by the offset voltage of the differential ampli-fier and in which the output voltage during a sampling interval is substantially equal to that during the directly preceding hold interval.
." ' `'~:.' ... .
~6~L5~
PHN.11 3j5 2 9.~.1986 A sample-and-hold circuit arrangement in accordance with the invention is characterized in that the capacitor is ar-ranged in the connection from the first switch to the differential amplifier, and in that the arrangement also comprises a third am-plifier whose input is connected to the output of the differentialamplifier via a third switch, which third amplifier has an out-put terminal connected, via a fourth switch, to that side (electrode) ; of the capacitor which is connected to the first switch, the in-put terminal and the output terminal of the -third amplifier being interconnected via a branch including a second capacitor.
An advantage of the circuit arrangement in accordance with the invention is that during a hold interval the ou-tput voltage of ~the arrangement being the vol-tage of the output -terminal of the third amplifier is hardly influenced by -the offse-t vol-tage of the differentlal amplifier and during a sampling interval the output voltage of the arrangement is 9ubstantially the same as in the direotly preceding hold interval.
The invention is based on the idea of using the second amplifier only for eliminating the offset voltage of the differ-ential amplifier. The third amplifier across which the branchincluding the second capacitor is connected, serves for maintain-ing the output voltage during a succeeding sampling interval.
In an embodiment of the invention the second amplifier and the third amplifier are constructed in such way that their trans-fer characteristics are substantially identical.
An advantage of this improvement is tha-t when the second amplifier and the third amplifier are employed alternately in con-formity with the sampling interval and the hold interval respect-ively, the offset voltage of the differential amplifier is sub-stantially the same in the two intervals. This means that alsoduring the sampling interval the voltage on the output terminal of the third amplifier is practically independent of this offset voltage.
The invention will now be described in more detail, by way of example, with reference to the drawing. In the drawing:
~ ig. 1 is a basic diagram of a sample-and-hold circuit arrangement in accordance with the invention; and ~ ig. 2 shows a practical example of the sample-and-hold , ~6~5~
PHN,11.395 3 9.4.1986 circuit arrangement shown in ~ig. 1.
The arrangement shown in ~ig. 1 comprises an input terminal 1 which is connected to the terminal A of a capacitor 3 via a switch 2, the other terminal ~ of said capacitor being con-nected to the non-inverting input 4 of a differential amplifier 5, whose inverting input 6 is connected to a point carrying a reference voltage VR. ~he ou-tput terminal of the differential amplifier is connected to an input of a second amplifier ~ of an inverting type via a switch 7, the output of said amplifier 8 being connected to its input by a capacitor 9. This output is also connected to the non-inverting input 4 of the differential amplifier 5 v a switch 10.
~ urther, the output terminal of the differential ampli-fier 5 is connected to the input of a third amplifier 12 of an inverting type via a switch 11, the output 13 of this amplifier 12 being connecte~ -to its input by a capacitor l4, The output l3 is also connected to -the terminal A of -the capacitor 3 via a switch 15, The output terminal 16 connected to the output 13 con-stitutes the output of the circuit arrangement.
The arrangement operates as follows. An analog voltage VIN is applied to the input terminal 1. During a sampling inter-val the switches 2, 7 and 10 are closed. ~he other switches are then open. During a hold interval the switches 11 and 15 are closed.
The other switches are then open.
In the sampling interval the amplifier 5 is connected to the amplifier 8 to form a voltage follower. ~erminal 3 of the capacitor 3 is then at a potential VR ~ VoffSet, where VoffSet is the offset voltage of the differential amplifier 5. This results g IN (VR + VoffSet) across the capacitor 3, because the potential on terminal A of the capacitor 3 is VIN.
In the succeeding hold interval the amplifier 8 is dis-connected from 5 and the amplifier 12 is connected to the ampli-fier 5. The input voltage to the differential amplifier 5 is then changed because terminal A of the capacitor 3 (see ~ig. 1) is connected to the output 13 of the third amplifier 12. However, the charge of the capacitor 3 remains the same.
~ he potential on the ou-tput 13 and hence that on output terminal 16 now changes until the potential on termina] ~ is re-~L~ 6~L5~3 PHN.11.395 4 9.4.1986 stored to the value during the sampling interval. This also means that the potential on terminal A of the capacitor 3 and hence that on the output 16, iB restored to the value VI~ in the pre-ceding hold interval.
As a result of the presence of the capacitor 14 VIN on the output 16 is also maintained during the succeeding sampling interval. This will be explained with reference to ~ig. 2.
In ~ig. 2, which shows a practical embodiment of the invention, circuit elements corresponding to those in Fig. 1 bear the same reference numerals. ~he three amplifiers including the capacitors are shown in separate boxes.
The differential amplifier 5 comprises two N-channel MOS transistors 34 and 35 which are arranged as a differential pair whose oommon-source terminal is connected to the negative power-supply -terminal 31 by means of a current souroe 36. ~he gate of the transistor 34 is connected to capacitor 3 and the gate of the transis-tor 35 i8 ccnnected tc a point for carrying a reference voltage VR. ~he drain of the transistor 34 is ccnnected to the output of the differential amplifier 5 by a current mirror comprising P-channel MOS transistors 32 and 33, and the drain of the transistor 35 is connected directly to said output. 3y means of a switch 7 said output can be connected to the input of the amplifier 8 which comprises a P-channel MOS transistor 40 loaded by a current source 41. The output of this amplifier is fed back to the input by the series arrangement of a resistor 37 and a capacitor 9. The resistor 37 serves to improve the stability of the amplifier.
The amplifier 12 comprises a P-channel MOS -transistor 53 which is driven directly by the output of the amplifier 5 when the switch 11 is closed. An N-channel MOS transistor 55 is ar-ranged in series with the transistor 53 and is driven in phase opposition with the latter. ~or this purpose the amplifier 12 comprises a first current mirror comprising P-channel MOS tran-sistors 51 and 52. ~he current gain of this current mirror is, for example, two. The input of this current mirror is connected to a current source 56 and to the drain of a P-channel MOS tran-sistor 50 arranged in parallel with the transistor 53. ~he area of this transistor 5O is, for example, 1/5 of that of the -tran-6~LS~3 p~IN.11.395 9.4.1986 sistor 53. The output of the first current mirror is connectedto the input of a second current mirror comprising the transistors 54 and 55. The current gain of this current mirror is, for example, ten. The output 13 of the amplifier 12 is connected to the input o the amplifier 129 by the series arrangement of a resistor 57 and a capacitor 14. ~he resistor 57 serves to improve the stability of the amplifier.
If the current, from the current source 56 is 25 /uA, the negative feedback via the resistor 57 and the capacitor 14 ensures that the voltage on the input becomes such that the quiescent current through the transistors 53 and 5~ is sub-stantially 100 /uA. ~he current from the current source 56 is then distributed between the transistors 50 and 51 in such a way that the current in the transistor 50 is 20 /uA and that in the lS transistor 51 is 5 /uA. ~he voltage on the inpu-t of the amplifier 12 can now inorease until the -transis-tor 50 is cut off and -the transistor 51 carries the full current from the current souroe 56.
~he maximum output current is then 500 ~ , which is relatively large in comparison with the quiescent current.
As already stated in the description with reference to Fig. 1, the switches 7 and 11 are closed alternatively, so that voltage is applied to the capacitor 9 and the capacitor 14, alternatively.
The voltage on the capaci-tor 14 is maintained during a Z5 sampling interval. Consequ~ntly, the potential on the output 13 is maintained during the sampling interval.
In the present example the reference voltage VR is ap-proximately 5 V, the capacitor 3 is approximately 10 p~, the capacitor 9 is approximately 10 p~, the capacitor 14 is approximately 10 p~, the resistor 37 is approximately 20 kOhms, and the resistor 57 is approximately 20 kOhms, the current sources 36 and 41 approximately 25 /uA.
~he switches 2, 7, 10 and 15 may be, for example, solid-state switching devices. The switches 2 and 15 may be combined to form a change-over switch.
In the embodiment of :E?ig. 2 the offset voltage of the .
~2~ 5~3 PH~.11.395 6 9.4.1986 differential amplifier in the switched-in condition of the in-verting amplifier 8 is substantially equal to that in the switched-in condition of the amplifier 12. This is because the -transfer characteristics of the amplifiers 8 and 12 are substantially identical.
~ y means of the circuit arrangement shown in the ~igures an analog voltage (on 1) is converted into a sampled voltage (on 16), which conversion is hardly influenced 'Dy the offset voltage of the differential amplifier 5, whilst during a sampling inter-val the sampled voltage is maintained at the level which it had in the directly preceding hold interval.
PHN.11.395 l 904.1986 Sample and-hold circuit arrangement.
~ he invention relates to a sample-and-hold circuit arrangement comprising an input terminal, at least two switches, a capacitor, a aifferential amplifier and a second amplifier of an inverting type, said second amplifier having an input terminal connected to an output terminal of said differential amplifier, the inpvt terminal of the arrangement being connected to an in-put of -the differential amplifier via one of the switches and an output of the second amplifier being connected to an input of the differential amplifier via the second swi-tch.
Such a sample-and-hold circuit arrangement is known fxom United States Patent Specification 3,696,30~. During the hold intervals the output voltage of this circuit arrangement is hardly influenced by the offset voltage of the differential ampli-fier.
In this respect the offset voltage of the differential amplifier is to be understood to mean that voltage between the inputs of the differential amplifier which yields a zero signal on the output terminal of this amplifier.
Xowever, a disadvantage of the known circuit arrange-ment is that its output voltage decreases to substantially zerovolts during the sampling in-tervals. If such circuit arrangements are employed for example in combination with electrical memories for data processing equipment it is often desirable that the out-put voltage of the arrangement during a specific sampling inter-val remains substantially the same as in the directly precedinghold interval.
It is the object of the invention to provide a sample~
and-hold circuit arrangement of the type defined in the opening paragraph, in which the output voltage during a hold interval is not influenced by the offset voltage of the differential ampli-fier and in which the output voltage during a sampling interval is substantially equal to that during the directly preceding hold interval.
." ' `'~:.' ... .
~6~L5~
PHN.11 3j5 2 9.~.1986 A sample-and-hold circuit arrangement in accordance with the invention is characterized in that the capacitor is ar-ranged in the connection from the first switch to the differential amplifier, and in that the arrangement also comprises a third am-plifier whose input is connected to the output of the differentialamplifier via a third switch, which third amplifier has an out-put terminal connected, via a fourth switch, to that side (electrode) ; of the capacitor which is connected to the first switch, the in-put terminal and the output terminal of the -third amplifier being interconnected via a branch including a second capacitor.
An advantage of the circuit arrangement in accordance with the invention is that during a hold interval the ou-tput voltage of ~the arrangement being the vol-tage of the output -terminal of the third amplifier is hardly influenced by -the offse-t vol-tage of the differentlal amplifier and during a sampling interval the output voltage of the arrangement is 9ubstantially the same as in the direotly preceding hold interval.
The invention is based on the idea of using the second amplifier only for eliminating the offset voltage of the differ-ential amplifier. The third amplifier across which the branchincluding the second capacitor is connected, serves for maintain-ing the output voltage during a succeeding sampling interval.
In an embodiment of the invention the second amplifier and the third amplifier are constructed in such way that their trans-fer characteristics are substantially identical.
An advantage of this improvement is tha-t when the second amplifier and the third amplifier are employed alternately in con-formity with the sampling interval and the hold interval respect-ively, the offset voltage of the differential amplifier is sub-stantially the same in the two intervals. This means that alsoduring the sampling interval the voltage on the output terminal of the third amplifier is practically independent of this offset voltage.
The invention will now be described in more detail, by way of example, with reference to the drawing. In the drawing:
~ ig. 1 is a basic diagram of a sample-and-hold circuit arrangement in accordance with the invention; and ~ ig. 2 shows a practical example of the sample-and-hold , ~6~5~
PHN,11.395 3 9.4.1986 circuit arrangement shown in ~ig. 1.
The arrangement shown in ~ig. 1 comprises an input terminal 1 which is connected to the terminal A of a capacitor 3 via a switch 2, the other terminal ~ of said capacitor being con-nected to the non-inverting input 4 of a differential amplifier 5, whose inverting input 6 is connected to a point carrying a reference voltage VR. ~he ou-tput terminal of the differential amplifier is connected to an input of a second amplifier ~ of an inverting type via a switch 7, the output of said amplifier 8 being connected to its input by a capacitor 9. This output is also connected to the non-inverting input 4 of the differential amplifier 5 v a switch 10.
~ urther, the output terminal of the differential ampli-fier 5 is connected to the input of a third amplifier 12 of an inverting type via a switch 11, the output 13 of this amplifier 12 being connecte~ -to its input by a capacitor l4, The output l3 is also connected to -the terminal A of -the capacitor 3 via a switch 15, The output terminal 16 connected to the output 13 con-stitutes the output of the circuit arrangement.
The arrangement operates as follows. An analog voltage VIN is applied to the input terminal 1. During a sampling inter-val the switches 2, 7 and 10 are closed. ~he other switches are then open. During a hold interval the switches 11 and 15 are closed.
The other switches are then open.
In the sampling interval the amplifier 5 is connected to the amplifier 8 to form a voltage follower. ~erminal 3 of the capacitor 3 is then at a potential VR ~ VoffSet, where VoffSet is the offset voltage of the differential amplifier 5. This results g IN (VR + VoffSet) across the capacitor 3, because the potential on terminal A of the capacitor 3 is VIN.
In the succeeding hold interval the amplifier 8 is dis-connected from 5 and the amplifier 12 is connected to the ampli-fier 5. The input voltage to the differential amplifier 5 is then changed because terminal A of the capacitor 3 (see ~ig. 1) is connected to the output 13 of the third amplifier 12. However, the charge of the capacitor 3 remains the same.
~ he potential on the ou-tput 13 and hence that on output terminal 16 now changes until the potential on termina] ~ is re-~L~ 6~L5~3 PHN.11.395 4 9.4.1986 stored to the value during the sampling interval. This also means that the potential on terminal A of the capacitor 3 and hence that on the output 16, iB restored to the value VI~ in the pre-ceding hold interval.
As a result of the presence of the capacitor 14 VIN on the output 16 is also maintained during the succeeding sampling interval. This will be explained with reference to ~ig. 2.
In ~ig. 2, which shows a practical embodiment of the invention, circuit elements corresponding to those in Fig. 1 bear the same reference numerals. ~he three amplifiers including the capacitors are shown in separate boxes.
The differential amplifier 5 comprises two N-channel MOS transistors 34 and 35 which are arranged as a differential pair whose oommon-source terminal is connected to the negative power-supply -terminal 31 by means of a current souroe 36. ~he gate of the transistor 34 is connected to capacitor 3 and the gate of the transis-tor 35 i8 ccnnected tc a point for carrying a reference voltage VR. ~he drain of the transistor 34 is ccnnected to the output of the differential amplifier 5 by a current mirror comprising P-channel MOS transistors 32 and 33, and the drain of the transistor 35 is connected directly to said output. 3y means of a switch 7 said output can be connected to the input of the amplifier 8 which comprises a P-channel MOS transistor 40 loaded by a current source 41. The output of this amplifier is fed back to the input by the series arrangement of a resistor 37 and a capacitor 9. The resistor 37 serves to improve the stability of the amplifier.
The amplifier 12 comprises a P-channel MOS -transistor 53 which is driven directly by the output of the amplifier 5 when the switch 11 is closed. An N-channel MOS transistor 55 is ar-ranged in series with the transistor 53 and is driven in phase opposition with the latter. ~or this purpose the amplifier 12 comprises a first current mirror comprising P-channel MOS tran-sistors 51 and 52. ~he current gain of this current mirror is, for example, two. The input of this current mirror is connected to a current source 56 and to the drain of a P-channel MOS tran-sistor 50 arranged in parallel with the transistor 53. ~he area of this transistor 5O is, for example, 1/5 of that of the -tran-6~LS~3 p~IN.11.395 9.4.1986 sistor 53. The output of the first current mirror is connectedto the input of a second current mirror comprising the transistors 54 and 55. The current gain of this current mirror is, for example, ten. The output 13 of the amplifier 12 is connected to the input o the amplifier 129 by the series arrangement of a resistor 57 and a capacitor 14. ~he resistor 57 serves to improve the stability of the amplifier.
If the current, from the current source 56 is 25 /uA, the negative feedback via the resistor 57 and the capacitor 14 ensures that the voltage on the input becomes such that the quiescent current through the transistors 53 and 5~ is sub-stantially 100 /uA. ~he current from the current source 56 is then distributed between the transistors 50 and 51 in such a way that the current in the transistor 50 is 20 /uA and that in the lS transistor 51 is 5 /uA. ~he voltage on the inpu-t of the amplifier 12 can now inorease until the -transis-tor 50 is cut off and -the transistor 51 carries the full current from the current souroe 56.
~he maximum output current is then 500 ~ , which is relatively large in comparison with the quiescent current.
As already stated in the description with reference to Fig. 1, the switches 7 and 11 are closed alternatively, so that voltage is applied to the capacitor 9 and the capacitor 14, alternatively.
The voltage on the capaci-tor 14 is maintained during a Z5 sampling interval. Consequ~ntly, the potential on the output 13 is maintained during the sampling interval.
In the present example the reference voltage VR is ap-proximately 5 V, the capacitor 3 is approximately 10 p~, the capacitor 9 is approximately 10 p~, the capacitor 14 is approximately 10 p~, the resistor 37 is approximately 20 kOhms, and the resistor 57 is approximately 20 kOhms, the current sources 36 and 41 approximately 25 /uA.
~he switches 2, 7, 10 and 15 may be, for example, solid-state switching devices. The switches 2 and 15 may be combined to form a change-over switch.
In the embodiment of :E?ig. 2 the offset voltage of the .
~2~ 5~3 PH~.11.395 6 9.4.1986 differential amplifier in the switched-in condition of the in-verting amplifier 8 is substantially equal to that in the switched-in condition of the amplifier 12. This is because the -transfer characteristics of the amplifiers 8 and 12 are substantially identical.
~ y means of the circuit arrangement shown in the ~igures an analog voltage (on 1) is converted into a sampled voltage (on 16), which conversion is hardly influenced 'Dy the offset voltage of the differential amplifier 5, whilst during a sampling inter-val the sampled voltage is maintained at the level which it had in the directly preceding hold interval.
Claims (2)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A sample-and-hold circuit arrangement comprising an input terminal, at least two switches, a capacitor, a differential amplifier and a second amplifier of an inverting type, said second amplifier having an input terminal connected to an output terminal of said differential amplifier, the input terminal of the arrangement being connected to an input of the differential amplifier via one of the switches and an output of the second amplifier being connected to an input of the differential ampli-fier via the second switch, characterized in that the capacitor is arranged in the connenction from the first switch to the dif-ferential amplifier, and in that the arrangement also comprises a third amplifier whose input is connected to the output of the differential amplifier via a third switch which third amplifier has an output terminal connected, via a fourth switch, to that side (electrode) of the capacitor which is connected to the first switch, the input terminal and the output terminal of the third amplifier being interconnected via a branch including a second capacitor.
2. A sample-and-hold circuit arrangement as claimed in Claim 1, characterized in that the second amplifier and the third amplifier are constructed in such a way that their transfer characteristics are substantially identical.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| NL8501492 | 1985-05-24 | ||
| NL8501492A NL8501492A (en) | 1985-05-24 | 1985-05-24 | SAMPLING AND HOLD SWITCHING DEVICE. |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1246158A true CA1246158A (en) | 1988-12-06 |
Family
ID=19846036
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000509659A Expired CA1246158A (en) | 1985-05-24 | 1986-05-21 | Sample-and-hold circuit arrangement |
Country Status (8)
| Country | Link |
|---|---|
| US (2) | US4672239A (en) |
| EP (1) | EP0205201B1 (en) |
| JP (1) | JPH0634359B2 (en) |
| KR (1) | KR940010421B1 (en) |
| CA (1) | CA1246158A (en) |
| DE (1) | DE3667350D1 (en) |
| NL (1) | NL8501492A (en) |
| SG (1) | SG87390G (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4962325A (en) * | 1988-09-09 | 1990-10-09 | Analog Devices, Inc. | Sample-hold amplifier circuit |
| DE69014414T2 (en) * | 1989-05-29 | 1995-06-14 | Philips Electronics Nv | Sampling and holding arrangement. |
| JPH0695439B2 (en) * | 1989-09-26 | 1994-11-24 | アナログ・ディバイセス・インコーポレーテッド | Current mode sample and hold amplifier |
| US5495192A (en) * | 1992-02-10 | 1996-02-27 | Yozan Inc. | Sample hold circuit |
| JP2944302B2 (en) * | 1992-05-27 | 1999-09-06 | 株式会社沖エル・エス・アイ・テクノロジ関西 | Sampling circuit |
| JP2945805B2 (en) * | 1992-10-01 | 1999-09-06 | 松下電器産業株式会社 | A / D converter |
| DE69420631T2 (en) * | 1993-06-02 | 2000-04-06 | Canon Kk | Signal processing device |
| US5532624A (en) * | 1995-01-31 | 1996-07-02 | At&T Corp. | High-speed and accurate sample and hold circuits |
| US6262610B1 (en) * | 1999-08-25 | 2001-07-17 | National Semiconductor Corporation | Voltage sample and hold circuit for low leakage charge pump |
| KR100436127B1 (en) * | 2000-06-28 | 2004-06-14 | 주식회사 하이닉스반도체 | semiconductor memory device having sense amplifier and method for driving sense amplifier |
| EP1689075B1 (en) * | 2005-02-03 | 2018-07-11 | Texas Instruments Inc. | Multi-stage amplifier to reduce pop noise |
| JP2006216205A (en) * | 2005-02-07 | 2006-08-17 | Denso Corp | Sample and hold circuit |
| JP5191214B2 (en) * | 2006-12-21 | 2013-05-08 | セイコーインスツル株式会社 | Comparator circuit |
| JP2010010921A (en) * | 2008-06-25 | 2010-01-14 | Fujitsu Ltd | A/d converter and method for a/d conversion |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3516002A (en) * | 1967-05-02 | 1970-06-02 | Hughes Aircraft Co | Gain and drift compensated amplifier |
| US4119960A (en) * | 1977-02-11 | 1978-10-10 | Siliconix Incorporated | Method and apparatus for sampling and holding an analog input voltage which eliminates offset voltage error |
| US4209717A (en) * | 1977-11-07 | 1980-06-24 | Litton Industrial Products, Inc. | Sample and hold circuit |
| NL8020352A (en) * | 1979-09-27 | 1981-07-01 | American Micro Syst | SAMPLING AND HOLDING CIRCUIT WITH SHIFT LIFT. |
| JPS58187015A (en) * | 1982-04-26 | 1983-11-01 | Nippon Telegr & Teleph Corp <Ntt> | Switched capacitor circuit |
| US4546324A (en) * | 1982-12-27 | 1985-10-08 | Intersil, Inc. | Digitally switched analog signal conditioner |
-
1985
- 1985-05-24 NL NL8501492A patent/NL8501492A/en not_active Application Discontinuation
-
1986
- 1986-05-09 US US06/861,161 patent/US4672239A/en not_active Expired - Fee Related
- 1986-05-21 DE DE8686200877T patent/DE3667350D1/en not_active Expired - Lifetime
- 1986-05-21 CA CA000509659A patent/CA1246158A/en not_active Expired
- 1986-05-21 EP EP86200877A patent/EP0205201B1/en not_active Expired
- 1986-05-22 KR KR1019860003989A patent/KR940010421B1/en not_active IP Right Cessation
- 1986-05-24 JP JP61118439A patent/JPH0634359B2/en not_active Expired - Lifetime
-
1987
- 1987-05-22 US US07/053,770 patent/US4764689A/en not_active Expired - Fee Related
-
1990
- 1990-10-25 SG SG873/90A patent/SG87390G/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| NL8501492A (en) | 1986-12-16 |
| KR860009428A (en) | 1986-12-22 |
| SG87390G (en) | 1990-12-21 |
| US4764689A (en) | 1988-08-16 |
| EP0205201A1 (en) | 1986-12-17 |
| JPS61273796A (en) | 1986-12-04 |
| JPH0634359B2 (en) | 1994-05-02 |
| DE3667350D1 (en) | 1990-01-11 |
| KR940010421B1 (en) | 1994-10-22 |
| US4672239A (en) | 1987-06-09 |
| EP0205201B1 (en) | 1989-12-06 |
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| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |