CA1252870A - Packet switch trunk circuit queueing arrangement - Google Patents
Packet switch trunk circuit queueing arrangementInfo
- Publication number
- CA1252870A CA1252870A CA000507812A CA507812A CA1252870A CA 1252870 A CA1252870 A CA 1252870A CA 000507812 A CA000507812 A CA 000507812A CA 507812 A CA507812 A CA 507812A CA 1252870 A CA1252870 A CA 1252870A
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- CA
- Canada
- Prior art keywords
- memory
- data
- data packets
- packet
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
Abstract
POCKET SWITCH TRUNK CIRCUIT QUEUEING ARRANGEMENT
Abstract A trunk circuit interfaces a multichannel data signal to a communication facility using a high priority queue (HPQ) memory, a low priority queue (LPQ) memory, and a data packet sorter including a separate LPQ counter for each data channel. Each LPQ channel counter keeps track of data packets from the associated channel which are stored in the LPQ memory. The packet sorter sorts data packets according to size. Small data packets from each channel which are smaller than a predetermined length are sorted for storage in the HPQ memory only when the associated LPQ channel counter is zero. Small data packets having a non-zero LPQ channel count and large data packets are stored in the LPQ memory. The trunk circuit first transmits data packets from the HPQ memory and then from the LPQ memory.
Abstract A trunk circuit interfaces a multichannel data signal to a communication facility using a high priority queue (HPQ) memory, a low priority queue (LPQ) memory, and a data packet sorter including a separate LPQ counter for each data channel. Each LPQ channel counter keeps track of data packets from the associated channel which are stored in the LPQ memory. The packet sorter sorts data packets according to size. Small data packets from each channel which are smaller than a predetermined length are sorted for storage in the HPQ memory only when the associated LPQ channel counter is zero. Small data packets having a non-zero LPQ channel count and large data packets are stored in the LPQ memory. The trunk circuit first transmits data packets from the HPQ memory and then from the LPQ memory.
Description
FACK~T Sl~ITCH TRtlNK CIRCIlII QUEUEING AR~ANG~MENT
T___ni_a1_F_el,d This invention rela-tes to packet switching networks and, more particularly, to a trunk circuit for interconnecting two packet s~itch nodes over a communication trunk.
Back~round of_the Invention Interactive terminals and other data devices typically transmit information in intermittent bursts.
~acket switching systems, including some local area networks (LAN), enable efficient communica~ions between different data devices, connected together over a data bus, by breaking up the bursty data transmissions into short data packets and by multiplexing together the data packets from several different data devices onto the data bus. The location of a pacXet switching system is often referred to as a node. ~1hen internodal data communication is reguired, a trunk circuit is utilized to interface the packet nodes to the private or public facilities (trunks) which interconnect the nodes. The design of such trunk circuits or wodules for interfacing wideband nodes via low-speed data trunks requires the consideration of the associated queueing delays on the trunk, particularly for interactive da~a messages. One known arrangement ~described in the article entitled "Queueing and Framing Disci~lines For a Mixture of Data Traffic Types"j authored by A. ~ Fraser and S. P. ~organ and published in the AT~_Bell_L_bora o_le_ Technical Journ_l, July August 1984, Vol. 63, No. 6, Part 2) utilizes a queueing discipline whereby short interactive data messages are given priority over longer data messages. That arrangement, however, re~uires separate data queues for each data channel of the trunk circuit. To keep trunk :
.
: . .
7~
circuit cost low these queues are implemented in soft~are rather than in hardware circuits.
Summary of the Invention In accordance with one aspect of the invention there is provided a data packet sorter for interfaciny a received multichannel packet data stream to a communication line, said sorter comprisiny means for sorting received multichannel data packets equal ~o or greater than a predetermined size Eor storage in a first memory and for sorting multichannel data packets less than said predetermined size for storage in said first memory in response to a signal from an associated channel counter indicating that the count is not zero; and counter means including a channel counter associated with each channel of the received multichannel packet data stream for counting, for each channel, the number of data packets written into said first memory by incrementing said associated channel counter for each data packet written into said first memory and decrementing the associated channel counter for each data packet read from said first memory.
In accordance with another aspect of the invention there is provided a method of sorting a received multichannel packet data stream for transmission over a communication line, the method comprising the steps oE:
sorting multichannel data packets e~ual to or greater than a predetermined size for storage in a first memory and for sorting multichannel data packets less than said predetermined size for storage in said first memory in response to a signal from an associated channel counter indicating that the count is not zero; and counting, Eor each channel o~ the received multichannel packet data stream, the number of data packets written into said ~irst memory by incrementing an associated channel counter for each data packet written into said first memory and decrementing the associated channel counter for each data packet read from said first memory.
a~
- 2a -According to the present invention, a trunk circuit packet sorter utilizes only one high priority queue (HPQ) memory and one low priority data ~ueue (LP~) memory for all of the data channels of ~he trunk circui~, and requires a separate LPQ counter for each data channel. Each LPQ channel counter keeps track of data from the associated channel which is stored in the LPQ
memory. The packet sorter sorts data packets accordiny to size. Small data packets, less than a predetermined length, from each data channel are sorted for storage in the HPQ memory only when the LPQ counter associated with that data channel is zero. That is, a smaller data packet from a channel is stored in the HPQ memory when there is no data from that channel in the LPQ memory. Small data packets having a non-zero LPQ channel count and large data packets are stored in the LPQ memory. This assures that data packets from the same channel will not be ~ransmitted out of order.
The packet sorter is part of the trunk circuit which enables internodal data transmission over a trunk ~acility. The trunk circuit transmits data packets from the LPQ memory only after having transmitted all of the data packets from the HPQ memory. Data packets are grouped together ~o form a data frame for transmission over the trunk facility.
Brief Description of the Drawing The characteristics and operation of the present invention will be more apparent from the following detailed description taken in conjunction with the drawing in which:
FIG. 1 shows the application of a trunk circuit interfacing a trunk facility to a node;
FIG. 2 shows a block diagram of the trunk circuit;
FIG. ~ sho-"s the da-ta f~rmat utilized by the trunk circuit;
FI~. 4 shows a flou chart de~cribing the operation of the packet sorter of the trunk circui.t, FIG. ~ shows a flow chart describing the memor~
ead operation of the trunk circuit; and FIG. 6 shows a block diagram of ~he transmit part of the trunk circuit.
Detail_d Descri2t___ Sho~n in EIG. 1 is an illustrative application o a trunk circui~ useful for interfacing nodes 101 and 1n~ to an internodal trunk facility 103. The nodes 101 and 102 may be a packet switching system or more specifically a local area network (LAN) which interconnects nodes, concentrators and devices (such as terminals, computers, workstations, host printers, etc.~.
Such an LAN is described in the article entitled "A New Local ~rea Network Architecture Using A Centralized Bus", authored by Anthony S~ Rcampora and Michael G. Hluchyj and published in the IEEE_Communication Ma~a~ine, Augus~ 1984, VolO 22, No. 8~
As FIG. 1 shows, a node also contains a clock module 104, a switch module 105, a control module 106, a device interface module 107 and trunk interface module 108 (also referred to as a trunk circuit) along with ~he transmit, broadcast, and contention data busses. The clock module 104 is responsible for system timing, switch module 105 translates a data source address to a data destination address under control of control module 106.
The contention bus is used b~ the interface modules (107, 108) to gain access to the time-slot multiplexed transmit bus. The transmit bus and broadcast bus are used for sending and receiving packets, respect.i~ely. The header of each source packet 110 ~laced on the transmit bus by an interface module contains a source addre.ss consisting of a module number followed by a channel number. The module numbsr uniquel~ identifies the transmittln~ interface 37~) .. ..
module, and the channel number is used to distinguish among the different conversations passing through that module.
As FIG. 1 shous, each packet placed on the transmit bus is removed by the switch module 105 ,/hich translates the source module and channel Du,nbers to the destination module and channel numbers on the destination packet 111. The specific translation is esta~lished by a prior call-set-up procedure. ~he packet is then retransmitted on the broadcast b~s where it is re~eived by the specified destination module. In this waY, a virtual circuit transport mechanism is implemented, wherein common control processor 106 at node 101 handles call step-up and take-down along with necessary maintenance and administration functions.
Assume a data transmission from device 114 of node 101 to device 113 of node 102. The user enters data into device 114 which is then transmitted to device interface module 107 where it contends for transmission time on the transmit bus. '~hen device 114 gets a chance to transmit, it sends a source packet 110 over the transmit bus to s~itch 105 which translates the source module address and channel number to the address of trunk circuit 108 and perhaps a new channel number. Trunk circuit 108 receives the data Packet over the desi~nated channel along ~ith other data Packets on other channels.
In accordance ~ith the present invention, trunk circuit 108 combines the data packets for transmission over trunX facility 103 to node 102. At node 102 the data packets are received by another trunk circuit 112~ In a similar manner as previously described, trunk circuit 112 transmits the data via the circuits 115 of node 102 to device 113. Once the user at device 11LI of node 101 is throuqh transmitting, a signal is sent to control module 106, which in turn informs the switchin~ module 105 to taXe down the connection, and control module 106 informs the control module of node 102 as well.
3t~
The transmission rate betwee~ r.odes 101 and 102 depends upon the type of trunk facility 103 emploYed.
When trunk facility 103 is a lo~-speed, data facility, such as digital data system (~DS) trunks, efficien~ data transmission requires that the trunk ci~cuits 108, 112 utilize efficient queueiny disciplines~ This is particularly impor-tant when the devices communicate using interactive "bursty" type of data, such as when terminals communicate with computers. As will be described in the following paragraphs, the present in~ention utllizes a ~ueueing discipline which assures that the interactive messages get priority over and are interspersed with bulk message data (for example, a file transfer) in such a way that delay requirements for mixed data ty~es are met even when the trunk is heavily used.
In the following description, ~hen an element has an associated reference number, the figure ~here that referenced element is first referenced is the first digit of the reference number. Thus, for example, memory 203 is first referenced in FIG. ~.
Shown in FIG. 2 is a functional block diagram of trunk circuit 108. In a well-known manner, interface 201 interfaces trunk circuit 108 to the transmit bus TBUS and contention bus as well as to the broadcast bus BBU~ shown in FIG. 1~ The data format at different locations of the trunk circuit 108 is illustrated in FIG. 3. The data packets on the broadcast bus BBUS, illustrated by format 301, includes a module number, a channel number and 16 data envelopes. When the module number of the data packet 301 designates trunk circuit 108 to receive the data packet, bus interface 201 does a parity check on the data packet. If the data packet is error-free then, as shown by format 302, interface 201 strips off the module number and eliminates all null data envelopes. A sin~le null envelope is appended which indicates the end of the data~packet.
~5~3'7~
The operation of data packet sorter 202 makes reference to the flo~ chart shown in FIG. L~ . The data packet sorter circuit 202 receives data packets~ 400, and compares the numher of data envelopes in the recei~ed data packets against a predetermined size N. ~ote, a data packet contains data from only one channel. If the number of data envelopes in a received data packet is smaller than N, the LPQ channel packet counter for the channel number associated ~ith the received data packet is checked, 402, for a zero count. If the LFQ channel packet counter 205 is zero the data packet is written into the HPQ memory 204 in step 403. However, if the data packet has less than N bytes and LPQ channel packet count 205 is not zero, it is written into the LPQ memory and the LPQ
packet counter is incremented 405. Finally, if the data packet has N or more bytes it is stored in LPQ memorY 203, in step 404, and the LPQ channel counter 205 is incremented in step 405.
The present data sorter maintains data se~uence in each channel even when the data from one channel is in both the ~PQ memorY and HPQ memory, providiny that all new data from a channel goes into the LPQ memorY as long as any data from the channel is stored in the LPQ memory.
Both LPQ memory 203 and HFQ memorY 204 may be implemented using any of the well known varieties of first-in-first~
out (FIFO)-tYpe memory chips. Because HPQ memory 2n4 holds the shorter data messages it would probably be of much smaller size than the LPQ memory 203.
The transmit control circuit 206 reads data packets from the LPQ memory 203 and HPQ melnory 204 and assembles them in channel framer circu~t 207. ~his operation is described by the flow chart shown in FIG. 5.
After the transmit control circuit 206 starts, in step 500, it checks, in step 501, if HP~ memorY 204 is emp~y, i.e., no data packets therein. If HPQ meinorY 204;
is not empty, a data packet is read, 502, and the Process (500, 501, 502) continues until all data packets are read.
~5~3t7~3 ~hen HPQ memory 204 is empty, the LPQ memo~y 203 is checked in step 5~3. I~ the I~Q memory is elnpty the transmit control circuit 206 returns to start location 500 and cycles throuyh steps 500, 5C~1 and 503 ur,til eitner the LPQ or HPQ memory is not empty~
If LPQ memory 2~)3 has data packets ~hey are read one at a time, 504~ and the LPQ per channel counter associated with that data pachet is decremented, 505.
Thereafter control returns to step 500 and then the HPQ
memory is again checked, step 501. Thus, the HPQ
memory 204 is checked, step 501, after each LP~ memorY
read, step 505, to assure that the high priority data packets of ~PQ memory 204 are transmitted prior to the low priority data packets of LPQ memory 203r Assuming that HPQ memory is empty, the sequence of steps 500, 501, 503, 504 and ~05 continues until all data packets are read from LPQ memory 203 ~ It sh~uld be noted that if transmit control circuit 206 is in the process of removing a data packet from LPQ memory 203 and a ne~ data packet arrives in the empty HPQ memorY 204r it completes the removal of the data packet from LPQ
memory 203 and then begins serving HPQ memory 204 and continues to do so until H~Q memorY 204 is empty.
Transmit control circuit 206 includes a channel framer 207 which receives the data packets from LPQ and HPQ memories and formats them into a data frame for transfer to a universal synchronous asynchronous receive transmit circuit (USART~ 20~. The USART transmits the data frame to trunk facility 103.
The channel framin~ for the trunk circuit could utilize any of the ~ell knoYn formats. The disclosed trunk circuit utilizes a mixed frame, i.e., LP~ and HPQ
data packets are mixed together in a frameO ComPlete packets are transmitted over the trunk until the total number of transmitted bytes exceeds some maximum value.
Different maximum fram~ lengths can be specified depending on uhether the frame contains data from the HPQ (e.g., 7~3 256-~yte limit for frames containing only LPQ pacXe-ts, 64-~yte limit for frames containing one or more HPQ
packets).
As shown in 303, as each data Facket from HPQ
memory 204 is read, the data ~ytes (HP~1-HP~J) are counted and packaged together with the channel number (chan ~) and packet length (len B) to form data packet PK1 of 304.
Similarly, as each data packet from LPQ memor~ 2G3 is read, the data bytes (LPQ1~LPQK) are counted and packaged together with the channel number (chan A) and packet length (len A) to form data packet PX2 of 304, It should be noted that while data pacJcets are discussed herein as including data bytes o 8 bits, in general the data packets can more generally include data envelopes of any bit length.
As shown in 304, data paclcets PK1-PKZ are assembled together with a flag, status, and error detection code CRC to form a data frame (Frame Y) of 305.
Note the length OI data Packets PK1-PKZ and data frames Y-1, Y, Y+1, are different. Data frame lengths can be predetermined so as to control system efficiency and delay characteristics. GenerallY long frames increase efficiency and short frames decrease frame delays. A
sor~ed framing discipline can also be utilized by the present trunk circuit whereby ~PQ and HPQ data packets may be combined to form a frame, but any LP~ data packet is Prevented from bein~ added to a frame that contains any HPQ data packets.
As shown in FIG~ 2, the transmit part of the trunk circuit (FIG. 6~ includes a Packet sorter 202, IPQ
memory 203, HPQ memory 204, and transmit controller 206.
As shown in FIG. 6, the packet sorter 202 includes ~er channel counter 205 and memorY storing logic 216, which is shown as every circuit in 202 which is not part of Per channel counter 205. In FIG. 6, transmit controller 206 includes control circuit 624, channel framer 207 and a variety of registers.
, .
B7~J
~ 9 _ The remaining detailed descrip~ion of trunk circuit 1Q8 makes joint reference to FIGs. ~, 3 and 6.
Data packets arriving over broadcast bus (BB7JS) are serîally loaded into bus inter-face 201 and then loaded 5 into buEfer 601 in parallel over leads D0-D8 using the data ~rite '~JR siynal. As the data packet 302 is loaded into buffer 601 a length counter 602 is increlnented by si~nal WR to compute the number of envelopes in that data packet. ~When the data packet is completely received, the 10 contents of the length counter 602 are transferred into the length register 603 making the length counter 602 available for the next data packet.
At this time, the first data byte in the packet, the channel number of 302, is transferred simultaneously 15 from buffer 601 into the data register 604 and into the channel counter 605. The end of packet circuit 623 detects if the data byte in buffer 601 is the null byte which separates data packets. A null signal is outputted to transmit control circuit 206 to prevent the null byte 20 from being stored.
At this point the packet sorter decides to which memory tLPQ or H~Q) the packet is to be routed. To do that, first the contents LEN of length register 603 are compared in comparator 606 to a predetermined threshold 25 value X se-t in unit 615. The threshold X can be set using a dip switch. If the contents LEN of length register 603 is less than the threshold X, that indication is set in data packet size flip-flop 607. The signal SML out of flip-flop 607 indicates that a small data packet is 30 received. At the same time, ths channel number in channel counter 6P5 is used to address a particular location in the per channel count memory 608. Memory ~;08 has a location for storing the count for each Possible channel number of a data packet. The contents of the addressed 35 memory location, which contains the number of packets stored in LPQ memory for that channel number, is transferred into D counter 609. Counter 609 outputs a . .
, :
3~713 - lC -signal FC~T indicatin~ when -t~e counter value is ~'c its maximum ~e.g~, ~55) and signal ZCNT indicating when the counter value is 0.
Gate 611 provides a da-ta packet load signal HPL
to HPQ memory 204 in response to ~hree slgnals. The three signals include the zero count signal (ZC~1T) for that channel o t~ne I.PÇ memoryi the si.gnal S~L indicating a small data packet was received; and the signal HPF*
indicating that the high prioritY queue 204 is not full.
When the ~hree conditions are ,~et, AND gate 611 generates load signal HPL to load the data from data register 604 into high Priori~y gueue 204. If no load signal HPL is generated, the data is not loaded in the HPQ memory 204 and trunk circuit 108 determines if the data should be loaded into the LPQ memory 203 or discarded. When load signal HPL is at lo~ic 0, inverter 515 enables AND gate 614.
At this point, the second memory full channel si~nal FCNT from counter 60g indicates whether the per channel count of that channel number is at its maximum value 255. If the count is 255, then signal FCNT disables gate 614, via NOR gate 613~ from generating a load signal LPL for T.pQ memory 203 and hence no more data for that channel number can be accepted into the lo~ priority queue 203. Hence, signal FCNT prevents data from that channel nu~lber from being written into the low Priority queue 203 and hence the data packet is discarded. ~ote, it is discarded in data register G04 by being written over b~ the next data ~ord from buffer 601.
If the full count FCNT of that channel number has not been reached then the high water mark signal, HWM, from the low priority queue 203 is checked. The HWM
signal indicates that the LPQ memory 203 is almost full and hence no new data Packets should be written into LPQ 203~ I the HWM signal is set (logic 1), then trunk circuit 108 discards new data packets arrivin~ for all new channel numbers. Note, a new channel nulnber is determined ~5,.~'~'7(7 wnen the ~ero count siqnal ZC~T is logic 1 for tnat channel. There~ore, if ZC~IT and ~ are ~)oth l~gic 1, indica-ting, respectivel~, a ne,l channel and a LPQ
memory 203 that is allnost full, AND gat~ 612 is *nabled gatin~ a signal, through NOP gate 613, which inhlbits gate S14 from generating a lGad signal LPL. If the data packets are n~-t from a new channel ~hen signal ZC~T is not at logic 1. Consequently, AND gate 614 is ena~led by gates 612, 613 and load signal LPL is generated causing the data packet to be loaded into the L~Q memory 203.
~ hen the data packet is loaded into the L~Q
memory 203, -transmit control circuit 206 generates signal IC~T which causes channel counter 605 to increment its count for the chann2l number associated with that data packet. ~hen the data packet is subsequently removed from the LPQ memory 203, the corresponding channel number is loaded from transmit register 619 into channel counter 605 and transmit control circuit 206 generates a signal DCNT
~hich decrements the count in counter 605 for that channel number.
Memories IPQ and HPQ each have a status register, 617 and 618, respectively, which indicates the status of each memorY. Register 618 of HPQ memory 204 generates output ready signal ORH and new data packet available signal NPAH. Similarly, register 617 of LPQ
memory 203 ~enerates output ready signal ORL and new data packet available signal NPAL. ~henever signal ORH is logic 1, it indicates that a data packet is available and transmit control circuit 206 causes data to be read from HPQ memorY 204 and into the high queue HQ register 621 and transferred into the transmit register 619 for subsequent transmission into USART 208. When signal ORH is not logic 1 the transmit control circuit 206 examines the state of signal ORL. When signal ORL is logic 1 data is read from LPQ memory 203 and into low queue LQ
register 622 and transferred into transmit register 61g.
~;~tj~
Transmit control circui~ 206 continlJeS reading data from LPQ memory 203 until a new packet signal NPhH i5 received. A NPh~ signal indicates that a new data pac~.et has arrived in HQP memory 2QL~ and i~ is ready for transmission. As previously discussed in EIG. 5, data packets in HPQ memory 204 are given priority over data packets in LPQ memory 203. Thus, as soon as a data packet is transmitted from LPQ memory 203, trunk control circuit 206 transmits any new data packets in H~
memory 204 before continuing to transmit the next data packet from LPQ memory 203~
Thereafter, as previously described in FIGs~ 2 and 3, using well kno~Jn circuitry channel framer circuit 207 of transmit control circuit 206 then formats the data packets into the format shown by 303. The channel framer circuit 207 may establish frame size when one of the following conditions occur. The frame length can be set when both the LP~ or HPQ memories are emPty, when the HPQ memory is empty, or when the frame has reached a ~rede~ermined length. Obviously, other criteria of conditions could be utilized to determine frame size.
The data frames may also be formatted into the HDLC or other standard form by the USART 208 and then outputted.
Mote, if the data enveloPes (~PQ1, LFQ1, etc., of 303) are not the standard byte size (i.e., 8 bits long) a byte stuffing algorithm is required as part of transmit control circuit 206~ The USART 208 receives the data frame one byte at a time in parallel from the transmit control circuit 206 and transmits the data packe~ frames serially over standard interface 21Q to trunk 103.
With reference PrimarilY to FIG. 2, data is received by the receive part of USART 208. The USART 208 receives the HDLC frames from trunk 103 via standard interface 210 ~nd when a frame is com~letely received the USA~T appends a status byte to indicate whether -there were any errors associated with that frame~ The status byte is examined br ~he recei2~ frame status check ci~cuit 212 and ' ~ ' .
if there is any error that frame i5 discarded by generating and sending a rejec~ slynal REJ to receive FIFC 213. If there are no errors, the frame is accepted by generating and sending an accept ACC signa~ to receive FIF~ 2130 Subseyuently, frame disassernbly circuit 214 disassembles the frame into data packets and converts the data to the format compatib~e with the bus interface circuit 2010 Basically, frame disassembly circuit 214 uses the length fields of the frame (e.g., see frame 303) to determine packet boundaries. The length field enables the circuit to separate data packets, each data packet is then marked with null envelope separating the packets.
These lisassembled data packets are then loaded into transmit FIFO 215 for transmission via bus interface 201 to the TBus of trunk circuit 108.
It is anticipated that many other well known circuits can be utilized to implement some or all of the circuitry and functions of the presen~ invention. ~1hile the present memory circuit invention is implemented using complementary metal o~ide semiconductor (CMOS) technology it is anticipated that other embodiments using any of the well known discrete, hybrid or integrated circui~
technigues can be utilized. Additionally, substantial parts of the functions provided in trunk circuit, particularly the logic and memor~ circuitry, can be implemented in software or using a microprocessor and associated firmware. Finally, while the present invention is described as being utilized in a trunk circuit for interfacing to a trunk, it more generally can be utilized ~ith any tYPe communication line.
While the present invention counts the number of data packets stored in the lo~ prioritY queue, ~ith a straightforward modification we could count the number of data packets stored in both the low and high priority queues. Whenever a packet is removed from either queue, the count would then be decremented. hs a result, a data source ~hich generates a stream of small data packets is ~S~8~7~3 prevented from obtaining priority service under heavy loads when packet queuein~ ~ccurs~
Thus, ~hat has been disclosed is merely illustrative of the present invention and other arran~ements or methods can be implemented by those skilled in the art without departing from the spirit and scope of the present invention.
. , , ~ .
T___ni_a1_F_el,d This invention rela-tes to packet switching networks and, more particularly, to a trunk circuit for interconnecting two packet s~itch nodes over a communication trunk.
Back~round of_the Invention Interactive terminals and other data devices typically transmit information in intermittent bursts.
~acket switching systems, including some local area networks (LAN), enable efficient communica~ions between different data devices, connected together over a data bus, by breaking up the bursty data transmissions into short data packets and by multiplexing together the data packets from several different data devices onto the data bus. The location of a pacXet switching system is often referred to as a node. ~1hen internodal data communication is reguired, a trunk circuit is utilized to interface the packet nodes to the private or public facilities (trunks) which interconnect the nodes. The design of such trunk circuits or wodules for interfacing wideband nodes via low-speed data trunks requires the consideration of the associated queueing delays on the trunk, particularly for interactive da~a messages. One known arrangement ~described in the article entitled "Queueing and Framing Disci~lines For a Mixture of Data Traffic Types"j authored by A. ~ Fraser and S. P. ~organ and published in the AT~_Bell_L_bora o_le_ Technical Journ_l, July August 1984, Vol. 63, No. 6, Part 2) utilizes a queueing discipline whereby short interactive data messages are given priority over longer data messages. That arrangement, however, re~uires separate data queues for each data channel of the trunk circuit. To keep trunk :
.
: . .
7~
circuit cost low these queues are implemented in soft~are rather than in hardware circuits.
Summary of the Invention In accordance with one aspect of the invention there is provided a data packet sorter for interfaciny a received multichannel packet data stream to a communication line, said sorter comprisiny means for sorting received multichannel data packets equal ~o or greater than a predetermined size Eor storage in a first memory and for sorting multichannel data packets less than said predetermined size for storage in said first memory in response to a signal from an associated channel counter indicating that the count is not zero; and counter means including a channel counter associated with each channel of the received multichannel packet data stream for counting, for each channel, the number of data packets written into said first memory by incrementing said associated channel counter for each data packet written into said first memory and decrementing the associated channel counter for each data packet read from said first memory.
In accordance with another aspect of the invention there is provided a method of sorting a received multichannel packet data stream for transmission over a communication line, the method comprising the steps oE:
sorting multichannel data packets e~ual to or greater than a predetermined size for storage in a first memory and for sorting multichannel data packets less than said predetermined size for storage in said first memory in response to a signal from an associated channel counter indicating that the count is not zero; and counting, Eor each channel o~ the received multichannel packet data stream, the number of data packets written into said ~irst memory by incrementing an associated channel counter for each data packet written into said first memory and decrementing the associated channel counter for each data packet read from said first memory.
a~
- 2a -According to the present invention, a trunk circuit packet sorter utilizes only one high priority queue (HPQ) memory and one low priority data ~ueue (LP~) memory for all of the data channels of ~he trunk circui~, and requires a separate LPQ counter for each data channel. Each LPQ channel counter keeps track of data from the associated channel which is stored in the LPQ
memory. The packet sorter sorts data packets accordiny to size. Small data packets, less than a predetermined length, from each data channel are sorted for storage in the HPQ memory only when the LPQ counter associated with that data channel is zero. That is, a smaller data packet from a channel is stored in the HPQ memory when there is no data from that channel in the LPQ memory. Small data packets having a non-zero LPQ channel count and large data packets are stored in the LPQ memory. This assures that data packets from the same channel will not be ~ransmitted out of order.
The packet sorter is part of the trunk circuit which enables internodal data transmission over a trunk ~acility. The trunk circuit transmits data packets from the LPQ memory only after having transmitted all of the data packets from the HPQ memory. Data packets are grouped together ~o form a data frame for transmission over the trunk facility.
Brief Description of the Drawing The characteristics and operation of the present invention will be more apparent from the following detailed description taken in conjunction with the drawing in which:
FIG. 1 shows the application of a trunk circuit interfacing a trunk facility to a node;
FIG. 2 shows a block diagram of the trunk circuit;
FIG. ~ sho-"s the da-ta f~rmat utilized by the trunk circuit;
FI~. 4 shows a flou chart de~cribing the operation of the packet sorter of the trunk circui.t, FIG. ~ shows a flow chart describing the memor~
ead operation of the trunk circuit; and FIG. 6 shows a block diagram of ~he transmit part of the trunk circuit.
Detail_d Descri2t___ Sho~n in EIG. 1 is an illustrative application o a trunk circui~ useful for interfacing nodes 101 and 1n~ to an internodal trunk facility 103. The nodes 101 and 102 may be a packet switching system or more specifically a local area network (LAN) which interconnects nodes, concentrators and devices (such as terminals, computers, workstations, host printers, etc.~.
Such an LAN is described in the article entitled "A New Local ~rea Network Architecture Using A Centralized Bus", authored by Anthony S~ Rcampora and Michael G. Hluchyj and published in the IEEE_Communication Ma~a~ine, Augus~ 1984, VolO 22, No. 8~
As FIG. 1 shows, a node also contains a clock module 104, a switch module 105, a control module 106, a device interface module 107 and trunk interface module 108 (also referred to as a trunk circuit) along with ~he transmit, broadcast, and contention data busses. The clock module 104 is responsible for system timing, switch module 105 translates a data source address to a data destination address under control of control module 106.
The contention bus is used b~ the interface modules (107, 108) to gain access to the time-slot multiplexed transmit bus. The transmit bus and broadcast bus are used for sending and receiving packets, respect.i~ely. The header of each source packet 110 ~laced on the transmit bus by an interface module contains a source addre.ss consisting of a module number followed by a channel number. The module numbsr uniquel~ identifies the transmittln~ interface 37~) .. ..
module, and the channel number is used to distinguish among the different conversations passing through that module.
As FIG. 1 shous, each packet placed on the transmit bus is removed by the switch module 105 ,/hich translates the source module and channel Du,nbers to the destination module and channel numbers on the destination packet 111. The specific translation is esta~lished by a prior call-set-up procedure. ~he packet is then retransmitted on the broadcast b~s where it is re~eived by the specified destination module. In this waY, a virtual circuit transport mechanism is implemented, wherein common control processor 106 at node 101 handles call step-up and take-down along with necessary maintenance and administration functions.
Assume a data transmission from device 114 of node 101 to device 113 of node 102. The user enters data into device 114 which is then transmitted to device interface module 107 where it contends for transmission time on the transmit bus. '~hen device 114 gets a chance to transmit, it sends a source packet 110 over the transmit bus to s~itch 105 which translates the source module address and channel number to the address of trunk circuit 108 and perhaps a new channel number. Trunk circuit 108 receives the data Packet over the desi~nated channel along ~ith other data Packets on other channels.
In accordance ~ith the present invention, trunk circuit 108 combines the data packets for transmission over trunX facility 103 to node 102. At node 102 the data packets are received by another trunk circuit 112~ In a similar manner as previously described, trunk circuit 112 transmits the data via the circuits 115 of node 102 to device 113. Once the user at device 11LI of node 101 is throuqh transmitting, a signal is sent to control module 106, which in turn informs the switchin~ module 105 to taXe down the connection, and control module 106 informs the control module of node 102 as well.
3t~
The transmission rate betwee~ r.odes 101 and 102 depends upon the type of trunk facility 103 emploYed.
When trunk facility 103 is a lo~-speed, data facility, such as digital data system (~DS) trunks, efficien~ data transmission requires that the trunk ci~cuits 108, 112 utilize efficient queueiny disciplines~ This is particularly impor-tant when the devices communicate using interactive "bursty" type of data, such as when terminals communicate with computers. As will be described in the following paragraphs, the present in~ention utllizes a ~ueueing discipline which assures that the interactive messages get priority over and are interspersed with bulk message data (for example, a file transfer) in such a way that delay requirements for mixed data ty~es are met even when the trunk is heavily used.
In the following description, ~hen an element has an associated reference number, the figure ~here that referenced element is first referenced is the first digit of the reference number. Thus, for example, memory 203 is first referenced in FIG. ~.
Shown in FIG. 2 is a functional block diagram of trunk circuit 108. In a well-known manner, interface 201 interfaces trunk circuit 108 to the transmit bus TBUS and contention bus as well as to the broadcast bus BBU~ shown in FIG. 1~ The data format at different locations of the trunk circuit 108 is illustrated in FIG. 3. The data packets on the broadcast bus BBUS, illustrated by format 301, includes a module number, a channel number and 16 data envelopes. When the module number of the data packet 301 designates trunk circuit 108 to receive the data packet, bus interface 201 does a parity check on the data packet. If the data packet is error-free then, as shown by format 302, interface 201 strips off the module number and eliminates all null data envelopes. A sin~le null envelope is appended which indicates the end of the data~packet.
~5~3'7~
The operation of data packet sorter 202 makes reference to the flo~ chart shown in FIG. L~ . The data packet sorter circuit 202 receives data packets~ 400, and compares the numher of data envelopes in the recei~ed data packets against a predetermined size N. ~ote, a data packet contains data from only one channel. If the number of data envelopes in a received data packet is smaller than N, the LPQ channel packet counter for the channel number associated ~ith the received data packet is checked, 402, for a zero count. If the LFQ channel packet counter 205 is zero the data packet is written into the HPQ memory 204 in step 403. However, if the data packet has less than N bytes and LPQ channel packet count 205 is not zero, it is written into the LPQ memory and the LPQ
packet counter is incremented 405. Finally, if the data packet has N or more bytes it is stored in LPQ memorY 203, in step 404, and the LPQ channel counter 205 is incremented in step 405.
The present data sorter maintains data se~uence in each channel even when the data from one channel is in both the ~PQ memorY and HPQ memory, providiny that all new data from a channel goes into the LPQ memorY as long as any data from the channel is stored in the LPQ memory.
Both LPQ memory 203 and HFQ memorY 204 may be implemented using any of the well known varieties of first-in-first~
out (FIFO)-tYpe memory chips. Because HPQ memory 2n4 holds the shorter data messages it would probably be of much smaller size than the LPQ memory 203.
The transmit control circuit 206 reads data packets from the LPQ memory 203 and HPQ melnory 204 and assembles them in channel framer circu~t 207. ~his operation is described by the flow chart shown in FIG. 5.
After the transmit control circuit 206 starts, in step 500, it checks, in step 501, if HP~ memorY 204 is emp~y, i.e., no data packets therein. If HPQ meinorY 204;
is not empty, a data packet is read, 502, and the Process (500, 501, 502) continues until all data packets are read.
~5~3t7~3 ~hen HPQ memory 204 is empty, the LPQ memo~y 203 is checked in step 5~3. I~ the I~Q memory is elnpty the transmit control circuit 206 returns to start location 500 and cycles throuyh steps 500, 5C~1 and 503 ur,til eitner the LPQ or HPQ memory is not empty~
If LPQ memory 2~)3 has data packets ~hey are read one at a time, 504~ and the LPQ per channel counter associated with that data pachet is decremented, 505.
Thereafter control returns to step 500 and then the HPQ
memory is again checked, step 501. Thus, the HPQ
memory 204 is checked, step 501, after each LP~ memorY
read, step 505, to assure that the high priority data packets of ~PQ memory 204 are transmitted prior to the low priority data packets of LPQ memory 203r Assuming that HPQ memory is empty, the sequence of steps 500, 501, 503, 504 and ~05 continues until all data packets are read from LPQ memory 203 ~ It sh~uld be noted that if transmit control circuit 206 is in the process of removing a data packet from LPQ memory 203 and a ne~ data packet arrives in the empty HPQ memorY 204r it completes the removal of the data packet from LPQ
memory 203 and then begins serving HPQ memory 204 and continues to do so until H~Q memorY 204 is empty.
Transmit control circuit 206 includes a channel framer 207 which receives the data packets from LPQ and HPQ memories and formats them into a data frame for transfer to a universal synchronous asynchronous receive transmit circuit (USART~ 20~. The USART transmits the data frame to trunk facility 103.
The channel framin~ for the trunk circuit could utilize any of the ~ell knoYn formats. The disclosed trunk circuit utilizes a mixed frame, i.e., LP~ and HPQ
data packets are mixed together in a frameO ComPlete packets are transmitted over the trunk until the total number of transmitted bytes exceeds some maximum value.
Different maximum fram~ lengths can be specified depending on uhether the frame contains data from the HPQ (e.g., 7~3 256-~yte limit for frames containing only LPQ pacXe-ts, 64-~yte limit for frames containing one or more HPQ
packets).
As shown in 303, as each data Facket from HPQ
memory 204 is read, the data ~ytes (HP~1-HP~J) are counted and packaged together with the channel number (chan ~) and packet length (len B) to form data packet PK1 of 304.
Similarly, as each data packet from LPQ memor~ 2G3 is read, the data bytes (LPQ1~LPQK) are counted and packaged together with the channel number (chan A) and packet length (len A) to form data packet PX2 of 304, It should be noted that while data pacJcets are discussed herein as including data bytes o 8 bits, in general the data packets can more generally include data envelopes of any bit length.
As shown in 304, data paclcets PK1-PKZ are assembled together with a flag, status, and error detection code CRC to form a data frame (Frame Y) of 305.
Note the length OI data Packets PK1-PKZ and data frames Y-1, Y, Y+1, are different. Data frame lengths can be predetermined so as to control system efficiency and delay characteristics. GenerallY long frames increase efficiency and short frames decrease frame delays. A
sor~ed framing discipline can also be utilized by the present trunk circuit whereby ~PQ and HPQ data packets may be combined to form a frame, but any LP~ data packet is Prevented from bein~ added to a frame that contains any HPQ data packets.
As shown in FIG~ 2, the transmit part of the trunk circuit (FIG. 6~ includes a Packet sorter 202, IPQ
memory 203, HPQ memory 204, and transmit controller 206.
As shown in FIG. 6, the packet sorter 202 includes ~er channel counter 205 and memorY storing logic 216, which is shown as every circuit in 202 which is not part of Per channel counter 205. In FIG. 6, transmit controller 206 includes control circuit 624, channel framer 207 and a variety of registers.
, .
B7~J
~ 9 _ The remaining detailed descrip~ion of trunk circuit 1Q8 makes joint reference to FIGs. ~, 3 and 6.
Data packets arriving over broadcast bus (BB7JS) are serîally loaded into bus inter-face 201 and then loaded 5 into buEfer 601 in parallel over leads D0-D8 using the data ~rite '~JR siynal. As the data packet 302 is loaded into buffer 601 a length counter 602 is increlnented by si~nal WR to compute the number of envelopes in that data packet. ~When the data packet is completely received, the 10 contents of the length counter 602 are transferred into the length register 603 making the length counter 602 available for the next data packet.
At this time, the first data byte in the packet, the channel number of 302, is transferred simultaneously 15 from buffer 601 into the data register 604 and into the channel counter 605. The end of packet circuit 623 detects if the data byte in buffer 601 is the null byte which separates data packets. A null signal is outputted to transmit control circuit 206 to prevent the null byte 20 from being stored.
At this point the packet sorter decides to which memory tLPQ or H~Q) the packet is to be routed. To do that, first the contents LEN of length register 603 are compared in comparator 606 to a predetermined threshold 25 value X se-t in unit 615. The threshold X can be set using a dip switch. If the contents LEN of length register 603 is less than the threshold X, that indication is set in data packet size flip-flop 607. The signal SML out of flip-flop 607 indicates that a small data packet is 30 received. At the same time, ths channel number in channel counter 6P5 is used to address a particular location in the per channel count memory 608. Memory ~;08 has a location for storing the count for each Possible channel number of a data packet. The contents of the addressed 35 memory location, which contains the number of packets stored in LPQ memory for that channel number, is transferred into D counter 609. Counter 609 outputs a . .
, :
3~713 - lC -signal FC~T indicatin~ when -t~e counter value is ~'c its maximum ~e.g~, ~55) and signal ZCNT indicating when the counter value is 0.
Gate 611 provides a da-ta packet load signal HPL
to HPQ memory 204 in response to ~hree slgnals. The three signals include the zero count signal (ZC~1T) for that channel o t~ne I.PÇ memoryi the si.gnal S~L indicating a small data packet was received; and the signal HPF*
indicating that the high prioritY queue 204 is not full.
When the ~hree conditions are ,~et, AND gate 611 generates load signal HPL to load the data from data register 604 into high Priori~y gueue 204. If no load signal HPL is generated, the data is not loaded in the HPQ memory 204 and trunk circuit 108 determines if the data should be loaded into the LPQ memory 203 or discarded. When load signal HPL is at lo~ic 0, inverter 515 enables AND gate 614.
At this point, the second memory full channel si~nal FCNT from counter 60g indicates whether the per channel count of that channel number is at its maximum value 255. If the count is 255, then signal FCNT disables gate 614, via NOR gate 613~ from generating a load signal LPL for T.pQ memory 203 and hence no more data for that channel number can be accepted into the lo~ priority queue 203. Hence, signal FCNT prevents data from that channel nu~lber from being written into the low Priority queue 203 and hence the data packet is discarded. ~ote, it is discarded in data register G04 by being written over b~ the next data ~ord from buffer 601.
If the full count FCNT of that channel number has not been reached then the high water mark signal, HWM, from the low priority queue 203 is checked. The HWM
signal indicates that the LPQ memory 203 is almost full and hence no new data Packets should be written into LPQ 203~ I the HWM signal is set (logic 1), then trunk circuit 108 discards new data packets arrivin~ for all new channel numbers. Note, a new channel nulnber is determined ~5,.~'~'7(7 wnen the ~ero count siqnal ZC~T is logic 1 for tnat channel. There~ore, if ZC~IT and ~ are ~)oth l~gic 1, indica-ting, respectivel~, a ne,l channel and a LPQ
memory 203 that is allnost full, AND gat~ 612 is *nabled gatin~ a signal, through NOP gate 613, which inhlbits gate S14 from generating a lGad signal LPL. If the data packets are n~-t from a new channel ~hen signal ZC~T is not at logic 1. Consequently, AND gate 614 is ena~led by gates 612, 613 and load signal LPL is generated causing the data packet to be loaded into the L~Q memory 203.
~ hen the data packet is loaded into the L~Q
memory 203, -transmit control circuit 206 generates signal IC~T which causes channel counter 605 to increment its count for the chann2l number associated with that data packet. ~hen the data packet is subsequently removed from the LPQ memory 203, the corresponding channel number is loaded from transmit register 619 into channel counter 605 and transmit control circuit 206 generates a signal DCNT
~hich decrements the count in counter 605 for that channel number.
Memories IPQ and HPQ each have a status register, 617 and 618, respectively, which indicates the status of each memorY. Register 618 of HPQ memory 204 generates output ready signal ORH and new data packet available signal NPAH. Similarly, register 617 of LPQ
memory 203 ~enerates output ready signal ORL and new data packet available signal NPAL. ~henever signal ORH is logic 1, it indicates that a data packet is available and transmit control circuit 206 causes data to be read from HPQ memorY 204 and into the high queue HQ register 621 and transferred into the transmit register 619 for subsequent transmission into USART 208. When signal ORH is not logic 1 the transmit control circuit 206 examines the state of signal ORL. When signal ORL is logic 1 data is read from LPQ memory 203 and into low queue LQ
register 622 and transferred into transmit register 61g.
~;~tj~
Transmit control circui~ 206 continlJeS reading data from LPQ memory 203 until a new packet signal NPhH i5 received. A NPh~ signal indicates that a new data pac~.et has arrived in HQP memory 2QL~ and i~ is ready for transmission. As previously discussed in EIG. 5, data packets in HPQ memory 204 are given priority over data packets in LPQ memory 203. Thus, as soon as a data packet is transmitted from LPQ memory 203, trunk control circuit 206 transmits any new data packets in H~
memory 204 before continuing to transmit the next data packet from LPQ memory 203~
Thereafter, as previously described in FIGs~ 2 and 3, using well kno~Jn circuitry channel framer circuit 207 of transmit control circuit 206 then formats the data packets into the format shown by 303. The channel framer circuit 207 may establish frame size when one of the following conditions occur. The frame length can be set when both the LP~ or HPQ memories are emPty, when the HPQ memory is empty, or when the frame has reached a ~rede~ermined length. Obviously, other criteria of conditions could be utilized to determine frame size.
The data frames may also be formatted into the HDLC or other standard form by the USART 208 and then outputted.
Mote, if the data enveloPes (~PQ1, LFQ1, etc., of 303) are not the standard byte size (i.e., 8 bits long) a byte stuffing algorithm is required as part of transmit control circuit 206~ The USART 208 receives the data frame one byte at a time in parallel from the transmit control circuit 206 and transmits the data packe~ frames serially over standard interface 21Q to trunk 103.
With reference PrimarilY to FIG. 2, data is received by the receive part of USART 208. The USART 208 receives the HDLC frames from trunk 103 via standard interface 210 ~nd when a frame is com~letely received the USA~T appends a status byte to indicate whether -there were any errors associated with that frame~ The status byte is examined br ~he recei2~ frame status check ci~cuit 212 and ' ~ ' .
if there is any error that frame i5 discarded by generating and sending a rejec~ slynal REJ to receive FIFC 213. If there are no errors, the frame is accepted by generating and sending an accept ACC signa~ to receive FIF~ 2130 Subseyuently, frame disassernbly circuit 214 disassembles the frame into data packets and converts the data to the format compatib~e with the bus interface circuit 2010 Basically, frame disassembly circuit 214 uses the length fields of the frame (e.g., see frame 303) to determine packet boundaries. The length field enables the circuit to separate data packets, each data packet is then marked with null envelope separating the packets.
These lisassembled data packets are then loaded into transmit FIFO 215 for transmission via bus interface 201 to the TBus of trunk circuit 108.
It is anticipated that many other well known circuits can be utilized to implement some or all of the circuitry and functions of the presen~ invention. ~1hile the present memory circuit invention is implemented using complementary metal o~ide semiconductor (CMOS) technology it is anticipated that other embodiments using any of the well known discrete, hybrid or integrated circui~
technigues can be utilized. Additionally, substantial parts of the functions provided in trunk circuit, particularly the logic and memor~ circuitry, can be implemented in software or using a microprocessor and associated firmware. Finally, while the present invention is described as being utilized in a trunk circuit for interfacing to a trunk, it more generally can be utilized ~ith any tYPe communication line.
While the present invention counts the number of data packets stored in the lo~ prioritY queue, ~ith a straightforward modification we could count the number of data packets stored in both the low and high priority queues. Whenever a packet is removed from either queue, the count would then be decremented. hs a result, a data source ~hich generates a stream of small data packets is ~S~8~7~3 prevented from obtaining priority service under heavy loads when packet queuein~ ~ccurs~
Thus, ~hat has been disclosed is merely illustrative of the present invention and other arran~ements or methods can be implemented by those skilled in the art without departing from the spirit and scope of the present invention.
. , , ~ .
Claims (12)
1. A data packet sorter for interfacing a received multichannel packet data stream to a communication line, said sorter comprising means for sorting received multichannel data packets equal to or greater than a predetermined size for storage in a first memory and for sorting multichannel data packets less than said predetermined size for storage in said first memory in response to a signal from an associated channel counter indicating that the count is not zero; and counter means including a channel counter associated with each channel of the received multichannel packet data stream for counting, for each channel, the number of data packets written into said first memory by incrementing said associated channel counter for each data packet written into said first memory and decrementing the associated channel counter for each data packet read from said first memory.
2. The data packet sorter of claim 1 wherein said sorting means includes means for storing said multichannel data packets less than said predetermined size in a second memory in response to a zero count signal from the associated channel counter.
3. The data packet sorter of claim 2 wherein said counter means further counts all data packets written into said second memory and decrements when each data packet is read from said second memory.
4. A trunk circuit for interfacing a received multichannel packet data stream to a communication trunk, said trunk circuit comprising a first memory;
a second memory;
means for sorting multichannel data packets equal to or greater than a predetermined size for storage in said first memory and for sorting multichannel data packets less than said predetermined size in said first memory in response to a signal from an associated channel counter indicating that the count is not zero;
means for storing said multichannel data packets less than said predetermined size in said second memory in response to a zero count signal from the associated channel counter;
counter means including a channel counter associated with each channel of said received multichannel packet data stream for counting, for each channel, the number of data packets written into said first memory by incrementing said associated channel counter for each data packet written into said first memory and decrementing the associated channel counter for each data packet read from said first memory; and means for reading a data packet from said first memory only after having first read all of the data packets from said second memory.
a second memory;
means for sorting multichannel data packets equal to or greater than a predetermined size for storage in said first memory and for sorting multichannel data packets less than said predetermined size in said first memory in response to a signal from an associated channel counter indicating that the count is not zero;
means for storing said multichannel data packets less than said predetermined size in said second memory in response to a zero count signal from the associated channel counter;
counter means including a channel counter associated with each channel of said received multichannel packet data stream for counting, for each channel, the number of data packets written into said first memory by incrementing said associated channel counter for each data packet written into said first memory and decrementing the associated channel counter for each data packet read from said first memory; and means for reading a data packet from said first memory only after having first read all of the data packets from said second memory.
5. The trunk circuit of claim 4 further comprising a framing means for grouping data packets read from said first and said second memories into a data frame for output to said communication trunk.
6. The trunk circuit of claim 5 wherein said framing means further includes means for setting the frame length at a first predetermined number of data bytes when the data includes only data packets from said second memory and for setting the frame length at a second predetermined number of data bytes when the data includes data packets from both said first and second memories.
7. The trunk circuit of claim 4 wherein said second memory generates a full memory signal and wherein said sorting means is responsive to said full memory signal for storing all data packets in said first memory.
8. The trunk circuit of claim 4 wherein said first memory generates a high water mark signal indicating that said first memory is almost full and wherein said sorting means is responsive to said high water mark signal and a zero count signal from the channel counter means associated with a received data packet for inhibiting the writing of the received data packet into said first memory.
9. The trunk circuit of claim 4 wherein said associated channel counter means generates a full count signal when the number of data packets stored in said first memory for a channel exceeds a predetermined limit and wherein said sorting means is responsive to said full count signal for disabling the writing of any data packets from the full channel into said first memory.
10. A method of sorting a received multichannel packet data stream for transmission over a communication line, the method comprising the steps of:
sorting multichannel data packets equal to or greater than a predetermined size for storage in a first memory and for sorting multichannel data packets less than said predetermined size for storage in said first memory in response to a signal from an associated channel counter indicating that the count is not zero; and counting, for each channel of the received multichannel packet data stream, the number of data packets written into said first memory by incrementing an associated channel counter for each data packet written into said first memory and decrementing the associated channel counter for each data packet read from said first memory.
sorting multichannel data packets equal to or greater than a predetermined size for storage in a first memory and for sorting multichannel data packets less than said predetermined size for storage in said first memory in response to a signal from an associated channel counter indicating that the count is not zero; and counting, for each channel of the received multichannel packet data stream, the number of data packets written into said first memory by incrementing an associated channel counter for each data packet written into said first memory and decrementing the associated channel counter for each data packet read from said first memory.
11. The method of sorting of claim 10 wherein said sorting step includes the step of:
writing said data packets less than said predetermined size in a second memory when the associated channel counter is zero.
writing said data packets less than said predetermined size in a second memory when the associated channel counter is zero.
12. A method of operating a trunk circuit for interfacing a received multichannel packet data stream to a communication trunk, the method comprising the steps of:
sorting multichannel data packets equal to or greater than a predetermined size for storage in a first memory and for sorting multichannel data packets less than said predetermined size for storage in said first memory in response to a signal from an associated channel counter indicating that the count is not zero;
storing said multichannel data packets less than said predetermined size in a second memory in response to a zero count signal from the associated channel counter;
counting, for each channel of the received multichannel packet data stream, the number of data packets written into said first memory by incrementing said associated channel counter for each data packet written into said first memory and decrementing the associated channel counter for each data packet read from said first memory; and reading a data packet from said first memory only after having first read all of the data packets from said second memory.
sorting multichannel data packets equal to or greater than a predetermined size for storage in a first memory and for sorting multichannel data packets less than said predetermined size for storage in said first memory in response to a signal from an associated channel counter indicating that the count is not zero;
storing said multichannel data packets less than said predetermined size in a second memory in response to a zero count signal from the associated channel counter;
counting, for each channel of the received multichannel packet data stream, the number of data packets written into said first memory by incrementing said associated channel counter for each data packet written into said first memory and decrementing the associated channel counter for each data packet read from said first memory; and reading a data packet from said first memory only after having first read all of the data packets from said second memory.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US730,995 | 1985-05-06 | ||
| US06/730,995 US4644533A (en) | 1985-05-06 | 1985-05-06 | Packet switch trunk circuit queueing arrangement |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1252870A true CA1252870A (en) | 1989-04-18 |
Family
ID=24937632
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000507812A Expired CA1252870A (en) | 1985-05-06 | 1986-04-29 | Packet switch trunk circuit queueing arrangement |
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| US (1) | US4644533A (en) |
| EP (1) | EP0201252B1 (en) |
| JP (1) | JPH0638609B2 (en) |
| KR (1) | KR910003243B1 (en) |
| CA (1) | CA1252870A (en) |
| DE (1) | DE3681756D1 (en) |
Families Citing this family (85)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4920534A (en) * | 1986-02-28 | 1990-04-24 | At&T Bell Laboratories | System for controllably eliminating bits from packet information field based on indicator in header and amount of data in packet buffer |
| US4780870A (en) * | 1986-09-05 | 1988-10-25 | American Telephone And Telegraph Company, At&T Bell Laboratories | Packet switch |
| GB2201066B (en) * | 1986-11-14 | 1991-08-21 | Fuji Xerox Co Ltd | Storage star network |
| US4910731A (en) * | 1987-07-15 | 1990-03-20 | Hitachi, Ltd. | Switching system and method of construction thereof |
| US5365519A (en) | 1991-03-05 | 1994-11-15 | Hitachi, Ltd. | ATM switch1ng system connectable to I/O links having different transmission rates |
| JP2569118B2 (en) * | 1987-07-15 | 1997-01-08 | 株式会社日立製作所 | Switching system and configuration method thereof |
| USRE36751E (en) * | 1987-07-15 | 2000-06-27 | Hitachi, Ltd. | ATM switching system connectable to I/O links having different transmission rates |
| FR2618279B1 (en) * | 1987-07-16 | 1989-10-20 | Quinquis Jean Paul | PRIORITY DATA PACKET SWITCHING SYSTEM. |
| US5285445A (en) * | 1987-12-17 | 1994-02-08 | U.S. Philips Corporation | Switching network and switching network control for a switching node in a wideband transmission system |
| US4821264A (en) * | 1988-02-04 | 1989-04-11 | Bell Communications Research, Inc. | Adaptive concentration communication network ISDN access |
| US4872159A (en) * | 1988-03-31 | 1989-10-03 | American Telephone And Telegraph Company At&T Bell Laboratories | Packet network architecture for providing rapid response time |
| DE68926795T2 (en) * | 1988-03-31 | 1997-01-09 | At & T Corp | Architecture and organization of a high-performance metropolitan data transmission network |
| IT1224493B (en) * | 1988-10-17 | 1990-10-04 | Cselt Centro Studi Lab Telecom | LABEL CONTROL AND SWITCHING INTERFACE FOR FAST SWITCHING OF ASYNCHRONOUS PACKAGE |
| US4914650A (en) * | 1988-12-06 | 1990-04-03 | American Telephone And Telegraph Company | Bandwidth allocation and congestion control scheme for an integrated voice and data network |
| US4916694A (en) * | 1988-12-22 | 1990-04-10 | Amp Incorporated | Packet network timing analyzer |
| US4953157A (en) * | 1989-04-19 | 1990-08-28 | American Telephone And Telegraph Company | Programmable data packet buffer prioritization arrangement |
| US5001706A (en) * | 1989-06-23 | 1991-03-19 | At&T Bell Laboratories | Packet cross connect switch system including improved throughput |
| US5042032A (en) * | 1989-06-23 | 1991-08-20 | At&T Bell Laboratories | Packet route scheduling in a packet cross connect switch system for periodic and statistical packets |
| US4979165A (en) * | 1989-06-23 | 1990-12-18 | At&T Bell Laboratories | Multiple queue bandwidth reservation packet system |
| US5020055A (en) * | 1989-06-23 | 1991-05-28 | May Jr Carl J | Multi-length packet format including fixed length information words |
| US5003535A (en) * | 1989-06-23 | 1991-03-26 | At&T Bell Laboratories | Packet synchronization utilizing a multi-length packet format including check sequences |
| US4962498A (en) * | 1989-06-23 | 1990-10-09 | At & T Bell Laboratories | Multi-length packet format including check sequence(s) |
| US5020054A (en) * | 1989-06-23 | 1991-05-28 | May Jr Carl J | Packet format including unique network identity |
| US5200864A (en) * | 1989-06-28 | 1993-04-06 | International Business Machines Corporation | Combining small records into a single record block for recording on a record media |
| US5274772A (en) * | 1989-06-28 | 1993-12-28 | International Business Machines Corporation | Data processing systems having means for selectively combining records into signal blocks for recording in a record medium |
| US5335328A (en) * | 1989-06-28 | 1994-08-02 | International Business Machines Corporation | Methods for recording and reading data from a record member having data in any one of a plurality of block formats including determining length of records being transferred |
| US5377332A (en) * | 1989-10-02 | 1994-12-27 | Data General Corporation | Bus arbitration algorithm and apparatus |
| US5166930A (en) * | 1990-12-17 | 1992-11-24 | At&T Bell Laboratories | Data channel scheduling discipline arrangement and method |
| US5224099A (en) * | 1991-05-17 | 1993-06-29 | Stratacom, Inc. | Circuitry and method for fair queuing and servicing cell traffic using hopcounts and traffic classes |
| US5313454A (en) * | 1992-04-01 | 1994-05-17 | Stratacom, Inc. | Congestion control for cell networks |
| JP2833387B2 (en) * | 1992-11-30 | 1998-12-09 | 日本電気株式会社 | Switch bus monitor circuit |
| US5797033A (en) * | 1995-03-31 | 1998-08-18 | Cirrus Logic, Inc. | Direct memory access for storing and retrieving data based on packet size |
| US6122281A (en) * | 1996-07-22 | 2000-09-19 | Cabletron Systems, Inc. | Method and apparatus for transmitting LAN data over a synchronous wide area network |
| US6370147B1 (en) | 1998-04-23 | 2002-04-09 | 3Com Corporation | Method for addressing of passive network hosts in a data-over-cable system |
| US6223222B1 (en) | 1998-05-14 | 2001-04-24 | 3Com Corporation | Method and system for providing quality-of-service in a data-over-cable system using configuration protocol messaging |
| US6636485B1 (en) | 1998-05-14 | 2003-10-21 | 3Com Corporation | Method and system for providing quality-of-service in a data-over-cable system |
| JP4111472B2 (en) | 1998-05-15 | 2008-07-02 | キヤノン株式会社 | COMMUNICATION CONTROL METHOD AND DEVICE AND COMMUNICATION SYSTEM |
| US6560203B1 (en) | 1998-05-27 | 2003-05-06 | 3Com Corporation | Method for changing type-of-service in a data-over-cable system |
| US6331987B1 (en) | 1998-05-27 | 2001-12-18 | 3Com Corporation | Method and system for bundling data in a data-over-cable system |
| US6775276B1 (en) | 1998-05-27 | 2004-08-10 | 3Com Corporation | Method and system for seamless address allocation in a data-over-cable system |
| US6510162B1 (en) | 1998-05-27 | 2003-01-21 | 3Com Corporation | System and method for managing channel usage in a data over cable system |
| US6442158B1 (en) | 1998-05-27 | 2002-08-27 | 3Com Corporation | Method and system for quality-of-service based data forwarding in a data-over-cable system |
| US6275853B1 (en) | 1998-05-27 | 2001-08-14 | 3Com Corporation | System and method for extending communications features using generic management information base objects |
| US6205150B1 (en) * | 1998-05-28 | 2001-03-20 | 3Com Corporation | Method of scheduling higher and lower priority data packets |
| US6885657B1 (en) * | 1998-11-30 | 2005-04-26 | Broadcom Corporation | Network telephony system |
| JP4109770B2 (en) * | 1998-12-02 | 2008-07-02 | キヤノン株式会社 | Communication control method and equipment |
| US6662135B1 (en) | 1998-12-09 | 2003-12-09 | 3Com Corporation | Method and apparatus for reflective mixer testing of a cable modem |
| US6657991B1 (en) | 1998-12-21 | 2003-12-02 | 3Com Corporation | Method and system for provisioning network addresses in a data-over-cable system |
| US6351773B1 (en) | 1998-12-21 | 2002-02-26 | 3Com Corporation | Methods for restricting access of network devices to subscription services in a data-over-cable system |
| US6986157B1 (en) | 1998-12-21 | 2006-01-10 | 3Com Corporation | Method and system for dynamic service registration in a data-over-cable system |
| US6577642B1 (en) | 1999-01-15 | 2003-06-10 | 3Com Corporation | Method and system for virtual network administration with a data-over cable system |
| US6490298B1 (en) | 1999-02-26 | 2002-12-03 | Harmonic Inc. | Apparatus and methods of multiplexing data to a communication channel |
| US7099338B1 (en) | 1999-02-27 | 2006-08-29 | 3Com Corporation | System and method for insuring dynamic host configuration protocol operation by a host connected to a data network |
| US6697862B1 (en) | 1999-05-21 | 2004-02-24 | 3Com Corporation | System and method for network address maintenance using dynamic host configuration protocol messages in a data-over-cable system |
| US6654387B1 (en) | 1999-05-21 | 2003-11-25 | 3Com Corporation | Method for network address table maintenance in a data-over-cable system using a network device registration procedure |
| US6754622B1 (en) | 1999-05-24 | 2004-06-22 | 3Com Corporation | Method for network address table maintenance in a data-over-cable system using destination reachibility |
| US6985437B1 (en) | 1999-05-25 | 2006-01-10 | 3Com Corporation | Method for dynamic performance optimization in a data-over-cable system |
| US6785292B1 (en) | 1999-05-28 | 2004-08-31 | 3Com Corporation | Method for detecting radio frequency impairments in a data-over-cable system |
| US7089580B1 (en) | 2000-03-29 | 2006-08-08 | 3Com Corporation | Method for improved cable modem ranging in a data-over-cable system |
| US6804262B1 (en) | 2000-04-28 | 2004-10-12 | 3Com Corporation | Method and apparatus for channel determination through power measurements |
| JP4713810B2 (en) * | 2000-05-02 | 2011-06-29 | セラヴァンス， インコーポレーテッド | Reductive alkylation process for glycopeptides |
| US6757738B1 (en) * | 2000-05-18 | 2004-06-29 | Nortel Networks Limited | Method and apparatus for improving channel utilization |
| US6944881B1 (en) | 2000-06-19 | 2005-09-13 | 3Com Corporation | Method for using an initial maintenance opportunity for non-contention ranging |
| US6816500B1 (en) | 2000-07-10 | 2004-11-09 | 3Com Corporation | Apparatus, method and system for multimedia access network channel management |
| US7107326B1 (en) | 2000-10-13 | 2006-09-12 | 3Com Corporation | Method and system for integrating IP address reservations with policy provisioning |
| US7068597B1 (en) | 2000-11-27 | 2006-06-27 | 3Com Corporation | System and method for automatic load balancing in a data-over-cable network |
| US6948184B1 (en) | 2000-11-30 | 2005-09-20 | 3Com Corporation | System and method for calibrating power level during initial ranging of a network client device |
| US6940874B2 (en) * | 2000-11-30 | 2005-09-06 | 3Com Corporation | Method for reducing interference from initializing network devices in a data-over-cable system |
| US6952428B1 (en) | 2001-01-26 | 2005-10-04 | 3Com Corporation | System and method for a specialized dynamic host configuration protocol proxy in a data-over-cable network |
| US7073055B1 (en) | 2001-02-22 | 2006-07-04 | 3Com Corporation | System and method for providing distributed and dynamic network services for remote access server users |
| US7222255B1 (en) | 2001-02-28 | 2007-05-22 | 3Com Corporation | System and method for network performance testing |
| US7088678B1 (en) | 2001-08-27 | 2006-08-08 | 3Com Corporation | System and method for traffic shaping based on generalized congestion and flow control |
| US7085306B1 (en) | 2001-10-30 | 2006-08-01 | 3Com Corporation | System and method for a multi-frequency upstream channel in a computer network |
| US7072337B1 (en) | 2002-01-25 | 2006-07-04 | 3Com Corporation | System and method for resolving network addresses for network devices on distributed network subnets |
| GB2386283A (en) * | 2002-03-05 | 2003-09-10 | Pa Consulting Services | Packet data communications network |
| US7570584B1 (en) | 2002-03-29 | 2009-08-04 | Cisco Technology, Inc. | Network-wide congestion control of SPVC signaling messages |
| US7447205B2 (en) | 2003-05-09 | 2008-11-04 | Hewlett-Packard Development Company, L.P. | Systems and methods to insert broadcast transactions into a fast data stream of transactions |
| US6996654B2 (en) | 2003-05-09 | 2006-02-07 | Hewlett-Packard Development Company, L.P. | Systems and methods for generating multiple transaction identifiers to reduced latency in computer architecture |
| US7114054B2 (en) | 2003-05-09 | 2006-09-26 | Hewlett-Packard Development Company, L.P. | Systems and methods for increasing transaction entries in a hardware queue |
| US20040225707A1 (en) * | 2003-05-09 | 2004-11-11 | Chong Huai-Ter Victor | Systems and methods for combining a slow data stream and a fast data stream into a single fast data stream |
| US8223966B2 (en) * | 2006-05-10 | 2012-07-17 | Mediatek Inc. | Multiple stream decrypting and decoding systems and related methods thereof |
| US7916731B2 (en) * | 2006-11-30 | 2011-03-29 | Broadcom Corporation | Method and system for efficient rapid loss detection in a bonding system |
| US9753691B2 (en) | 2013-03-15 | 2017-09-05 | Intel Corporation | Method for a stage optimized high speed adder |
| KR101763731B1 (en) * | 2013-03-15 | 2017-08-01 | 인텔 코포레이션 | A method for implementing a line speed interconnect structure |
| US11003459B2 (en) | 2013-03-15 | 2021-05-11 | Intel Corporation | Method for implementing a line speed interconnect structure |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57119542A (en) * | 1981-01-19 | 1982-07-26 | Nec Corp | Control station device |
| JPS58106933A (en) * | 1981-12-21 | 1983-06-25 | Fujitsu Ltd | Memory buffer reserving system |
| US4516238A (en) * | 1983-03-28 | 1985-05-07 | At&T Bell Laboratories | Self-routing switching network |
| US4542497A (en) * | 1983-03-28 | 1985-09-17 | At&T Bell Laboratories | Wideband digital switching network |
| US4472801A (en) * | 1983-03-28 | 1984-09-18 | At&T Bell Laboratories | Distributed prioritized concentrator |
| US4538259A (en) * | 1983-07-05 | 1985-08-27 | International Business Machines Corporation | System for digitized voice and data with means to compensate for variable path delays |
| US4583219A (en) * | 1984-07-16 | 1986-04-15 | At&T Bell Laboratories | Trunk for packet switching |
-
1985
- 1985-05-06 US US06/730,995 patent/US4644533A/en not_active Expired - Lifetime
-
1986
- 1986-04-28 EP EP86303181A patent/EP0201252B1/en not_active Expired - Lifetime
- 1986-04-28 DE DE8686303181T patent/DE3681756D1/en not_active Expired - Fee Related
- 1986-04-29 CA CA000507812A patent/CA1252870A/en not_active Expired
- 1986-05-06 JP JP61102227A patent/JPH0638609B2/en not_active Expired - Lifetime
- 1986-05-06 KR KR1019860003504A patent/KR910003243B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR910003243B1 (en) | 1991-05-24 |
| JPS61260742A (en) | 1986-11-18 |
| JPH0638609B2 (en) | 1994-05-18 |
| EP0201252A2 (en) | 1986-11-12 |
| EP0201252A3 (en) | 1988-01-13 |
| US4644533A (en) | 1987-02-17 |
| DE3681756D1 (en) | 1991-11-07 |
| EP0201252B1 (en) | 1991-10-02 |
| KR860009566A (en) | 1986-12-23 |
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