CA1256563A - Method and apparatus for simulating memory arrays in a logic simulation machine - Google Patents

Abstract

METHOD AND APPARATUS FOR SIMULATING MEMORY
ARRAYS IN A LOGIC SIMULATION MACHINE

ABSTRACT OF THE DISCLOSURE
A method and apparatus for simulating memory devices in a logic simulation machine. Both include a finite state machine (FSM) having input/output (I/O) sources, instruction storage resources, a real memory resource, and instruction execution resources. A plurality of memory device ports to be simulated are defined and associated with corresponding respective subsets of the I/O resources of the FSM.
Permutated sets of simulated memory array access signals, such as data, address, and control, are bound to selectable ones of the simulated memory ports and stored in the FSM, with the parameters of the memory operation established by the simulated signals. Stored sets of access instructions, representative of memory access operations, are augmented by the simulated signals and executed by the FSM against the real memory resource. All array instructions representing the same memory array share the same address space in the real memory resource.

Description

H~THOD AND APPARAT~S FOR SIM~LATING Me~oRy ARRAYS IN A LOGIC SIM~LATION MAC~IN~

~ACRGROUND OF ~E I~VENTION
This invention is concerned with the simulation of multi-port memory array operation by means of a special purpose processor utilizing simulated access signals provided by a logic simulation machine which produces signals representative of the operation of logic surrounding the simulated memory arrays.
Simulation is extensively used in the design of electronic loyic circuitsO Once a logic circuit's design has been reduced, its operation can be examined indirectly by means of a logic simulation machine (LSM) that operates to represent the operation of the circuit under a set of specified test conditions. The purpose of the machine simulation is to detect design errors in a simulated logic and enable the logic designer to correct the errors before manufacture of the design.
A particular logic simulation machine is described in a series of articles found in the Proceedings of the 1983 IEEE
International Conference on Computer Design. The articles are: ~Introduction to the I~M Los Gatos Logic Simulation Machine~ John R. ~oward et al, "The IBM Los Gatos Simulation Machine Hardware, n Ted Burggraff et al, "The IBM
Los ~atos Logic Simulation Machine Software, n Jack Rohn et al, and "Using the IBM Los Gatos Logic Simulation Machine, r John ~. Howard et al. The LSM described in those articles was first disclosed in United States Patent No7 4,360,286 of Cocke et al.

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~6~3 The LSM of U. S. Patent No. 4,360,286 is a highly parallel machine that incorporates a plurality of functionally equivalent processors, each able to simulate a portion of a logic network. The operations of the parallel processors are oxchestrated and integrated by means of a control unit including an interactive processor switch that provides connectivity between the processors and a control processor that exercises overall control of the machine and provides input/output and programming capability. The operation of the prior art LSM is based upon the execution in each of the parallel processors of a series of instructions, with each instruction initiating a machine operation step that corresponds to the operation of a single logic gate. The machine operates cyclically, with each basic cycle corresponding to a single updating of all signal values in a simulated logic gate.
~ hile extremely efficient in simulating logic circuits made up of discrete gates, the prior art LSM only awkwardly simulates memory arrays for the reason that the machine 20 simulation operates on the individual bits involved in logic gate operation. Therefore, for the prior art LSM to simulate, for example~ operation on each bit of an 8X32R
memory array, over 256,000 individual instructions would be required. Clearly~ the prior art logic simulator awaits an advance whereby multi-bit memory operation can be simulated by a minimal set of instructions. Preferably, each simulated memory reference would be implemented by a single instructîon.

~5~ 3 S~MMARY OF T~E INVENTION
The advance awaited by the prior LSM i~ realized in the invention by def ining a memory array access instruction (narray instructionn) that implements simulation of a memory reference operation and permitting it to operate on a plurality of simulated memory access signals. Each array instruction operates on its associated plurality of signals in a single instruction execution step to simulate a predefined memory re~erence at a particular port of a 10 simulated memory array, with the memory refer~nce parameters set by the simulated signals. In this context, the phrase "memory reference" denotes a memory read or write operation, while the term nmemory reference parameter" refers to the specific set of data, address, and memory control conditions under which the .~imulated memory reference is made~
The method of the invention simulates memory references made on a machine accessible memory array by execution upon a logic simulation machine in which an interfacing finite state machine ~SM) simulates at least one memory array.
The steps of the simulation method include defining one or more memory port names to correspond to a simulated memory array and associating the memory port names with corresponding respective subsets of the input/output tI/O) resources Qf the FSM. Memory array instructions defining simulated memory references are bound to selectable ones of the defined port names and stored in the FSM. Simulated memory access signals f rom the LSM are p~rmutatively entered into the respective I/O resource subsets according to a predetermined pattern that associates the si~nals wi~h particular ones of the memory access instructions. Finally, 5~3 the instruction sets are executed on the ~SM to simulate access to the memory array, using the associated memory access signal~ to establish the memory reference parameters of respective simulated operations.
The finite state machine of th invention is a pipeline processor intended to simulate operations on machine-accessible multl-port memory arrays in response to simulated memory access signals provided by a logic simulation machine. The processor includes a first permutating input~output (I/O) facility that receives simulated memory access siqnals during one machine operation cycle while providing permutated simulated memory access signals received during a previous machine operation cycle. A
programmable input permutation memory arranges the storage of received simulated memory access signals in respective subsets of the first permutating I~O facility in response to a predetermined programed permutation pattern. A
programmable simulation profile memory receives and stores array instructions defining a plurality of memory ~ort names ~hat are associated with corresponding respective subsets of the ~irst or a second permutatinq I/O storage facility~ The array instructions further define simulated memory references to be performed on simulated memory arrays that are defined by the port namesO A programmable output permutation memory extracts memory port output signals stored in ihe second permutative I/O facility in response to a predetermined programed permutation pattern. The processor also includes an array instruction execution circuit that recei~es the permutatively stored memory access signals from the first I/O resource and array instructions .

from the memory simulation profile memory; executes the received array instructions to simulate the performance o memory references on defined memory port names according to memory access parameters established by the received permutated memory access signals; and provides the simulated memory output signals.
Therefore, the primary objective of the present invention is to provide a method and means that simulate, ~y means of a single instruction, a memory reference involving a plurality of simulated memory access parameter si~nals.
This important objective and other objects and advantages of the present invention will become evident when the following detailed description is read in conn~ction with the below-described drawin~s.
BRIEF DESCRIPTION OF T~ DRA~INGS
Figure 1 is a bl~ck diagram illustrating a representative operational system environment of the invention~
Figure 2 is a schematic block diagram illustrating the primary functional zones of the invention.
Figure 3 is an illustration of a memory array simulated by the invention showing how port names are used to define the array.
Figure 4 is an illustra~ion of how the memory array simulation of Figure 3 is implemented by a combination of software and hardware in the invention.
~ igures SA and 5B are schematic block diagrams of the hardware embodiment of the invention.

Si63 . , . . . . ~ . ~ . . , Figure 6 illustrates clock wav~eforms that are used to synchronize the flow of data through the hardware embodimen~
of Figures 5A-5B in a pipeline fashion.
Figure 7 is a state diagram illustrating the operation of a real memory controller in the hardware embodiment of Figures 5A-5B.
Figure 8 is a timing diagram illustrating the pipelined operation of the hardware embodiment of Figures 5A-5~.
Figure 9 is a diagram illustrating the partitioning of the real memory of Figure 5B.
Figures 10A-10C illustrate partitioning, writing to, and reading from the AIN/BIN memory of Figure 5A.
Figures llA-llC illustrate partitioning, reading from~
and writing to the AOUT~BO~T memory of Figure 5B.
Figure 12 is a block diagram of write control and write address generation lo~ic of Figure 5Bo Figure 13 is a.waveform diagram illustrating operation o~ the logic of Figure 12.
Figure 14 is an illustration of a three-port memory device being simulated.
Figure 15 illustrates an exemplary set of array instructions for simulating the device of Figure 14~
~ igure 16 is a waveform diagram illustrating the operation of the invention in simulating ~he memory array of ~igure 14.
DETAILE:D DESCRIl?TIOea OE' TE~ PREFÆRRED EMsoDIM~NT
Logic simulation machines employing parallel processing technology to simulate the operation of logic circuits under design are known in the art. In this regard, reference is ~2~ 3 made to the four articles cited above. Figure 1 illustrates a block diagram of the LSM system described in the articles.
The LSM includes a control processor and a plurality of logic ~imulators. The control processor controls, schedules and synchronizes the various operations undertaken by the system in simulating the operation of a particular logic design. In addition, the control processor interfaces between the simulation system and a host/interface processor through which descriptions of logic desiyns and test patterns are entered in a high level programmin~ language.
The prior LSM host/interface processor includes a compiler that translates the high level design descriptions into a specific machine-understandable simulation program. As presented in the article cited above that is entitled "The lS IBM Los Gatos Logic Simulation Machine Softwaren, the prior art compiler includes the ability to interpret high level commands, assemble a list of instructions to implement the comman~s, and schedule allocation of the resources available on the LSM~
The resources of the LSM7 in addition to ~a control processor 10, include an inter-processor switch 12 and logic simulator processors 16, 18. The inter-processor switch 12 is an NXN crossbar that enables any one of the logic simulator processors to communicate with any other processor in the LSM.
The logic simulator processors 16, 18 are well understood and reference is made once again to the ~.S.
Patent 4,306,286 of Cocke et al. ~s described in the Cocke patent, the logic simulator processors 16, 18 operate in parallel to simulate particular portions of a simulated ~2~ i3 logic design and exchange simulated data ~ignals through the inter-processor switch 12~
To initiate a logic design simulation, the as6embled instructions are passed through the control processor 10, via the inter-processor ~witch 12 into instruction and data memories in specific ones of the processors 16, 18. As is known, the compiler possesses the ability not only to distribute instructions to the processors 16, 18, but also the ability to order those instructions within each processor and to schedule the inter-processor communications necessary to the simulation.
The basic LSM signal unit has four possible states which are encoded in two bits; a value bit and an undeined bit. The states are~ uninitialized, undefined, logical 0, and logical 1. The uninitialized state represents a signal state not initialized prior to simulation, or not yet computedt once simulation has begun. The other three states are the result of initialization prior to simulation or the result of instruction execution during simulation. In the discussion following, when the basic signalling unit is referred to as a bit~ it is to be understood that, in the posited operational environment, the bit includes the value and undefined bits of the Cocke LSM. However, it must be appreciated that, in other contexts, the below described invention can be adapted to other basic simulation signal units.
The invention resides in a memory simulator 20 that îs ~onnected to a logic simulation machine suoh as the prior art LSM of ~.S~ Patent 4,306l286~ The memory simulator 20 invests the LSM with the capability vf simulating multi-port _9_ memory arrays based on ~he particular structure and function of a programming and hardware construct~ m e benefit conferred on the prior art LSM by the invention can be appreciated when a typical logic design including an internal memory is simulated on a prior art LSM not including a memory simulator 20: such a simulation is done at the cost of one LSM instruction per memory storage space.
For example, in a logic design including a 32x32 bit memory, the prior art system would require 1024 LSM instructions to operate on all of the memory bits, which would consume the total operational capacity of one of the logic simulator processors 16, 18. Contrastin~ly, the memory simulator 20 can simulate the operation of the same memory by the use of a single instruction per memory port (that is, per Read or Write port~
Figure 2 illustrates the basic architecture of the memory array simulator 20. The memory array simulator 20 includes a simula~ion profile memory 22, an input data permutation circuit 24, array instruction execution 26, a real memory resource 30, and an output data permutation circuit 32. Also included in the simulator 20 is a conventional clock generation circuit (CLOCR ~EN) 33 that produces a number of clocks for synchronizing simulator operations with the LSM. A memory in a simulated logic design is represlnted by a series of memory array instructions entered into the simulation profile memory 22.
Each simulated memory is represented by as many memory array instructions as are needed ~o represent the read or write por s of ~hat memory~ In the preferred embodiment, each i3 memory array instruction models only a uniquely-named Read or Write port~
Data signal~ representing memory access parameters such as data to be written in the simulated memory, address data identifying the memory sector to be operated on, and control data indicating port or device selection is received from logic simulator processors and passed through the input data permutation circuit 24. The input data permutation circuit rearranges the simulated memory access parameter signals in such a manner as to associate respective signals with particular array instructions in the profile memory ~2. As described below, the input dat~ permutation circuit 24 permutes the simulated signals according to a permutation pattern that is entered into the circuit 24 at the time that the access instructions are entered into the memory ?2.
During operation of the memory simulator 20, simulated signals are combined with respective associated instructions in the instruc~ion execution assembly 26. The combined data assembled in the information execution assembly includes all of the simulated data, address and control ~formation necessary to enable the assembly to perform the simulated memory access operation against the real memory 30.
Simulated read operations cause data to be extracted ~rom the real memory 30 and passed through the output data permutation circuit 32 to various locations in the L5M. The output data permutation circuit also has embedded a permutation pattern that schedules the forwarding of the simulated read data to the LSM.
During an initial program load (IPL~ mode of operation, memory array instructions are entered into the simulation ;5~3 profile memory 22 and respective permutation patterns are lodged in the permutation circuits 24 and 32. During the simulation ~RUN) mode of operation, simulated memory accesæ
signals are received from and forwarded to the LSM tbrough the input and output data permutation circuits respectively.
As illustrated, all communications with LSM in the IPL and R~N modes are conducted through the inter-processor switch 12.
Refer now to Figures 3 and 4 for an understanding of how memory hardware is simulated in the invention by the use ~f memory array instructionsO Figure 3 represents a random access memory (RAM) that is to be simulated in connection with a particular logic design. As is conventional, the RAM
must have at least one address port A through which address data ~ADDATA~ are received to specify the resource storage sector(s) to be accessed. Access to the RAM is had by way of one or more write ports tWPORT) or read ports ~RPORT).
An access operation through a write port, of course, entails the entry of data through a specified write port into 20 memory ~ector identified by address data provide`a to the write port's associated address port. Data is conventionally extracted from an addressed sector of the RAM
thro~gh a specif ied read port. As is conventional, memory de~ice operation is gated by a chip ~or port) select signal, which is indicated by a control C signal provided through a select port of the RAM.
Assume that the RAM of Figure 3 is to possess three ~emory access ports, a read port RDPORT 1, a write port WPORT 1, and another write port, WPO~ 2. The group of memory array instructions that fully define the performance ~2S~3 o~ one memory reference through each port are three: array instruction 1, corresponding to a read opera~ion through RDPORT 1, array instruction 2, corresponding to a write operation through WPORT 1, and a third array instruction correspondi~g to a data entry operation to be conducted through WPORT 2.
The real memory 30 is used to provide authentic memory response to each memory access instruction to be performed during a simulation. The real memory is partitioned into as many sectors as there are memory devices to be simulated.
The array instructions representing a given memory device all map into the same partition sector of the real memory.
In most cases, all of the array instructions corresponding to a particular memory device are assigned a common real memory base address; the exceptions are discussed below.
Nhen a memory simulation is compiled, the real memory is sectioned to accommodate the memory devices to be simulated. Simulated data, address, and control signal values for each operation to be simulated on each memory are collected in the input data permutation circuit-~4. If a read or write operation is indicated by an associated memory array instruction, the memory simulator 20 performs the appropriate real memory access to a compound address consisting of the real memory base address for the sector assigned to the memory device and the address represented by the simulated address signals. If a memory read operation is simulated, data is obtained from the real memory locations indicated by the compound address and is staged through the output data permutation circuit 32.

i3 ~3-The RUN m~ e ~ op~ration of the memory simulator 20 i.sdivided in~o a sequ~n4e o~ cycles during ea~n o~ which all of the mem~ry array inst.:rUcti~ the simulation profilè
memory 22 are ~P~r~ d onc~. Simulated signal values representin!~ oata, addr~, and cOntrol bits are collected and arran~d in the input data pe.rmutatiOn circuit 24 d~ring one cycle and extracted and examined during the following cycle while another set of sim~llated signals -is being assembled. Read data obtained rom the real memory 30 during a cycle is held for the duratio~ of the cy~cle in the output data permutation circuit 22 and.-~orwarded to the inter-processor switch 12 the following cycle.
Refer now to Figures 5A and 5B and Figure ~ for a detailea~ cription of the structure and operation of the memory simulator ~0~ Memory access instructions ar- stored in and provided from an access instruction circuit incl.uding a si~ulation profile memory 40, an address counter and comparator 42, and an access instruction profile latch 44.
The simulation prcfile memory 40 is a 31 bit by 256 word memory that stores one 31 bit data word for each array instruction to be executed. The access instructions are read out of the simulation profile memory 40 in the sequence of their storage by an address counter and comparator circuit 42.
- The address counter and comparator circuit 42 includes an 8-bit register for receiving a binary number corresponding to the number of array instructions to be executed during each cycle of an on-going simulation. Even if the memory simulator 20 is not to be used during the on-going simulation, it must still receive an initial binary number corresponding to the number o~ refresh instructionsrequired by the real memory 30 during the simulation period.
The counter of the circuit 42 has tbe ability to count ~rom zero to the binary number representing the number of array instructions to be executed. The count output i~ used to address the simulation profile memory 40, and it will be appreciated that as the counter counts from zero to the binary number, the array instructions held in the memory 40 will be addres~ed in seguence during the count-up on the counter. The address counter and comparator circuit 42 further includes provision for comparing the current counter output with the received binary number. When the counter output equals the binary number value, the counter is ~topped. For so long as the counter output is less than the binary number representing the number of instructions, a signal on signal line 43 indicates that the current instruction addressed in the memory 40 is a valid instructionO When the counter output ~quals the binary value, the comparator output on line 43 indicates that there are no more instructions to execute. -~
As each array instruction is read out of the profilememory 401 it is entered into the array instruction prof ile latch 44. For an understanding of the array instruction format, the latch 44 includes a 32-bit register subdivided 25 into the format exhibited by each array instruction to be executed~ The first field (BASE ADDR) of an array instruction includes the base address in real memory that defines the storage sector dedicated to the memory device whose port the array instruction represents. In the preferred embodiment, the base address corresponds to 6~

address zero in the memory device being simulated. The next field ln an array instruction indicates the width of the address ~ield (A~DR WIDTH) of the memory device being simulated. For example~ an address width of 4 implies an address field for four bits, which define a me~ory device having the capacity to store sixteen words. This value is used by address generation logic described below when computing the real memory address to determine the number of address bits out of a predetermined maximum number of bits that are valid ~or a particular simulated memory device.
The array instruction RAM TYPE field indicates the type of array instruction being executea; preferably, the RAM
TYPE field consists of one bit in which one state indicates a reference through a read port and an opposite state, a write port reference.
The ~ORD WIDT~ f ield conveys the word size of the memory device being simulated. This value is used by below-described ou~put memory control to specify the number of data bits out of a predetermined maximum that are valid for the current array instruction. The prèdetermined maximum number of bits represent the word size (width~ of the real memory resource. Thus~ for example, if the real memory were 36 bits wider and a current array instruction were simulating an array having word width of 8 bits, ~he WORD ~IDTH field entry would be 8~ Finally, the REFRES~
INSTRVCTION field consists of a single bit used by below-described decode logic to distinguish between a valid array instruction intended to simulate a memory reference operation and a refresh operation to be performed on the real memory. In addition to the array instruction fields, q5~3 the array instruction profile latch 44 al~o receives the VALID INSTR~CTION indicator provided by the address counter and comparator circuit 4~.
The memory parameter simulation data that flow into the memory simulator 20 through the switch 12 during each major cycle are received and stored in a predetermined permutatio~
pattern. The pattern represents the scheduling imposed upon the data intake operation of the memory simulator by the compilation of a program input by a user. In this sense, permutation refer~ to the storage of individual units of data as they arrive during a major cycle in storage sectors not related to their place in the sequence of data flowing to the memory simulator from the inter-processor shitch 12.
Such permutation is necessary because the memory access parameter signals, relating to memory data, address, and control signals are produced by the independent operations of the logic simulations processors 16, 1~.
The input permutation memory 46 of the memory simulator in~ludes a pair of identical storage memories/ each having siX in~ividual elements that are interleaved--with the individual elements of the other memory in the schematic illustration of Figure 5A. Each of the individual elements consists of a 1 bit x 1024 storaqe location memory device.
One of the two memories of the memory 46 is referred to as the AfIN memory~ the other is denoted the BfIN memory.
During a cvcle, data flowing into the memory simulator are permuted into one of the two memories, while data permuted during the previous cycle are sequentially read from the other memory.

Further describing the memory 46, each of the A/IN and B/IN memories consists of three distinct sectionsr each comprising a pair of identical memory elements. Me~ory elements are paired in the preferred embodiment because the unit simulation signal in the LSM of the incorporated patent consists of two bits, one termed the ~value" bit, and the other, the ~undefined" bit. Reference i~ made to the Cocke patent for an understanding of the function of these bits.
It should be evident that the paired data structure is included only for an understanding of the operation of the preferred embodiment of the invention in connection with a particular type of logic simulation construct; in practice, the memory 46 (and the output memory described below) can have any structure that accommodates the basic signaling unit of the simulation context in which the memory simulator 20 operates.
Continuing with the description of the preferred embodiment, the following discussion of write and read operations of the memory 46 during the RUN mode of operation will be presented in terms of the A/IN memory. I~ is to be understood that the description is precisely the same for the B/IN memory.
During the R~N mode of operation, when the A~I~ memory is being written to, the address to which the currently-available signal is delivered for stora~e is deter~ined bythe current output of an input permutation memory 50. The input pèrmutation memory in the preferred embodiment stores 1024 words in a linear sequence, and each word is 12 bits wideO Each stored word defines a unique address in the A~IN
memory where the currently-available signal is to be stored.

~5~ 3 ~ .

The input permutation memory 50 i8 stepped through sequentially each major cycle and provide~ the write addresses for the A/XN memory. This allows the A/IN memory to be written to in the permutative order imposed by the compilation of the particular logic design being simulated.
The input permutation memory 50 is addressed by a delayed minor cycle counter 52 which simply counts up from 0 to 1024 each major cycle, providing, in se~uence, the input permutation memory addresses. In the preferred embodiment, the delayed counter 52 is set to a "negative 5" at the beginning of the each major cycle and is counted down f rom negative 5 when the cycle begins. The presetting of the delayed counter 52 to the initial value takes into account rive LSM pipeline clocks that are consumed before valid 15 input data is received from the inter-processor switch 120 When written, the A/IN memory elements are accessed in the pairs described above. The tWQ high order bits of the write address currently available from the input permutation memory- 50 are decoded to select which pair of memory 20 elements are to be written. The remaining 10 bi~s define the addresses in the selected pair element into which the ~urrently available signal is to be written. Thus, the two bits forming a simu~ation signal and representing a single data, control, or address bit for a given arriay instruction are written to the same address in a selected pair of A/IN
memory elements. It is reiterated here that the input permutation memory 50 is used tG address the A/IN memory so that the memory can be written in any order desired. It will be evident that a yiven order will be required and the IPM 50 will rec~iive the A/IN addresses in a sequence ~2~65i~3 ~19--correspondiny to the correct order during the IPL MODE. The order is referred to as a programmed permutation p~tternO
As discussed above, the particular operational environment being used to frame the discussion of the invention requires the delayed counter 52 to be preset to "negative 5" or 1019. Thus, the first five invalid signals will be written in the addresses contained in the IPM at addresses 1019 - 1023. When the first valid signal arrives from the inter-processor switch 14, it is written to the address contained in the IPM at address zero, the next valid data is writ~en to the address contained in the IPM at address oner and so on until the last valid data is written to the address contained in the IPM at address 1023.
In the read aspect of the R~N mode, ~11 three A/IN
memory element pairs are accessed simultaneously with the same address. The address is available from the AIN/BIN
address counter 54, which is a conventional 12-bit counting device whose current count is used as the read address for the A/IN memory. Only the low order 10 bits of the counter 54 are used to address the A/IN memory (the two high order bits are ignored)~ The counter 54 counts incrementally from address 0 to address 1023 each cycle.
The A/IN and B/IN memories are alternated in their respective roles once each major cycle by the operation of the address multiplexer 55. The address multiplexer provides both address and R/W control signals to the individual memory elements of the memory 46. Thus, for example, during one cycle, the address multiplexer will assume one state wherein each A~IN memory element receives a control signal indicating a memory read operation and .

receives the ten least ~ignificant bits of the A/IN - B/IN
address counter, while write control signals and the ten least significant bits of the currently-addressed IPM
location are sent to the B/IN memory element pair indicated S by the high order two bits of the currently-addressed IPM
locationO The next cycle, these functions are reversed.
Simulated memory access parameters are combined with respective array instructions in the AIN/BIN latch 58. The latch 58 comprises two logical pieces: one for staging the memory access parameters fed from the memory 46 and another for storing and forwarding an array instruction received from the array instruction profile latch 44. The first piece of the latch 58 is further subdivided into three fields, each corresponding to a respective type of access parameter. The three access parameters that are staged into the fields in the first section of the latch 58 are denoted in Figure 5A as WRITE DATA, CONTROL, and ADD~ESS Thus, simulated data to be written during a memory write operation is stored in the latch field entitled ~RITE DATA, the control bit (chip or port select signal) is fed to ~he CONTROL field while the memory address to be referenced by the current array instruction operation for the memory being simulated is latched to the ADDR~SS field. In the preferred embodiment, the three latch fields, that is the ~RITE DATA, CONTROL, and ADDRESS, comprise serial shift registers, each recei~i~ng serial stream of parameter signals from the currently-read portion of the memory 46, and arranging them in a sequential format for a single parallel shift to the next stage of the memory simulator pipeline.

~2~i~5~3 The other portion o~ the AIN/BIN latch 5B store5 an array instruction that is shifted from the profile latch 44.
It should be evident that the combination of memory access parameter data from the permutating memory with an array instruction establishes the complete set of information necessary to define a memory reference operation to be conducted at a specified port of a particular memory being simulated. In this respect, referring to the storage fields in the latch 58: the BASE ADDRESS field indicates which simulated memory element is to be operated on; the RAM
TYPE defines the type of reference operation (read or write~
to be performed; if the reference operation is a write operation, data to be written is in the WRITE DATA field;
the simulated address at which the defined operation is to be performed is in the ADDRESS field; while the CONTROL
field value determines whether or not a simulated SELECT
signal is to be prov.ided to the simulated device.
The control decode circuit 60 comprises a conventional gate array for decoding information contained in the 20 CONTROL, ADDRESS, RAM TYPE, REFRESH INSTR~ and VALID INSTR
fields of the latch 58. The control decode circuit 60 is essentially a four-state machine whose states are defined by equations (1) - ~4).

READ - VALID~REFRES~CS READ (CS and ADD BITS ~DEFINEDn) ~1) ~RITE = VALXD-REFRES~ CS~WRITE (CS and ADD ~ITS "DEFINED")(2) ~L2~.,5~i3 REFRESH = VALID~REFRESH (3) NO OP = VALID ~ (CS OR ADD BITS "UNDEFINEDn) ~4) The READ state of the control decode machine 60 is entered when the array instruction is not a refresh instruction, is valid, and defines a READ operation and when the CONTROL siqnal is in a state corresponding to the SELECT
state of a conventional port or chip sele~t signal. The conditions determinative of the ~RITE state of the decode machine 60 correspond to those for the READ state, with the exception that the RAM TYPE signal indicates a ~RITE
operation. The additional conditions for validity o~
equations (1~ and (2) are that the undefined bits in the CONTRUL and ADDRESS fields of the latch 50 are in a state indicating that the ~ompound CONTROL and ADDRESS signals are defined. The decode machine S0 will enter a REFR~S~ state when a valid refresh instruction has been entered into the latch 58 from the profile memory. Finally, the decode machine 60 will indicate that no operation (NO OP) is to be performed when either the VALID INSTRUCTION field indicates that an instruction is invalid or an undefined CONTROL or ADDRESS bit is set.
The real memory address at which the current array instruction is to be performed is produced by the real address circuit 62, which uses the ADDR ~IDTH field of the latch 58 to determine how many bits in the ADDRESS field are valid for the current array instruction. The valid address bits are decoded and added to the base address in the BASE

~2~

ADDR ~ield of the latch. The result is the real memory address for the given memory reference operation.
Once the state of the control decode machine 60 and the real memory address have been determined, the operational flow of the memory simulator passes to the instruction execution circuit.
The instruction execution circuit includes a real address latch 64, a real memory interface control circuit 66, and a gating and driver circuit 68. The real address latch 64 receives the data in the WRITE DATA field of latch 58, a pair of CONTROL BITS that define one o~ four states decoded by the control decode machine 60, the real address generated by the real address generation circuit ~2, and the data in the RAM TYPE:, WORD WIDTH, and VALID I~STR fields of the latch 58. The control bits and the valid instruction signal are provided from the corresponding fields of the real address latch 64 to the real memory interface control circuit 66.
The real memory interface control circuit 66 consists of conventional programmable logic that is controlied by an embedded program; the logic responds to the current state defined by the control decode machine 60 and the valid i~struction information to control operations performed agains~ the real memory 70O
- Figure 7 is a state diagram representative of the operation of the real memory interface control circuit 6S.
Operation includes an initial WAIT state in which the circuit will remain any time the control decode machine 60 generates a NO O~ signal according to equation (4) above~ A
STORE cycle is entered whenever the decode machine 60 produces a WRITE command, the instruction in the real addres~ latch 64 is valid, and the memory simulator is in the R~N mode. Similarly, the control circuit 66 will enter a FETCH cycle when the decode machine 60 indicates a READ
operation is to be performed~ the address latch instruction is valid~ and the simulator is in the RUN mode. During the STORE and FETC~ cycles, the control circuit 66 generates appropriate control si~nals on a plurality of control lines provided to the gating and driver circuit 680 These lines conduct memory access siynals that define the simulated memory reference in terms of control signals appropriate to operate the re~l memory 70; they also conduct address, write data, and control bit gating signals that enable the gating and driver circuit 68 to provide the real address, write data, and control bits held in the real address latch 64 to the memory 70. The memory access and gating signals are presented in the proper order and for the time period specified for correct operation of the memory 700 Thus, when the instruction currently held in the latch 64 corresponds to a ~RITE memory operation, the control circuit 66 will sequence appropriate signals to the gating CiECUit 68 to cause the ~ating circuit to provide, in proper order, the control signals, the calculated real memory address, and the data to be stored to the real memory 70.
Similarly, for a reference corresponding to a READ
operation, the interface control circuit 66 will provide control si~nals and the calculated real address to the gating circuit 58 in the sequence required for reading data ~rom the real memory 70. Further, at the end of a real memory FETC~ cycle, the control circuit 66 will provide 1~S~ ;63 clock pulse that will cause the :Eetched data to be loaded into the real memory output la~ch 72 so that the obtained data can be latched for tran~fer to the output permutation circuit.
The REF~ESH cycle of the control circuit is entered under the conditions defined in equation (3), at start-up of memory simulator operations, or whenever a predetermined refresh time-out period elapses without conduction of a XEFRES~ operation. In the REFRESH cycle, the control circuit 66 provides the appropriate signals through the gating circuit 68 to conduct a conventional REF~ES~
operation on the real memory 70.
As illustrated, the real memory output latch 72 1atches data read ~rom the real memory 70, with the latching under the control of a clock pulse from the control circuit S6.
Because the real memory 70 is asynchronous to the rest of the memory simulator logic, read data is available before the memory simulator is ready to use it. Therefore, the data is held in the latch 72 until it can be transferred to the output permutation circuit. In further explanation of the lllustration of Figure 5B, both the real memory 70 and the real memory output latch 72 have provision for storing the basic signal units defined for the operational context of the preferred embodiment; that is, they provide storage 25 ~or the "value" and "undef ined" bits of each signal unit.
The data latched to the real memory output latch 72 is forwarded to the output data permutation circuit.
The output data permutation circuit consists of a memory data latch 74, a write control and address generation 30 logic circuit 76~ a minor cycle counter 77, an output i6~i63 permutation memory tOPM) 78, an A/OUT and B/OUT output memory consisting of value and undefined sections 80a and 80b~ and an address multiplexer comprising two sections indicated by reference numerals 82a and 82b.
The memory data latch 74 consists of a latch that receives the .results of a real memory read operation from the output latch 72 along with the word width and RAM type instruction for the just-executed operation that is held in the latch 64. Under control of the write control and write address generation logic 76, the read data in the latch 74 is clocked out serially and written into the A/O~T or B/O~T
memory. The WORD WIDTH and RAM TYPE data are used by the logic circ.uit 76 to control how many read data bits are written to the selected memory.
The write control and write address generation logic 76 controls the trans~er of simulated read data into the A/O~T
or B~OUT memory from the data latch 74~ The transfer is controlled by a S~IFT CLOCR signal provided on sisnal path 83 and an ADDRESS signal and WRITE ENABLE signal provided on .20 the compound signal path 850 The SHIFT CLOC~ on the data path 83 serially shifts the data entered in parallel into the memory data latch 74 from the real memor~ 70~ The destination of the serially-shifted data alternates between the A/OUT and the B/OUT memories on alt~rnate cycles, with the value bits going to one of the memory element pair 80a and the undefined bits going to the corresponding one of the memory elements 80b. ~rite control for entry of the serially-shifted data is provided by the ADDRESS and ~RITE
ENABLE si~nals on the compound data path 85, The ADDRESS
signal defines the address in the destination memory where ~6S$3 the serially-shifted data is to be stored, while the WRITE
ENABLE signal effects the entry of the serially-shifted data into the indicated memory location.
To produce the S~IFT CLOCR, WRITE ADDRESS, and WRITE
5 ENA~LE signals, the logic 76 includes a write address counting capability that is reset to zero at the beginning o~ each cycle. Then, as a cycle progresses, the logic 76 increments the write address each time the RAM TYPE field of the memory data latch 74 indicates a read array instruction reaches the latch~ Each time the RAM TYPE field indicates a read array instruction, the write address count is incremented by a total equivalent to the value in the WORD
WIDTH field, which limits the number of bits written to the output memory to exactly the word width of thè memory being simu~ated by the array instruction that initiated the READ
operation. If the WORD WIDTH field value indicates that a data word is less than the real memory word size, the excess data bits in the memory data latch 74 are ignored. When the desired bits have been written into the A/OUT or B/OUT
memory, the generation logic 76 points to the first empty memory location following the word just written. The first bit of the next read data word will be stored in the location indicated by the pointer. Thus, the read data is stored contiguously in the output memory. In the preferred embodiment, if a NO OP occurs when a READ operation is indicated by the .RAM TYPE field of the latch 74 ~as, for example, when unldefined bits are detected by the control decode machine 60 or when the control bit associated with the read array instruction indicates no access), undefined data will be written into the selected memory.

~C~ 3 Data is extracted each cycle from the output memory by the complementary operations of the minor cycle counter 77 and output permutation memory (OPM~ 7~. The minor cycle counter 77 is a 10-bit counter used to address the OPM
during the RUN mode of operation. It is reset to a negative three at the beginning of each cycle to account for the number of pipeline clocks required to bring valid data to the memory data latch 74. The OPM 78 is a conventionally-addressable memory element having the capacity to store 10~4 words of 10 bits each. Tt is stepped through sequentially each major cycle by action of the minor cycle counter 77, and it provides the read address for the A/OUT or B/O~T
memory. This allows the A/OUT and B/OUT memories to be read in any order and the data stored in them to be permuted~
The A/OUT and B/OUT memories are driven out of phase each cycle by operation of the address multiplexers 8~a and 82b. Thusf during one cycle~ READ ADDRESS signals from the OPM and READ ENABLE signals generated by combinational logic ~not shown) associated with the multiplexer will be provided to either the A/OUT or B/OUT, while write addresses and write enable signals originating in the generation logic 76 will be provided to the other of the memories~
The pipeline operation of the memory simulator can be understood by reference to Figure 6, where a load write enable clock (LWE~, processor clock (PCR), address register clock (ARCR), pipeline clock ~1 (RCK 1), pipeline clsck ~2 (RCR 2), I/O clock (IOCR), mastex processor clock (MPCX), and cycle preload and clear (RAR~ signal are illustrated.
All of the clocks except MPCR are provided by conventional clock circuitry (not shown) which corresponds to the clock ~25~ 3 generator 33 of Figure 2. These clock~ are ultimately derived from the LWE clock available from the LSM. The MPCK
and RAR signals are provided from thé control processor 10.
The L~E clock is received from an external source; in the preferred embodiment, it is received directly from the control processor 10. Preferably, the LWE clock has a 50 nanosecond pulse with a periodicity of approximately 167 nanoseconds. During the ~UN mode of the memory simulator 20, the LWE clock is a continuous stream of pulses. The write enable signals for the A/IN and B/IN memories 46 are derived directly from the LWE clock during the RUN mode.
The IOCR, PCR, and ARCR signals are derived by inverting the LWE clock and delaying the inverted waveform by 50 nanoseconds~ IOC~ stays inactive every l9th pulse of LWE
(equivalent to a missing pulse) in RUN mode. The ARCR is used to clock the minor cycle counter delayed 52 and the minor cycle counter 77 during the RUN mode of operation.
Thus, when data is being entered into the memory simulator 20 through the memory 46, the address of the IPM 50 is incremented through the minor cycle counter delayed 52 on a particular transition of each pulse of ARCR/ Data is written to the memory 46 on the corresponding transition of the following pulse of LWE, thereby establishing the correct phasing for the writing of simulated data access parameters into the memory 46. Corresponding timing relationships are established for readi~g data from the memories 46 and 80a, 80b.
The IOCR signal is fed to the address counter 54 and to the serially-shifted WRITE DATA~ CONTROL, and ADDR~SS
sections of the AIN/BIN latch 58 to serially clock into i3 ~hose sections data which is serially read from the input memory 46 by the counting action of the address counter 54.
Since the eounter 54 is counted up in response to IOCK, the use of IOCK in the serial input subsections of the latch 58 synehronizes the transfer of data to those subsections from the memory 46. Similarly, ARCR causes the read address from the OPM 78 to change in synchronism with the LWE, thereby insuring that data is transferred from the memories 80a, 80b to the switch 12.
The memory simulator 20 is operated in a pipeline fashion by virtue of the phasing of the pipeline elocks RCR
1 and RCK 2. RCK 1 is the primary pipeline clock; it is derived from PCR and is active only during the RUN mode.
RCR 1 occurs with the first pulse of PCR and once every 19 pulses of PCR thereafter. The second pipeline clock, RCK 2, is also derived from PCR and is active only during the RUN
mode. RCK 2 occurs once every 19 pulses of PCK and is eoincident with the PCR pulse occurring immediately prior to ~CR 1.
The pipeline operation of the memory simulator is illustrated in Figure ~ where the path of three successive instruetions fro~ the SPM 40 are traced. The first instruetion read, INSTi, is assumed to be one requiring the real memory 70 to be read, which is indieated by (R3. The seeond instruction, INSTj~ is a write (~ instruetion, ~hile the third instruction, INSTk, is another read ~R3 instruction. The phasing of the pipeline clocks is shown horizontally across the top of the Figure 8 graph.
The sequence is as follows. On the first oscurrence of RCR 1~ INSTi is latched to the instruction profile lateh and 5i~3 the address counter and comparator circuit 42 (ACC) is incremented to the SPM address where INSTj i5 stored~
Between the first occurrence of RCK 1 and the following RCK

2, data defining the simulated read address and the control bit for INSTi is serially shifted from the A/IN or B/IN
memory to the AIN/BIN latch (ABL) by IOCR. Now, tracing the horizontal line illustrating the progress of INSTi, at the first RCK 2 following the instruction's entry into the IPL
and the corresponding read parameter data into the ABL, INSTi is latched into the ABL. Immediately upon INSTi being latched to the ABL, the control decode and real address generation for the instruction are performed.
On the second occurrence of RCR 1, the control bits and generated real address for INSTi are clocked, toget~er with the information in the RAM TYPE, WORD WIDTH, and VALID INSTR
fields of the instruction into the real address latch 64 (RAL). At the same time, INST; is entered into the IPL and the ACC count is incremented to point to INSTk.
Between the second occurrence of ~CR 1 and the following occurrence of RCK 2, the real memory 70 is read at the real address in the RAL and the read data is clocked into the real memory output latch 70 5RMOL). At the same time, the memory reference parameter data (~RITE, CONTROL, and ADDRESS) is serially entered into the ABL to set the conditions or execution of the STORE operation required for INSTj.
On the RCR 2 pulse following the second occurrence of RC~ 1, the data fetched from the real memory in execution o I~STi is entered into the memory data latch 74 ~MDL) from the RMOL 720 As described above, this data is shifted fro~

~:5~i~i6.3 -.

the MDL into the memory 80a, 80b by the action of the generation logic 76 described above~ At the s~me time, the STORE ope~ation re~uired for INSTj is set up by decoding of the control bit~ and generation of the real memory address.
On the third occurrence of RCR 1 the write data, control bits, and real memory address, ~ogether with the information in the RAM TYPE, WORD WIDTH, and VALID INSTR
fields of INSTji are entered into the RAL ~4, following which the STORE operation for the instruction is executed.
On the same occurrence of RCR 1, INS~k ~s entered into the IPL, and the progress of this instruction follows that of the first.
Reference is now made to Figures 9, 10A-10C, and llA-llC for an understanding of how the real memory 70, input memory 46, and o~tput memory 80a, 80b~ respectively, are partitioned and accessed during the operati~n of the memory simulator 2~. As shown in Figure 9, the simulation profile memory (SPM) 40 has instructions stored at consecutive addresses that are accessed in se~uence as explained hereinabove. Referring now to the first instructi`on IN5TR 0 at SPM address location 0, a field of the instruction contains a real memory base address, BADDi, that defines the first address in the real memory 70 where data for the memory reference ~imulated by instruction INSTR 0 is held.
The field of the real memory 70 devoted to instruction I~STR
0 ends at BADDi ~ (J l)~ where J is the value in the address width field of instruction INSTR 0. Other instructions in ~he SP~ 40 representing memory reference operations against the same simulated memory device will also have the base address BADDi. For example, if instruction INSTR 0 ~2~6S6.3 .

simulates a write operation, it may be that a read operation i8 to be executed against the written data. ln this case, the subsequent read operation would be conducted by a FETCH
operation against the data written to the real memory 70 beqinning at storage location BADDi by instruction INSTR 0.
The partitioning of the real memory 70 is done during IPL
and is implemented through compiler assignment of base addresses to array instructions.
The input memory 46 is partitioned during IPL, and the partitioning can be understood with reference to Figure lOA.
Figure l~A illustrates the three element pairs of the A/IN
portion of the memory 46, however, it i5 to be understood that the illustration and explanation which follow are valid also for the B/IN portion of the memory~ Each element of a pair of the A/IN memory consists of a one bit by 1024 location storage device. In the preferred embodimentr provision is made for simulation of memory devices having the ability to store words up to 36 bit~ in length in up to 64R storage locations; therefore, provision is made in the A/IN memory pairs for receiving words and addresses of the maximum size, as well as the control bits for each instruction. This is illustrated in Figure lOA by the partitioning of the A/IN memory elements as follows. For each instruction in the SPM 40 and therefore for each simulated port, the same 18 storage spaces are reserved in each of the A/IN elements, with the space in the first pair of elements dedicated to the first 18 bits of a data word, the identical storage sectors in the second element pair to the second 18 bits of a data word, and corresponding storage 30 sectors in the third pair of elements dedicated to 16 , ,. ~ ., ~6~3 address bits and one control bit. As shown in Figure lOA, this results in the dedication of the first 18 storage spaces in each element of all of the A/IN pairs to the accumulation of simulation data for the first instruction.
Permutation of data flowing into the memory 46 from the switch 1~ during a major cycle is illustrated in Figure lOBr As described above, the IPM 50 has 1024 separately addressable storage spaces in each of which is stored the address in the memory 46 where a simulation signal from the switch 12 will be stored. It will be understood that the compiler will have the ability to schedule the delivery of simulated memory access signals to the memory simulator during each cycle. That deli~ery schedule is reflected in the AIN/BIN memory addresses stored in the IPM 50 during the IPL mode of operation. During the RUN mode of operation the IPM addresses are provided in sequence and each prompts the provision of the address at which the currently-provided siqnal bits are to be stored. As illustrated, the upper two MSB's of the address are decoded to select one of the three memory element pairsr while the ten LSB's s~ecify the particular address in the selected memory pair where the currently-available value and undefined bits are to be stored.
Figure lOC illustrates the reading of data stored in the A~IN memory pairs. It will be recalled that data is read sequentially from the memory 46 under control o~ the address counter 54. The address counter 54 is reset to 0 at the beginning o each major cycle and counts incrementally from 0 through 1023, which will result in the data stored in the A/IN pairs being read out sequentially to the AIN/BIN

. . .

6~3 latch 58. The first three fields of the latch 58 are stored in three pairs of serial-in-parallel-out shift registers.
These registers are indicated in Figure 10C by reference numeral 90; each consists of an 18-bit device. Data is shifted serially from each A/IN memory element into an associated one of the registers 90 during the 18 PCK cycles that occur between each cycle of RCK 1. Thus, each of the registers 90 will be filled with 18 bits of data from 18 contiguous storage spaces in one of the A/IN memory elements. Then, at the next ~C~ 1, the data are transferred to the next stage of the pipeline. As shown in Figure 10C, the ~RITE DATA field of the latch 58 consists of the data in the first two sets of registers 90. The CONTROL bits are in the second storage spaces of the last pair of reyisters, while the ADDRESS field information is held in register storage cells 2-17 of the last register pair.
The operation of the output permutation memory 80a, 80b will be understood by referring to Figures llA-llC. As shown in Figure llA, the value and undefined bits resultin~
from three read memory instructions are stored in consecutive locations in A/OUT memory elements 80a and 80b, respectively. Assume that the word widths for the three instructions are: 16, 3, 10. The partitioning of the memory elements 80a, 80b results in the 16 data bits of the first instruction being deliYered to locations 0-15; the 3 data bits of the second read instruction are in locations 16-18; and the 10 data bits of the third instruction are in locations 19 28.
Refer now to FigureS llB and llC for an understanding of ~rite and read functions performed on the AOUT/BOUT

~5i65~
.

memory. The address multiplexer 82a, 82b i~ not shown in Figures llB and llC since it only alternates the write and read control signal~ illustrated in these Figures between the A/OUT and B/O~T memories each machine cycle.
Writing the read data bits to the memory eiement is illustrated in Figures llB, 12, and 13. In Figure llB, the write control and write address generation logic 76 provides address and control signals necessary to store read data from the memory data latch (MDL) 74 to cvnsecutive storage locations in the A/OUT memory elements. As shown in Figures llB and 12, the generation logic 76 generates the necessary address, enable, and MDL shift clock signals in response to read data storage control signals including RCK 1 and RCR 2 and the information stored on the RAM TYPE and ~ORD WIDTH
fields of the MDL 74. Generation of the address, enable, and MDL shift clock signals entails the operative collaboration of an oscillator 90, a gated clock circuit 91, a delay circuit 92, a gating circuit 94, a width counter (CNTR) 95, a zero count detector ~6, and an address counter (ADD COUN~) 98.
The oscillator 90 is conventional and generates an output oscillatory clock signal on signal line 85a (see Figure 5B) that is denoted as the AO~T/BOUT ~E (~RITE
ENABLE); this signal enables the entry of data into the AOVT/BO~T memories The ~E signal on line 85a is delayed slightly through the delay circuit 92 to provide a counter clock (CNTR CLR) that is used to clock the counters 9~ and 98. The counter clock signal is provided to the gating circuit 94 to synchronize writing the AOUT/BOU~ memories with the pipeline clocks. ~hen the gatin~ circuit 94 ~: .

~2~i6~63 decodes a read instruction, it produces LOAD and ENABLE
signals. The LOAD signal enables the width counter 95 to be preset to the value in the WO~D WIDTH field. The ENABLE 1 signal is fed to the counters 95 and 98. When the width counter g5 is preset to a non-zero value, the zero count detection circuit 96 provides an enable (ENABLE 2) signal to the width and a~dress counters 95 and 98. ~hen both ENABLE
signals are available, both of the counters 95 and 98 are able to count in synchronism with the CNTR CLR signal: the width counter 95 counts down to zero from its preset value;
and the address counter 98 counts up~ When the width counter 95 reaches a zero count, the ~ero count detector 96 removes the ENABLE 2 signal from the width and address counters 95 and 98.
The address counter 98 i~ zeroed at the beginning of each cycle and counts up in synchronism with CNTR CLR each time it is enabled by the detection circuit 96~ Therefore, for each read instruction, the address counter will increment its count by a value equal to the value in the word width field of the instruction, and will `count up during the instruction from the count at which it was stopped at the end of the previous read instruction.
Therefore, the output of the address counter 98 is a ~e~uentially increasing count that forms the sequential addresses provided on signal line 85b to the A/OUT memory elements 80a, BOb.
Thè WE signal line 85a is also input to the gated clock 91 generatin~ the serial shift clock of the MDL on signal line 83. The MDL shift clock serially shifts out the read data previously entered in parallel to the MDL 74 ~rom the ':

~251~63 real memory 70. The gated clock circuit 91 is conventionally gated by the signals ~ABLE 1 and ENABLE 2 so that shif tin9 f rom the MDL to the AOUT/BOUT memories is done only when required. Eor example, no MDL shift clock is required when the MDL is being parallel loaded by RC~ 2, or if a write array instruction is being executed.
The time relationships between the various signals that affect the writing of data to the AOUT/BOUT memories is shown in Figure 13. At the be~inning of each cycle, RAR
causes the gating circuit 74 to reset the LOAD signal;
ENABLE 1, on the other hand, is reset to its inactive state by RCK 2 if the previous RCR 2 has loaded a read array instruction. At the positive transition 102 of RCK 2 assume that the MDL 74 has latched to it read data bits and WORD
15 WIDT~ and RAM TYPE field information. The transition 102 causes the gating circuit 94 to reset its ENABLE 1 signal.
Immediately after the RCR 2 transition, the RAM TYPE signal from the corresponding MDL storage location assumes a state corresponding to a READ operation. The response of the gating circuit 94 to the READ indic~tion is delayed until the first transition of CNTR CLR followin~ the RCR 1 pulse 104. The counter clock transition lQ5 causes the ~ating circuit to produce a set pulse of the LOAD signal that lasts for one cycle of the CNTR CLR and causes the width cou~ter 95 to be preset at transltion 106 of CNTR CLR to ~he value in the ~ORD WIDT~ field of the MDL. At the end of the LOAD
pulse, the gating circuit 94 sets the ENABLE 1 pulse; next the coun~ det~ctor 96 sets the the ENABLE 2 pulse;
following this, the ENABLE pulses permit the counters ~5 and 98, respectively, to begin counting in s~nchronism with the ~ 3 CNTR CLK. First bits are avai}able from the MDL shift registers (llOa and llOb in Figure llB) when the MDL is loaded at RCK 2 80 no shift of the bits is required before the first write to the AO~T~BO~T memory. After the load by RCK 2, CNTR CLR shifts the bits serially from the M~L. The first write to the A/O~T memory elements occurs on the negative edge 114 of WE; at transition 118 of CNTR Cl,R, the next value and undefined bits of read data are available from the MDL shift registers llOa, llOb; and the A/OUT
address at which these 2 bits are to be writte~ is generated. The bits are written at the negative transition 120 of ~E. This process continues to enter bits sequentially intv the A/O~T memory elements 80a, 80b until a zero count is detected from the ~idth counter 95, at which time ENABLE 2 will be changed by the detector 96 to a state disabling both coun~ers 95 and 98 from incrementing any further; ENABLE 1 will be reset with the next RCK 2 or RAR.
output permutation of the data entered sequentially into an AOUT/BOUT memory pair is accomplished as illustrated in Figure llC~ During the IPL mode, the OP~ 78 has a sequence of AO~T/BOUT memory addresses entered into its storage space. The AO~T/BO~T addresses are stored in a ~equence corresponding to the OPM address sequence, but define an AOUT/BOUT address sequence imposed by the 25 host/interf ace processor compiler to synchronize the delivery of read data to the overall simulation being oonducted on the logic simulation machineO In the preferred embodiment, the output permutation memory addresses comprise 10-bit values~ each defining a unique one of 1024 l-bit storage spaces in each of the A/OUT memory elements 80a, ~2~ 3 80b. The destination of the informcltion extracted from the output permutation memory i5 the interprocessor switch 12.
Therefore, in Figure llC, the OPM 78 may have a fiequence of addresses in it that include the sequence fragment indicated by OPM addresses 078-080. At these addresses are stored A/OUT addresses i, j, and bt respectively. Thus, it should be evident that the sequence fragment 078-080 of OPM addresses, together with the A/OUT
addresses stored at those locations, provide a unique mapping that extracts information stored sequentially in the A/OUT in a nonsequential, but predetermined permutation pattern.
The method and apparatus described hereinabove provide several unique features that are best understood by way of operational examples. The first feature illustrates how the well-known technique of ~write through~ can be simulated.
~Write through" refers to the ability of a memory device to write and read a data object simultaneously with the read operation reflecting the data object being written. In this 2Q respect, a three port array is postulated having one write and two read ports. The array is further specified to have the capacity of storing 16 four-bit words. Therefore, its address bus must be at least 4 bits wide to permit addressing the 16 words; and the data input and output busses must also be ~ bits wide to conduct the data words into and out of the device~ Further, three separate control ports are specified, eaeh for selecting a respective one of the three data throughput ports. The simulated device is illustrated in Figure 14 as a random acoess memory (RAM~L
The ~our-bit wide address bus connected to the simulated RAM

is denoted in Figure 14 by ADDR (0,3). In this notation, ADDR refers to the address bus, while the parenthetical notation provides explicit names for each of the address bus signal paths. A similar notation is followed for the write and read data busses connected to the respective write and read ports of the RAM. In this example, each port is to be control~ed by its own dedicated control port, with, for example, the write control port denoted as DO ~RITE.
It is postulated in the instant example that the simulated RAM is to be referenced more than once during each of a number of consecutive major cycles during the R~N
mode of operation. In this regard a major cycle consists of an arbitrary number of machine cycles~ The array instruction formats are illustrated in Figure 15. The array instructions for the simulation are stored consecutivel~ in the SPM 40 at SPM address locations j t ~ r and jf2 1 respectively. The array instruction fields are abbreviated as follows. BA refers to the base addres~ field in which the real memory address i refers to the first addres~ in the real memory storage sector assigned to the simulated RAM.
The address field is denot~d by A~, and contains a value equal to the width of the address bus ~4). RT refers to the RAM TYPE field in which 1 corresponds to a read instruction, while O indicates a write~ The WW field is the ~ORD ~IDT~
field and contains a 41 indicating a data objeçt size of 4, and implicitly defining the write and read busses as being 4 bits in width. The REFRESH instruction field contains a 0 indicating that tbe array instruction should not stimulate a REFREsa operation for the real memory~

.

The waveforms in Figure 16 illustrate an actual simulation performed by the inventor using the embodiment described for the instant example. The initial conditions of the array simulation included initialization of the array in~ormation to all zeros during IPL and ordering of the array instructions so that the instruction representing the READ 2 port precedes the instruction representing the WRITE
port, while the WRITE port instruction precedes the READ 1 instruction. These initial conditions were realized through the conventional operation of the compiler in the host processor of the prior art system.
In Figure 16, the simulation is illustrated by waveforms representing the decoding of value and undefined bits representing a given data bit in the portions of the CONTROL, ADDRESS and WRITE data fields of the AIN/BIN
memories and the READ data fields of the AOUT~BOUT memories~
Additionally, the decoded bits of the CONTROL data fields for each port are representedO Uninitialized data is represented by ?, while undefined data is denote~d by *, logical zeroes and ones conventionally represented by corresponding wave levels.
The simulation is shown proceeding through approximately four major cycles during R~N mode. In Figure 16, when the simulation begins/ the control lines for each port are inactive, corresponding to a logical zero at each of the DO (control) lines. This indicates that no memory reference is being executed against the associated port. In the preferred embodiment~ when a read array instruction is associated in the latch 58 with a CO~TROL field value of 0, no read memory access occurs and the read data transferred ~256~63 to the A/OUT or B/OUT memory is forced to the undefined state. This is indicated in the first major cycle of Figure 16 by *
During the first major cyc~e, write and address data S are defined, while the read data obtained from the real memory 70 are uninitializedO It should be understood that the real memory 70 can have initial data entered into it during IPL; however~ in this example the memory is uninitialized.
At the beginning of the second major cycle, during the first machine cycle, defined data for the read control lines (Do READ 1 and DO READ 2) and the address port are transferred to the memory simulator 20 from the switch 12 and are captured in the A/IN or B/IN memory. Beginning with the second machine cycle of major cycle 2, the read control and address signals are taken from the A/IN or B/IN memory~
real memory access i~-performed~ and read data is stored in the A/O~T or B/OUT memory. Beginning with the third machine cycle of the second major cyrle, the read data is passed to the interprocessor switch 12 from A/ W T or B/OVT memories.
At the beginning of the third major cycle, the write control line DO WRIT~ becomes active, the address is still address 1, while the write dat is again all ones~ The read control lines are active during the third major cycle. ~ow~
the positive state of the DO WRITE control line causes the simulated data to be entered into the real memory 70 during the first two machine cycles of the third major cycle. At the beginning of the third machine cycle, the data written at the indicated address changes to all ones at the first read port. Because the read instruction representing the 3L~Sf~ 3 -4~-second read port precedes the write in~truction, it doesn't "see" the new data until one machine cycle after the new data is "seen" by the first read port. Thus, the all ones written are not available to the second read port until one machine cycle after the new data is available from the first read port. The "write througha simulation is thus provided by the recognition at the first simulated read port of data entered into the simulated RAM through the ~RITE port during the same machine cycle of the simulator 20 (that is, the third machine cycle of the third major cycle~.
The memory simulator of the invention inherently has two levels of delay between starting a simulated reference (read or write) and seeing the results flowing through the switch 12. Ordering a read array instruction after a write array instruction provides that he write instruction data can be read as soon as possible after execution of the write array instruction. If the instructions are ordered so hat a rPad instruction precedes a write, an additional machine cycle of delay is incurred. Most simulation scenarios can tolera~e this additional level of delayD
However, i~ the extra level of delay between a write and read instruction is unacceptable, the desi~ner has the option of ordering instructions so that the write instruction precedes the read instruction.
The other feat:ure provided by the invention permits the simulation of a m~lory device having data objects wider than the data width storage capability of the real memory 70. In the case where a memory device is simulated whose data width is greater than, for example, the 36 bit maximum available in the real memory 70, the simulated devioe is represented by two (or more) array instructions, each with a word width field (~) of 36 (or less) bits. This permit~ the two array instructions corresponding to the two separate pieces of the same memory device to be executed independently. In this case, the ~imulated address and control data for each piece wo~ld be identical, with the only difference being in the data written or read during each instruction. The simulated memory device therefore would have two independent array instructions compiled for each port to be simulated (each instruction accounting for one section of the data field), and each instruction would be assigned by the compiler a separate area of real memory 70 against which its operations are ~o be conducted. Of course, each separate area of the memory 70 would be accessed by its own base address.
Finally, the invention provides for simulation of a memory device whose addressable size exceeds the 64~ word maximum represented- by a single array instruction (as a consequence of the 16-bit wide address width field). In this case the memory device can be partitioned into two (or ZO more) pieces of 6~K words (or less) each, in which the high order address bit (or bits) would be used to gate the control lines to each partition, effectively providing unique control lines to each partition. The remaining address lines and the data lines are common in this case to both partitions. In this respect, the instructions wo~ld be assigned separate areas of the real memory, each having a respective base address, and each corresponding to a resp~ctive partition of the memory being simulated.
Therefore, it will be evident that any memory device of arbitrary width and storage capacity and possessing an arbitrary number of reference ports can be simulated using the method and means of the invention. It will further be appreciated that any memory reference operation conducted against any simulated memory device will be OpQrative to affect a data object of arbitrary size, in contradistinction to the logic simulation machine of the prior art in which each simulated operation can be conducted only against data objects one bit in width.
Obviously, many modifications and variations o~ the present invention are possible in light of the above teachings, therefore, it is to be understood that the invention may be practiced in embodiments other than those specifically described.
I claim:

Claims (10)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A method for simulating machine-accessible multiport memory arrays, said method being executable upon a highly-parallel logic simulation machine in which an interfacing finite state machine (FSM) emulates at least one memory array, comprising the steps of:
defining and associating a plurality of memory port names with corresponding respective subsets of the input/output (I/O) resources of the FSM, said port names corresponding to a memory array to be simulated;
binding and storing sets of array instructions to selectable ones of said port names, said array instructions defining simulated memory access operations to be performed on said simulated memory array;
permutatively entering simulated memory access signals from said LSM into said I/O resource subsets according to a predetermined pattern of association with said sets of array instructions;
executing said stored sets of array instructions on said FSM using said memory access signals to simulate access to said memory array; and permutatively providing simulated memory access signals from said FSM indicating execution of stored array instructions on said FSM.

2. The method of Claim 1 wherein said simulated access operations correspond to read and write instructions included in said array instructions and said step of executing includes executing said read and write instructions in a predetermined order to simulate write-through of said array.

3. The method of Claim 1 wherein said FSM includes an addressable storage resource and said step of defining and associating includes associating at least one of said memory port names with a subset of said addressable storage resource, said subset being identified by a single base address.

4. The method of Claim 3 wherein said addressable storage resource has a predetermined data storage width (w) and, for a memory having a data width greater than w, said step of defining and associating includes providing two or more array instructions, each defining the same memory port name of said memory, but associating the defined memory port name with a different respective subset of said addressable storage resource.

5. The method of Claim 3 wherein each said array instruction defines up to a maximum number of simulated address spaces and, for a memory having greater than N
address spaces, said step of defining and associating includes providing two or more array instructions, each associating a respective portion of the simulated address spaces with a different respective subset of said addressable storage resource.

6. A pipelined processor for simulating a machine-accessible multiport memory in response to simulated memory access signals provided by a highly-parallel logic simulation machine, comprising:
first and second permutative data input/output (I/O) means for receiving simulated memory access signals during one machine operation cycle while concurrently providing permuted simulated memory access signals received during a previous machine operation cycle;
programmable input permutation means for permuting received simulated memory access signals into respective subsets of said first permutative I/O means in response to a predetermined programmed permutation pattern;
programmable memory simulation profile means for receiving and storing array instructions defining and associating a plurality of memory port names with corresponding respective subsets of said first and second permutative I/O means and defining simulated memory access operation to be performed on a simulated memory having ports defined by said port names;
programmable output permutation means for permuting memory port output signals through said second permutative I/O means in response to said predetermined programmed permutation pattern; and memory instruction execution means for receiving permuted memory access signals from said first I/O means and array instructions from said memory simulation profile means for executing said received array instructions to simulate the performance of memory access operations against a memory at defined memory port names in response to data provided from said respective first I/O means subsets, and for providing said memory port output data.

7. The processor of Claim 6 wherein said simulated access operations correspond to read and write instructions included in said array instructions in a predetermined order which, when executed by said memory instruction execution means, simulates write-through of said memory.

8. The processor of Claim 6 wherein said memory simulation profile means includes an addressable storage resource and said array instructions associate at least one of said memory port names with a subset of said addressable storage resource, said subset being identified by a single base address

9. The processor of Claim 8 wherein the addressable storage resource has a predetermined data width (w) and a memory having a data width greater than w is simulated by two or more array instructions, each defining the same memory port name, but associating the defined memory port name with a different respective subset of said addressable storage means.

10. The processor of Claim 6 wherein each said array instruction defines up to a maximum number N of simulated address spaces in said memory and a memory having a number of address spaces greater than N is defined by two or more array instructions, each associating a respective portion of the address spaces of said memory with a different respective subset of said addressable storage resource.