CA1266096A - Fully programmable linear feedback shift register - Google Patents
Fully programmable linear feedback shift registerInfo
- Publication number
- CA1266096A CA1266096A CA000552722A CA552722A CA1266096A CA 1266096 A CA1266096 A CA 1266096A CA 000552722 A CA000552722 A CA 000552722A CA 552722 A CA552722 A CA 552722A CA 1266096 A CA1266096 A CA 1266096A
- Authority
- CA
- Canada
- Prior art keywords
- flip
- flops
- data
- shift register
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/31813—Test pattern generators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/582—Pseudo-random number generators
- G06F7/584—Pseudo-random number generators using finite field arithmetic, e.g. using a linear feedback shift register
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
Abstract
Title of the Invention: FULLY PROGRAMMABLE LINEAR
FEEDBACK SHIFT REGISTER
ABSTRACT OF THE DISCLOSURE
Basic block shift registers are cascaded to form a fully programmable linear feedback shift register. Each of the basic block shift registers comprises a plurality of flip-flops, each of which includes control logic circuits.
A polynomial equation is first fed into the linear feedback shift register for setting the respective flip-flops into predetermined logic states, which are used to encode messages to be shifted by the programmable linear feedback shift register. The number of flip-flops in the programmable linear feedback shift register can be varied, in accordance to the polynomial equation. Likewise, the polynomial equation also determines the number of times the programmable linear feedback shift register is to circulate the encoded messages.
FEEDBACK SHIFT REGISTER
ABSTRACT OF THE DISCLOSURE
Basic block shift registers are cascaded to form a fully programmable linear feedback shift register. Each of the basic block shift registers comprises a plurality of flip-flops, each of which includes control logic circuits.
A polynomial equation is first fed into the linear feedback shift register for setting the respective flip-flops into predetermined logic states, which are used to encode messages to be shifted by the programmable linear feedback shift register. The number of flip-flops in the programmable linear feedback shift register can be varied, in accordance to the polynomial equation. Likewise, the polynomial equation also determines the number of times the programmable linear feedback shift register is to circulate the encoded messages.
Description
~60g~
Title of the Invention: FULLY PROGRAMMABLE LINEAR
FEEDBACK SHIFT REGISTER
FIELD OF THE INVENTION
The present invention relates to shift registers and more particularly to a fully programmable linear feedback shift register.
BRIEF DESCRIPTION OF THE PRIOR ART
Linear feedback shift registers which use a number of flip-flops for circulating information by means of a sequence of bits are known. It is further known that such shift registers may be used for error coding and pseudo-random number generation. However, for each of these applications, a differently configured shift register needs to be used. Further, the hardware for the shift registers can get to be quite e~tensive, where repeatability is desired for a great number of times.
BRIEF DESCRIPTION OF THE PRESENT INVENTION
The present invention achieves a successful resolution of the aforesaid problems by presenting a linear feedback shift register which is fully programmable, thereby eliminating the need to have a particular configured shift register for a specific function. The 1ip-flops and control logic circuits in the present invention shift register are configured in such a way that the register can be used, aside from the above-mentioned functions of a conventional linear feedback shift register, for encoding and encryption of information. To do this, the present invention shift 09~
register utilizes a plurality of flip-flop stages each with its own control logic circuits. Each flip-flop stage is identical; and consequently, the shift register can be programmed for different lengths, as the number of flip-flops need not remain static. The output of any one of the flip-flops can be fed, via a feedback circuit, to the beginning stage of the shift register, thereby providing a myriad of different length shift registers.
Therefore, it is an object of the present invention to provide a linear feedback shift register which is fully programmable.
It is a further object of the present invention to provide a shift register adaptable for different types of applications without having its components reconfigured.
It is yet another objective of the present invention to provide a shift register having a plurality of flip-flops, which can easily be added to or subtracted from the shift register.
The above-mentioned objects and advantages of the present invention will become more apparent and the invention itself will be best understood by reference to the following description of an embodiment of the invention taken in conjunction with the accompanying drawings, wherein:
BRIEF DESCRIPTION OF THE FIGURES
Figure 1 is an illustration of how the present invention shift register can be used in an overall system;
Figure 2 (including 2A and 2B) is a schematic representing the detailed digital realization of the present invention shift register;
Figure 3 ~including 3A and 3B) is a schematic diagram showing the cascading of a number of Figure 2 shift registers.
DETAILED D~SCRIPTION OF THE PRESENT INVENTION
Referring now to Figure 1, there is shown a crypto-communication system wherein a present invention shift register is incorporated. In this system, a fully programmable linear feedback shift register 2A, hereinafter to be referred to as FPLFSR 2A, is connected to a data source 4A, a micro-processor 6A and a modem 8A. Data which is to be transmitted to a corresponding system is sent from data source 4A to FPLFSR 2A, wherein this data is encoded, before being sent to the corresponding system. It should be appreciated that the operation of FPLFSR 2A is controlled by micro-processor 6A. Upon receiving the encoded data, modem 8B transmits the encoded data to FPLFSR 2B, wherein the encoded data is unscrambled. It shvuld be noted that both sets of transmitting and receiving components are identical and that the equations used for scrambling and unscrambling the data are the same.
Having described a possible application of the present invention, attention is directed to Figure 2, wherein a schematic drawing of the present invention shift register is shown. It must be emphasized that although 4 flip-flops are shown, the shift register is not limited to such a number, for an indefinite number of flip-flops and/or a multiple number of basic block shift registers can be cascaded to form shift registers having different numbers of flip-flops. As shown, FPLFSR 2 has four identical ~lip-flops FFA, FFB, FFC, and FFD. These flip-flops, for this example, are shown to be D-type flip~flops. Each of the flip-flops is associated to a number of logic gates, which are also identical. For example, in stage B, associated with flip-flop FFB are three AND gates 12B, 18B and 14B, exclusive OR gate 16B
and an OR gate 20B. Except for the first stage, that is, stage A, all of the loyic gates in remaining stages B, C and D are similarly connected to their respective flip-flops. Thus, it is sufficient that only one of these stages is discussed.
Focusing on stage B, it is seen that the outputs of AND
gates 12B and 14B are connec-ted as inputs of exclusive OR gate 16B. The output of exclusive OR gate 16B and the output of the remaining AND gate 18B are input to OR
gate 20B, the output of which is connected to input D of flip-flop FFB. AND gate 14B has four inputs. The first input comes from the F P line ~Feedback/Parallel Load Control line). This line primes flip-flops FFA to FFD
of the FPLFSR for parallel loading from lines FCn_PLn -to be discussed below - when the logic state thereon is low; for normal operation, the logic state of F_P
remains high. The second input going into AND gate 14B
is from a FCl_PL1 line (Feedback Control/Parallel Load line). It should be noted that the FCl_PL1 line is but one of four similar lines, referred to hereinabove as the FCn_PLn lines. Data fed from these lines are to be used either for parallel loading of a polynomial equation or for feedback control of the flip-flops.
A third input into AND gate 14B comes from the output of exclusive OR gate 26. The inputs and function of exclusive OR gate 26 will be described in greater ~2~0~
detail, infra. The last input going into AND gate 14B
comes fro~ an FFEl line (Flip-flop Enable line), which is but one of three identical lines. AND gate 12B, along with AND gates 12C and 12D, has three inputs. The first input for AND gate 12B comes from line F_P, which was described ~arlier. A second input comes from line FFEl. The last input comes from the output of flip-flop FFA of Stage A. AND gate 18B, like AND gates 18C and 18D, also has three inputs: the first input is fed from line FFEl; the second input is connected to line FCl_PLl; and the last input is connected to a line having a logic state opposite to that of line F P.
The output of flip-flop B is fed to the input of AND
gate 12C of flip-flop Stage C. Likewise, the output of flip-flop Stage C is sent to the input of AND gate 12D, thereby completing a series of cascaded flip-flop stages. Of course, the flip-flops are controlled by the timing pulses from the CLK line. Also, each of the flip-flops gets its power from VCC.
There are differences between the connections of the logic gates in flip-flop Stage A, when compared to the remaining flip-flop stages of the Figure 2 embodiment.
For example, for AND gate 12A, there are only two inputs. The first input is fed from line F_P while the second input is fed from line QIN, which is the serial data input for the first stage of the shift register;
alternatively, the second input of AND gate 12A may be fed the cascaded output from the last flip-flop of a previous shift register. Another difference in flip-flop Stage A is that there are only two inputs to AND gate 18A. The first input is fed from line FCO_PL0 while the second input is fed from line F_P', which has a logic state opposite to that of line F_P. As shown, the change of the logic state is due to the insertion of NOT gate 22 between line F_P and the inputs to respective AND gates 18A, 18B, 18C and 18D.
As was mentioned previously, the outputs of the respective flip-flop stages are cascaded from one stage to the next. Also, these outputs, i.e., Q0, Q1, Q2 and Q3, are respectively connected to AND gates 30A, 30~, 30C and 30D. For AND gate 30D, a second input is connected to line FFE3. The output of line FFE3 is converted into the opposite logic state by NOT gate 2gC
and fed as an input to AND gate 30C, which has an input fed from line FFE2. The logic state of line FFE2 is converted to an opposed sense by NOT gate 28B and fed to AND gate 30B, which also has as a third input line FFE1.
The logic state of line FFEl is inverted by NOT gate 28A
and fed as an input to AND gate 30A. Each of the outputs of AND gates 30A to 30D is input to OR gate 32, which has as its output signal NEWOUT. NE~OUT
represents the output of the last flip-flop stage used in the shift register. The outputs of the respective flip-flops are also connected as inputs to OR gate 34, thereby generating therefrom a CRC OUT output (Cyclic Redundancy Check Output). This output wlll be high when any of the flip-flop outputs is high in the basic shift register building block of Figure 2.
Output NEWOUT is fed to an input of AND gate 24, which also has an input signal from a F E line (Feedback Enable Line). The output from AND gate 24 is fed as an input to exclusive OR gate 26. An additional input to exclusive OR gate 26 is fed from line DATAIN. The output from exclusive OR gate 26 is fed simultaneously to the inputs of respective AND gates 14A, 14B, 14C and 14D. The same output is further routed to a CAS EN line 6~9~
~Cascade Enable Line). The CAS_EN line may be used to cascade the Figure 2 basic block shift register to an additional similar basic shift register block via the latter' 5 DATAIN line.
In operation, to initiate the system, a polynomial equation has to be first input into the respective flip-flops. This equation determines the number of flip-flops to be used, as well as the number of cycles before an initial message will repeat. For example, were a polynomial equation of X20 + x3 + 1 used, one would be able to ascertain from this equation that 20 flip-flops are to be used for the particular shift register. In the event that a basic building block shift register, for example, that shown in Figure 2, is available, then five of these basic blocks would be cascaded together, per Figure 4, so that there is a total of 20 flip-flops. In other words, the order of the polynomial equation signifies the number of flip-flops to be used in that particular programmable linear feedback shift register.
Too, the number of times which a message is to be circulated through the flip-flops of the shift register before it repeats, can be determined by subtracting one from base two to the power of the most significant digit. Hence, for the example just cited, a 20 flip-flop shift register would have to repeat the message 22 - 1, i.e., 1,048,575, times.
Returning now to the same polynomial equation, it should be noted that x3 represents the FC3_PL3 llne in Figure
Title of the Invention: FULLY PROGRAMMABLE LINEAR
FEEDBACK SHIFT REGISTER
FIELD OF THE INVENTION
The present invention relates to shift registers and more particularly to a fully programmable linear feedback shift register.
BRIEF DESCRIPTION OF THE PRIOR ART
Linear feedback shift registers which use a number of flip-flops for circulating information by means of a sequence of bits are known. It is further known that such shift registers may be used for error coding and pseudo-random number generation. However, for each of these applications, a differently configured shift register needs to be used. Further, the hardware for the shift registers can get to be quite e~tensive, where repeatability is desired for a great number of times.
BRIEF DESCRIPTION OF THE PRESENT INVENTION
The present invention achieves a successful resolution of the aforesaid problems by presenting a linear feedback shift register which is fully programmable, thereby eliminating the need to have a particular configured shift register for a specific function. The 1ip-flops and control logic circuits in the present invention shift register are configured in such a way that the register can be used, aside from the above-mentioned functions of a conventional linear feedback shift register, for encoding and encryption of information. To do this, the present invention shift 09~
register utilizes a plurality of flip-flop stages each with its own control logic circuits. Each flip-flop stage is identical; and consequently, the shift register can be programmed for different lengths, as the number of flip-flops need not remain static. The output of any one of the flip-flops can be fed, via a feedback circuit, to the beginning stage of the shift register, thereby providing a myriad of different length shift registers.
Therefore, it is an object of the present invention to provide a linear feedback shift register which is fully programmable.
It is a further object of the present invention to provide a shift register adaptable for different types of applications without having its components reconfigured.
It is yet another objective of the present invention to provide a shift register having a plurality of flip-flops, which can easily be added to or subtracted from the shift register.
The above-mentioned objects and advantages of the present invention will become more apparent and the invention itself will be best understood by reference to the following description of an embodiment of the invention taken in conjunction with the accompanying drawings, wherein:
BRIEF DESCRIPTION OF THE FIGURES
Figure 1 is an illustration of how the present invention shift register can be used in an overall system;
Figure 2 (including 2A and 2B) is a schematic representing the detailed digital realization of the present invention shift register;
Figure 3 ~including 3A and 3B) is a schematic diagram showing the cascading of a number of Figure 2 shift registers.
DETAILED D~SCRIPTION OF THE PRESENT INVENTION
Referring now to Figure 1, there is shown a crypto-communication system wherein a present invention shift register is incorporated. In this system, a fully programmable linear feedback shift register 2A, hereinafter to be referred to as FPLFSR 2A, is connected to a data source 4A, a micro-processor 6A and a modem 8A. Data which is to be transmitted to a corresponding system is sent from data source 4A to FPLFSR 2A, wherein this data is encoded, before being sent to the corresponding system. It should be appreciated that the operation of FPLFSR 2A is controlled by micro-processor 6A. Upon receiving the encoded data, modem 8B transmits the encoded data to FPLFSR 2B, wherein the encoded data is unscrambled. It shvuld be noted that both sets of transmitting and receiving components are identical and that the equations used for scrambling and unscrambling the data are the same.
Having described a possible application of the present invention, attention is directed to Figure 2, wherein a schematic drawing of the present invention shift register is shown. It must be emphasized that although 4 flip-flops are shown, the shift register is not limited to such a number, for an indefinite number of flip-flops and/or a multiple number of basic block shift registers can be cascaded to form shift registers having different numbers of flip-flops. As shown, FPLFSR 2 has four identical ~lip-flops FFA, FFB, FFC, and FFD. These flip-flops, for this example, are shown to be D-type flip~flops. Each of the flip-flops is associated to a number of logic gates, which are also identical. For example, in stage B, associated with flip-flop FFB are three AND gates 12B, 18B and 14B, exclusive OR gate 16B
and an OR gate 20B. Except for the first stage, that is, stage A, all of the loyic gates in remaining stages B, C and D are similarly connected to their respective flip-flops. Thus, it is sufficient that only one of these stages is discussed.
Focusing on stage B, it is seen that the outputs of AND
gates 12B and 14B are connec-ted as inputs of exclusive OR gate 16B. The output of exclusive OR gate 16B and the output of the remaining AND gate 18B are input to OR
gate 20B, the output of which is connected to input D of flip-flop FFB. AND gate 14B has four inputs. The first input comes from the F P line ~Feedback/Parallel Load Control line). This line primes flip-flops FFA to FFD
of the FPLFSR for parallel loading from lines FCn_PLn -to be discussed below - when the logic state thereon is low; for normal operation, the logic state of F_P
remains high. The second input going into AND gate 14B
is from a FCl_PL1 line (Feedback Control/Parallel Load line). It should be noted that the FCl_PL1 line is but one of four similar lines, referred to hereinabove as the FCn_PLn lines. Data fed from these lines are to be used either for parallel loading of a polynomial equation or for feedback control of the flip-flops.
A third input into AND gate 14B comes from the output of exclusive OR gate 26. The inputs and function of exclusive OR gate 26 will be described in greater ~2~0~
detail, infra. The last input going into AND gate 14B
comes fro~ an FFEl line (Flip-flop Enable line), which is but one of three identical lines. AND gate 12B, along with AND gates 12C and 12D, has three inputs. The first input for AND gate 12B comes from line F_P, which was described ~arlier. A second input comes from line FFEl. The last input comes from the output of flip-flop FFA of Stage A. AND gate 18B, like AND gates 18C and 18D, also has three inputs: the first input is fed from line FFEl; the second input is connected to line FCl_PLl; and the last input is connected to a line having a logic state opposite to that of line F P.
The output of flip-flop B is fed to the input of AND
gate 12C of flip-flop Stage C. Likewise, the output of flip-flop Stage C is sent to the input of AND gate 12D, thereby completing a series of cascaded flip-flop stages. Of course, the flip-flops are controlled by the timing pulses from the CLK line. Also, each of the flip-flops gets its power from VCC.
There are differences between the connections of the logic gates in flip-flop Stage A, when compared to the remaining flip-flop stages of the Figure 2 embodiment.
For example, for AND gate 12A, there are only two inputs. The first input is fed from line F_P while the second input is fed from line QIN, which is the serial data input for the first stage of the shift register;
alternatively, the second input of AND gate 12A may be fed the cascaded output from the last flip-flop of a previous shift register. Another difference in flip-flop Stage A is that there are only two inputs to AND gate 18A. The first input is fed from line FCO_PL0 while the second input is fed from line F_P', which has a logic state opposite to that of line F_P. As shown, the change of the logic state is due to the insertion of NOT gate 22 between line F_P and the inputs to respective AND gates 18A, 18B, 18C and 18D.
As was mentioned previously, the outputs of the respective flip-flop stages are cascaded from one stage to the next. Also, these outputs, i.e., Q0, Q1, Q2 and Q3, are respectively connected to AND gates 30A, 30~, 30C and 30D. For AND gate 30D, a second input is connected to line FFE3. The output of line FFE3 is converted into the opposite logic state by NOT gate 2gC
and fed as an input to AND gate 30C, which has an input fed from line FFE2. The logic state of line FFE2 is converted to an opposed sense by NOT gate 28B and fed to AND gate 30B, which also has as a third input line FFE1.
The logic state of line FFEl is inverted by NOT gate 28A
and fed as an input to AND gate 30A. Each of the outputs of AND gates 30A to 30D is input to OR gate 32, which has as its output signal NEWOUT. NE~OUT
represents the output of the last flip-flop stage used in the shift register. The outputs of the respective flip-flops are also connected as inputs to OR gate 34, thereby generating therefrom a CRC OUT output (Cyclic Redundancy Check Output). This output wlll be high when any of the flip-flop outputs is high in the basic shift register building block of Figure 2.
Output NEWOUT is fed to an input of AND gate 24, which also has an input signal from a F E line (Feedback Enable Line). The output from AND gate 24 is fed as an input to exclusive OR gate 26. An additional input to exclusive OR gate 26 is fed from line DATAIN. The output from exclusive OR gate 26 is fed simultaneously to the inputs of respective AND gates 14A, 14B, 14C and 14D. The same output is further routed to a CAS EN line 6~9~
~Cascade Enable Line). The CAS_EN line may be used to cascade the Figure 2 basic block shift register to an additional similar basic shift register block via the latter' 5 DATAIN line.
In operation, to initiate the system, a polynomial equation has to be first input into the respective flip-flops. This equation determines the number of flip-flops to be used, as well as the number of cycles before an initial message will repeat. For example, were a polynomial equation of X20 + x3 + 1 used, one would be able to ascertain from this equation that 20 flip-flops are to be used for the particular shift register. In the event that a basic building block shift register, for example, that shown in Figure 2, is available, then five of these basic blocks would be cascaded together, per Figure 4, so that there is a total of 20 flip-flops. In other words, the order of the polynomial equation signifies the number of flip-flops to be used in that particular programmable linear feedback shift register.
Too, the number of times which a message is to be circulated through the flip-flops of the shift register before it repeats, can be determined by subtracting one from base two to the power of the most significant digit. Hence, for the example just cited, a 20 flip-flop shift register would have to repeat the message 22 - 1, i.e., 1,048,575, times.
Returning now to the same polynomial equation, it should be noted that x3 represents the FC3_PL3 llne in Figure
2. Of course, the least significant digit 1 of the polynomial equation actually represents the coefficient of x. Therefore, for this particular polynomial ~2~
equation, there are 20 flip-1Op stages, with the logic state of lines FC3_PL3 and FC0_PL0 being high. Any messages - represented by 0's and l's - which are to be shifted by the shift register, will be encoded by this polynomial equation; and the encoded message will repeat after 22 1 cycles.
To input the polynomial equation into the different flip-flop stages, line F P is set to a high state. At this time, the data in the FCn_PLn lines are fed in parallel to the respective flip-flops. If there are more flip-flop stages available than is needed for a particular shift register, the FFEn lines can be used to designate from which flip-flop stage the final output of a message will be taken. For instance, were only three flip-flop stages needed in the Figure 2 basic block shift register, then line FFE3 would be set to the low state, i.e., 0, while lines FFE2 and FFEl would be set to the high state, i.e., 1. By first setting the logic states of the respective FFE lines, the last flip-flop stage D is effectively eliminated from the basic block shift register. Accordingly, output Q2 from flip-flop FFC, which output is connected to an input of AND gate 30C, becomes the final output of the Figure 2 basic ; block shift register. The Q2 output, along with outputs from Ql and Q0, which are respectlvely connected to AND
gates 30B and 30A, is gated by OR gate 32 and fed to the NEWOUT line. As was mentioned previously, the output from this NEWOUT line is to be used as a feedback signal and is routed to AND gate 24.
For normal feedback operation, after a polynomial equation has been fed into the respective flip-flops, line F_P is kept in the high state. This means that no parallel loading would occur on each rise of a clock pulse, supplied by clock line CLKo During this normal operation, feedback occurs~ The feedback is initiated by first setting the ~_E line on a high logic state.
When line F_E is high, the data stored in the flip-flops are advanced to the next stage and the feedback control data on the FCn_PLn lines are preloaded into the flip-flops of the shift register. Any input messages would be fed serially from line QIN to the first flip-flop stage, Stage A for this example. If there is shifting, and if line F_E and output from line NEI~OUT
are both set high, the output from the last flip-flop stage is exclusively ORed with the feedback control data from the FCn_PLn lines before being fed into the first stage (Stage A) of the shift register. Therefore, whatever polynomial equation is on the FCn_PLn lines gets shifted back into the shift register. This shifting will continue until the required number of times for circulating the message is satisfied.
In an effort to make sure that the flip-flops in a particular basic block shift register are operating correctly, the outputs of these flip-flops, i.e., Q0 to Q3, are gated to OR gate 34 which output, when registering a high logic, signifies that at least one of the flip-flops is in a high logic state. This signal is for error checking and can easily be measured, for instance, by attaching an oscilloscope to the CRC_OUT
line.
As was mentioned previously, the basic block shift registers can be cascaded into a shift register having multiple flip-flops. Such is shown in Figures 3A and 3B
wherein five basic block shift registers, each containing four flip-flop stages, are cascaded to form a o~:~
20 flip-flop stage fully programmable linear feedback shift register.
While a preferred embodiment of the invention is disclosed for purposes of explanation, numerous changes, modifications, variations, substitutions, and equivalents, in whole or in part, will now be apparent to those skilled in the art to which the invention pertains. Accordingly, it is intended that the invention be limited only by the spirit and scope of the appended claims.
~L2~6C~
TP~ANSCRIPT ON
#INTIALIZATION
FORCE F_P 0 0 ~RANDOM NUMBER INPUTTED
FORCE FC0_PL0 1 0 FORCE FCl_PLl 1 0 force fe4_p14 1 0 foree fe5_pl5 1 0 foree fe6_pl6 1 0 foree fe7_pl7 1 0 FORCE FC8_PL8 1 0 FORCE FC9_PL9 1 0 FORCE FC10_PL10 1 0 FORCE FCll PLll 1 0 force fe12 pll2 1 0 foree fc13_pll3 1 0 foree fc14_pll4 1 0 force fc15_pll5 1 0 FORCE FC16_PL16 1 0 FORCE FC18_PL18 1 0 FORCE FC19_PL19 1 0 #FLIP FLOPS ENABLED ~IERE
FORCE FFEl 1 0 APPENDIX Al 9~
force ffe5 1 0 force ffe6 1 0 force ffe7 1 0 FORCE FFEll 1 0 force ffel3 1 0 force ffel4 1 0 force ffel8 1 0 force ffel9 1 0 #FEEDBACK
FORCE F_El 0 0 force f_e2 0 0 FORCE F_E3 0 0 force f e4 0 0 FORCE F_E5 1 0 #POLYNOMIAL PROGRAMMED TO FEEDBACK CONTROL LI~ES HERE
FORCE FC0_PL0 1 60 FORCE FCl PLl 0 60 FORCE FC2_PL2 0 60 FORCE FC3_PL3 1 60 force fc4_pl4 0 60 force fc5_pl5 0 60 force fc6_pl6 0 60 force fc7_pl7 0 60 FORCE FC8_PL8 0 60 FORCE FC9_PL9 0 60 FORCE FC10_PL10 0 60 FORCE FCll_PLll 0 60 force fc12_pll2 0 60 force fc13_pll3 0 60 force fc14_p114 0 60 force fc15_pll5 0 60
equation, there are 20 flip-1Op stages, with the logic state of lines FC3_PL3 and FC0_PL0 being high. Any messages - represented by 0's and l's - which are to be shifted by the shift register, will be encoded by this polynomial equation; and the encoded message will repeat after 22 1 cycles.
To input the polynomial equation into the different flip-flop stages, line F P is set to a high state. At this time, the data in the FCn_PLn lines are fed in parallel to the respective flip-flops. If there are more flip-flop stages available than is needed for a particular shift register, the FFEn lines can be used to designate from which flip-flop stage the final output of a message will be taken. For instance, were only three flip-flop stages needed in the Figure 2 basic block shift register, then line FFE3 would be set to the low state, i.e., 0, while lines FFE2 and FFEl would be set to the high state, i.e., 1. By first setting the logic states of the respective FFE lines, the last flip-flop stage D is effectively eliminated from the basic block shift register. Accordingly, output Q2 from flip-flop FFC, which output is connected to an input of AND gate 30C, becomes the final output of the Figure 2 basic ; block shift register. The Q2 output, along with outputs from Ql and Q0, which are respectlvely connected to AND
gates 30B and 30A, is gated by OR gate 32 and fed to the NEWOUT line. As was mentioned previously, the output from this NEWOUT line is to be used as a feedback signal and is routed to AND gate 24.
For normal feedback operation, after a polynomial equation has been fed into the respective flip-flops, line F_P is kept in the high state. This means that no parallel loading would occur on each rise of a clock pulse, supplied by clock line CLKo During this normal operation, feedback occurs~ The feedback is initiated by first setting the ~_E line on a high logic state.
When line F_E is high, the data stored in the flip-flops are advanced to the next stage and the feedback control data on the FCn_PLn lines are preloaded into the flip-flops of the shift register. Any input messages would be fed serially from line QIN to the first flip-flop stage, Stage A for this example. If there is shifting, and if line F_E and output from line NEI~OUT
are both set high, the output from the last flip-flop stage is exclusively ORed with the feedback control data from the FCn_PLn lines before being fed into the first stage (Stage A) of the shift register. Therefore, whatever polynomial equation is on the FCn_PLn lines gets shifted back into the shift register. This shifting will continue until the required number of times for circulating the message is satisfied.
In an effort to make sure that the flip-flops in a particular basic block shift register are operating correctly, the outputs of these flip-flops, i.e., Q0 to Q3, are gated to OR gate 34 which output, when registering a high logic, signifies that at least one of the flip-flops is in a high logic state. This signal is for error checking and can easily be measured, for instance, by attaching an oscilloscope to the CRC_OUT
line.
As was mentioned previously, the basic block shift registers can be cascaded into a shift register having multiple flip-flops. Such is shown in Figures 3A and 3B
wherein five basic block shift registers, each containing four flip-flop stages, are cascaded to form a o~:~
20 flip-flop stage fully programmable linear feedback shift register.
While a preferred embodiment of the invention is disclosed for purposes of explanation, numerous changes, modifications, variations, substitutions, and equivalents, in whole or in part, will now be apparent to those skilled in the art to which the invention pertains. Accordingly, it is intended that the invention be limited only by the spirit and scope of the appended claims.
~L2~6C~
TP~ANSCRIPT ON
#INTIALIZATION
FORCE F_P 0 0 ~RANDOM NUMBER INPUTTED
FORCE FC0_PL0 1 0 FORCE FCl_PLl 1 0 force fe4_p14 1 0 foree fe5_pl5 1 0 foree fe6_pl6 1 0 foree fe7_pl7 1 0 FORCE FC8_PL8 1 0 FORCE FC9_PL9 1 0 FORCE FC10_PL10 1 0 FORCE FCll PLll 1 0 force fe12 pll2 1 0 foree fc13_pll3 1 0 foree fc14_pll4 1 0 force fc15_pll5 1 0 FORCE FC16_PL16 1 0 FORCE FC18_PL18 1 0 FORCE FC19_PL19 1 0 #FLIP FLOPS ENABLED ~IERE
FORCE FFEl 1 0 APPENDIX Al 9~
force ffe5 1 0 force ffe6 1 0 force ffe7 1 0 FORCE FFEll 1 0 force ffel3 1 0 force ffel4 1 0 force ffel8 1 0 force ffel9 1 0 #FEEDBACK
FORCE F_El 0 0 force f_e2 0 0 FORCE F_E3 0 0 force f e4 0 0 FORCE F_E5 1 0 #POLYNOMIAL PROGRAMMED TO FEEDBACK CONTROL LI~ES HERE
FORCE FC0_PL0 1 60 FORCE FCl PLl 0 60 FORCE FC2_PL2 0 60 FORCE FC3_PL3 1 60 force fc4_pl4 0 60 force fc5_pl5 0 60 force fc6_pl6 0 60 force fc7_pl7 0 60 FORCE FC8_PL8 0 60 FORCE FC9_PL9 0 60 FORCE FC10_PL10 0 60 FORCE FCll_PLll 0 60 force fc12_pll2 0 60 force fc13_pll3 0 60 force fc14_p114 0 60 force fc15_pll5 0 60
Claims (13)
1. A fully programmable linear feedback shift register, comprising:
a plurality of cascaded flip-flops;
first means working cooperatively with the flip-flops for selecting a number of the flip-flops;
second means connected to the outputs of the flip-flops and the first means for receiving data from the last of the selected flip-flops;
first input means electrically connected to the flip-flops and a load control means for, upon a first command from the load control means, feeding a first set of data in parallel to the selected flip-flops, thereby establishing in the selected flip-flops a set of predetermined data, wherein the load control means, when not commanding the input means to feed the first set of data in parallel to the flip-flops, initiates a second command for inputting from a second input means a second set of data serially to the selected flip-flops;
third means connected to the second means and working cooperatively with the load control means and the first input means for routing the data from the last of the selected flip-flops to the first of the selected flip-flops, thereby causing the data in the respective selected flip-flops to advance to succeeding selected flip-flops;
whereby the second set of data is encoded by the set of predetermined data and wherein the encoded data are circulated through the selected flip-flops.
a plurality of cascaded flip-flops;
first means working cooperatively with the flip-flops for selecting a number of the flip-flops;
second means connected to the outputs of the flip-flops and the first means for receiving data from the last of the selected flip-flops;
first input means electrically connected to the flip-flops and a load control means for, upon a first command from the load control means, feeding a first set of data in parallel to the selected flip-flops, thereby establishing in the selected flip-flops a set of predetermined data, wherein the load control means, when not commanding the input means to feed the first set of data in parallel to the flip-flops, initiates a second command for inputting from a second input means a second set of data serially to the selected flip-flops;
third means connected to the second means and working cooperatively with the load control means and the first input means for routing the data from the last of the selected flip-flops to the first of the selected flip-flops, thereby causing the data in the respective selected flip-flops to advance to succeeding selected flip-flops;
whereby the second set of data is encoded by the set of predetermined data and wherein the encoded data are circulated through the selected flip-flops.
2. A fully programmable linear feedback shift register according to claim 1, wherein the predetermined data includes data for presetting the number of times the encoded data are to circulate through the selected flip-flops.
3. A fully programmable linear feedback shift register according to claim 2, wherein the first means comprises a plurality of data lines having logic states thereof controlled by an external controlling means.
4. A fully programmable linear feedback shift register according to claim 2, wherein each flip-flop has at its input a plurality of logic circuits and wherein these circuits include AND, exclusive OR and OR gates.
5. A fully programmable linear feedback shift register according to claim 2, wherein the second means includes a plurality of AND gates having outputs thereof connected to an OR gate, the inputs of the AND gates being cascaded by a plurality of NOT gates.
6. A fully programmable linear feedback shift register according to claim 2, wherein the flip-flops are of the D type.
7. A fully programmable linear feedback shift register according to claim 2, wherein the third means includes an alternate feedback control input, an AND gate and an exclusive OR gate and wherein the third means is initiated by combining the data output from the second means and a feedback enable signal from the alternate feedback control input.
8. A fully programmable linear feedback shift register according to claim 2, further comprising:
a redundancy check output for determining whether any of the flip-flops is in a high logic state.
a redundancy check output for determining whether any of the flip-flops is in a high logic state.
9. Apparatus for generating and decoding digital data, the apparatus having a plurality of shift registers in cascade, the shift registers being variable in length, each of the shift registers comprising;
a plurality of cascaded flip-flops;
a plurality of data lines, corresponding to the number of flip-flops, each electrically connected to a particular flip-flop;
a plurality of enable lines each connected to a corresponding one of the flip-flops, a high logic state in an enable line signifying the selection of the corresponding flip-flop as a stage of the shift register;
a load control means working cooperatively with the data lines and the selected flip-flops for initiating the feeding in parallel of a set of predetermined data from the data lines to the selected flip-flops, thereby establishing in the selected flip-flops predetermined data; the load control means, when not working cooperatively with the data lines for feeding in parallel a set of predetermined data to the flip-flops, initiates the inputting of a set of data serially to the selected flip-flops from a serial data input, the set of serial data being encoded by the set of previously stored predetermined data;
a plurality of identical logic circuits each electrically connected to an output of a corresponding flip-flop, one of the logic circuits receiving data from the last of the selected flip-flops, the logic circuits having one common output;
a feedback circuit having an input connected to the output of the logic circuits and an output electrically connected to the inputs of the respective flip-flops, the feedback circuit working cooperatively with the data lines for routing the data from the last of the selected flip-flops to the first of the selected flip-flops, thereby causing the data in the respective selected flip-flops to advance to succeeding flip-flops;
whereby the set of encoded data is circulated through the selected flip-flops.
a plurality of cascaded flip-flops;
a plurality of data lines, corresponding to the number of flip-flops, each electrically connected to a particular flip-flop;
a plurality of enable lines each connected to a corresponding one of the flip-flops, a high logic state in an enable line signifying the selection of the corresponding flip-flop as a stage of the shift register;
a load control means working cooperatively with the data lines and the selected flip-flops for initiating the feeding in parallel of a set of predetermined data from the data lines to the selected flip-flops, thereby establishing in the selected flip-flops predetermined data; the load control means, when not working cooperatively with the data lines for feeding in parallel a set of predetermined data to the flip-flops, initiates the inputting of a set of data serially to the selected flip-flops from a serial data input, the set of serial data being encoded by the set of previously stored predetermined data;
a plurality of identical logic circuits each electrically connected to an output of a corresponding flip-flop, one of the logic circuits receiving data from the last of the selected flip-flops, the logic circuits having one common output;
a feedback circuit having an input connected to the output of the logic circuits and an output electrically connected to the inputs of the respective flip-flops, the feedback circuit working cooperatively with the data lines for routing the data from the last of the selected flip-flops to the first of the selected flip-flops, thereby causing the data in the respective selected flip-flops to advance to succeeding flip-flops;
whereby the set of encoded data is circulated through the selected flip-flops.
10. Apparatus according to claim 9, wherein the predetermined data includes data for presetting the number of times the set of encoded data is to circulate through the selected flip-flops.
11. Apparatus according to claim 9, further comprising:
a redundancy check output for determining whether any of the flip-flops has a high logic output.
a redundancy check output for determining whether any of the flip-flops has a high logic output.
12. Apparatus according to claim 9,wherein each logic circuit comprises an AND gate.
13. Apparatus according to claim 9, wherein the feedback circuit comprises an AND gate having its output connected to a first input of an exclusive OR gate and an alternate feedback control signal being fed to a second input of the exclusive OR gate.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/934,588 US4734921A (en) | 1986-11-25 | 1986-11-25 | Fully programmable linear feedback shift register |
| US934,588 | 1986-11-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1266096A true CA1266096A (en) | 1990-02-20 |
Family
ID=25465769
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000552722A Expired - Fee Related CA1266096A (en) | 1986-11-25 | 1987-11-25 | Fully programmable linear feedback shift register |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4734921A (en) |
| EP (1) | EP0290589A4 (en) |
| JP (1) | JPH01501979A (en) |
| CA (1) | CA1266096A (en) |
| WO (1) | WO1988004097A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE68928600T2 (en) * | 1988-09-07 | 1998-07-02 | Texas Instruments Inc | Extended test circuit |
| US6304987B1 (en) * | 1995-06-07 | 2001-10-16 | Texas Instruments Incorporated | Integrated test circuit |
| JP3005250B2 (en) | 1989-06-30 | 2000-01-31 | テキサス インスツルメンツ インコーポレイテツド | Bus monitor integrated circuit |
| DE69326681T2 (en) * | 1993-04-06 | 2000-02-10 | Hewlett Packard Co | Method and apparatus for generating linear feedback shift register sequences |
| GB2304941B (en) * | 1995-06-24 | 1999-09-08 | Motorola Ltd | Feedback and shift unit |
| JPH10117147A (en) * | 1996-10-09 | 1998-05-06 | Nec Corp | Data generating circuit for error check |
| US6201870B1 (en) | 1997-03-20 | 2001-03-13 | Massachusetts Institue Of Technology | Pseudorandom noise sequence generator |
| US6097889A (en) * | 1997-06-23 | 2000-08-01 | Motorola, Inc. | Signal processing apparatus with stages in a signal path operating as LFSR of alternable type and method for processing signals |
| US6408413B1 (en) | 1998-02-18 | 2002-06-18 | Texas Instruments Incorporated | Hierarchical access of test access ports in embedded core integrated circuits |
| US6405335B1 (en) | 1998-02-25 | 2002-06-11 | Texas Instruments Incorporated | Position independent testing of circuits |
| US6118869A (en) * | 1998-03-11 | 2000-09-12 | Xilinx, Inc. | System and method for PLD bitstream encryption |
| US7058862B2 (en) * | 2000-05-26 | 2006-06-06 | Texas Instruments Incorporated | Selecting different 1149.1 TAP domains from update-IR state |
| US7146506B1 (en) * | 1999-05-25 | 2006-12-05 | Intel Corporation | Digital video display system |
| US6728915B2 (en) | 2000-01-10 | 2004-04-27 | Texas Instruments Incorporated | IC with shared scan cells selectively connected in scan path |
| US6769080B2 (en) | 2000-03-09 | 2004-07-27 | Texas Instruments Incorporated | Scan circuit low power adapter with counter |
| US20070016842A1 (en) * | 2005-07-13 | 2007-01-18 | Microchip Technology Incorporated | Method and apparatus for configuring a cyclic redundancy check (CRC) generation circuit to perform CRC on a data stream |
| US7668893B2 (en) * | 2005-08-30 | 2010-02-23 | Micron Technology, Inc. | Data generator having linear feedback shift registers for generating data pattern in forward and reverse orders |
| US10708043B2 (en) | 2013-03-07 | 2020-07-07 | David Mayer Hutchinson | One pad communications |
| JP6093207B2 (en) * | 2013-03-08 | 2017-03-08 | 株式会社メガチップス | Linear feedback shift register |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3278727A (en) * | 1963-11-25 | 1966-10-11 | Borg Warner | Digital frequency selector |
| GB1190809A (en) * | 1967-06-26 | 1970-05-06 | Ericsson Telefon Ab L M | Improvements in and relating to the Generation of a Pulse Code |
| US3566230A (en) * | 1968-02-20 | 1971-02-23 | Leeds & Northrup Co | Electronic counters |
| US4173003A (en) * | 1970-12-28 | 1979-10-30 | The United States Of America As Represented By The Secretary Of The Navy | Deltic (time compressor) with adjustable multiplication ratio |
| US3742381A (en) * | 1971-06-09 | 1973-06-26 | California Inst Of Techn | Wideband digital pseudo gaussian noise generator |
| JPS5040656B2 (en) * | 1971-11-12 | 1975-12-25 | ||
| US3887869A (en) * | 1972-07-25 | 1975-06-03 | Tau Tron Inc | Method and apparatus for high speed digital circuit testing |
| US3911330A (en) * | 1974-08-27 | 1975-10-07 | Nasa | Nonlinear nonsingular feedback shift registers |
| US4234849A (en) * | 1976-07-26 | 1980-11-18 | Hewlett-Packard Company | Programmable frequency divider and method |
| JPS53143549U (en) * | 1977-04-18 | 1978-11-13 | ||
| US4438350A (en) * | 1977-11-17 | 1984-03-20 | Scientific Circuitry, Inc. | Logic circuit building block and systems constructed from same |
| JPS5951783B2 (en) * | 1978-04-07 | 1984-12-15 | 東光株式会社 | programmable down counter |
| US4334194A (en) * | 1978-12-26 | 1982-06-08 | The United States Of America As Represented By The Secretary Of The Army | Pulse train generator of predetermined pulse rate using feedback shift register |
| JPS55123239A (en) * | 1979-03-15 | 1980-09-22 | Matsushita Electric Ind Co Ltd | Programmable divider |
| DE3009945A1 (en) * | 1979-03-15 | 1980-09-18 | Nippon Electric Co | INTEGRATED, LOGICAL CIRCUIT WITH FUNCTIONAL TEST |
| US4296380A (en) * | 1979-05-21 | 1981-10-20 | Matsushita Electric Industrial Co. | Programmable digital frequency divider for synthesizing signals at desired frequency |
| US4380816A (en) * | 1981-06-03 | 1983-04-19 | Raytheon Company | Apparatus for recycling complete cycles of a stored periodic signal |
| JPS61237521A (en) * | 1985-04-12 | 1986-10-22 | Mitsubishi Electric Corp | Coding and decoding circuit of error correction code |
-
1986
- 1986-11-25 US US06/934,588 patent/US4734921A/en not_active Expired - Fee Related
-
1987
- 1987-11-23 WO PCT/US1987/003056 patent/WO1988004097A1/en not_active Application Discontinuation
- 1987-11-23 JP JP63500466A patent/JPH01501979A/en active Pending
- 1987-11-23 EP EP19880900182 patent/EP0290589A4/en not_active Withdrawn
- 1987-11-25 CA CA000552722A patent/CA1266096A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US4734921A (en) | 1988-03-29 |
| EP0290589A4 (en) | 1991-08-14 |
| EP0290589A1 (en) | 1988-11-17 |
| WO1988004097A1 (en) | 1988-06-02 |
| JPH01501979A (en) | 1989-07-06 |
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