CA1275326C - Error correction apparatus for digital data - Google Patents
Error correction apparatus for digital dataInfo
- Publication number
- CA1275326C CA1275326C CA000528110A CA528110A CA1275326C CA 1275326 C CA1275326 C CA 1275326C CA 000528110 A CA000528110 A CA 000528110A CA 528110 A CA528110 A CA 528110A CA 1275326 C CA1275326 C CA 1275326C
- Authority
- CA
- Canada
- Prior art keywords
- error
- series
- word
- pointers
- pointer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
- G11B20/1806—Pulse code modulation systems for audio signals
- G11B20/1809—Pulse code modulation systems for audio signals by interleaving
Abstract
ERROR CORRECTION APPARATUS FOR DIGITAL DATA
ABSTRACT OF THE DISCLOSURE
An error correcting system in which received digital data is subjected to correcting processes by first and second error correction codes alternately is provided with memories to store first and second series error pointers for a plurality of series of the first and second error correction codes, and such first and second series error printers are read to determine which series are without error, whereupon the correcting processes of the first and second error correction codes are omitted with respect to the error-free series. As a result, the number of times effective correcting processes can be repeated within a limited time is increased and the correcting capability can be substantially improved.
ABSTRACT OF THE DISCLOSURE
An error correcting system in which received digital data is subjected to correcting processes by first and second error correction codes alternately is provided with memories to store first and second series error pointers for a plurality of series of the first and second error correction codes, and such first and second series error printers are read to determine which series are without error, whereupon the correcting processes of the first and second error correction codes are omitted with respect to the error-free series. As a result, the number of times effective correcting processes can be repeated within a limited time is increased and the correcting capability can be substantially improved.
Description
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Field of th~ Invention . ~ . . .
This inven-tion relakes generally to the correction of digital ~iqnals and, ~lore specifically, is directed to ~he correction o exrors in digital audio signals which are, for exampl~, recorded on a magnetic tape or the like.
Descr~ on of the Prior Art It is Xnown to use the so-called cross-interleave technique for transforming a digital data signal into an error correctable code structure for digital data transmisslon or for recording and reproducing. It is the usual practice, when using the cross-interleave techni~ue, to use modulo-2 adders to generate two parity series P and Q, each representing predetermined numbers of the data words in two different arrangements. Because each word of the digital data signal will be contained in the two parity series, this known cross-interleave technique provides a substantial error correcting capability, particularly when the correcting procésses axe repeatedly performed.
In the error correcting system employing the cross-interleave technique in a conventional PCM tape recorder, for example, a so-called 8 mm VTR for digital audio signals, if only one error word is found to exist in the P or Q series by detecting word error pointers of such series, that single error word is correc ed. ~owever, in all other cases, that is, when no error word exists so that it is unnecessary to corxect the same, or when two or more error words exist and hence cannot be corrected, the word error pointers are merely read out and no error correction ~,,, .
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process is performed. Thus, when no error word exists or when two or more error words exist, the time required to read out the word error pointers is wasted.
When using the cross-interleave technique, the number of error words that can be corrected is increased, so that the error correcting capability is improved, by increasing the number of ~imes ~hat the error correcting processes are repeated in respect to the P and Q seri~s.
However, since the overall time available for ~he error correcting processes is usually limited to a predetermined time interval, the previously described wasted time required for reading out word error pointers ~hen no error correction is or can be ef~ected, necessarily limits the number of repetitions of the correcting processes that can be performed within such limited time interval. Hence, enhancement of the correcting capability is restricted.
OBJECTS AND SUMMARY OF T~E INVENTION
Accordingly, it is an object o~ the present invenkion to provide an error correcting system in which the number of times that the effective correcting processes can be repeated within the limited time available therefor is increased so as to improve the error correcting capability.
Generally, in accordance with this invention, in an error correcting system in which the digital data is transformed into an error correctable code structure including first and second error correction codes, and the correcting processes by the first and second error correction codes are alternately performed, a memory is provided for storing first series error pointers indicating ' -, ~ . ' 7~
the pre~ence or abse~ce of an error in each of ~he first error cor~ection code series, and a memory is provided for storing second series error pointers indicating the pr~sence or absence of an error in each of the second error correction code series, and the first or second series error pointers ~re read out from the respective memory before pexforminy the error correcting processes by the first or second error coxrec~ion code for the respective series with the correcting processes being omitted in respect to Pach series which is indicated to be free of error by the respectlve irst or second ~eries error pointer.
It will be appreciated that, by referring to the series error pointer indicative of the presence or absence of an error in the words forming the respective series under consideration, it is possible to omit the reading out of the word error pointers for determining whether or not the correcting processes can be or even need to be performed.
When the correcting processes are repeatedly performed, the number of error words to be corr~cted gradually decreases so that the number of series having no erxor is increased.
Thus, in accordance with the invention, the time wasted in accessing th~ word error pointers for series that contain no errors can be drastically reduced with the result that the numbers of error words that can be corrected within a limited time is increased.
~ he above, and other objects, features and advantages of the present invention, will be apparent in the fo1lowing detailed description of ~he invention which is ~o be read in connection with the accompanying drawings.
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_IEE DES ~
Fig. lA iS a diagrammatic representation of the arrangement of data and the relationship thersof to parity series tha~ have been used in recording PCM audio signals;
Fig. lB diagrammatically represents the capacities of random access memories (RAMs) for storing parity series error pointers in an error corracting apparatus according to an embodiment of the invention;
Fig. 2 is a diagrammatic representation of a block of data to which the invention may be applied;
Fig. 3 is a bloc~ diagram showing an error correcting apparatus according to an embodiment of the invention; and FigsO 4 and 5 are flow charts to which reference will be made in explaining the operation of the error correcting apparatus according to an emhodiment of the invention.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
An embodiment of the present invention will her~inafter be described as applied to errcr corxection of PCM audio signals recorded and reproduced by a conventional or standard 8 mm. VTR. In such 8 mm. VTR, a magnetic tape having a width of 8 mm. is wound around th~ p~ripheral surfac~ of a rotary drum with a wrap angle of 2~1. Within this wrap angle, a range of 180 is used as the recording region for video signals, and a range of 36 is used as the recording region for PCM audio signals. A pair of rotary heads are attached to the drum with an angular distance of 180 therebetween, and the drum is ro~ated at the frame 3~i frequency. The rotary heads move obliquely across the magnetic tape in sliding contact therewith so as to trace succes~ive slan~ or oblique tracks. The video signal for one field i9 supplied to one of the rotary heads so as to be recorded thereby in ~ respective track while scanning the recordi~g region for the video signals. The PCM audio signals for one field, after having been encoded with the error correction code and subjected to suitably time base compression, are supplied to one of the heads so as to be recorded thereby in the respecti~e track while scanning the recording region for PCM signals.
In the 8 mm. VTR, the encoding and decoding processes fox error correction ara executed with the PCM
audio signals for one field being used as a unit, for example, as disclosed in detail in U.S~ Patent No.
4,562,578, having an assi~nee in cdmmon herewith. Such unit is comprised of 132 blocks, with each block including 8 words of digital audio data Wo-W7 and 2 words of parity data P and Q. A cyclic redundancy check (CRC~ code for error detection is added to the data of each block, and each block further has added thereto, before its recording, a block synchronizing signal and a block address signal, as indicated on Figs. lA and 2. If the data of the first block is taken out of context and examined separately, it will appear as shown in Fig. 2, it being understood that, after this first block, there will follow the second ~lock, the third block, - - up to the 132d block, moving from left to right on Fig. lA.
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In the ~wo-dimensional or matrix arrangement of ~he data unit shown on Fig. lA, each of the 132 blocks arranged laterally one after the other contains 8 data words, that is, there are 1056 words in the data uni-t. The dlgital audio signal oE one field in the NTSC system is comprised of 1050 words with each ~ord consisting of 8 bits.
Therefore, 6 words of suitable control data are included in the data unit along with the audio PCM signals of the right and left channels for one field. In Fi~. lA, the data for each block is arranged in a vertical column and each of the hoxizontally extending lines identified as Q,WorWl,W2,W3,P, W4,W5,W6, and W7 is comprised of 132 words of data.
A first parity series (the P series) is formed by 9 words taken ~xom the audio data series Wo-W7 and the parity series P with a dista~ce between such words of 14 blocks or 15 ~ocks in the lateral direction, and with the words contained in this parity series P being symbolized by solid circles on Fig. lA. A second parity series Q is formed of 10 words symbolized by open circles in Fig. lA and which are taken from the audio data series W0 to W7, the first parity series P and the second parity series Q with a distance of 12 blo~ks between adjacen~ symbols. As is apparent from Figs~ lA and 2, the first parity series P is desirably positioned at the center of the respective block, while the second parity series Q is positioned at an end of the block.
As noted above, that each of thP data word series Wo-W7 and each of the parity series P and Q arranged in a ~ respective horizontal line in the matrix of Fig. lA has ,:
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. . .
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132 words in the respective series~ Therefore, each element of the P and Q series can be identified by a number n (n=O
to 131~.
As hereinafter described in detail, in accordance with the present invention, a random access memory (~AM) 11 is provided to store l-bit error pointers for the parity s~ries P and, similarly a random access memory (R~M) 12 is provided to store l-bit error pointers for the parity series Q. Since there are 132 elements or words in each of the parity series P and Q, each of the series error pointer RAMs 11 and 12 has a 132 bit-capacity, as shown in Fig. lB.
As is well known, the presence or absence of an error in each block is detected by the respective CRC code.
Since simple parity is used~ if the CRC check dPtermines that only a single error word exists in the P or Q series, that single error word can be corrected. Moreover, by repeating the decoding or error correcting processes in respect to the P and Q series, the error correcting capability can be improved. As is well known, in the case of the PC~ audio signals, erroneous data that cannot be corrected by the error correction code are interpolated or replaced by the average of the correct data existing before and after the uncorrected erroneous data.
Referring now to Fig. 3, it will be se.en that, in an embodiment of the present invention there illustrated, the reproduced or received PCM data and parity data appli~d to an input 1 are stored or written in a data RAM 2 at addresses determined by an address generator 3. Such reproduced data, prior to being stored in RAM 2, is ;
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sllbjected to error d~tection by a CRC arithmetic operating circuit (not shown) which provides l~bit word error point2rs indicating whether or not an error is detected in each word.
The ~ord error pointers are applied to an input 4 and are writ~en therefrom in a word pointer RA~I 5. The data RAM 2 has a capacity suitable to store the reproduced data for one fi~ld which, as previously indicatzd, consists of 10 words of PCM data and parity data in each of 132 blocks.
Therefore, data RAM 2 has a sufficient capacity to store 1320 ~ords of data~ On the other hand, word pointer RAM 5 has a capacity of 1320 bits, so as to be capable o~ storing a l~bit word error pointer for each of the words included in one field of data. The addresses in the word pointer RAM 5 at which the word error pointers are written are also determined by address generator 3. The data stored in data ~AM 2 and the word error pointers stored in word pointer RAM
5 are supplied through a switching circuit 6 to a correc~ing circuit 7 and a counter 8.
In order to pexfol~ the correcting processes of the P series, the 9 word error pointers indicating the 9 woras forming the first of the P series are read from word pointer RAM 5 and passed through switching circuit 6 to counter 8. I~ o~ly one word error pointer corresponding to a word error is detected by counter 8, the latter causes correcting circuit 7 to correct the corresponding single error word, whereupon tbe corrected data or word is written into data RAM 2 in place of the error word and, at the same time, the word error pointer corresponding to the corrected error word is cleared from word pointer R~M 5. If no error 53~
wo~d is de-tacked, or if two or more exror words are detected or counted among the 9 word error pointers corresponding to the :Eirst P series, no correcting process is executed, that is, correctlng circuit 7 is inoperative to correct any data in ~1 2. The foregoin~ operaticns are repeated with respect to each of the 132 series of the P series, and also in respect to each of the 132 series of th~ Q series.
When no error word i5 detected or counted by counter 8, or when one error word has been corxected by correcting circuit 7, a correction completion pulse generating circuit 9 is operated to produce a correction completion pulse for a purpose hereinafter described in detail.
A timing pulse generator 10 is provided to prodl~ce suitable timing pulses for controlling the operations of address generator 3, switching circuit 6 and correct~ny .circuit 7. When word error pointer~ are ~eing read out from word poi.nter RAM 5 to be counted by counter 8 and when the word error pointers in RAM 5 are cleared after the correction of an error word, switching circuit 6 is disposed in the condition illnstrated on Fig. 3, that is, word pointer RAM 5 is connected to correcting circuit 7 and counter 8 by switching circuit 6. On the other hand, when an error word in data RAM 2 is to be replaced by a corrected word, switching circuit 6 is changed-over to connect RAM 2 . with correct.ing circuit 7.
As previously noted, the l-bit P series error pointers and the l-bit Q series error pointers are stored in P and Q series pointer RA~s ll and 12. The parity series , ~ ' ' ' ; ' :
.
~ ;~ 7S~326 error pointer E~Ms ll and 12 ~re addressed, in common, by an address generator 13 in response to timing pulses from generator 10. As earlier noted r each of the P and Q series includes 132 series, and the re~pective l-bit series ~rror pointers are stored at 132 respective addresses in RAMs 11 and 12, respectively. Each of the parity series error pointer~ may have the logic le~el or value "1~ to indicate that an erxor word e~ists in the respective pari~y series, whereas the series error pointer has the value "O" to indicate that no error word exists in the respective series.
All of the series error pointers are initially set at the high value "1", and each of the series error pointers is cleared or changed to the low value "O" when no error word exists in the respective parity series and when a single error word has been corrected.
A switching circuit 1~ is provided to alternately connect the P and Q series error pointer R~Ms 11 and 12 to a pointer clearing circuit 15 and to a pointer discriminating circuit or dPtector 16. The pointer clearing circuit 15 is connected to generator 9 for receiving the correction completion pulse from the latter and, in response to such correction completion pulse, pointer clearing circuit 15 is effective to clear or return to 110~ the pointer of the respective series of the P or Q series which has, no error.
In other words, the P or Q series error pointer for the P or Q series in which an error word was corrected by circuit 7 is cleared to "O". The pointer discriminating circuit 16 detenmines whether the P or Q series error pointer addressed in the RAM 11 or 12, respectively, is "O" of "1", and timing ~, . '.
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pulse generator 10 lS actuated in respcnse to such detection or discrimination.
As shown on Fig. 3, t.he switching operation of switching circuit 14 is also controlled by timing pulses from tlminy pulse generator 10. Finally, the P and Q series error pointer R2~1s 11 and 12 are adapted to receive the respective series error pointers at inputs 17 and 18, for example, from a suitable P,Q decoding circuit (not shown).
It will be understood that, during the correction of the Q
series, the Q series erxor poin-ter RAM 12 i5 con~ected to pointer clearing circuit 15 and pointer discriminating circuit 16 by the switching circuit 14 in the condition shown. On the other hand, during the correction of the P
series, switching circuit 14 is changed-over to connect the P series exror pointer RAM 11 with circuits 15 and 16.
In the case of the application of the present invention to an 8 mm. VTR, there will be two sets of the data RAM 2, error word pointer RAM 5, P series error pointer RAM 11 and Q series error pointer RAM 12 for processing the PCM signals of alternate fields. Thus, during a field in which the PCM signal is being written in on~ set and error correcting operation are being performed thereon, the previously corrected PC~ signal and word error pointers are being read out from the other set.
The correction of errors in the above described embodiment of the invention will now be described with reference to ~he flow charts in Figs. 4 and 5. The first correcting processes are illustrated in Fig. 4 and will he described with respPct to an example in the P series.
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In step (1) the number n of the 132 series of the P series is initialized to 1l 0 l' , In step (2), the word error pointers ~or the 9 words form.i~g the P sexies identified by n=0 are read out of ~ord error pointer ~ 5. In step (3), it is determined by counter 8 if there is no error word among the 9 words forming the P series identified by n--0.
Of course, during steps ~21 and (3) switching circuit 6 remains in the position shown on Fig. 3 for connecting word error pointer RAM 5 with countex 8. If the answer to decisioa outline ~3) in Fig. 4 is "N" or "'NO", that is, one or more error words are counted ~y counter 8 among the 9 word errox pointers corresponding to the P series identified by n=0, the pxogram moves to st~p (4) in which it is determined if there is only one error word.
On the other hand, if the answer tc decision outline ~3)~ is "YES" or "Y", that is, if no error word is detected among the 9 words of data forming the P series identified by n=0, the program skips to step (6) in which correction completion pulse generator 9 causes pointer clearing circuit 1~ to clear the series error pointer stored in P series error pointer RAM 11 at the address for the P
series identified by n=0. Of course, at the time of such clearing of the series ,^-,rror pointer, switching circuit 14 is changed over to connect RAM 11 with pointer clearing circuit 15.
If the answer to the decision outline (4~ is "YES"
or "Y", that is, if one error word is detected in stap (4~, such error word is corrected in step ~5~, and then the program proceeds to step (6~ in which generator 9 provides a :; .
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correctlon completion pulse for causing pointer clearing circuit 15 ~o clear the series error pointer at the address in RA~ 11 corresponding to the P series identified by n=0.
Of course, during such correction of an error word, switching circuit 6 is changed-over to connet data ~AM 2 with correcting circuit 7.
On the other hand, if the answer to decision outline (4) is "NOi' or "N", that is, if two or more error words have been detected among the 9 data words forming the ~ series identified by n-0, no correcting process is or can be performed, that is, the program skips from step ~4) to step (7) in which the P series number n is increased by ~ , that is, to n=l. Similarly, upon the completion of step ~6) in which the series error pointer for the P series identified by n=0 is cleared, the program moves to step ~7) in which the identifying number n of the P series is incremented. The program moves from step (73 to step (8) in which it is determined whether the first correcting processes for the 132 series of the P series have been performed. In other words, step (8) determines if n=132.
If it is found that n~l32, the first correction procassing operation for the P series is terminated. However~ if n is found to be less than 132 in step (8), the program returns to step (2). After the first correcting processes ha~e been completed in respect to the P series, the first correcting processes are similarly e2ecuted in respect to the Q series.
As earlier noted, the COrrQCtion processing operations are desirably repeated in respect to the P series an~ the Q series. The second and each subsequent correction . ~:
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proces~i.ng opera~ion will now be described with reference to Fig. 5 in ~Ihich steps corresponding to those described above with reference to Fig. 4 are identifi.ed b~ the same reference numerals. Once again, the specific description of the correction processing operation illustrated on Fig. 5 will be with ref~r~nce to an example in the P series.
In the second or subsequent correction processing operation, the number n identifying the series of the P
series is initially set to n-0 in step (1). Then, with switchins circuit 14 changed-over to connect RAM 11 with pointer discriminating or detecting circuit 16, the program proceeds to step ~9) in which the 1-bit P series error pointer stored at the address for n=0 is read out of R2~1 11.
In step ll0), pointer discriminating circuit 16 detects if the P series error pointer being read out of RAM 11 is "1", that lS, if an error word is included in the 9 words of data which form the series of the P series identified by n=0. If the answer to the decision outline ~10) is "YES" or '~Y", that is, if the P series error pointer read out of RAM 11 is ~1", the program moves from step (10) to step (2) in which pointer discriminating circuit 16 actuates timing pulse generator 10 for causing the word error pointers , corresponding to the data words forming the series of the P
series identified by n=0 to be read out of RAM 5. In the next step (4) counter 8 determines from the word error pointers read out of RAM 5, if one error word exis~s among the 9 words making up the P series. If only one error word is detected in the P series being considered, th~ program moves to step (5) in which the single error word is :' ~
: -15-.. -: ; .
:.
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J~j corrected by correcting circuit 7 and, thereafter, corl-ection completion pulse generator 9 and pointer clearing circuit 15 are operative to clear to "O" the series error pointer stored in RAM 11 at the address corresponding to the P series identified by n-O. If two or more error words are detected by counte~ 8 in step (4), the error coxrecting step (5) and the series error pointer clearing step (6) are omitted and the program proceeds to s-tep (7). Similarly, if the l-~it P series error pointer read from the address in RAM 11 corresponding to n=O is I~On, that is, i~ the s~ries error pointer detectad in step (10) is not "1l', from which it follows that no error word exists in the 9 data words forming the P series being considered, the program skips steps (2),(4),~5) and (6) and proc~eds directly to step (7).
In step (7) the number n identifying the series of the P
s~ries being considered is incremented by 1, and then the program proceeds to step (8) in which it is determined whether n=132. If n is less than 132, the program is returned to step (9), whexeas, if n=132, the program is t~xminated. In other words~ the second or subsequent correction proces~ing operation illustrated in Fig. 5 is repeated in respect to each of the P series. Similarly, the second and subsequent correction processing operations are performed in respect to the Q series~
It will be appreciated that error correction in accordanca with the present invention is not limi ted to : digital data that has been transformed into an error correctable code structure by the cross-interleave technique, but can be similarly applied to the product code .. . .
.- . ~ . .
" ' ' :
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~o~6 for p~rforminy error correction coding processes in the vertical and horizontal directions of the two-dimensional data arrangement. Further, the error correction code that is used is not limited to the simple parity code employed in the described example, but other codes, such as, the Reed-Solomon code or the like can also be used.
It will be appreciated that, in correcting errors according to the invention by means of two or more correction series and by repeating the correcting processes in respect to each series, the correcting processes are omitted in respect to any of such series devoid of error.
Therefore, the number of repetitions of the correcting processes that can ke effected in respect to each series within a specified time can be increased as compared with conventional error correcting systems in which the corxecting processes are performed even in respect to series that do not contain error.
~ aving described an illustrative embodiment of the invention, it is to he understood that the invention is not ; limited to that precise embodiment, and that various changes and modifications can bP effected therein by one skilled in the art without departing from the spirit or scope of the invention as defined in the append~d claims.
;::
~:
. .
Field of th~ Invention . ~ . . .
This inven-tion relakes generally to the correction of digital ~iqnals and, ~lore specifically, is directed to ~he correction o exrors in digital audio signals which are, for exampl~, recorded on a magnetic tape or the like.
Descr~ on of the Prior Art It is Xnown to use the so-called cross-interleave technique for transforming a digital data signal into an error correctable code structure for digital data transmisslon or for recording and reproducing. It is the usual practice, when using the cross-interleave techni~ue, to use modulo-2 adders to generate two parity series P and Q, each representing predetermined numbers of the data words in two different arrangements. Because each word of the digital data signal will be contained in the two parity series, this known cross-interleave technique provides a substantial error correcting capability, particularly when the correcting procésses axe repeatedly performed.
In the error correcting system employing the cross-interleave technique in a conventional PCM tape recorder, for example, a so-called 8 mm VTR for digital audio signals, if only one error word is found to exist in the P or Q series by detecting word error pointers of such series, that single error word is correc ed. ~owever, in all other cases, that is, when no error word exists so that it is unnecessary to corxect the same, or when two or more error words exist and hence cannot be corrected, the word error pointers are merely read out and no error correction ~,,, .
.
'.' ~ ,' : , ' 53~2~
process is performed. Thus, when no error word exists or when two or more error words exist, the time required to read out the word error pointers is wasted.
When using the cross-interleave technique, the number of error words that can be corrected is increased, so that the error correcting capability is improved, by increasing the number of ~imes ~hat the error correcting processes are repeated in respect to the P and Q seri~s.
However, since the overall time available for ~he error correcting processes is usually limited to a predetermined time interval, the previously described wasted time required for reading out word error pointers ~hen no error correction is or can be ef~ected, necessarily limits the number of repetitions of the correcting processes that can be performed within such limited time interval. Hence, enhancement of the correcting capability is restricted.
OBJECTS AND SUMMARY OF T~E INVENTION
Accordingly, it is an object o~ the present invenkion to provide an error correcting system in which the number of times that the effective correcting processes can be repeated within the limited time available therefor is increased so as to improve the error correcting capability.
Generally, in accordance with this invention, in an error correcting system in which the digital data is transformed into an error correctable code structure including first and second error correction codes, and the correcting processes by the first and second error correction codes are alternately performed, a memory is provided for storing first series error pointers indicating ' -, ~ . ' 7~
the pre~ence or abse~ce of an error in each of ~he first error cor~ection code series, and a memory is provided for storing second series error pointers indicating the pr~sence or absence of an error in each of the second error correction code series, and the first or second series error pointers ~re read out from the respective memory before pexforminy the error correcting processes by the first or second error coxrec~ion code for the respective series with the correcting processes being omitted in respect to Pach series which is indicated to be free of error by the respectlve irst or second ~eries error pointer.
It will be appreciated that, by referring to the series error pointer indicative of the presence or absence of an error in the words forming the respective series under consideration, it is possible to omit the reading out of the word error pointers for determining whether or not the correcting processes can be or even need to be performed.
When the correcting processes are repeatedly performed, the number of error words to be corr~cted gradually decreases so that the number of series having no erxor is increased.
Thus, in accordance with the invention, the time wasted in accessing th~ word error pointers for series that contain no errors can be drastically reduced with the result that the numbers of error words that can be corrected within a limited time is increased.
~ he above, and other objects, features and advantages of the present invention, will be apparent in the fo1lowing detailed description of ~he invention which is ~o be read in connection with the accompanying drawings.
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_IEE DES ~
Fig. lA iS a diagrammatic representation of the arrangement of data and the relationship thersof to parity series tha~ have been used in recording PCM audio signals;
Fig. lB diagrammatically represents the capacities of random access memories (RAMs) for storing parity series error pointers in an error corracting apparatus according to an embodiment of the invention;
Fig. 2 is a diagrammatic representation of a block of data to which the invention may be applied;
Fig. 3 is a bloc~ diagram showing an error correcting apparatus according to an embodiment of the invention; and FigsO 4 and 5 are flow charts to which reference will be made in explaining the operation of the error correcting apparatus according to an emhodiment of the invention.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
An embodiment of the present invention will her~inafter be described as applied to errcr corxection of PCM audio signals recorded and reproduced by a conventional or standard 8 mm. VTR. In such 8 mm. VTR, a magnetic tape having a width of 8 mm. is wound around th~ p~ripheral surfac~ of a rotary drum with a wrap angle of 2~1. Within this wrap angle, a range of 180 is used as the recording region for video signals, and a range of 36 is used as the recording region for PCM audio signals. A pair of rotary heads are attached to the drum with an angular distance of 180 therebetween, and the drum is ro~ated at the frame 3~i frequency. The rotary heads move obliquely across the magnetic tape in sliding contact therewith so as to trace succes~ive slan~ or oblique tracks. The video signal for one field i9 supplied to one of the rotary heads so as to be recorded thereby in ~ respective track while scanning the recordi~g region for the video signals. The PCM audio signals for one field, after having been encoded with the error correction code and subjected to suitably time base compression, are supplied to one of the heads so as to be recorded thereby in the respecti~e track while scanning the recording region for PCM signals.
In the 8 mm. VTR, the encoding and decoding processes fox error correction ara executed with the PCM
audio signals for one field being used as a unit, for example, as disclosed in detail in U.S~ Patent No.
4,562,578, having an assi~nee in cdmmon herewith. Such unit is comprised of 132 blocks, with each block including 8 words of digital audio data Wo-W7 and 2 words of parity data P and Q. A cyclic redundancy check (CRC~ code for error detection is added to the data of each block, and each block further has added thereto, before its recording, a block synchronizing signal and a block address signal, as indicated on Figs. lA and 2. If the data of the first block is taken out of context and examined separately, it will appear as shown in Fig. 2, it being understood that, after this first block, there will follow the second ~lock, the third block, - - up to the 132d block, moving from left to right on Fig. lA.
~ ~5i3;2~
In the ~wo-dimensional or matrix arrangement of ~he data unit shown on Fig. lA, each of the 132 blocks arranged laterally one after the other contains 8 data words, that is, there are 1056 words in the data uni-t. The dlgital audio signal oE one field in the NTSC system is comprised of 1050 words with each ~ord consisting of 8 bits.
Therefore, 6 words of suitable control data are included in the data unit along with the audio PCM signals of the right and left channels for one field. In Fi~. lA, the data for each block is arranged in a vertical column and each of the hoxizontally extending lines identified as Q,WorWl,W2,W3,P, W4,W5,W6, and W7 is comprised of 132 words of data.
A first parity series (the P series) is formed by 9 words taken ~xom the audio data series Wo-W7 and the parity series P with a dista~ce between such words of 14 blocks or 15 ~ocks in the lateral direction, and with the words contained in this parity series P being symbolized by solid circles on Fig. lA. A second parity series Q is formed of 10 words symbolized by open circles in Fig. lA and which are taken from the audio data series W0 to W7, the first parity series P and the second parity series Q with a distance of 12 blo~ks between adjacen~ symbols. As is apparent from Figs~ lA and 2, the first parity series P is desirably positioned at the center of the respective block, while the second parity series Q is positioned at an end of the block.
As noted above, that each of thP data word series Wo-W7 and each of the parity series P and Q arranged in a ~ respective horizontal line in the matrix of Fig. lA has ,:
"::, .
. . .
1 Z 7~ 3~
132 words in the respective series~ Therefore, each element of the P and Q series can be identified by a number n (n=O
to 131~.
As hereinafter described in detail, in accordance with the present invention, a random access memory (~AM) 11 is provided to store l-bit error pointers for the parity s~ries P and, similarly a random access memory (R~M) 12 is provided to store l-bit error pointers for the parity series Q. Since there are 132 elements or words in each of the parity series P and Q, each of the series error pointer RAMs 11 and 12 has a 132 bit-capacity, as shown in Fig. lB.
As is well known, the presence or absence of an error in each block is detected by the respective CRC code.
Since simple parity is used~ if the CRC check dPtermines that only a single error word exists in the P or Q series, that single error word can be corrected. Moreover, by repeating the decoding or error correcting processes in respect to the P and Q series, the error correcting capability can be improved. As is well known, in the case of the PC~ audio signals, erroneous data that cannot be corrected by the error correction code are interpolated or replaced by the average of the correct data existing before and after the uncorrected erroneous data.
Referring now to Fig. 3, it will be se.en that, in an embodiment of the present invention there illustrated, the reproduced or received PCM data and parity data appli~d to an input 1 are stored or written in a data RAM 2 at addresses determined by an address generator 3. Such reproduced data, prior to being stored in RAM 2, is ;
, ~ ~7~
sllbjected to error d~tection by a CRC arithmetic operating circuit (not shown) which provides l~bit word error point2rs indicating whether or not an error is detected in each word.
The ~ord error pointers are applied to an input 4 and are writ~en therefrom in a word pointer RA~I 5. The data RAM 2 has a capacity suitable to store the reproduced data for one fi~ld which, as previously indicatzd, consists of 10 words of PCM data and parity data in each of 132 blocks.
Therefore, data RAM 2 has a sufficient capacity to store 1320 ~ords of data~ On the other hand, word pointer RAM 5 has a capacity of 1320 bits, so as to be capable o~ storing a l~bit word error pointer for each of the words included in one field of data. The addresses in the word pointer RAM 5 at which the word error pointers are written are also determined by address generator 3. The data stored in data ~AM 2 and the word error pointers stored in word pointer RAM
5 are supplied through a switching circuit 6 to a correc~ing circuit 7 and a counter 8.
In order to pexfol~ the correcting processes of the P series, the 9 word error pointers indicating the 9 woras forming the first of the P series are read from word pointer RAM 5 and passed through switching circuit 6 to counter 8. I~ o~ly one word error pointer corresponding to a word error is detected by counter 8, the latter causes correcting circuit 7 to correct the corresponding single error word, whereupon tbe corrected data or word is written into data RAM 2 in place of the error word and, at the same time, the word error pointer corresponding to the corrected error word is cleared from word pointer R~M 5. If no error 53~
wo~d is de-tacked, or if two or more exror words are detected or counted among the 9 word error pointers corresponding to the :Eirst P series, no correcting process is executed, that is, correctlng circuit 7 is inoperative to correct any data in ~1 2. The foregoin~ operaticns are repeated with respect to each of the 132 series of the P series, and also in respect to each of the 132 series of th~ Q series.
When no error word i5 detected or counted by counter 8, or when one error word has been corxected by correcting circuit 7, a correction completion pulse generating circuit 9 is operated to produce a correction completion pulse for a purpose hereinafter described in detail.
A timing pulse generator 10 is provided to prodl~ce suitable timing pulses for controlling the operations of address generator 3, switching circuit 6 and correct~ny .circuit 7. When word error pointer~ are ~eing read out from word poi.nter RAM 5 to be counted by counter 8 and when the word error pointers in RAM 5 are cleared after the correction of an error word, switching circuit 6 is disposed in the condition illnstrated on Fig. 3, that is, word pointer RAM 5 is connected to correcting circuit 7 and counter 8 by switching circuit 6. On the other hand, when an error word in data RAM 2 is to be replaced by a corrected word, switching circuit 6 is changed-over to connect RAM 2 . with correct.ing circuit 7.
As previously noted, the l-bit P series error pointers and the l-bit Q series error pointers are stored in P and Q series pointer RA~s ll and 12. The parity series , ~ ' ' ' ; ' :
.
~ ;~ 7S~326 error pointer E~Ms ll and 12 ~re addressed, in common, by an address generator 13 in response to timing pulses from generator 10. As earlier noted r each of the P and Q series includes 132 series, and the re~pective l-bit series ~rror pointers are stored at 132 respective addresses in RAMs 11 and 12, respectively. Each of the parity series error pointer~ may have the logic le~el or value "1~ to indicate that an erxor word e~ists in the respective pari~y series, whereas the series error pointer has the value "O" to indicate that no error word exists in the respective series.
All of the series error pointers are initially set at the high value "1", and each of the series error pointers is cleared or changed to the low value "O" when no error word exists in the respective parity series and when a single error word has been corrected.
A switching circuit 1~ is provided to alternately connect the P and Q series error pointer R~Ms 11 and 12 to a pointer clearing circuit 15 and to a pointer discriminating circuit or dPtector 16. The pointer clearing circuit 15 is connected to generator 9 for receiving the correction completion pulse from the latter and, in response to such correction completion pulse, pointer clearing circuit 15 is effective to clear or return to 110~ the pointer of the respective series of the P or Q series which has, no error.
In other words, the P or Q series error pointer for the P or Q series in which an error word was corrected by circuit 7 is cleared to "O". The pointer discriminating circuit 16 detenmines whether the P or Q series error pointer addressed in the RAM 11 or 12, respectively, is "O" of "1", and timing ~, . '.
:
~7~3~
pulse generator 10 lS actuated in respcnse to such detection or discrimination.
As shown on Fig. 3, t.he switching operation of switching circuit 14 is also controlled by timing pulses from tlminy pulse generator 10. Finally, the P and Q series error pointer R2~1s 11 and 12 are adapted to receive the respective series error pointers at inputs 17 and 18, for example, from a suitable P,Q decoding circuit (not shown).
It will be understood that, during the correction of the Q
series, the Q series erxor poin-ter RAM 12 i5 con~ected to pointer clearing circuit 15 and pointer discriminating circuit 16 by the switching circuit 14 in the condition shown. On the other hand, during the correction of the P
series, switching circuit 14 is changed-over to connect the P series exror pointer RAM 11 with circuits 15 and 16.
In the case of the application of the present invention to an 8 mm. VTR, there will be two sets of the data RAM 2, error word pointer RAM 5, P series error pointer RAM 11 and Q series error pointer RAM 12 for processing the PCM signals of alternate fields. Thus, during a field in which the PCM signal is being written in on~ set and error correcting operation are being performed thereon, the previously corrected PC~ signal and word error pointers are being read out from the other set.
The correction of errors in the above described embodiment of the invention will now be described with reference to ~he flow charts in Figs. 4 and 5. The first correcting processes are illustrated in Fig. 4 and will he described with respPct to an example in the P series.
.
'7,53~&~
In step (1) the number n of the 132 series of the P series is initialized to 1l 0 l' , In step (2), the word error pointers ~or the 9 words form.i~g the P sexies identified by n=0 are read out of ~ord error pointer ~ 5. In step (3), it is determined by counter 8 if there is no error word among the 9 words forming the P series identified by n--0.
Of course, during steps ~21 and (3) switching circuit 6 remains in the position shown on Fig. 3 for connecting word error pointer RAM 5 with countex 8. If the answer to decisioa outline ~3) in Fig. 4 is "N" or "'NO", that is, one or more error words are counted ~y counter 8 among the 9 word errox pointers corresponding to the P series identified by n=0, the pxogram moves to st~p (4) in which it is determined if there is only one error word.
On the other hand, if the answer tc decision outline ~3)~ is "YES" or "Y", that is, if no error word is detected among the 9 words of data forming the P series identified by n=0, the program skips to step (6) in which correction completion pulse generator 9 causes pointer clearing circuit 1~ to clear the series error pointer stored in P series error pointer RAM 11 at the address for the P
series identified by n=0. Of course, at the time of such clearing of the series ,^-,rror pointer, switching circuit 14 is changed over to connect RAM 11 with pointer clearing circuit 15.
If the answer to the decision outline (4~ is "YES"
or "Y", that is, if one error word is detected in stap (4~, such error word is corrected in step ~5~, and then the program proceeds to step (6~ in which generator 9 provides a :; .
~ 13-~ .~
., ~.z~
correctlon completion pulse for causing pointer clearing circuit 15 ~o clear the series error pointer at the address in RA~ 11 corresponding to the P series identified by n=0.
Of course, during such correction of an error word, switching circuit 6 is changed-over to connet data ~AM 2 with correcting circuit 7.
On the other hand, if the answer to decision outline (4) is "NOi' or "N", that is, if two or more error words have been detected among the 9 data words forming the ~ series identified by n-0, no correcting process is or can be performed, that is, the program skips from step ~4) to step (7) in which the P series number n is increased by ~ , that is, to n=l. Similarly, upon the completion of step ~6) in which the series error pointer for the P series identified by n=0 is cleared, the program moves to step ~7) in which the identifying number n of the P series is incremented. The program moves from step (73 to step (8) in which it is determined whether the first correcting processes for the 132 series of the P series have been performed. In other words, step (8) determines if n=132.
If it is found that n~l32, the first correction procassing operation for the P series is terminated. However~ if n is found to be less than 132 in step (8), the program returns to step (2). After the first correcting processes ha~e been completed in respect to the P series, the first correcting processes are similarly e2ecuted in respect to the Q series.
As earlier noted, the COrrQCtion processing operations are desirably repeated in respect to the P series an~ the Q series. The second and each subsequent correction . ~:
~ ~75i3~
proces~i.ng opera~ion will now be described with reference to Fig. 5 in ~Ihich steps corresponding to those described above with reference to Fig. 4 are identifi.ed b~ the same reference numerals. Once again, the specific description of the correction processing operation illustrated on Fig. 5 will be with ref~r~nce to an example in the P series.
In the second or subsequent correction processing operation, the number n identifying the series of the P
series is initially set to n-0 in step (1). Then, with switchins circuit 14 changed-over to connect RAM 11 with pointer discriminating or detecting circuit 16, the program proceeds to step ~9) in which the 1-bit P series error pointer stored at the address for n=0 is read out of R2~1 11.
In step ll0), pointer discriminating circuit 16 detects if the P series error pointer being read out of RAM 11 is "1", that lS, if an error word is included in the 9 words of data which form the series of the P series identified by n=0. If the answer to the decision outline ~10) is "YES" or '~Y", that is, if the P series error pointer read out of RAM 11 is ~1", the program moves from step (10) to step (2) in which pointer discriminating circuit 16 actuates timing pulse generator 10 for causing the word error pointers , corresponding to the data words forming the series of the P
series identified by n=0 to be read out of RAM 5. In the next step (4) counter 8 determines from the word error pointers read out of RAM 5, if one error word exis~s among the 9 words making up the P series. If only one error word is detected in the P series being considered, th~ program moves to step (5) in which the single error word is :' ~
: -15-.. -: ; .
:.
': :
J~j corrected by correcting circuit 7 and, thereafter, corl-ection completion pulse generator 9 and pointer clearing circuit 15 are operative to clear to "O" the series error pointer stored in RAM 11 at the address corresponding to the P series identified by n-O. If two or more error words are detected by counte~ 8 in step (4), the error coxrecting step (5) and the series error pointer clearing step (6) are omitted and the program proceeds to s-tep (7). Similarly, if the l-~it P series error pointer read from the address in RAM 11 corresponding to n=O is I~On, that is, i~ the s~ries error pointer detectad in step (10) is not "1l', from which it follows that no error word exists in the 9 data words forming the P series being considered, the program skips steps (2),(4),~5) and (6) and proc~eds directly to step (7).
In step (7) the number n identifying the series of the P
s~ries being considered is incremented by 1, and then the program proceeds to step (8) in which it is determined whether n=132. If n is less than 132, the program is returned to step (9), whexeas, if n=132, the program is t~xminated. In other words~ the second or subsequent correction proces~ing operation illustrated in Fig. 5 is repeated in respect to each of the P series. Similarly, the second and subsequent correction processing operations are performed in respect to the Q series~
It will be appreciated that error correction in accordanca with the present invention is not limi ted to : digital data that has been transformed into an error correctable code structure by the cross-interleave technique, but can be similarly applied to the product code .. . .
.- . ~ . .
" ' ' :
~D '~
~o~6 for p~rforminy error correction coding processes in the vertical and horizontal directions of the two-dimensional data arrangement. Further, the error correction code that is used is not limited to the simple parity code employed in the described example, but other codes, such as, the Reed-Solomon code or the like can also be used.
It will be appreciated that, in correcting errors according to the invention by means of two or more correction series and by repeating the correcting processes in respect to each series, the correcting processes are omitted in respect to any of such series devoid of error.
Therefore, the number of repetitions of the correcting processes that can ke effected in respect to each series within a specified time can be increased as compared with conventional error correcting systems in which the corxecting processes are performed even in respect to series that do not contain error.
~ aving described an illustrative embodiment of the invention, it is to he understood that the invention is not ; limited to that precise embodiment, and that various changes and modifications can bP effected therein by one skilled in the art without departing from the spirit or scope of the invention as defined in the append~d claims.
;::
~:
. .
Claims (8)
1. An apparatus for correcting errors in received digital data signals having parity series and CRC codes, comprising:
word error pointer memory means for storing word error pointers generated on the basis of the CRC codes included in said received digital signals;
parity series error pointer memory means for storing series error pointers of predetermined parity series of said received digital signals;
means for reading out said word error pointers of said predetermined parity series from said word error pointer memory means;
counting means for determining how many of said word error pointers read from said word error pointer memory means indicate error words;
means for correcting errors included in said received digital signals of said predetermined parity series when only one of said word error pointers read from said word error pointer memory means indicates an error word; and means for clearing the series error pointer for the error corrected series from said parity series error pointer memory means.
word error pointer memory means for storing word error pointers generated on the basis of the CRC codes included in said received digital signals;
parity series error pointer memory means for storing series error pointers of predetermined parity series of said received digital signals;
means for reading out said word error pointers of said predetermined parity series from said word error pointer memory means;
counting means for determining how many of said word error pointers read from said word error pointer memory means indicate error words;
means for correcting errors included in said received digital signals of said predetermined parity series when only one of said word error pointers read from said word error pointer memory means indicates an error word; and means for clearing the series error pointer for the error corrected series from said parity series error pointer memory means.
2. An apparatus according to claim 1; further comprising pointer discriminating means for checking the series error pointers stored in said parity series error pointer memory means, and being operative, when the checked series error pointer shows no error, to check the next series error pointer without reading out the corresponding word error pointers from said word error pointer memory means.
3. An apparatus according to claim 1; wherein all of said series error pointers in said parity series error pointer memory means are set at the beginning of an error correcting operation on a predetermined amount of said received digital data.
4. An apparatus according to claim 1; wherein said clearing means also clears the corresponding series error pointer when said counting means shows no error in the words corresponding to the read out word error pointers.
5. A method for correcting errors in received digital data signals having parity series and CRC codes, comprising the steps of:
storing word error pointers generated on the basis of the CRC codes included in said received digital signals;
storing series error pointers of predetermined parity series of the received digital signals;
reading the stored word error pointers of said predetermined parity series;
determining how many of said word error pointers which are read indicate error words;
correcting errors included in the received digital signals of said predetermined parity series when only one error word is indicated by the word error pointers which are read; and clearing the stored series error pointer corresponding to the error corrected series.
storing word error pointers generated on the basis of the CRC codes included in said received digital signals;
storing series error pointers of predetermined parity series of the received digital signals;
reading the stored word error pointers of said predetermined parity series;
determining how many of said word error pointers which are read indicate error words;
correcting errors included in the received digital signals of said predetermined parity series when only one error word is indicated by the word error pointers which are read; and clearing the stored series error pointer corresponding to the error corrected series.
6. A method according to claim 5; further comprising the steps of checking one of the stored series error pointers and, when the checked series error pointer shows no errors in any of the corresponding words, checking the next series error pointer without reading the stored word error pointers.
7. A method according to claim 5; in which all of said series error pointers are set at the initiation of the error correcting operation on a predetermined amount of said received digital data.
8. A method according to claim 5; further comprising also clearing the corresponding series error pointer when the word error pointers which are read indicate no word errors.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61019676A JPS62177768A (en) | 1986-01-31 | 1986-01-31 | Error correcting device |
| JP019676/86 | 1986-01-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1275326C true CA1275326C (en) | 1990-10-16 |
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ID=12005834
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000528110A Expired - Lifetime CA1275326C (en) | 1986-01-31 | 1987-01-26 | Error correction apparatus for digital data |
Country Status (11)
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|---|---|
| US (1) | US4796261A (en) |
| EP (1) | EP0232133B1 (en) |
| JP (1) | JPS62177768A (en) |
| KR (1) | KR950007947B1 (en) |
| CN (1) | CN1006337B (en) |
| AT (1) | ATE93340T1 (en) |
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| CA (1) | CA1275326C (en) |
| DE (1) | DE3787034T2 (en) |
| ES (1) | ES2042545T3 (en) |
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| US4876616A (en) * | 1987-07-22 | 1989-10-24 | Sony Corporation | Apparatus for reproducing a digital signal |
| JP2692085B2 (en) * | 1987-08-31 | 1997-12-17 | ソニー株式会社 | Error correction method |
| JPH02148127A (en) * | 1988-11-29 | 1990-06-07 | Hitachi Ltd | Magnetic disk controller |
| JP2832024B2 (en) * | 1989-03-18 | 1998-12-02 | キヤノン株式会社 | Code transmission method |
| JP2722647B2 (en) * | 1989-04-11 | 1998-03-04 | 富士通株式会社 | Magnetic tape controller |
| JP3153995B2 (en) * | 1989-07-29 | 2001-04-09 | ソニー株式会社 | Decryption device |
| JPH0447569A (en) * | 1990-06-15 | 1992-02-17 | Canon Inc | Digital recording and reproducing device |
| DE69223694T2 (en) * | 1991-07-18 | 1998-04-23 | Canon Kk | Coding and decoding system for error correction |
| DE69325415T2 (en) * | 1992-05-18 | 1999-11-25 | Canon Kk | Data processing device |
| JP3318841B2 (en) * | 1992-08-20 | 2002-08-26 | ソニー株式会社 | Reproduction device and reproduction method |
| JPH06290553A (en) * | 1993-04-02 | 1994-10-18 | Sony Corp | Recording and reproducing device |
| JPH11339402A (en) * | 1998-05-28 | 1999-12-10 | Sanyo Electric Co Ltd | Code error correction detecting apparatus |
| US6327691B1 (en) | 1999-02-12 | 2001-12-04 | Sony Corporation | System and method for computing and encoding error detection sequences |
| FR2812116A1 (en) * | 2000-07-19 | 2002-01-25 | Schlumberger Systems & Service | Method and device for secured writing of data in rewritable memory, for use in microelectronics and chip cards |
| US7389463B2 (en) * | 2001-05-29 | 2008-06-17 | Thomson Licensing | Hierarchical block coding for a packet-based communications system |
| KR101129348B1 (en) * | 2002-06-21 | 2012-03-27 | 톰슨 라이센싱 | Method of forward error correction |
| FR2861517B1 (en) * | 2003-10-23 | 2006-01-27 | Thomson Licensing Sa | METHOD OF RECONSTRUCTING LOST PACKETS AND APPARATUSES IMPLEMENTING THE METHOD |
| US7783954B2 (en) * | 2006-09-11 | 2010-08-24 | Globalfoundries Inc. | System for controlling high-speed bidirectional communication |
| US8839053B2 (en) | 2010-05-27 | 2014-09-16 | Microsoft Corporation | Error correcting pointers for non-volatile storage |
| US9032244B2 (en) | 2012-11-16 | 2015-05-12 | Microsoft Technology Licensing, Llc | Memory segment remapping to address fragmentation |
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| JPS5710558A (en) * | 1980-06-20 | 1982-01-20 | Sony Corp | Error correcting method |
| CA1161565A (en) * | 1980-06-20 | 1984-01-31 | Yoichiro Sako | Method of error correction |
| JPS58123253A (en) * | 1982-01-19 | 1983-07-22 | Sony Corp | Error correcting device |
| JPS58198935A (en) * | 1982-05-15 | 1983-11-19 | Sony Corp | Data transmitting method |
| JPS605474A (en) * | 1983-06-23 | 1985-01-12 | Nec Home Electronics Ltd | Ram input circuit for decoder of pcm recording and reproducing device |
| JPS6052964A (en) * | 1983-09-02 | 1985-03-26 | Matsushita Electric Ind Co Ltd | Error correcting method |
| US4637021A (en) * | 1983-09-28 | 1987-01-13 | Pioneer Electronic Corporation | Multiple pass error correction |
| JPH0812612B2 (en) * | 1983-10-31 | 1996-02-07 | 株式会社日立製作所 | Error correction method and apparatus |
| NL8400630A (en) * | 1984-02-29 | 1985-09-16 | Philips Nv | DECODING DEVICE FOR A FLOW OF CODE SYMBOLS PROTECTED BY WORDS BY A DOUBLE REED-SOLOMON CODE WITH A MINIMUM HAMMING DISTANCE OF 5 ON THE CODE SYMBOLS AND A BLEACHING MECHANISM BETWEEN THE TWO CODES. |
| JPH07111815B2 (en) * | 1984-07-23 | 1995-11-29 | 株式会社日立製作所 | Digital signal recording system |
| US4706250A (en) * | 1985-09-27 | 1987-11-10 | International Business Machines Corporation | Method and apparatus for correcting multibyte errors having improved two-level code structure |
-
1986
- 1986-01-31 JP JP61019676A patent/JPS62177768A/en active Pending
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1987
- 1987-01-22 US US07/005,786 patent/US4796261A/en not_active Expired - Lifetime
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- 1987-01-29 EP EP87300783A patent/EP0232133B1/en not_active Expired - Lifetime
- 1987-01-29 AT AT87300783T patent/ATE93340T1/en not_active IP Right Cessation
- 1987-01-29 DE DE87300783T patent/DE3787034T2/en not_active Expired - Fee Related
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- 1987-01-30 AU AU68163/87A patent/AU594422B2/en not_active Ceased
- 1987-01-30 BR BR8700426A patent/BR8700426A/en not_active IP Right Cessation
- 1987-02-02 CN CN87100569A patent/CN1006337B/en not_active Expired
Also Published As
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|---|---|
| EP0232133A3 (en) | 1988-11-02 |
| DE3787034T2 (en) | 1994-01-05 |
| CN1006337B (en) | 1990-01-03 |
| US4796261A (en) | 1989-01-03 |
| ATE93340T1 (en) | 1993-09-15 |
| EP0232133A2 (en) | 1987-08-12 |
| AU6816387A (en) | 1987-08-06 |
| AU594422B2 (en) | 1990-03-08 |
| DE3787034D1 (en) | 1993-09-23 |
| EP0232133B1 (en) | 1993-08-18 |
| ES2042545T3 (en) | 1993-12-16 |
| CN87100569A (en) | 1987-08-12 |
| KR950007947B1 (en) | 1995-07-21 |
| BR8700426A (en) | 1987-12-15 |
| JPS62177768A (en) | 1987-08-04 |
| KR870007502A (en) | 1987-08-19 |
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