CA1276227C - Input voltage compensated, microprocessor controlled, power regulator and method - Google Patents

Abstract

INPUT VOLTAGE COMPENSATED, MICROPROCESSOR CONTROLLED, POWER
REGULATOR AND METHOD

ABSTRACT OF THE DISCLOSURE

A regulating A.C. power controller regulates the selected levels of power to be applied to a plurality of loads by producing a digital signal directly from the A.C. voltage with a pulse duration representative of load power which can be applied as an input to the microprocessor without the need for prior analogue to digital conversion. The load power level is displayed in terms of percentage of power source. Remote control units, such as a computer, can be connected with the power controller to program it for power level settings and warm up time.

Description

~276'~27 INPU~ VOLTAGE COMPENSATED, MICROPROCESSOR CONTROLLED, POWER
.REGULATOR AND METHOD

This invention relates to an electronic regulatlng A.C.
5 power controller. More particular]y, it relate~ to such a controller in which different level~ of powee are manually selectable and regulated through control of trigger on-time control of an electronic A.C. ~witch interconnectlng the A.C.
power source and the load.
~ number of A.C. voltage regulator circuits are known in which A.C. power to a lamp or other load is regulated through control of an A.C. electronic switch interconnecting the source of A.C. input power, such a~; standard 120 VAC, 60 ~, A.C.
line power, and the load. Disadvantageously, in some of these circuits regulation is achieved only through a feed~ack system connected with the load to sense the load power or voltage across the load. This information is used to advance or retard, duris~(3 each half wave of A.C. power, the time relative to zero crossing, or phase anqle, when the electronic switch is triggered into conduction. If the average voltage across the load increases or deceeases, the trigger phase angle ls advanced or retarded, respectively, and the portion of each half wave of A.C. input power which is applied to the load through the switch is decreased or lncreased, respectively. Examples of such circuits aee shown in U.S. Patents 3,538,427 of Oltendorfs ~,300,075 o~
Foose et al. and 4,359,670 of Hosaka et al. This general ty~e of feedback regulator is also stlown and described in G.E.
~pplication ~ote 200.35, entltled ~llsing the Triac for Control o~
A.C. Power", p. 8r published in July 1970 by the Semiconductor 30 Products Department of General Electric Company, Syracuse, New York.
While the circuit~ function to perform as intended, they ' ~2762Z7 have a degree of complexlty and co~t associated wlth the load sensing feedback circuit which leads to relatively sluggi~h response and resultant inaccuracie~ and increase in costs.
~t least some of the~e problem~, however, are overcon-e in ~.C. power regulator of Bandou sho~n ~n Japane~e patent 58-106617, publi~hed June 25, 1983. In this circuit a microprocessor is employed to elimlnate the feedback circuit required in the above A.C. power regulators noted above to reduce the cost, weight, complexity and ~ize of the regulator. This, however, is achieved only at the e~pense of an analogue to digital convertor which converts at least a part, if not all, of each llalE wave o A.C. inpu~ power into digital form. This is used to mea~ure incremental changes reflected in the A.C. input voltage when the power switch is triggered to control ttle trigger angle of the power switch for regulation purposes. Likewise, in tl~e device shown in U.S. patent 4,359,670 of llosaka et al. an analogue to digital converter is required to convert an analocJIle feedback signal to digital form beEore it can be applied to a microprocessor used to control the application of load power.
While use of a microprocessor is clearly advantageolls over other control devices, analogue to digital converters are re~atively expensive and can increase by more than double the electronic component cost of the contro]ler. In U.S. patent 3,691,452 o~
Aguiar, a circuit is shown for dieect control of load power ~y a digital signal without tl)e need for an analogue to digital conversion step. Unfortunately, the benefits of a microprocessor are lost in the process and no power regulation is achleved.

~MMARY OF THE~ N~loN

Accordingly, this invention seeks to provide a regulating ~.C. power controller which has no negative feedl-ack circuits connected directly with the load to sense load l-owe~ or voltage and which advantageously employs a microprocessor wit~ t the disadvantageous nèed for expensive analogue to digital converters.

~l 2 ~276227 The invention in one aspect pertains to an A.C. power regulator with a power input terminal for connection to a source of A.C. input power, an electronic triggerable switch interconnecting the source of A.C. power and a power output terminal connectable with a load, and means for triggering the switch into conduction. The improvement comprises means responsive to the A.C. power source voltage at the power input terminal for periodically generating a distal load power pulse having a time duration which varies in proportion to the load power, the digital load power pulse generating means including means for generating a pulse during whatever time period that the magnitude of the A.C. power source voltage exceeds a preselected threshold voltage and which substantially varies in direct proportion with the load power. The pulse is generated during whatever time period that the input A.C. power voltage magnitude exceeds a threshold magnitude of approximately one half the nominal maximum magnitude of the input A.C. power voltage occurring approximately between the phase angles of 45 degrees and 135 degrees of positive half waves and between 225 degrees and 315 degrees of negative half waves. Means responsive to the time duration of the digital load power pulse control the triggering means to substantially maintain a selected level of load power despite nominal fluctuations in the source of A.C.
power voltage, the controlling means including a microprocessor for directly converting the digital pulse into a binary representation of the load power.

The invention also comprehends a method of controlling the application of power to a plurality of loads for a source of A.C. input power, comprising the steps of selecting a preselected level of power savings for the load, generating a load power regulation signal in response to the time duration of a signal measured, at least in part, by the passage of the A.C. input power source voltage through a preselected threshold, and regulating the portion of each half wave of A.C.
power to the load in accordance with said load power regulation signal to substantially maintain the selected level of power ~7~i2~7 savlngs notwith8tandlng fluctuatlon ln the magnltude of A~C.
input power source voltage.
~BIE~_~E~BI~IION OF TI~E DBa~ 5 The foregoing objects features and advantaqes will be described in greater aetail ana aaditional aavantageous features wlll be made apparerlt from a detailed descrlption of the preferred embodiment which is given in reference to the several figures of the drawings, in whic~
Fig. 1 iB a partially perspective, partially schematic illustration of a preferred embodiment of the regulating ~.C.
power controller of the pre~ent invention;
Flg. 2 is a functional block diagram of a preferred embodiment of the regulatlng ~.C. power controller~
Fig. 3 is a functional block diagram of a preferred embodiment of the control circuit 28 of Fig. 2;
Fig. 4~ i8 a circuit ~chematic of a preferred embodiment of the functional block of Fig. 3~ as shown with Fig. 2;
Fig. 4B is a circuit schematic of the preerred embodiments of the voltage divider/low pass filter, input buffer, full wave recti~ier, zero crossing detector, 45 degree threshold detector an(l OR gate functional blocks of Fig. 3;
Figs. 5~, 5~, 5C and SD are representative waveforms ~1, Wl' and T; W2: W3 and W4 produced at various points ln the circuitry shown in Figs. 3 and 4B;
Figs. 6~, 6B and 6C are waveforms illustrating the 45 degree threshold detectors Fig. 7~ is a flow chart of a preferred embodiment of the computer program employed in the microprocessor of Flg. 3 in wh~ch the load power pulse duration D
of waveform W3 or M of waveform W4 i6 converted to the trigger control slgnal T of Fig. SA via a look-up table~
Fig. 7B iB a flow chart of a preferred embodiment of the measurement sub-routine SRMR of Fig. 7A; and Figs. 7C through 7G detail important support sub-routines called ~rom the main line progralns, and further illustrate the combination oE arithmatic calculation6 and non-linear look-up of data neces~ary to provide adequate and stable control.

~276227 ~ eferring Eirst to FIG. 1, a preferred embodlment 10 of the electronic regulating A.C. power controller i8 seen to have a housing 12 which protectively enclo~e~ the controller c~rcuitry shown in Flgs. 2 - 6 and described below. Preferably, the controller has N channels for controlling the application of power to N loads, where N is any positive integer greater than one. ~s seen in the embodiment of FIG. 1, N is the integer six, an~ there are six substantia11y identical channels for indlvidually controlling the application of power to six di~ferent loads 11, such as load N. Eacb channel, such as CIIANNEL 6", ha~ associated therewith an output terminal 14, including a releasible, standard-sized A.C. plug receptacle moullted to housing 12, a by-pass switch 16.
When power is ~eing applied to the load at any level re~ucell relative to full power, then the display element 18 provides a lighted indication of same. The by-pass switches, wlen actuat~3, cause the full power to be applied from the A.C. input power terminal directly to tlle load connected with the OUtp~lt terminal associated with the particular channel being bypassed ~hen the by-pass swltch ls not actuated, then the power i8 limited in accordance with the savlngs that has been se1ected for tllat particular channel. when the by-pass swltcl i~ actuated, a llglt ln the back thereof is lit to indlcate the by-pas~ status. Also associated with each channel is a four position ~dip~ SWitCI
which has sixteen composite states assoclated wltll sixteen different levels of powee savings Erom approximately 10% to 40~`.
Whatever power savlngs has been set, is shown on tle display optionally associated with that channel. Selectlon of power savings for each channel is made theough mean~ of a nanual power savings selection swltcbes 17 asæoclated with each channel or ~y means of telemetered lnformation tran~mltted from a remote master computer or conteo11er connected via a cable 36 to a connector 36A. All the power output termlna1s 14 ultlmately receive their power feom conventional A.C. lnput power circuits of the buildjng ~7~7 --in wl~ic~l tlle c~ntroller i~ 1Ocated wl~lcl~ 18 provld~d Lo tlle controller at a 8ingle power input termlnal, Speci~lcally, he power input termlnal i9 connected to the bulldlng power clr~uits or other suitable source of standard A.C. input power 21 t~rou(31 mean~ of an electrical coed 20 and a conventional A.C. plu~ 22.
One addltlonal swltch a~qociated with each channel is a warm-up tlme delay selectlon switch 24 which is also preferably in the form of a four position ~dip~ swltch sub-~tantially identical to the power savings selection switch 17, but which is used to select warm-up time delay of two to thirty-two minutes in two mlnute increments during which Eull power 1s applied to the load. This is needed slnce certain types of loads, such as fluorescent lamps, require full power for a period of time be~ore they warm up. After warm-up, only a controlled portion of full power is applied to the load, so power savings can be achieved.
The controller 10 of the present invention functions to automatically provide full power for a preselected time period r''egardless of the selected power savings. After the warm-up time delay has lapsed, however, then the controller functions to gradually reduce the power to the load to the selected level.
Advantageously, through the use of a miceoprocessor and other space and weight savings approaches in the design, a six chanllel controller built in accordance with the present invention has a substantially reduced size of approximately 6 1/2 inches ~y 7 1/2 inches by 23 inches and a welght of only approximately 22 pounds. The housing 12 is also peeferably mounted Witll means ~or making direct hard wire connectiorl with the loads instead of using releasible connectors.
In the event that A.C. input power drops to a voltage l-elow a preselected level or is temporarily terminated entirely, the controller will function to apply full power to tlle loads regardless of the preselected power savings for tl-at load so long as the low voltage condition continues. After voltage returns to its nocmal level, then the controller automatically reverts to it~ power ~avings mode of operation, In addition, at any time, such as in the event of power loss, all channels are restartable 3L276Z27 `--in re~ponse to manual actuation of a master, ~ystem re3~t switch 26.
The controller also include~ one or more swltches (not shown) for setting the controller to operate at either of two standard nomlnal voltages or two standard nomin~l Ere~uencies for .C. line power, such a~ nominal voltages of 120 volts an(l 277 volts and nominal freqllencies of 50 l1Z and 60 llz. Sixteen aml~s of current can be provided to the load at either of these voltages and frequencies irrespective of the input power voltage to the controller. The controller itself can be powered ~y either 120 or 277 volts ~.C. power from source 21.
The nominal voltage as indicated above typlcally fluctuates over a nominal range of operating voltage of plus or minus approximately ten percent. The controller, however, functions to reduce resultant fluctuation in average voltage to the variolls loads to no more than plus or mlnus one percent.
Referring now to FIG. 2, contained within housiny 12 is a c~ntroller circuit 28 which has a remote Input interface 30 for interconnecting remote control signals from a remote master controller 32 with the controller circuit 28. In a preEerred embodiment, the connection between the remote master controller 32 and the remote input interface 30 i9 via a communication cal-le 34 connected to the remote input ~nterface 30 by means oE a connector 36.
If provided with remote control capability, then the manual inputs provided to the controller circuit by way oE a manua1 input interface circult 42 are ove~ridden by communicati~u~ from the remote master controller 32. Preferably, the communications peotocol is RS-232 (three wire) at 3nO baud. The package address is established by way of an eigllt position ~dip~ swi~ch which provldes indivldual addresses for up to 256 six channel packages.
In the event of a loss of communication, each channel will revert to the manual switch settings for control upon a local power-up or reset conditlon.
Alternatively, another programming method is to provide a portable programming and dlsplay unit ~not shown) which plugs lZ762~
into the connector 36. In ~u~h ca~e, ~ceferably t~le conncctor 36 comprise~ a "D" RS-2~2C connector. The porta~le programmin-3 Ul)it comprise~ a key-pad, a time oE day clock and calen~3ar and dislllay wllich serves as a pcogrammln9 en~ry d~splay to permit enterin~J of the same control parameters otherwlse accompllshed via entry at a remote master controller 32, as described above. Preferably, wllen used with the portable programming unit, the controller will, after programming, maintain loeal time to within one second per day and will maintain time and other peogramming inEorma~ion ~y way of a back-up battery to provide power to the memory durin~J
power Eailure conditlon3. Sixteen or more programming statements per channel are preferably capable of being entered and stored in the controller circuit.
Referring now to Fig. 3, a preferred embodiment of the controller circuit 28 includes a microprocessor 44 for each load l through N with suitable inputs 46 connected with tlle manual input interface 42 and suitable inputs 4a from the remote lnp~lt interface circuit 30. Each microprocessor 44 responds to the signals at the inputs 46 and 48 to establish the preselected level of savings for the particular load l through N associated therewith. In addition, the mlcroproeessor has three inputs 50, 52 and 54 which are respeetively eoupled to a zero crossing deteetor 56 and logic OR gate 58 and, most importantly, a 45 degree threshold detector 60. The zero crossing detector 56 produces a waveform W2 shown in Fig. 5B that eomprisises a narrow pulse generated at the zero cross~ng of the A.C. power voltage from souree 21 which corresponds to the zero voltage points of a waveform Wl shown in Fig. SA. The waveform W2 is applied ~Ot11 to input 50 of microproeessor 44 and to one of the inputs of OR
gate 58. The 45 degree threshold deteetor 60 also receives the waveform Wl at lts input 62 and produces, in response thereto, a waveform W3 shown in Fig. 5C.
This waveform W3 is applied to both input 54 of mieroproce~sor 44 and to the remaining input of OR gate 58. o~
gate 58, in turn, dlsjunctively responds to the waveforms W2 and W3 to produce a waveform W4 whieh ls applied to input 52 of ~J --~ .276227 micro~rocessor 44, lhe waveform Wl has a magnltude Wl~ i5 ~lirectly proportional to the magnltude of the A.C. ~ower solJrce voltage from source 21 which is provided on power bus 64. ~he waveform Wl Is produced on the output of a full wave rect~fler 66 whicll full wave rectifies an A.C. slgnal produced on a volta(Je dividee/low pass filter circuit 6n which has one input connected to the ~.C. voltage bus 64 and it~ other input connected to a ground reEerence potential 70. The unrectified A,C. signal produced on the output of voltage divider/low pas~ filter 6~ is coupled to the input o~ full wave rectifier 66 through an input bu~fer 72.
The microprocessor 44 responds to the signal~ at its inputs 46, 48, 50, 52 and 54 to selectively apply trigger signals on its outputs 74 respectively connected to load control switches 76 which are respectively associated with load 1 through load N.
Referrinq to Figs. 6A - 6C, in keeping with an important aspect of the invention, the waveform W3 of Fig. 5C comprises a load power signal with a digital pulse having a width, or time dllration, D which varies in proportion with variations in the peak amplitude ~ of waveEorm Wl, which, as noted above, is directly proportional to the peak magnitude of the A.C. power source voltage provided at power input terminal 19. As seen in Figs. 6A, 6B and 6C, when the waveform Wl has a peak magnitude Al, the pulse produced by the app~oximately 45 degree tllresho]d detector has a width Dl, and when the peak amplitude is reduced to a lesser magnitude ~2, the pulse is reduced to a duration, D2, whicl) ls less than Dl. The microprocessor is responsive to the width D of this pulse for controlling the phase angle at wbich that the trigger signals are applied to the load control switches to substantially maintain the level of load power selected for each of tbe loads despite nominal 1uctuations (~ 10~) in the .C. power source voltage.
Referring to Fig. 5A, this load power pulse of waveEorm Wl îs generated from a time tl occurring when the instantaneous amplltude first exceeds a preselected threshold leYel B during each halfwave until a tlme t2 when the instantaneous amplitude decreases below the preselected thresl~old level ~.
A(lvan~ageously, micropLocessors have very hlgil fre-luency oscillators wlth frequencies on the order of one m~llion l~rtz and, thus, are very goofl at precisely and directly measuring time duration of the pulse wldth D of waveform Wl. Because of tllis accuracy of measurement, improved regulation control is achieved relative to a unit in which the control slgnal must first be con-verted to digital form before being provided to the microprocessor 44.
Importantly, I have discovered that if the threshold level 13 is selected to be approximately one-half the nominal peak magnitude ~, the width of the pulse closely follows or is directly proportional to the load power over a substantial range of fluctuations of A.C. power source voltage amplitude on ~he order of plus or minus ten percent. Accordingly, using this pu]se duration the on time triggering the load control swit~lles results in an improved regulat:ion of load power without the need fo~ any direct load power or voltage feedback circuits and without the need of expensive analogue to digital converters.
Specifically, the derivative of the pulse duration D with respect to the peak amplitude A equals 2B~A~AL- B seconds/volt.
~IIUS~ for value of B approximately equal to 1/2 A, the duratio is approximately directly proportional to load power.
Alternatively, the pulse duration M of the zero state pulse occurring between time T2 and the next ~ero crosslny plllse of waveorm W2, wtlich is generated by OR gate 58 as part of waveform W4, can be employed by the microprocessor as a measurement of amplitude. I~owever, in this case, the pulse duration M, instead o~ being directly proportional to the amplitude, is approximately inversely proportional to the amp~itude. Specifically, the duration M is approximately defined by the formula M=(K-D)/2 where K=8.33 msec. and D equals the duration of the positive pulse of waveform W4.
Referring now to Fig. 4A, a preferred embodiment of tlle load control switch 76 is seen to employ a bi-directional thyristor interconnecting the load in serie~ between the positive A.C.

~276227 power line bus 64 and the neutral power llne bu~ 65 tl~rou~31lLI
I:ral~scon(iuctlve termlnals of thyr1l3tor 7n. Thyrlstor 78 al~
has a gate or trlgger input termln;31 80 wl~ich ls lntercorll)ected tl~rou~h a transformer B2 and an ~.C. coupling capacltor 84 to tl~e collector output of an NPN transisl;or 86. The collector of transistor ~6 is connected to a sultable D.C. supply volta(Je v+
through a load resistor 88.
When the microprocessor generates a positive pulse on its output 74 which is applied to the base of transistor 86 transistor 86 begins to switch to a conductive state. Ttlis causes discharge of capacitor 84 and generation of a trigger pulse that causes the thyristor ?8 to switch to a conductive state. The thyristor rema~ns in a conductive state even after the trigger signal is remoYed until the current through its transconductive terminals drops to substantially zero.
~ eferring now to Fig. 4~, preferred embodiments of the voltage divider/low pass filter 68 of the input, the input l~uf~er 72,.the Eull wave rectifier 66, the zero crossing detector 56 tl~e 45 de~ree thresl~old detector 60 and the ~ND gate 5n shown in functional ~lock form in Fig. 3, will be described in detail.
Voltage division is achieved in the voltage divider/low pass rilter 68 through a pair oE resistors 90 and 92 connected in series between the active ~.C. voltage bus 64 and ground reEerence potential 70. The voltage produced at their juncture is directly proportional to the A.C. power source voltage but i9 reduced to a signal level appropeiate for the subsequent circuitry. The voltage produced at the juncture 94 is filtered by low pass filter capacitor 96 interconnected between the juncture 94 and ground reference potential 70. This simple filter removes higher frequency noise and harmonic distortion which could otllerwise interfere with the desired measurement. In addition, this network produces a precise and stable attenuation, and 45 degree phase shift between waveform Wl', Rtp, the power supply volta~Je, and voltage produced at the output of full wave rectifier 66 and applied to the remaining detection portion of the cardiac output monitor. It has been establiRhed by experiment that the reqion ~ 276227 of power savings for gas dlscllar(Je lig~tlng flxtur~s is in tl~e range of 60-90 de(~ree phase delay rom ttle zero-cro3~in-Js of waveEorm Wl, which is ]5-45 degrees Erom the zero cro~slngs o~
waveEoem W' zero crossing period.
The output voltage ~roduced at juncture 94 is coup]el~ Lo llc non-inverting input of an operational amplifier 98 whic~l is a voltage-follower and functions to ~uffer the input and to provide a low output impedence for the remaining circuitry.
The output of the ampllEier 98 is connected to a phase inverter 100 interconnected with a half-wave rectiEier 102. The phase inverter 100 is an operational amplifier with an inverting input connected to the output of lnput buffer 72 through a coupling resistor 104. Negative feedback is provided through a feedback resistor 106 interconnected between its output and the inverting input, and the non-inverting input.is connected to ground reference potential 70. In this configuration, the amplifier 103 functions as a precise 180 degree phase inverter which pro3llces an amplitude at its output 108 that is held accurate to within 1%
o~ the magnitude of the voltage applied to its input frollltlle input ~uffer 72. This precise gain of negative one is established by virtue of the accuracy of resistors 106 and 104.
The non- inverting input to amplifier 103 generated by input buffer 72 is connected directly to the input of a first diode 110 oE halfwave rectifier 102 through a lead 112. The inverting output of amplifier 103, on the the other hand, is connected to another diode 114. The cathodes of diodes 110 and 114 are interconnected together, and accordingly a full wave rectified wavefocm Wl ls produced at their juncture. A bias reislor 116 i~
connected between the juncture and ground reference potential 70.
The full wave rectified waveforln Wl is coupled througll a lead 118 to the inputs of both the zero cro~sing detector 56 an-l the 45 degree threshold detector 60. The zero crossing detector 56 comprises an operational ampliier 120 having an invertin(3 input connected to lead 118 and a non-inverting input connected to ground reerence potential 70. In this configurat~on, the amplifier 120 function~ as an amplitude-comparltor, or Schmitt ~ 276Z~7 t~ger, to detect the negative cusp of waveeorm W3. When the voltage magnitude decreases to a lcvel substant1ally equal to ~ero, a positive zero cro9~ing pul~e i8 produced a8 shown in waveform Fig. 5~. Thi8 pul8e continues to be generated until the magnitude again increase8 above a zero voltage level by a sligl~t amount.
The 45 degeee threshold detectoe 60 also comprises an operational amplifer 122 having its non-invertlng input connectea to lead 118 and its inverting input connected to ground reference potential 70 through a variable resistor 124. The value of the variable resistor 124 is selected to achieve a threshold level that is approximately equal to one-half of the nominal peak amplitude of the waveform Wl. Adjustment is provided so that the power controller can be u~ed with A.C. power sources oE
different ma~nitude as noted above. It is referred to as a 45 degree threshold detector, of course, because the 50% amplitude level is reached at the 45 degree phase angle of the sine wave.
The variation in the duration of the pulse produced on the output of operational amplifier 122 is proportional to the tangent of the threshold angle.
The OR gate comprises a pair of diodes 126 and 128 having thelr annodes respectively coupled to the outputs of operational ampllfiers 120 and 122 and their cathodes interconnected at the output which is biased to ground reference potential 70 theouyh a resistor 130. Whenever either wav~-form W2 or W3 are positive, the OR gate 70 output signal W4 is positive.
The variation in the duration of pulse duration D or pulse duration M is used by the microprocessor 44 to control the tillle that the load control switches are triggered in order to regulate the load power. This l~ achieved through means of either a look-up table which is stored within the memory of the microprocessor or through means of a calculation.
Referring to the flow chart of Fig. 7A, the computer program employed in the microprocessor or computer of Fig. 3 converts the load power pulse duration D of waveform W3 or pulse duration M of waveform w4 to the trigger control signal T of Fig. 5A via a look-up table. For purposes of discussion it will be presumed that control signal T is derived from measurements of pulse duration D. In any event as seè~ there are two major parts to ~k`- 13 ~2762~7 the program: a 8et-up portlon illu8trated by funct~onal box 132, 13~, 13~, 138, 140 and 142 and a control portlon repre8ented by function boxes 144, 146, 148, 150, 15~, 154 and 156 and 158. The set up portion starts when power is first applied (or reapplied aEter a powec loss condition) and establishes a warm-up time delay before the control portion is entered. The control portion includes a continuously running real-time loop for power regulation which cycles once for each half cycle of the AC input power line frequency (e.g. once each 8.~3 milliseconds for 60 Hz line frequency).
Duriny the set-up portion, the percentage of power savings preselected for each load via the savings selection switches 17 or manual input interface 42 via the remote input interface 30, Fig. 2, is read and stored, as shown by function 136, KEAD
SAVINGS SWITC~3. Likewise, the microprocessor reads the setting of the warm-up time delay selection switch 24 as shown by function 138, READ WARM-UP TIME SWITCH. The computer then counts the number of zero crossing pulses of waveform W2, Fig. 5B, as shown by function 140, COUNT ZCP PULSES W2. When the count reads a number which is equivalent to the warm-up time T.0 selected in the range of 2 to 32 minutes, the warm-up period ends and the control portion of the program is entered, as shown by the function 142, COUNT=T.0~2-32 MINS).
The first function performed in the control portion is loading of the zero crossing point into a ZCP memory as shown by function 144, LOAD ZCP MEMORY. As soon as waveform W2 switches to a l-state at the beginning of each half-wave of AC
power, the function 146, WAVEFORM W2 IN l-STATE?, causes the loading of the thyristor trigger delay obtained Erom the sub-eoutine SRMK into a timer regiRter a~ shown by function 148, LOADR TIMER. Once the time delay R has passed, and the answer to the question of function 150, R TIMER TIMED OUT? is affirmative, a pulse generate sub-routine SRTP, function 152, Fig. 7C, is caused to genecate the trigger pulse to the thyrister to apply power to the load.
The sub-routine function 154, SRMK, iS entered in order for the microprocessor to make measurements of intervals D or M from which it computes a new value for R the thyrister trigger delay.
~s shown in detail in Fig. 7B, this delay is loaded into the R
timer, OL register, of function 148, LOAD R TI~ER. The external data inputs, or external communications, are then monitored by sub-r~utine function 156, SRXCON shown in detail in ~ig. 7D. The ,~` `1'~

~.27~i227 sub-routine functlon 15B, SRSLC, i8 then entered for saving lamp control calculations, as shown in detail in Pig. 7E. The control portion loop i8 then completed. The program then recycles to the beginning of the control loop and waits for detection of the next zero crossing point, or ZCP pulse.
Turning to Fig. 7B, the measurement sub~routine SRMK is seen to begin with the function 160, CLEAR R TIMER, of clearing the R
timer, or register, of any trigger delay inforamtion. The function 162, WAVEFORM W3 IN l-STATE?, causes the sub-routine to then look for the positive transition of waveform W3. ~s soon as this positive transition is detected, the function 164, START R
TIMER, cause~ the sub-routine to start incrementing the R
register. This continues until function 166, WAVEFORM W3 IN 0-ST~TE, senses the negative transition of waveform W3, Fig. 5C.
The R register is then read into the appropriate location of a register associated with the sub-routine 170 SRCALCT pursuant to function 168, READ R TIMER. As will be described in greater detail with reference to Fig. 7F, the register of sub-routine 170 SRC~LCT stores the data from the R register for each of eight successive half-cycles, and the data from the latest half-cycle replaces that of the oldest half-cycle stored on a first in, first out basis. In this way the data from eight half-cycles are averaged.
The average numeric value of the data from the SRCALCT sub-routine, or N, is passed to an index register where it isthen converted via a LOOK UP TABLE program function 172 to a new angle M which has been compensated for the highly-nonlinear characteristics of fluorescent fixtures.
This value M is then added to the preselected fixture constant C and a fixed value S representing the preselected savings as preselected by the savings switch as shown by the program function 174, M~C+S=PD, to produce the phase delay value PD. Once the value P~ is determined, the subroutine is ended and returns to the main program in which the value PD is used to set the thyrister time delay in the next half cycle.
Thus, the control loop operates in real time during each half cycle in the first part of the half cycle time, and the t~igger time delay is generated by decrementing the register R
The initial value stored in regi~ter R is established Erom the measurements made of line voltage in preceeding loops. When the COUI)t in register R has been decremented to zero, the control switch 76, Fig. 3 is triggered on pursuant to the sub-routine P27~i227 SRTP, Fig. 7C. This trlgger-on-tlme wlll occur generally ~ithln the first quarter of the half cycle. The last quarter of each half cycle is devoted to measurlng the present value of line-voltage using the measurement sub-routlne SRMK, Fig. 7B. After the SRMK ~ub-routine, the control program enters the communicat~on sub-routine of Fi9. 7D and then the savings lamp illumination control sub-routine of Fig. 7E.
Referring to Fig. 7C, the sub-routine SRTP of Fig. 7C
generates three 100 microsecond positive pulse~ at 74 of Fig. 3.
On entry to SRTP the Y index register is saved at function 180, PSNY, because it is in use in the main program. It is restored u~on exit at function 198, PLY. The number three is placed in a register as shown by function 183, and is the number of pulses to be output. The Y index register i8 used to time the output pulses, as shown by function 184, it is loaded with the number 14. At the next function program step, 186, output reqister 80 is loaded to put output 74 of Fig. 3 into a logic l-state. Y is decremented to zero, as shown by functions 188 and 189, and this occupies a 100 microsecond interval. At the end of this interval Y is reloaded with the number 28 and shown by function 190 and output 74 is set to a logic 0-state by writing FE16 to port 80 as shown by function 192. Y is then decremented again to zero as shown by the loop of functions 194 and 195. On exit from this loop, the pulse counter register is decremented as shown by function 196. If not zero upon test at function 197, the loop repeats. Thus three output pulses of 100 microsecond duration and 200 microsecond spacing are produced.
Referring to Fig. 7D, the sub-routine SRXCOM permits the remote master controller 32, ~ig. 2, such as another dedicated microprocessor, to communicate with the controller cirucit 28 through the remote input interface 30 via a wire communication protocol (e.g. protocol R5-232). This is preferably comprised of a parallel data protocol for a port of eight bits and at least four additional parallel control lines.
Generally, upon entry into the SRXCOM sub-routine, the control data port i5 read into the controller circuit accumulator. If the value read is zero, the controller circuit exits the sub-routine SRXCOM. If the value i8 non-zero, the control circuit is caused to read the remote input data port and store this data in, for example, the register controlling savings before returning to the main program at ten. A return port line to the remote master controller 32, Fig. 2, may serve as a data-~27~i227 taken flag.
Specifically, at 156 in Fiq. 7A the main program calls subroutine XCOM, or SRXCOM of Fig. 7D. If the external data receiver has placed data on the I/O port 81 Comm Status (200), this data will cause a branch within the subroutine 202. The branch begin~ at function 204 where the communication port instruction is read. (In thiR example, the data in the "savings"
control register is replaced.) Finally, at function 208 a number is placed in the communicatlon status register Zp81as shown by function 210 which indlcates the data has been accepted.
Referring now to Fig. 7E, the ~ub-routine SLC functions to intensity modulate a light emitting diode, or LED, by duty cycle ratio control when the main control loop oE the program is operating. The constants of the savings register ~2 is used to control the average on current in the LED.
Generally, the contents of the savings register 24 is transferred by a temporary counter register 30. An inner delay loop is established using the ~yl~ index register. The counting reqister 30 is decremented each time the inner loop goes to zero. Thus, the time duration of the asserted signal on the savings lamp drive port connected to the savings lamp 43 of Fig.
3 is thus linearly proportional to the number contained in register 22.
Specifically, the savings lamp 43 is turned on by setting a port wire into a logid l-state, as shown at 220. This port will be held high for a variable time determined by the contents of the savings register, function 174 of Fig. 7B, referred to here at function 222 as Zp 22. Zp 22 of function 222 is transferred to a temporary register, as shown by function 224, which is later decremented to zero at function~ 230 and 232. The decrement rate, established by the Y index register as shown by functions 226, 228 and 229 is identical in principle to the pulse timing of Fig. 7C. After this variable interval, the savings lamp is pulsed off as shown by functions 234 and 236.
Referring now to Fig. 7F, the sub-routine SRCALCT functions to perform a 16 bit addition of eight numbers corresponding to eight successive microprocessor measurements and then divides this sum by eight to obtain an average value. The number eight is arbitrarily controlled by the number in the X registee.
The cesult of the averaging computation is left in locations oE
and oF on the qlobal page prior to exiting the sub-routine.
Spe~;ifica}ly, the time-duration measurement process ~2'76227 illu8trated ~n Fig. 6 pcoduce~ a number, every half-cycle, which number iB placed in eight global page registers 18, 19, ... etc.
These registers are referred to at function 254 of Fig. 7F. The C~LCT subroutine will average these eight numbers. Upon entry to the subroutine, the X index register, being used in the main program of Fig. 7A is saved at function 240 and upon exit from the subroutine, this index register will be restored at 266. At function 242 the two registers are cleared to hold the results of the computation of the loop consisting of functions 248, 250, 252, 254, 256, 25B, 260 and 261. At function 246 the X index register is set to eight and it is later decremented at function 260 to run the loop of functions 248-261 eight times.
Within this loop, a double precison addition of the eight locations is made with the result stored in Zp oE and Zp oF.
~fter the eight additions, the program exits from the loop at function 261. At function 262 the X index register is set to the number three. Double precision registers oF (MSD) and oE (LSD) are now shifted to the right by the count of X in the loop formed by functions 263, 265 and 266. Three shifts are equivalent to division by eight.
Referring to Fig. 7G, tbis sub-routine is the conventional method for converting one number of a set, possibly linear, which represents the power, to another number of another set, possibly non-linear, which represents the appropriate phase angle.
Presuming the input number is N, then the contents of the register Y
will be N. The accumulator is now loaded with the second number from a table starting with a second number from a table starting on memory at the number "BASEn. If N=~ then Y=~, and the number at BASE is in the accumulator upon exit from the sub-routine. Likewise, if Y is 10, then the number at BASE + lU
is in the accumulator upon exiting from the sub-routine.
Specifically, referring to Fig. 7G, it is assumed that the input number is ~N" and that "N" i8 the contents of register R.
Tt-e accumulator is loaded from R with this number at function 3U0 and transferred to Y at function 302. At function 304 the accumulator is now loaded from a table of numbers starting at B~SE. If the Y index register can hold on eight bit number, then the tube, being at BASE, can be 256 numbers long. The stored numbers can result in any curve shape deslred.

7~i227 Whlle a detailed desceiptlon of a preferred embodlment of my invention has been descrlbed herein, lt should be appreclated that many variations may.be made with respect thereto wlthout departing Erom the ~cope of the inventlon as deflned by the following claim8.

.

Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. In an A.C. power regulator with a power input terminal for connection to a source of A.C. input power, an electronic triggerable switch interconnecting the source of A.C. power and a power output terminal connectable with a load, and means for triggering said switch into conduction, the improvement comprising:
means responsive to the A.C. power source voltage at said power input terminal for periodically generating a distal load power pulse having a time duration which varies in proportion to the load power, said digital load power pulse generating means including means for generating a pulse during whatever time period that the magnitude of the A.C. power source voltage exceeds a preselected threshold voltage and which substantially varies in direct proportion with the load power, said pulse being generated during whatever time period that the input A.C. power voltage magnitude exceeds a threshold magnitude of approximately one half the nominal maximum magnitude of the input A.C. power voltage occurring approximately between the phase angles of 45 degrees and 135 degrees of positive half waves and between 225 degrees and 315 degrees of negative half waves; and means responsive to the time duration of the digital load power pulse for controlling said triggering means to substantially maintain a selected level of load power despite nominal fluctuations in the source of A.C. power voltage, said controlling means including a microprocessor for directly converting the digital pulse into a binary representation of the load power.