CA1297994C - Input output interface controller connecting a synchronous bus to an asynchronous bus and methods for performing operations on the buses - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus.
The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous "handshaking" manner.
The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, and SC/IOIU, such as a unit operation, a storage operation, and a message acceptance operation.

Description

79~4 AN INPUT OUTPUT INT~RFACE CONTROLLER CONNECTING 3 A SYNCHRONOUS BUS TO AN AS~NCHRONOUS BUS 4 The subject matter of this application relates to 10 computer systems~ and more particularly, to a new 11 implementation of bus~s and interface circuits which 12 interface peripherals to storage controllers and 13 main memory. This application describes a new 14 implementation of a slower asynchronous first bus, a 15 ~aster synchronous second bus, and an interface 16 controller which interconnects and buffers the 17 slower first bus to the faster second bus. 18 Computer systems include peripheral input OtltpUt 20 (I/0) equipment which must communicate with an 21 instruction processing unit (IPU) and a main memory. Z2 This communication occurs via a bus, interconnecting 23 the IPU and main memory to the peripheral equipment~ 24 for transmitting commands, instructions andidata 25 from the IPU/main memory to the peripherals and from 26 the peripherals to the IPU/main memory. There are 27 different types of buses. Some are ~aster, in their 28 operation, than others. If a faster bus were to 29 interface with a slower bus, the ~aster bus would 30 overrun the slower bus. In addition, the needs of 31 the IPU/main memory are different than the needs of 32 the peripherals. Therefore, a second bus, for 33 transmitting commands, instructions and data from 34 and to the IPU/main memory, must be different than a 35 ~irst bus for transmitting commands, instructions 36 and data from and to the peripherals. Consequently, 37 a need exists for the first bus, for communication 38 with the peripherals, the second bus, for , 39 communication with the IPU/main memory, and an 40 interface circuit, interconnecting the two busses, 41 for interfacing and buffering the first bus with the 42 second bus. 43 ., .

, .,: ~ . , , SU~MARY OF ~ INVENTION 3 It is a principal object of this invention to set 5 forth a new implementation of the first bus, termed 6 an SPD bus, a new implementatin of the second bus, 7 termed an adaptor bus, and a new implementation of 8 an input output interface controller (IOIC) 9 interconnecting and buffering the SPD bus with the 10 adapter bus. 11 The first bus, hereinafter termed the SPD bus, is an 13 asynchronous bus which functions by way of a 1~
"handshaking" arrangement whereby a unit, on one end 15 of the bus, must seek access to the bus, obtain 16 access, search for another unit on the bus by 17 transmitting a command and address, and receive an 18 acknowledgement from the other unit before 19 transmitting data from the one unit to the other 20 unit. 21 The second bus, hereinafter termed the adapter bus, 23 is a synchronous bus which functions by way of a 24 "clocking" arrangement whereby a unit, on one end of 25 the bus, will transmit commands, data or26 instructions to another unit, on the other end of 27 the bus, when appropriate clock signals are 28 generated, clocking the commands, data or , 29 instructions into the other wnit. 30 However, the clocking arrangement oP the adapter bus 32 is inherently faster, in operation r than the 33 handshaking arrangement of the SPD bus. Therefore, 34 a need exists for an input output interface 35 controller (IOIC), interconnecting the adapter bus 36 to the SPD bus, to act as a buffer between the 37 adapter bus and the SPD bus so that the faster 38 adapter bus will not overrun the slower SPD bus. 39 The IOIC must therefore comprise a registers and i 40 buffers section for storing commands, instructions, 41 and data, an adapter bus control logic for 42 retrieving the commands, instructions and data from 43 , . .
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the adapter bus for placement in the registers and 3 buffers section of the IOIC and an SPD bus control 4 logic for retrieval of the commands~ instructions 5 and data from the register and buffers section of 6 the IOIC for placement on the SPD bus (and vice 7 versa). Furthermore~ since some arbitration scheme 8 must exist for determining who may access the SPD 9 bus, the IOIC must also comprise an arbiter circuit, 10 termed a Bus Control Unit, ~or determining who shall 11 access the bus. 12 Further scope of applicabili~y of the present 14 invention will become apparent from the detailed 15 description presented hereinafter. It should be 16 understood, however, that the detailed description 17 and the specific examples, while representing a 18 preferred embodiment of the invention, are given by 19 way of illustration only, since various changes and 20 modifications within the spirit and scope of the 21 invention will become obvious to one skilled in the ~2 art from a reading of the following detailed 23 description. 24 .. ..

A full understanding of the present invention will 29 be obtained from the detailed description of the 30 preEerred embodiment presented hereinbelow, and the 31 accompanying drawings, which are given by way oE 32 illustration only and are not intended to be 33 limitative o~ the present invention, and wherein: 34 figure 1 illustrates a system block diagram o a 36 computer system which incorporates an input output 37 inter~ace controller (IOIC), and a bus, otherwise 38 referred to as an SPD bus, attaching the IOIC to ; 39 various I/O processors and peripherals; ' 40 figure 2 illustrates a block diagram of the IOIC of 42 figure 1, the IOIC including a registers and buffers 43 '.

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section, an adapter bus control logic, an SPD bus 3 control logic, and a bus control unit; 4 figure 2a illustrates a section of figure 1 6 emphasizing an inter~ace section associated with the 7 I/O bus unit (IOBU), the IOIC, and the arbiter 8 logic/IoIu/storage control of figure 1; 9 figure 3 illustrates the registers and buffers 11 section of the IOIC of figure 2, which section 12 includes a destination select register and status 13 registers; 14 figure 4 illustrates the destination select register 16 of the registers and buffers section of figure 3; 17 figures 5 through 9 illustrate the status registers 19 of the registers and buffers section of figure 3; 20 figure 10 illustrates the adapter bus control logic ~2 of figure 2; . 23 figure 11 illustrates the spd bus control logic and 25 "the bus control unit of figure 2; 26 figure 12 illustrates further detail of the,spd bus 28 control logic of figure 2 and 11; , 29 figure 13 illustrates another sketch of the bus 31 control unit, IOIC lOj-lOm and IOBUs lOp-lOs;32 figure 14 illustrates a further construction of the 34 master control unit of figure 12; " 35 figure 15 illustrates a further construction of the 37 destination select register 20h of figure 3; 38 figure 16 illustrates a further construction of the 40 slave control unit of figure 12; 41 7~
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figure 16a illustrates the addressing scheme 3 associated with the Data Buffer 20a of figure 3; 4 igure 17 illustrates a further construction of the 6 storage opcode translator unit of figure 12; 7 figure 17a illustrates a detailed layout of the 9 address registers 20d of figure 3; 10 figure 18 illustrates a further construction of the 12 bus control unit of figures 2 and 11; 13 figure 18a is a schematic of an input output 15 interface controller (IOIC) and other input output 16 bus units (IOBUJ, including three sub buses which 17 comprise the SPD bus for the purpose of illustrating 18 the function of the Bus Control Unit 50 of figure 2; 19 figure 19 illustrates a more complete view of the 21 adapter bus, input output interface controller ~2 (IOIC), and spd bus of figure 1; 23 figure 20 illustrates the Dataflow of the Storage 25 Controller 10i,10e, 10g of figure 1, the Adapter Bus 26 interface 10n, and the Storage Bus interface 10f; 27 figure 21 illustrates a table of valid processor bus 29 operation instructions for the IOIC; 30 figure 21A illustrates IOIC generated memory 32 commands, that is, commands generated from the IOIC 33 to the common storage facility via the adapter bus; 34 figure 22 illustrates the key status ~K/S) bus bit 36 layout; ; 3 7 figure 23 illustrates a table of SPD bus storage , 39 commands; 1 40 figure 24 illustrates SPD bus unit operation 42 commands; 43 EN986033 _ 5 _ ;

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figure 25 illustra-tes the command status bus command bit layout;

figure 26 illustrates the command status bus status bit layout;

figure 26a illustrates a legend used in conjunction with figures 27-39;

figures 27 32 illustrate timing se~uence diagrams associated with the adapter bus; and figures 33-39 illustrate timing sequence diagrams associated with the SPD I/O bus.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to fiyure 1, a computer system 10, including an input output interface controller (IOIC) lOj-lOm, an adapter bus lOn, and an I/O bus (otherwise termed an SPD
bus or SPD I/O bu~) lOt-lOw is illustrated.

In addition to a discussion of the present inven-tion, the following descriptlon may present and discuss areas considered peripheral to that of the present invention.
complete and thorough discussion of these peripheral areas may be fourld in a techn:Lcal manual entitled "IBM~
System/370~M Pr:l.nciples of Operation", manual number G~22-7000, which manual ls avallable :~rom IBM
Corporatlon.

In fiyure 1, an instructlon processor unit lOa is connected to an instruc-tion cache (I-cache) lOb and a clata cache (D-cache) 10c. The lnstruction cache 10b and the data cache 10c are further connected to a common storage facility lOd and to an input/output interface unit logic circuit (IOIU logic) lOe via a storaye bus 10.~. The storage bus lOf is a 36 bLt ~3~9~

bidirectional three state bus made up of 4 bytes with parity. A storage control logic circuit 109 is connected to the common storage facility lOd via a control bus lOh and interfaces with the IOIU logic circuit lOe. The control bus lOh comprises ten control or handshake lines which include the following signal lines: storage command time, card select, storage buffer time, storage data strobe, storage data valid, storage disable, storage reresh time, input parity error, ECC error, correc-ted error, and three clocks. The IOIU logic circuit lOe further interfaces with an arbiter logic circuit lOi. Refresh logic lOx is disposed within. the arbiter logic circuit lOi. The arbiter logic circuit lOi receives access requests from the instruction cache lOb via line 2 and from the data cache lOc v:La line 1. The IOIU logic circuit lOe is further connected to an input/output interface controller 1 (IOIC O) lOj, to an input/output interface controller 2 (IOIC 1) lOk, to an input/output interface controller 3 (IOIC 2) lOL, and to an input/output interface controller 4 (IOIC
3) LOm via an adapter bus 10n. ~n this implementation, there may be a maximum of 16 IOIC~, although, for the sake of clarity and brevit~, four IOICs are shown in fiyure 1. The arbiter log.ic circuit lOi receives access requests from IOIC I 10 via ].ine 3, from IOIC ~ lOk via line 4, from IOIC 3 lOL via line 5, and from IOIC g 10m via line 6. The IOICs lOj, 10k, lOL, and 10m are connectecl to various input/output (I/0) subunit processors lOp, lOq, lOr, and lOs via I/O buses lOt, 10u, lOv, and lOw, respectively. Here:Lnafter, an I/O subun:lt processor lOp-lOs will be referred to as an I/O bus unit, or an IOBU and an I/O bus lOt-lOw will be referred to as the SPD bus. An SPD bus is capable of handling addressing signals for up to 32 IOBUs.
The arbiter logic circuit lOi receives bus adapter' access requests from the storage control logic lOg via line 7, an access request from the refresh logic 10~ via line 8, and a Processor Bus Operation (PBO) ENg86033 `t:~

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cycle steal (CS~ request from the storage control logic lOg via line 9.

The functional operation of the computer system of figure 1 will be described in the following paragraphs with reference to figure 1.

The instruction processor unit (IPU) lOa executes instructions stored in -the instruction cache lOb utilizing data stored in the data cache lOc. The results of the execution of the instructions are stored in the common storage facility lOd. If it is necessary to transfer the results to various ones of the IOBUs lOp, lOq, ].Or, and lOs, the results are retrieved from the common storage facility lOd by the storage control logic lOg and are transferred to the adapter bus lOn via the IOIU logic lOe ancl to the IOBUs lOp through lOs via the IOICs lOj through lOm and the SPD buses lOt through lOw.
However, the instruction cache lOb, the da-ta cache lOc, and/or one or more o~ the IOICs lOj through lOm may require access to the shared buses (storage bus lOf, and the adapter bus lOn) simultaneously. Since the shared buses can handle only one access at a time, some arbitration mechanism must be utili~ed to determine which unit will access the shared bus at a particular point in ti.me. In order to ma~e this determination, a plura:l.ity of units needing access, comprlsing the data cache lOc, the instruction cache lOb, the IOIC 1 10~, the IOIC 2 lOk, t.he IOIC 3 lOL, the IOIC 4 lOm, the storage control logic JOg and the re~resh logic lOx, each generate an access request si.gnal which is clirected to the arbiter logic lOi v:ia lines 1 through 9. In aeeordanco with a partieular arbi.tratioll scheme, the arbiter logic lOi determines which of the pl~lrality of units wi].l aecess the shared bus.

complete description of the arbiter logic lOi may be found in IJ.S. Patent No. 4,760,515, issued July, 26, 1988, assigned to the `- ~2~ f~

same assignee as tha-t of the present invention, entitlefl "an arbitration apparatus for determining priorit~ of access to a shared bus on a rotating priority basis".

A complete description of the instruction processing unit lOa of figure 1 may be found in a prior Canadian pending application serial number 538,165, filed on May 27, 1987, assigned to the same assignee as that of the present invention, entitled "a se~uence controller of an instruction processing unit for placing said unit in a ready, go, hold, or cancel state".

Referring to figure 2, a block diagram of each IOIC lOj, lOk, 101, and lOm, is illustrated.

Each IOIC lOj through lOm is interfaced between an adapter bus lOn, which moves data using system clocks (i.e. - it is a synchronous bus), and an I/O bus otherwise termed the SPD bus 10-t, lOu, lOv, and lOw, which moves data at a speed determined by the "handshaking" between one of the IOICs lOj, lOk, 101, and lOm and an I/O bus unit (IOBU), one of IOBUs lOp, lOq, lOr, and lOs (i.e. - it is an as~nchronous bus). Because of the difference between the data speeds of the adapter bus lOn and the SPD hus lOt, lOu, lOv, and lOw, the IOIC
lOj througll lOm must bufer all received data and control informatiotl in the IOIC buffers so that a faster adapter bus lOn w.ill not overrun a slower SPD bus lOt through OW .

:[n f.igure 2, an input output .inter~ace controller (IOIC) 10~, lOlc, 101, or lOm iE: shown as being interposed between the adapter hus lOrl on one end and the SPD bus lOt through lOw on the other end.

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Each of the IOICs 10j through 10m comprise a 3 registers and buffers section 20 connected to the 4 adapter bus 10n and one of the SPD susses 10t thru 5 10w; an adapter bus control logic 30 connected to 6 the registers and buffers section 20 and to the 7 adapter bus 10n; an SPD bus control logic 40 8 connected to the registers and buffers section 20, 9 to the adapt~r bus control logic 30, and to one of 10 the SPD buses 10t through 10w; and a bus controlll unit (BCU) 50 connected to the SPD bus control logic 12 40, to the adapter bus control logic 30, and to one 13 of the SPD buses 10t, 10u, 10v and 10w. 14 The registers and buffers section 20 of the IOIC16 include re~isters and buffers. The registers are17 used to hold data from both the IOIU 10e and the I/O 18 bus units (IOBUJ 10p through 10s. In addition to19 holding the data, the IOIC registers use this data 20 to generate commands and hold status information21 associated with the IOIC operation. The IOIC ~2 buffers are used to hold data originating from the 23 SPD bus 10t through 10w or the adapter bus 10n; 24 however, in contrast with the IOIC registers, the 25 IOIC buffers function solely to hold this data until 26 it can be passed on from one bus to the other. In 27 general, the IOIC registers and buffers 20 are used 28 to hold all the information needed by the IOIC to 29 transfer data from the adapter bus 10n to the SPD 30 bus 10t-10w or from the SPD bus 10t-10w to the 31 adapter bus 10n. The registers and buffers 20 are 32 controlled by two bus control logic blocks, the 33 adapter bus control logic 30 and the SPD bus control 34 logic 40. The adapter bus control logic 30 and the 35 SPD bus control logic 40 do not interfere with each 36 other, and both can be performing a function 37 simultaneously. They prevent buffers, in the 38 registers and buffers section 20, from being 39 overwritten if they are still being used. Parity is 40 checked and good parity is generated as new data, is 41 set in the buffers so that there will never be bad 42 parity in the buffers which could cause a machine 43 , .

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check when reading the buffers after a parity error 3 is detected. 4 The adapter bus control logic 30 controls all the 6 gating and setting of the registers and buffers with 7 respect to data ~rom and to the adapter bus 10n. It 8 also decodes all the commands that are transmitted 9 from the IPU 10a via the IOIU 10e to the IOIC 10j 10 through 10m and it controls their function or sends 11 the information to the SPD bus control ]ogic 40 if 12 the command is a unit operation. It requests the 13 adapter bus 10n and controls the data to and from 14 the adapter bus for storage operations with respect 15 to the I/O bus units (IOBU) 10p through 10s~. 16 The SPD bus control logic 40 controls all the gating 18 and setting of the registers and buffers 20 with 19 respect to data from and to an SPD bus 10t through 20 10w. It also decodes all the commands that come 21 from the IOBUs 10p through 10s to the IOIC 10j ~2 through 10m and controls their function. In 23 addition, it generates storage operation codes and 24 starting addresses for storage operations to the 25 common storage facility 10d. For message acceptance 26 and storage operations, it sends information to the 27 adapter bus control logic 30 so that data from those 28 operations can be sent to the common storage29 facility 10d via the adapter bus 10n. 30 The bus control unit ,~BCU) 50 of IOIC 10j-lOm 32 controls arbitration of the IOBUs 10p through 10s 33 access to the SPD bus 10t through 10w and monitors 34 the functions on the SPD bus. The BCU 50 includes a 35 programmable timer. If the SPD bus operation takes 36 too long, or hangs, the operation will timeout so 37 that the SPD bus can recover. Only the BCU 50 can 38 originate Direct Selection operations on the SPD bus 39 10t through 10w. Because an IOIC 10j through 10ml 40 contains the BCU 50, its address will always be "00" 41 on the respective SPD bus 10t through 10w. 42 . .

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The broad functional operation of the IOIC lOj-lOm, 3 the adapter bus lOn and the SPD bus lOt-lOw, will be 4 described in the following paragraphs with reference 5 to figure 2 of the drawings. 6 Let us assume that commands and/or data shall be 8 transmitted from the main memory or common storage 9 facility lOd to one of the IOBUs lOp-lOs. The IOIU lO
lOe relays the data for transmission to an IOIC. ll Since the adapter bus lOn is a synchronous bus (one 12 whereby data is transmitted when properly clocked 13 into a second unit from a first unit), the data in 14 the IOIU lOe is clocked into the registers and 15 buffers section 20 of the IOIC via the adapter bus. 16 The adapter bus control logic 30 controls the 17 retrieval of the data from the adapter bus lOn and 18 the subsequent storage of the data into the 1 registers and buffers section 20. The adapter bus 20 control logic 30 notifies the spd bus control logic 21 40 when the buffer is full. In response, the spd ~2 bus control logic 40 notifies the bus control unit 23 (BCU) 50. Since the BCU 50 is the arbiter ~or use 24 of and access to the SPD bus lOt-lOw, the BCU 50 25 determines when the spd bus control logic 40 may 26 have access to the SPD bus after the spd bus control 27 logic 40 requests the bus. When the BCU SO 28 determines that there is no other IOBU lOp-lOs 29 having a higher pxiority for access to the SPD bus, 30 the BCU 50 transmits an acknowledge bus (~C~B) 31 signal to the spd bus control logic 40 giving the 32 logic 40 the next access to the SPD bus lOt-lOw. 33 However, the spd bus control logic 40 cannot proceed 34 until it receives a bus grant (BUSG) signal from BCU 35 50. When the spd bus control logic 40 is given 36 access to the SPD bus, by receiving a bus grant 37 (BUSG) signal from the BC~ 50, it controls the 38 registers and buffers section 20 to place the data 39 stored therein onto the SPD bus. 1 40 However, since the SPD bus is an asynchronous bus, 42 the spd bus control circuit 40 does not place data 43 - :

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on the SPD bus via a clocking arrangement~ rather, 3 it places data on the SPD bus via a "handshaking" 4 arrangement. The "handshaking" arrangement is S
described in the following paragraph~ 6 The "handshaking" arrangement is essentially a 8 master/slave relationship, wherein the IOIC may be 9 the master and an IOgu may be a slave, or the IOBU 10 may be the master and the IOIC may be the slave. ll When the IOIC is attempting to place data on the SPD 12 bus for the purpose of transmitting such data to an 13 IOBU, the IOIC is the master and the IOsU is the 14 slave. As will be described in more detail below, 15 the SPD bus 10t-10w comprises an SPD address data 16 (A/D) bus, a command status (C/S) bus and an origin 17 destination (O/D) bus. When the data from the IOIC 18 registers and buffers section 20 is placed onto the 19 SPD bus, via the A/D bus, C/S bus, and O/D bus, 20 three signals are used by the spd bus control logic 21 40 of the IOIC and by the IOBUs attached to the SPD 22 bus: a master steering (MST~ signal, a master 23 select (MSEL) signal, and a ready (RDY) signal. 24 Prior to placement of the data from registers and 25 buffers 20 on the SPD bus, the spd bus control logic 26 40 generates the MST signal to all IOBUs. The MST 27 signal says: "I have the bus". Therefore, in the 28 above example, the spd bus control logic 40 of the 29 master IOIC transmits the MST signal to the arbiter 30 in the BCU 50 for the purpose of informing the BCU 31 that the master IOIC has access to the SPD bus. The 32 spd bus control logic 40 then controls the placement 33 of the data from the registers and buffers sectio-n 34 20 onto the SPD bus. The spd bus control logic 40 35 then transmits the MSEL signal to all its IOBUs. 36 The MSEL signal says: "data has been placed Oll the 37 bus and it is valid". Therefore, in the above 38 example, the spd hus control logic 40 of the master 39 IOIC transmits the MSEL signal to all prospectivel 40 slave IOBUs attached to its respective SPD bus, for 41 the purpose of informing the IOBUs that the data has ~2 been placed on the bus and the data is valid. When 43 .
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a slave IOBU has received the data, the slave IOBU 3 transmits the RDY signal back to the master IOIC, 4 from which the data was transmitted. The RDY signal 5 says: "I have received ~our data and I have placed 6 my own data on the SPD bus, if needed". Therefore, 7 in the above example, the slave IOBU transmits the 8 RDY signal to the master IOIC for the purpose of 9 informing the master IOIC that the slave IOBU has 10 received the transmitted data and, if necessary, has 11 proceeded to transmit its own data back to the 12 master IOIC. Because the SPD bus is asynchronous, 13 the response from the slave IOBU may be given at any 14 time. 15 Therefore, after the master IOIC has informed the 17 BCU 50 that it has access to the SPD bus, via the 18 MST signal, the master IOIC "talks" to the slave 19 IOBU via the MSEL signal, indicating the data has 20 been placed on the bus, and the slave IOBU "talks" 21 to the master IOIC via the RDY signal, indicating ~2 the data has been received and, if necessary, other 23 data is being returned ~o the master IOIC. 24 Referring to figure 2a, a section of figure 1 is 26 illustrated. In figure 2a, a pair of I/O bus units 27 (IOBU), one of 10p-10s, are connected to an 28 input/output interface controller ~IOIC), one of 29 10j-lOm, by way of an SPD I/O bus, one of 10t-10w. 30 The IOIC is also connected to the arbiter logic 31 10i/IOIU 10e/storage control 10g by way of the 32 adaptor bus 10n. Each I/O bus unit 10p-10s 33 includes, as a physical part thereof, an interface 34 section 12 an~ a main section, the main section 35 being the I/O bus unit minus the interface section 36 12. The IOIC 10j-lOm also includes, as a physical 37 part thereof, an interface section 12, on the SPD 38 bus side, an interface section 14, on the adaptor 39 bus side, and a main section. The main section of 40 the IOIC would include the IOIC minus interface 41 sections 12 and 14. The arbiter logic 10i/IOIU 42 10e/storage control 10g also incorporates an 43 .
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interface section 14 and a main section, the maln 3 section consisting of the arbiter lOi, IOIU lOe, and storage control lOg minus int~rface section 14. 5 In figure 2a, since the SPD I/O bus lOt-lOw must 7 interface with both the IOIC lOj-lOm and the I/O bus 8 units lOp-lOs, the interface sections 12 associated 9 with the the IOIC and the I/O bus units must be 10 identical to each other. In addition, the interface 11 sections 12 associated with the IOIC and the I/O bus 12 units must be be identical, in structure and13 function, to the structure and function of the SPD 14 I/o bus. Similarly, the interface sections 14 15 associated with the IOIC and the arbiter lOi/IOIU 16 lOe/storage control lOg must be identical to each 17 other and must be identical, in structure and 18 function, to the structure and function of the 19 adaptor bus lOn. 20 The structure and function of the adaptor bus lOn 22 and the SPD I/O bus lOt-lOw will be set forth in 23 detail in the following paragraphs. 24 The information contained the following paragraphs 29 will describe in detail (i) the construction and 30 function of the input output interface controller 31 (IOIC), (ii) the construction and function of the 32 storage controller which includes arbiter logic lOi, 33 IOIU logic lOe, and storage control logic lOg, (iii) 34 the construction and functional characteristics of 35 the adapter bus lOn, (iv) the construction and 36 functional charackeristics of the SPD I/O bus 37 lOt-lOw; and (v) a functional description of the SPD 3~
bus lOt-lOw, IOIC, adaptor bus lOn, and Storage 39 Controller lOe, lOg oper~ting in combination while 40 performing a variety of specific functional41 operations. ~ 42 .

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(i) Input Output Interface Controller (IOIC) 3 lOj-lOm 4 Referring to figure 3, a block diagram of the 6 registers and bu~fers section 20 of figure 2 is 7 illustrated. 8 In figure 3, the registers 2nd buffers section 20 10 comprises data buffers 20a connected to the adapter 11 bus lOn via an adapter address data (A/D) bus lOnl 12 and -to the SPD bus lOt-lOw via an spd address data 13 (A/D) bus lOtl; ~essage buffers 20b connected to the 14 adapter bus lOn via the adapter address data (A/D) 15 bus lOnl`and to the SPD bus lOt-lnw via the spd 16 address data (A/D) bus lOtl; a key buf~er 20c 17 connected to the adapter bus lOn via a key status 18 (K/S) bus lOn2 and to the SPD bus lOt-lOw via the19 spd address data ~A/D) bus lOtl; address registers 20 20d connected to the adapter bus lOn via the adapter 21 address data (A/D) bus lOnl and to the SPD bus 22 lOt-lOw via the spd address data (A/D) bus lOtl: a 23 selector bu~fer 20e connected to the adapter bus lOn 24 via the adapter address data ~A/D) bus lOnl a . 25 select data buffer 20f connected to the selector26 buf~er 20e and to the SPD bus lOt-lOw via the spd27 address data (A/DI bus lOtl; status registers 20g 28 connected to the adapter bus lOn via the adapter . 29 address data (A/D) bus lOnl and the key status (K/S) 30 bus lOn2 and to the SPD bus lOt-lOw via the spd 31 address data (A/D~ hus lOtl, an orig dest (O/D) bus 32 (origin destination bus) lOt3, and a comd status 33 (C/S) bus (command status bus) lOt2; a dest select 34 register 20h (destination select register) connected 35 to the adapter bus lOn via the adapter address data 36 (A/D) bus lOnl; a command register 20i connected to 37 the dest select register 20h and to the SPD bus38 lOt-lOw and the status registers 20g via the orig 39 dest (O/D) bus lOt3 and to the SPD bus lOt-lOw and ~0 the status registers 20g via the comd status (C/S) 41 bus lOt2; and a diagnostic buffer 20j connected to 42 the spd address data (A/D) bus lOtl. 43 .
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Hereinafter, the spd address data bus lOtl will be 3 referred to as the spd A/D buslOtl, origin destination bus lOt3 as the O/D bus lOt3, command 5 status bus lOt2 as the C/S bus lOt2, adapter address 6 data bus lOnl as the adapter A/D bus lOnl, and key 7 status bus lOn2 as ~he K/S bus lOn2. 8 Generally speaking, the buffers 20a, 20b, 20c, 20e, 10 20f and 20j function solely to store data ll temporarily as the data is transmitted from the SPD 12 bus lOt-lOw to the adapter bus lOn or vice-versa. 13 Buffers 20e, 20f functions solely to receive data 14 from the Adapter bus and and transmit the data to 15 the SPD bus; buffer 20j receives and sends data 16 from/to the SPD bus only. The buffers do not alter 17 or otherwise change the data while heing stored 18 therein. - 19 The data buffers 20a are eight data buffers which 21 are each four bytes wide. According to this ~2 implementation, the data buffers 20a can buffer up 23 to thirty two bytes of data, with parity, when the 24 IOIC is doing storage operations. However, an 25 additional 32 bytes of data could be buffered if one 26 so desired. The data buffers 20a are used when the 27 IOIC is a slave for storage and message acceptance 28 operations. The data path to and from the data 29 buffers is four bytes wide and the data must be byte 30 aligned by the IOBUs lOp-lOs before being sent to 31 the data buffers of the IOIC. 32 The message bufers 20b comprise two message 34 buffers, message buffer 1 and message buffer 2, each 35 being capable of buffering four bytes of data with 36 parity. The message buffers 20b are used when the 37 IOIC is master or unit operations. The data path 3~
to and from the message buffexs is four bytes wide 39 and the information in the message buffers is the 40 data on the spd address data tA/D) bus lOtl during 41 the two data cycles of a unit operation. There are 42 four processor bus operatlon tPBO) commands 43 ,, .
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EN9~6033 - 17 -~2~
associated with the message buffers. They are: load 3 message buffer reg 1 tLMsRl)~ load message buffer 9 reg 2 (LMBR2), copy message buffer reg 1 (CMBRl), 5 and copy message buffer reg 2 (CMBR2). The load 6 instructions are not performed when a Message 7 Origination Status Word (MOSW) busy bit is on; 8 instead, IOIC BUSY is returned to the adapter bus. 9 The key buffer 20c is five (5) bits wide, with ll parity, and is used to buffer the first five (S) 12 bits of the spd address data bus during a select 13 cycle when the IOIC 10j 10m is a slave. This data 14 is sent to the IOIU 10e, for storage protection and 15 message acceptable buffer selection, via the key 16 status bus portion of the adapter bus 10n following 17 receipt of a grant to access the adapter bus 10n. 18 The selector buffer 20e is four bytes wide, with 20 parity, and is used to buffer the data ~rom the RS 21 register of the IPU 10a, which is the data on the 22 adapter address data (A/D) bus 10nl following the 23 command time cycle of a processor bus operation 24 ~PBO) command. The selector buffer 20e is set in 25 each IOIC 10j-lOm following the command time cycle. 26 The select data buffer 20f is four bytes wide, with 28 parity, and is set with the data from the selector 29 buffer 20e when the IOIC address matches the 30 destination select address presented on the Adapter 31 Bus at Adapter Command Time and the IOIC is not 32 busy. The data from the buffer is placed on the spd 33 address data bus during the select cycle when the 34 IOIC 10j-lOm is master for a unit operation.35 The diagnostic bu~fer 20j is four bytes wide, with 37 parity, and is set with the data from the spd A/D 38 Bus 10tl during a Select Cycle when doing SPD Read, 39 Wrap commands and the IOIC is the slave. During the 40 two data cycles of this command the contents of t~e 41 diagnostic buffer are driven to the A/D Bus by the 42 IOIC. 43 .

.

The definitions of a select cycle, a data cycle, and 3 read wrap commands will become apparent from a 4 reading of the remaining portion of this detailed 5 description. 6 The registers 20d, 20g, 20h, and 20i are loaded with 8 data from the buses lOn and lOt-lOw, the data heing 9 used by the IOIC lOj-lOm to perform its operation. 10 The data in the registers is passed on to one or the 11 other of the buses lOn, lOt-lOw, but the IOIC12 lOj-lOm may alter the data before it is passed to 13 the respective bus. 14 Referring to figure 4, a sketch of the fields 16 associated with the dest select register 20h is 17 illustrated. The dest select tdestination select) 18 register 20h is four bytes wide, with parity. It is 19 used to buffer the adapter command, spd cornmand, 20 IOIC number, priority, and spd destination address. 21 This i~ the data on the adapter address data (A/D) 2~2 bus lOnl during the command time cycle of a 23 processor bus operation (PBO) instruction. The 24 destination select register 20h is set by each IOIC 25 "during command time cycle. The IOIC checks' this 26 data to see if there is an address match and27 determines the type of comrnand. ' 28 Referring to figure 3, the command register 20i is 30 four bytes wide, with parity, and is set with the 31 data ~rom the dest select register 20h when the IOIC 32 address matches and the IOIC is not busy. The data 33 for the spd cornmand status ~C/S) bus lOt2 and the 34 spd orig dest (O/D) bus lOt3 during the select cycle 35 comes from this register when the IOIC is master for 36 a unit operation. 37 The address registers 20d include four address 39 registers which are each four bytes wide. They are 40 used to store a maximum of four memory commands and 41 addresses. The first address register is set with 42 the data on the spd address data (A/D) bus lOtl 43 :

EN986033 - 19 ~

during the select cycle when t~le IOIC is a slave. 3 Next, the SPD bus control logic 40 looks at the SPD 4 bus command and byte three of the address register. 5 If the command is a storage command, it generates a 6 memor~ command which it then puts in byte zero of 7 the first address register. If, due to boundary 8 restrictions, the first memory command cannot store 9 all of the data in the data buffers, then, the SPD 10 bus control logic 40 generates a new memory command 11 and address and puts it in bytes zero and three of 12 the next address register. It can take up to four 13 memory commands to store the data buffered in one 14 spd storage operation. Therefore, the SPD bus 15 control logic 40 will generate up to four commands 16 and addresses and put them in the four address 17 registers. The SPD bus control logic 40 will18 generate one memory command when doing a read, 19 therefore, only the first address register is used 20 during a read. The data in bytes one and two is not 21 changed by the memory command generator. ~2 The status registers 20g comprise a plurality of 24 registers which contain bits that may be set25 directly by executing an instruction, are the 26 logical OR of other status bits, or are set~by the 27 IOIC. Some bits are hardwired and can only be 28 copied~ The following numbered paragraphs set forth 29 a description of each of the registers in status 30 registers 20g: 31 (1) message origination status word ~MOSW) register: 33 referring to figure 5, the MOSW is illustrated. The 34 MOSW is a thirty-two bit word used by the IOIC to 35 record status pertaining to unit operations 36 initiated by the ~OIC. The unit operations use MOSW 37 to indicate busy, error and operation end status. 38 When the IOIC accepts a unit operation, it resets 39 the operation end ~E) bit, bstatus ~BSTAT) data end 40 bit and the destination ~DEST) field of the MOSW 41 while setting the busy ~b) bit of the MOSW. The , 42 status summary ~S) is the logical OR of all the 43 ~ ~2~7~
error bits in the MOSW. When both the E and the S 3bits are one (1), an operation end interrupt (EIS(5)) is signaled. The gSTAT is received on the 5spd comd status (C/S) bus 10t2 at the end of the 6data cycles, the ssTAT containing the ending status. 7The DEST is recelved on the spd orig dest (O/D) bus 810t3 during the data cycles when doing Direct Select 9Unit operations. There are two Pso commands for 10reading the MOSW; they are: copy MOSW (CMOSW) and llmove MOSW (MMOSW). Both instructions read the MOSW 12but the MMOSW will reset all the other hits after 13reading the E bit and determining if the E bit is in 14an on condition (binary 1). 15 (2) message acceptance status word (MASW) register: 17referring to figure 6, the MASW is illustrated. The 18MASW is a thirty two bit word used by the IOIC to 19record status pertaining to message acceptance 20operations. It is the fourth word stored as part of 21the message acceptance operation. The MASW contains 22the CMD field, which represents the comd status bus 23during the select cycle, the IC number, which is the 24address of the IOIC, and the ORIG field, which is 25the bus address of the IOBU 10p-10s originating the 26 message acceptance operation. 27 , !

(3) monitor status word (MSW) register: referring 29 to figure 7, the MSW is illustrated. The MSW is a 30 thirty two bit word required by IOICs that support 31 the BCU 50 function for fault isolation. The 32 contents of the MSW are defined only between the 33 time that it is set and the next SPD bus operation. 34 The MSW records the state of the SPD bus 10t-10w at 35 the time it is set. In figure 7, the TAGS field 36 contains the state of master select (MSEL), ready, 37 master steering (MST), acknowledge bus and bus 38 grant. The C/S field contains a number representing 39 the comd status bus, and the O/D field contains al 40 number representing the orig dest bus. There are 41 three parity error bits in the MSW which indicate if 42 the comd status (C~S) bus 10t2, the orig dest ~O/D) 43 ' ~N986033 - 21 -7~

bus 10t3, or the spd address data (A/D) bus 10tl had 3 a parity error at the time when the MSW was set. 4 The arbitration field contains the state of the 5 request bus and the three request priority lines 6 along with the state of the board select line. The 7 MSW is set as the result of a bus timeout or the 8 execution of the se~ MSW (SMSW) PBO instruction- 9 The PBO command ~or reading the MSW i5 the copy MSW 10 (CMSW) command. 11 (g) IOIC status word (ICSW3 register: referring to 13 figure 8, the ICSW is illustrated. The ICSW is a 14 thirty-two bit word used by the IOIC to record 15 status pertaining to asynchronous bus events. In 16 figure 8, the ICSW includes a commands received 17 field, a status field, and a timeout field. When 18 the IOIC is a bus slave during a unit operation, it 19 'ORs' a one with the corresponding bits in the 20 Commands Received field for the Resume, Address 21 Request, and Suspend Request commands. The Status 2~
field contains bits for Unit Check (for both Unit OP 23 and Storage OP), Storage Error, and Buffer Not 24 Available. The Timeout bits are set when there is a 25 timeout and indicates the type (Idle/Operation) of 26 timeout. The Status Summary (S) bit is the logical 27 'OR' of all the bits i~ the ICSW that need to raise 28 an EIS(4) interrupt. There are two PBO commands 29 associated with the ICSW. They are Copy ICSW (CICSW) 30 for reading the word, and Reset ICSW under mask 31 (RICSW) ~or resetting the bits that can be reset~ 32 (5) IOIC control register (ICCR): referring to 34 figure 9, the ICCR is illustrated. In figure 9, the 35 ICCR includes an initialization state field, a 36 timeout field, a line length field, and an IOIC 37 status and control field. The ICCR is a thirty-two 38 bit word used to control IOIC functions and provide 39 status. The ICCR is also used to provide a 40 programming interface for data returned to another 41 IOBU 10p-10s via the Read Immediate Status SPD I/O 42 ~us command. The Timeout field holds the status of 43 the IOIC at the time of a timeout plus three errors 3 that can cause a timeou~. The Initialization State 4 and Line Length fields contain data needed by an s IOBU when doing a Read Immediate Status to the IOIC. 6 Initialization State bits are set and reset by PBO 7 commands and the line length field is set to 8 thirty-two bytes. The IOIC Status and Control bits 9 field is used by an IOIC to communicate status to 10 the program or to permit programmed control of IOIC 11 functions. The status control bits are Allow12 Arbitration, Activate BUS Clear, Ready (for both 13 Unit Op and Storage Op), Assigned BCU, and Monitor 14 Clock Disable. There are three PBO commands 15 associated with the ICCR. They are Copy ICCR (CICCR) 16 for reading the word, Set ICCR under mask (SICCR) 17 for setting state and control bits, and Reset ICCR 18 under mask (RICCR) for resetting the bits that can 19 be reset. The set and reset instructions are not 20 performed when the MOSW Busy bit is on and IOIC BUSY 21 is returned to the Adapter Bus. ~2 Referring to figure lO, a block diagram of the 24 adapter bus control logic 30 of figure 2 is 25 illustrated. ~ 26 .. . .
Thé Adapter Bus control logic 30 is used to control 28 all the IOIC lOj-lOm ~unctions needed for the29 transfer of data to and from the adapter bus lOn. 30 This includes handling of PBO instructions, keeping 31 track of Adapter Bus cycles for the IOIC, and 32 placing data in or getting data from the correct 33 registers and buffers of the IOIC. It also handles 34 status information Erom the Key/Status (K/S) Bus 35 lOn2 and puts that status in the Status Registers 36 20g or sends it to the SPD Bus Control Logic 40 to 37 be put on the comd status (C/S) bus lOt2. 38 In figure 10, the adapter bus control logic 30 40 comprises an IOIC match logic 30a responsive to an 41 SPD busy signal, to a hardware address signal, and 42 to selector buffer data. It outputs either an IOIC 43 .

acknowledge signal or an IOIC busy signal; a PBO 3 facility logic 30b connected to the IOIC match lo~ic 30a, responsive to the selectox buffer data and 5 generating a status register control signal, a load 6 command buffer signal, and a message buffer control 7 signal; a Pso sequencer 30c connected to the Pso 8 facili~y, responslve to adapter command time and 9 generating a load selector buffers signal; and a 10 storage op con~roller 30d receiving address register 11 bits, data valid signal, IOIC grant signal, and 12 adapter status signal and generating a data buffer 13 control signal, an address register control signal, 14 a key register control signal, an IOIC requests 15 signal, an SPD bus logic signal, and a storage 16 status signal. 17 With regard to the PBo sequencer 30c of figure 10, 19 the start of a PBO instruction to an IOIC is20 signaled by the adapter command time..signal from the 21 IOIU lOe of figure 1. At this time, in response to 22 the adapter command time signal, the PBO Sequencer 23 30c, in all the IOIC's lOj-lOm, starts/gates the 24 adapter address data bus lOnl by generating the Load 25 Selector Buffer control signal, the load selector 26 buffer control signal energizing the dest select 27 register 20h of figure 3 during the first cycle. 28 During the second cyc].e the PBO Sequencer 30c gates 29 the Adapter address data Bus lOnl to the selector 30 buffer 20e of figure 3. The PBO Se~uencer 30c also 31 keeps track of the cycle of the PBO instruction as 32 it is executed by the PBO Facil.ity logic 30b. 33 With regard to the IOIC address match logic 30a of 35 figure 10, the IOIC# field of the Dest Select 36 register 20h of figure 3 contains the address of the 37 IOIC for which the PBO instruction is intended. 38 This address is matched against a hardware address 39 in the IOIC. If there is a match, the IOIC Matchl 40 logic 30a looks at the Adapter Command field of the 41 Dest Select reg 20h of figure 3 for the type of 42 command. The types of commands that the match logic 43 30a looks for are ones that can be performed at any 3 time and ones that can only be performed when the 4 SPD Bus is not busy. The commands that can be 5 performed at an~ time will always send the IOIC 6 ACKNOWLEDGE signal back to the IOIU lOe when there 7 is a match. The other commands must determine if the 8 SPD Bus iS busy (MOSW Busy Bit). The IOIC 9 AcxNowLEDGE signal will be transmitted if the SPD 10 bus 10t-10w is not busy and the IOIC BVSY signal 11 will be transmitted if the SPD Bus 10t-10w is busy. 12 The IOIC 10j-lOm will not perform or hold the PBO 13 instruction after it sends the IOIC BUSY signal back 14 to the IOIU 10e. 15 With regard to the PBO facility 30b, the PBO17 Facility 30b takes the Adapter Command from the DEST 18 SELECT register 20h of figure 3 and decodes the PBO 19 instruction. If the PBO Facility 30b decodes a Unit 20 Operation, it will load the command buffers using 21 the Load Command Buffers controls. The process of ~2 loading the command buffers involves copying the 23 DEST SELECT REGISTER 20h to the COMMAND REGISTER 20i 24 and copying the SELECTOR BUEFER 20e to the SELECT 25 DATA BUFFER 20f. This is information that the SPD 26 Bus Control Logic 40 will need to complete the 27 operation on the SPD Bus. The PBO Facility 30b will 28 set the MOSW Busy Bit (figure 5) so that no other 29 Unit Operations can be accepted until this one has 30 ended. The Unit Operation decode will also send a 31 PBO request to the SPD Arbiter for use of the SPD 32 BUS. The PBO instructions that are not Unit 33 Operations all have to do with the IOIC Registers 34 and Buffers. The PBO Facility logic 30b, using the 35 Status Register 20g and Message Buffer Controls, 36 generates all the controls to gate and set the 37 correct data to or from the Adapter Bus 10n. 38 With regard to the storage operation controller 30~, 40 the storage commands, including the message41 acceptance command, are started by requesting the 42 ADAPTER BUS 10n from the IOIU 10e. There are two 43 EN986033 ~ 25 -7~
types of requests made by the Storage Op Controller 3 30d for access to the Adapter Bus, that is 7 the 4 command request ~IOIC CMD REQ) and the normal 5 request ~IOIC REQ). The SPD sus Control Logic 40 6 tells the Storage Op Controller 30d when it is time 7 to send the request. After requesting the bus, 8 nothing happens until the IOIC GRANT signal is 9 received from the IOIU 10e, granting the IOIC access 10 to the adapter bus lOn. When the grant is received 11 and validated, the request is dropped and the 12 Storage Op counter starts. The ADDRESS REGISTER 13 CONTROL signal gates the command and address onto 14 the Adapter Address data (A~D) Bus 10nl and the KEY 15 REGISTER CONTROL signal gates the key onto the key 16 status (K/S) Bus 10n2 during the cycle following the 17 receipt of IOIC GRANT. Looking at the command and 18 address, the DATA BUFFER CONTROL signal moves the 19 data between the DATA BUFFERS 20a and the Adapter 20 Bus 10n using data buffer pointers from the last 21 b~te of the address. After moving the data, the 2~2 storage op controller 30d waits for status on the 23 Key status (K/S) bus 10n2 and checks to see if 24 another storage operation is needed to move the data 25 in the data buffers 20a. If more data needs to be 26 moved, the Storage Op Controller 30d will start a 27 new storage operation with a request for the ADAPTER 28 BUS, via the ~OIC REQUESTS signal, and use the 29 command and address in the next Address Register~ 30 After all the data has been moved, the Storage Op 31 Controller 30d will give the SPD Bus Control Logic 32 40 his ending status. 33 Re~erring to ~igure 11, the SPD bus control logic 40 35 and the bus control unit (BCU) 50 of figure 2 is 36 shown again in figure 11. 37 The SPD Bus Control 40 and Bus Control Unit (BCU) 50 39 are the IOIC logic controllers for the SPD I/O Bus, 40 overseeing hus arbitration, processor initiated bus 41 operations and storage transfers. Figure 11 42 provides a high-level view of the SPD bus control 40 43 :l2~
and the BCU 50 logic. There are two distinct 3 operations that the logic must performO The SPD Bus Control Logic 40 containS the control unit for IOIC 5 bus functions. This includes handling storage 6 operations, messaye operations and unit operations. 7 The bus control logic 40 must perform tag 8 handshaking, provide proper bus control signals and 9 data validity indicators to the data flow logic, 10 IOIC Registers and Buffers. In addition to 11 providing controls to the data flow logic (where the 12 A/D Bus drivers physically reside), the bus control 13 logic 40 has direct responsibility for driving and 14 receiving the origin destination {O/D) bus and the 15 command/status interface (C/S) Bus. The Bus Control 16 Unit (BCU) 50 controls bus arbitration (the orderly 17 transfer of control from one bus user to another) 18 and includes several timers which are used to keep 19 track of the time a bus operation is taking to 20 complete. The objective behind the use of the timers 21 is to determine why a bus user has stopped the 22 operation of the SPD bus 10t-10w. 23 Referring to figure 12, a further construction of 25 the SPD bus control logic 40 of figures 2 and 11 is 26 illustrated. 27 The SPD bus control logic 40 is comprised of four 29 modules: a slave control unit 40b, a master control 30 unit 40a, a storage opcode translator 40c and an I/O 31 control global reset control 40d~ 32 The Slave Control Unit 40b provides control when the 34 IOIC is a bus slave. This module ~enerates the 35 ready (RDY) bus tag in response to receiving a 36 Master Select Tag (MSEL) from an I/O Bus Unit (IOBU) 37 on the SPD Bus. 38 The Master Control Unit 40a provides control wheni 40 the IOIC is a bus master. It sends the xequest bus 41 (REQB) signal to the Arbitration Unit (the BCU 50j 42 as if it were an IOBU and thus receives the 43 , .
..

arbitration lines Bus Grant (BUSG) and Acknowledge 3 Bus (ACKB). When it gains control of the SPD Bus, 4 it drives the Master Select (~5SEL) and Master 5 Steering (MST) tag lines and expects to receive the 6 Ready (RDY) tag. To the bus arbiter logic, the 7 master controller 40a looks like any other I/O bus 8 unit (IOBU). In perfoxming its function, the Master g Control Unit 40a uses the Selector Buffer 20e of 10 figure 3, and message buffer 1 (MsRl)/message buffer 11 2 (MBR2) associated with message buffers 20b12 illustrated in figures 3 and 19. 13 The Storage Opcode Translator unit 40c contains both 15 a hardwired opcode translation unit and a control 16 unit for holding the operands and addresses in the 17 Address Registers in the data flow logic. This unit 18 is necessary because the storaye information format 19 on the SPD Bus is incompatible with the memory 20 opcode format in the CPU. 21 The global reset control 40d brings the IOIC back to 23 an initial ready state after performing an operation 24 or in the event of a bus timeout. 25 . .
As illustrated in figure 12, both the Slave control 27 unit 40b and the ~aster control unit 40a have 28 communication lines which connect to the Adapter Bus 29 Control Logic 30 and the data flow Registers & 30 Buffers 20 of figure 2. They both share a need for 31 the origin/destination (O/D) Bus 10t3 and the 32 command/status (C/S) Bus 10t2 as well. The Storage 33 Opcode Translator unit 40c is a hardware 'assist' 34 for the Slave Control Unit 40b since it is during a 35 slave operation that the opcode translation is 36 required. Therefore control signals exist between 37 these two units when doing a storage operation. 38 Referring to figure 13, another sketch of the IOIC 40 10j-lm, BCU 50, and I/O bus units (IOBU) 10p-10s is 41 illustrated~ 42 7~

In figure 13, it is important to realize that, to 3 the BCU 50 (the arbiter ~or deciding access to the spd bus 10t-10w), the IOIC is viewed as an I/O Bus 5 Unit ~IOBU), the IOIC arbitrating for the SPD Bus 6 10t-10w like any other IOBU, even though, 7 physically, the Bus Arbiter (BCU) is a part of the 8 IOIC. 9 ~he Adapter Bus Control logic 30 tells the Master 11 Control unit 40a of the Spd Bus Control Logic 40 12 that a Processor Bus Operation (PsO) has been sent 13 to the IOIC. As shown in figure 12, the Master 14 Control Unit 40a sets the IOIC's "request SPD Bus" 15 line ON via the "REQB" signal. When this line is 16 set, the IOIC arbitrates for use of the SPD Bus like 17 any other IOBU. 18 Referring to figure 14, a further construction of 20 the master control unit 40a, of figure 12, is 21 illustrated. 2~2 The master control unit 40a comprises the command 24 register 20i of figure 3; the command register 20i 25 is connected to the O/D bus 10t3 and the C/S bus 26 10t2, and i9 further connected to a control index. 27 table 40a2 with decoder 40a2(1). The control index 28 table 40a2 is connected to direct select operation 29 control logic 40a3, unit write operation control 30 logic 40a4, and unit read operation control logic 31 40a5. The operation control logic 40a3, 40a4, and 32 40a5 are each connected to a status logging control 33 40a6, a tag control logic 40a7, and a request for 34 bus capture and poll control logic 40a8. 35 In figure 14, when the COMMAND REG 20i is loaded, 37 the Control Index Table 40a2, in response thereto, 38 selects either the direct selection operation 40a3, 39 the unit write operation 40a4, or the unit read i 40 operation 40a4, representative of the type of , 41 operation to be performed, in accordance with the . 42 contents of the COMMAND REG 20i. The direct 43 , ..

selection operation 40a3 logic (DIRSEL), unit write 3 operation 40a4 logic (UNIT WRITE), and unit read 4 operation 40aS logic (UNIT READ) each perform a 5 specific type of operation, described in connection 6 with a functional description of the present 7 invention set forth below. This logic also include 8 status indicators which are connected to the STATUS 9 LOGGING CONTROL bloc~ ~Oa6 as well as lines to 10 enable the TAG CONTROL LOGIC 40a7. The tag control 11 logic 40a7 generates the master select (MSEL), 12 master steering (MST), and receives the ready (RDY) 13 signals. The Request for Bus Capture and Poll 14 Control logic 40a8 generates the request bus "REQB" 15 signal, which requests access to the SPD bus16 lOt-lOw, and receives, in response thereto, the 17 acknowledge bus "ACKB" signal, which acknowledges 18 receipt of the REQB signal, and the bus grant "BUSG" 19 signal, which grants to the master control unit 40a 20 access to the SPD bus lOt-lOw. 21 Referring to figure 15, a bit layout of the command 23 register 20i of figures 3 and 14 is illustrated. 24 In figure 15, the low order byte of the command 26 register 20i provides the IOIC with the SPD command 27 bus information while the high order byte furnishes 28 the priority level of the IOIC request bus and the 29 O/D bus information. Certain bits of the 30 Destination Select register 20h of figures 3 and 4 31 are transmitted to Command register 20i. In figure 32 15, the numbers 5, 6, 7, 11, 12, 13, 14, 15, 16, 17, 33 27, 28, 29, 30, 31 represent the bits of the34 Destination Select register 20h which are 35 transmitted to the Command register 20i. "PB" is a 36 parity bit, and "SPR" is a spare. 37 Referring to figure 16, a detailed construction of 39 the slave control unit 40b of figure 12 is ;40 illustrated. 41 ~ t~ ~
In figure 16, the slave control unit 40b comprises a 3 control index table 40bl including a decoder 4 40bl(1), connected to the origin destination (O/D) 5 bus lOt3 and to the command status (C/S) bus lOt2, 6 on one end, and to a storage operation logic 4Ob2, a 7 unit write operation logic 40b3, and a unit read 8 operation logic 4Ob4 on the other end. The storage 9 operation logic 40b2 communicates with the opcode lO
translator 40c o~ figure 12. The storage operation 11 logic 4Ob2, unit write operation logic 40b3, and 12 unit read operation logic 4Ob4 are connected to a 13 tag control logic 4Ob5 and to an error & logging 14 control logic 40b6. 15 The tag control logic 40b5 of the slave control unit 17 40b generates RDY and receives MSEL. To maintain 18 the highest data rate possible on the SPD I/O Bus, 19 the logic implements completely asynchronous20 tag-line handshaking. This is perhaps the single 21 distinguishing feature of this particular design. ~2 The attendant problems of 23 asynchronous-to-synchronous interfacing are isolated 24 at the adapter bus interface which allows the SPD 25 Bus Control logic to be asynchronous in its 26 operation. There are two types of SPD Bus 27 operations that the Slave Controller must handle. 28 They are: 29 Unit Operations -- same mode of operation as the 31 unit operations with IOIC as the master, but 32 initiated by an IOBU with IOIC as the slave. 33 Storage Trans~er -- The IOIC is always the slave 35 unit or recipient o~ a storage trans~er request~ 36 The IOIC will read or write from 1 up to 32 bytes 37 o~ information in one SPD bus operation. 38 In figure 16/ the CONTROL INDEX TABLE 4Obl decodes 40 commands from the command status (C/S) Bus lOt2, via 41 decoder 40bl(1), and enables the proper control 42 required to perform the command. There are three 43 such controls: storage oper~tlon ~Ob2, unit write 3 operation 9Ob3, and unit read operation 4Ob4. Each 4 of these controls are described in more detail in 5 the following paragraphs: 6 Unit Operations - all unit operations are three 8 cycles in duration, i.e., three occurrence of 9 tag-line handshaking per operation. Control 10 signals, required to set status bits in their 11 related registers in the Data Flow logic, are sent 12 via the Internal Bus (which receives the Destination 13 Select register when not driving status 14 information). Several of the unit operations are 15 hardware interpreted commands. Upon receiving them, 16 the IOIC sets a status bit which triggers an17 interrupt to the CPU indicating that the IOIC 18 received one of these commands. However, it does 19 not involve any other hardware facility or control 20 sequencing other than generating the tag-line21 handshaking. These commands are D4 through D7. 2~2 Message acceptance commands cover SPD Command Bus 23 opcodes C0 through CF. They are handled differently 24 from other unit write commands due to the manner by 25 wh.ich the machine implements message buffer areas in 26 main memory. The operation is made to look similar 27 to a Storage Write of 16 bytes in length. However, 28 instead of sending the storage opcode for a write 29 16, the ~OIC sends '0A' indicating to the storage 30 control that this is a write message command from 31 the SPD Bus and must be processed according to the 32 message buffer areas. There are also specific 33 control lines within the IOIC to handle this type of 34 operation. 35 9torage Operations - storage transfers require 37 several operations to occur simultaneously within 38 the IOIC. Consequently, there are a myriad of 39 control lines necessary to properly sequence the ll 40 entire operation. In addition, not all the 41 necessary data lines can be resident on one chip due 42 to restrictions of the chip driver technology, thus 43 ~r~75~

further complicating ~he design. The operation can 3 he parti~ioned into three separate parts. They are: 4 Data Flow; S~orage Opcode Generation; and Access 5 with Main Memory. The first two operations take 6 place in parallel in the case of a write command to 7 main memory. The third part is implemented by the 8 Adapter hus Control logic of figure 10. 9 A functional description of the Slave Control Unit 11 40b will be set forth in the following paragraph 12 with reference to figure 16 of the drawings. 13 The IOIC registers and buffers 20, shown in figure 15 3, receives the SPD address/data bus 10tl. The 16 registers and buffers 20 is four bytes wide and17 eight registers deep for a total of 32 bytes of18 data. Since each register is one word in length, 19 the buffer address bits are taken from bits 27-29 of 20 the SPD A/D bus 10tl. During the select cycle, the 21 low order byte of the address is transferred from ~2 the registers and buffers 20 to the Slave Control 23 Unit 40b. The Storage Operation control 40b2 of the 24 Slave Control Unit 40b clocks in the address, 25 determines the starting buffer address, and, in the 26 case of a write, provides control signals and clocks 27 for the purpose of loading data from the SPD A/D bus 28 10tl into the buffer 20. When the proper number of 29 data cycles have been clocked into the buffer 20, 30 the Storage Operation control 40b2 provides signals 31 indicating that the buffer 20 has been loaded by 32 activating a control signal DATA IN END. In the ~ 33 case of a storage read command, the Storage 34 Operation control 40b2 waits for a signal from the 35 Adapter Bus Control logic 30. Upon receiving this 36 signal (ACTIVATE READY), it then begins clocking out 37 the data buffer 20a of figure 3 beginning at the 38 starting address until it detects that the proper 39 number of data cycles have been clocked out. i 40 Referring to figure 16a, a description of the 42 addressing scheme associated with the Data BuEfer 43 ~.

EN986033 - 33 _ 7~
20a of figure 3 is set forth in the following 3 paragraph with reference to ~igure 16a. 4 In figure 16a, the addressing for the data huffer 6 20a is taken directly from the starting address 7 provided from the requesting Iosu via the A/D bus 8 10tl. Since i~ is word addressed, the bits 9 correspond to address bits 27-29 of a buffer word 10 received in registers and buffers 20 via the A/D bus 11 10tl. It can be seen from this implementation that 12 starting addresses must start from no less than a 13 32-byte boundary (i.e., 00000 in the low order five 14 address bits) and end at the next 32-byte boundary 15 llllll in the low order address bits) within one SPD 16 bus operation. 17 Referring to figure 17, a~detailed construction of 19 the storage opcode translator unit 40c of figure 12 20 is illustrated. ~ 21 In figure 17, the storage opcode translator unit 40c 23 comprises a hardwired control unit 40cl connected to 24 a hardware assist storage opcode translator 40c2. 25 The translator 40c2 receives an address (byte 3) 26 40c3, a byte count 40c4, generates a new address 27 (byte 3) 40c5 and a new byte count 40c6. The 28 translator also generates a storage opcode 40c7. 29 The address (byte 3) 40c3 receives a starting 30 address 40c8. 31 With regard to the storage opcode translator 40c, 33 the IOIC must generate the proper opcode(s) and 34 ~ormat the data into packets acceptable for main 35 memory. However, for one storage operation on the 36 SPD ~us, there can be up to four separate memory 37 transEer operations generated. For this reason, the 38 opcode stack of the ~ddress Register is four39 instructions deep. When the IOIC receives a storage 40 write command, the opcode translator 40c is loaded 41 with the starting address and the byte count. From 42 this information the opcode translator 40c creates 43 EN986033 _ 34 _ 3.;2~7~
the opcode(s), loads them into the opcode stack and 3 signals to the Adapter sus Con~rol Logic 30 that it 4 has completed generating the opcode(s) by activating 5 OPCODE IN END. In contrast, a storage read command 6 causes only one opcode to be generated, regardless 7 of the command or the byte count. The opcode 8 translator 40c takes the list of memory read opcodes 9 and does a 'best fit' for the command and byte count 10 givenO After receiving the data from memory/ the 11 IOIC clocks out only the buffers needed. If the 12 operation is a storage write, the Adapter Bus 13 Control Logic begins access to main memory after 14 seeing both OPCODE IN END and DATA IN END active. 15 For a storage read, only OPCODE IN END is required 16 to be activated to begin the access. A high-level 17 view of the logic to implement the storage opcode 18 translator 40c is illustrated in figure 17. In 19 figure 17, the Starting Address register 40c8 is 20 loaded with information during the select cycle of 21 an SPD bus operation by the Storage Operation ~2 control 40b2 of figure 16. It is merely a temporary 23 holding register used by the translation unit 40c. 24 As soon as the translator unit 40c is activated, the 25 information is clocked into an input register, 26 Address (byte 3) register 40c3. The byte count 27 register 40c4 is loaded with information from the 28 SPD C/S bus duriny the select cycle as well. It is 29 updated with new data ever~ time a new opcode is to 30 be generated~ The new data represents the remaining 31 byte count for the storage transfer being serviced. 32 In a similar manner, the address ~byte 3) register 33 40c3 is updated with new data that represents the 34 next starting address associated with the storage 35 opcode that is generated. The hardware translator 36 unit 40c~ is a custom designed Arithmetic Logic Unit 37 (ALU). Together with the hardwired control unit 38 40cl, output registers New AdAress (byte 3) 40c5 and 39 New ~yte Count 40c6, input registers Address (byte 40 3) 40c3 and B~te Count 40c4, and the resultant 41 Storage Opcode 40c7, the entire unit functions as a 42 micro-instructiOn translator and generator. A43 functional description of the opcode translator unit 3 40c will be described in the paragraphs to follow 4 with reference to figures 17 and 17a. 5 Referring to figure 17a, a more detailed layout of 7 the address registers 20d of figure 3 is 8 illustrated. 9 In figure 17a, there are four (4) addresses stored 11 in address registers 20d, namely, a starting address 12 and three ~3) updated addresses. Four opcodes are 13 also stored in the address registers 20d. For ~4 example, in figuxe 17a, the four opcodes are stored 15 in a first opcode section OPl, a second opcode 16 section OP2, a third opcode section OP3, and a- 17 fourth opcode section OP4 o~ the address registers 18 20d of figures 3 and 17a. Similarly, the four 19 addresses are stored in a first address section Adl, 20 a second address section Ad2, a third address 21 section Ad3, and a fourth address section Ad4 of the 32 address register of figure 17a. The address23 registers 20d store four addresses for the following 29 reasons. Due to the type of memory used, associated 25 with common storaye facility 10d, and its unique 26 storage instruction format, for any SPD storage 27 operation, there can be up to four memory 28 instructions generated. Thus, four separate29 operations to storage facility 10d can be required 30 to complete just one SPD operation. Thus, four 31 addresses, stored in address registers 20d, are 32 required. Since storage transfers will always be 33 within one 32-byte address boundary, the address 34 changes only in the low order byte. 35 A functional description of the opcode translator 37 unit 40c will be set forth in the following38 paragraph with reference to figures 17 and 17a. 39 As the control unit 40cl clocks out the initial 41 storage opcode, it is initially stored in storage 42 opcode 40c7 and, then, subsequently stored in the 43 17~

first opcode OPl section of the address register 20d 3 of the registers and bu~ers section 20 of figure 4 17a via slave control unit 40b. The control unit 5 40cl determines if the output register New syte 6 Count 40c6 contains a zero count result. If not, 7 the output registers 40c5 and 40c6 of figure 17 are 8 transferred back to their corresponding input 9 registers 40c3 and 40c4. ~ new address and a new 10 byte count are produced in the hardware assist 11 storage opcode translator 40c2 in response to 12 control signals from the hardwired control unit 40cl 13 from the address and byte count transferred back to 14 the input registers 40c3 and 40c4. The new address 15 is restored in new address register 40c5 and the new 16 byte count is restored in new byte count register 17 40c6. A new storage opcode is also produced, the 18 new storage opcode being stored in storage opcode 19 register 40c7. The new address is subsequently 20 stored in second address section Ad2 of figure 17a, 21 the new storage opcode being subsequently stored in ~2 second opcode section OP2 of address register 20d, 23 in registers and buffers 20, of figure 17a via slave 24 control unit 40b~ The control unit 40cl then25 determines if the new byte count is zero. If not, 26 the new address and new byte count in registers 40c5 27 and 40c6 are again transferred back to input28 registers 40c3 and 40c4, and a further new address 29 and a further new byte count is produced in the 30 hardware assist storage opcode translator 40c2 in 31 response to control signals from the hardwired 32 control unit 40cl. The further new address and the 33 further new byte count are restored in output 34 registers 40cS and 40c6 of figure 17. A further new 35 storage opcode is also produced and stored in 36 storage opcode register 40c7 of figure 17. The 37 further new address is stored in third address 38 section Ad3 of address register 20d of figure 17a, 39 the further new storage opcode being stored in thlrd 40 opcode section OP3 of address register 20d of figure 41 17a via the slave control unit 40b. The control 42 unit 40cl re-exa~ines the further new byte count to 43 7~
determine if it is zero. If the further new byte 3 count is zero, the control unit 40cl then indicates 9 completion of the translation operation to the 5 Storage Operation Unit 40b2 of figure 16 which then 6 activates OPCODE IN END. 7 Referring to figure 18, a detailed construction of 9 the Bus Control Unit ~scu) 50 of figures 2 and 11 is 10 illustrated. 11 The BCU 50 comprises a scan adjustable bus-op timer 13 50a connected to an arbitration control unit 50b, 14 the arbitration control unit 50b being connected to 15 hardwired timer-length counters for architected 16 timers 50c. 17 The Bus Control Unit logic 50 contains the control 19 logic for generating the Bus Grant (BUSG) and 20 Acknowledge Bus (ACKB) control signals. It also 21 contains the Bus Idle Timer which detects the lack ~2 of a bus unit response with BUSG and ACKB present. 23 Although the setting of status bits is part of the 24 Bus Timeout logic, the actual timer resides in the 25 arbiter section of logic. The arbitration logic 50h 26 is more or less 'stand-alone' logic. That is, the 27 logic is primarily driven by the architected SPD I/O 28 Bus lines. However, ICCR Bit 17 is an internal 29 control line that allows the CPU (thru the SET ICCR 30 command) to exercise some control over the bus 31 arbitration. With this bit set, arbitration is 32 disabled for all bus requests coming in from the SPD 33 Bus. The IOIC will still be allowed to arbltrate 34 for the bus. In figure 18, the Bus Control Unit 35 (BCU) 50 is comprised of three modules, the first 36 two being an Arbitration Control Unit 50b, and a Bus 37 Operation Timer 50a which possesses a software 38 programmable control circuit which allows the timer 39 to be set to any of four different time-lengths. ' ~o The hardwired timer length counters for architected ~1 timers 50c contains two more timers that are 42 hardwired to be of a fixed length in accordance with 43 .

~ EN986033 ~ 38 ~Z~9~
their respective operations. The ArbitratiOn 3 Control Unit 50b is composed of sooe combinational logic circuits and several latches. The latches are 5 set according to the state of the MSEL, MST and REQB 6 lines. The unit is basically a priority decision 7 circuit that sets or resets the BUSG and ACKB lines 8 with respect to the state of the aforementioned 9 three tag lines at any given moment. 10 Referring to figure l9, a more detailed schematic of 12 the IOIC 10j-lOm is illustrated, including its 13 interface with the adapter bus 10n and its interface 14 with the SPD bus 10t-10w. Figure 19 illustrates the 15 IOIC which includes the registers and buffers 16 section 20, the BCU arbiter 50, and the IOIC adapter 17 and spd control logic 30 and 40. The spd bus18 10t-10w each include the spd address data (A/D) bus 19 10tl, the command status (C/S) bus 10t2, the origin 20 destination (O/D) bus 10t3, and the control line 21 group 10t4, which further includes the following 32 lines: REQUEST BUS, ACKNOWLEDGE BUS, BUS GRANT, 23 MONITOR CLOCK, BUS CLEAR, BOARD SELECT, MASTER 24 STEERING (MST), SLAVE READY, MASTER SELECT ~MSEL) 25 and POWER ON RESET. The adapter bus 10n is shown in 26 figure 19 as including the adapter address data 27 (A/D) bus 10nl, the key status (K/S) bus 10n2, the 28 control line group 10n3, which further includes the 29 following lines: COMMAND TIME, DATA VALID, 30 ACKNOWLEDGE, IOIC BUSY, BUS CHECK, IOIC REQ, IOIC 31 CMD REQ, and IOIC GRANT. 32 tii) The Storage Controller including Arbiter logic 35 10i, IOIU logic 10e and Storage Control logic 36 10~ 37 As illustrated in figure 1, the adapter bus 10n is 39 interconnected between one end of a storage ' 40 controller and each of four IOICs 10j-lOm. The 41 adapter bus 10n includes the adaptex address data 42 (A/D) bus 10nl, the key status (K/S) bus 10n2, and 43 EN986033 _ 39 _ - ~.Z~7~

the control line group lOn3. The storage controller includes arbiter logic lOi, input output interface unit (IOIU) lOe, and storage control logic lOg. A storage interface, includillg the storage bus lOf and the control bus lOh, interconnects the other end of -the storage controller to the common s-torage facilit~ lOd.

Re~erring to figure 20, a detailed construc-tion o~ the Storage Controller of figure ]., including the arbiter logic lOi, the IOIU logic lOe and the s-torage control logic lOg, is illustrated.

In figure 20, the control bus lOh of the storage interface inclu~es the following lines: CEL, EEL, PTY, STG DV, and STG CTLS. The control line group lOn3 of the aclapter bus lOn includes the following lines: OP END, I/O
REQ, I/O GRANT, adapter command time (ADPT CMD TIME), adapter data valid (ADPT DATA VALID), IOIC BUSY, IOIC
ACK, ADPT BUS CHECK, ancd EIS BIT 4.

The arbiter logic lOi is described in U.S. Patent No.

4,760,515, issued July 26, 1988, entitlecl "an arbitration apparatus for determining priority of access to a shared bus Otl a rotating priority basis".

The storage control ].ocJic l()g comprises a data in regi.ster 60a CO:tllleC tecl to storage bus lOf; a data Ollt rec.rister 60b is connecte(1 to an output of the data in reg:i.ster 60a and to the storaye bus lOE; an A-register 60c i.s connected, at its input, to the storage bus lOf and, at :il;~ output, to the adapter A/D bus lOnl, the output of the A--register 60c also being connected to a DTM recJister 600; a B-register 60cl is connected, at its input, to an inpuk of the A-regi~ter 60c and to the storage bus 10, the B-register 60d being also connected, at i.ts input, g~4 to the adapter A/D bus 10nl and to a further input 3 of the data in register 60a and to an input to a command address (cmd/addr~ register 60i; the 5 B-register 60d is connected, at its output, to the 6 adapter A/D bus 10nl and to the storage bus 10f via 7 the output of the data out register 60b and the 8 output of the data in registex 60a; the cmd/addr 9 register 60i is further connected, at its input, to 10 storage bus 10f, to an input of the data in register 11 60a, to an input of the A-register 60c and to an 12 input of the B-register 60d; a further input of the 13 cmd/addr register 60i is connected to an input of 14 the Dl'M register 60O, to the adapter A/D bus 10nl, 15 to a 370 offset register 60j, and to the MBOR0 16 register/MBSW0 register 60p of the IOIU logic 10e; 17 the cmd/addr register 60i output is connected to an 18 input of adder 60k, to an address input of a key 19 stack array 60h, and to the storage bus 10f via the 20 output of data out register 60b and the output of 21 the data in register 60a; the 370 offset register 2~2 60j output is connected to a further input of adder 23 60k; the adder 60k output is connected to the 24 address input of key stack array 60h and to.the 25 storage bus 10f via the output of data out reyister 26 60b and data in register 60a; an output of the key 27 stack array 6Oh is connected to an input of a key 28 data register 60g, the key data register 60g output 29 being connected to an input of an update logic 601 30 and an input of error detection logic 60m; an output 31 of update logic 601 is connected to an input o~ key 32 stack array 60h; a further input of error detection 33 logic 60m is connected to control bus 10h; an I/O 34 key register 60f has an input connected to the 35 adapter K/S bus 10n2, a key output connected to an 36 input of the error detection logic 60m, and a no-off 37 output connected to a zero input of the adder 60k; 38 an output of the DTM register 60O is connected to 39 the address input of the key stack array 60h and to 40 the storage bus 10f via the output of the cmd/addr 41 register 60i, the output of the data out register 42 60b and the output of the data in register 60a; an 43 EN9~6033 - 41 -~¢3~

I~O status register 60e is connected, at its inputr 3 to an output of the error detection logic 60m and is 4 connected, at its output, to the adapter K/S bus 5 10n2; an op end sum register 60w is connected at its 6 input to an op end line of the control line group 7 lOn3 and is connected at its output to the CPU EXT 8 INTERRUPTS line and to the storage bus 10f via the 9 outputs of the followingo B-register 60d, DTM 10 register 60O, cmd/addr register 60i, adder 60k, data 11 out register 60b and data in register 60a. 12 The input output interface unit (IOIU3 logic 10e 14 comprises a message buffex origination register 0 15 (MBOR0 registerJ/ MBSWO register 60p connected, 16 respectively, at its input to an input of the 370 17 offset register 60j, to an~input of cmd~addr 18 register 60i and DTM register 60O of the storage 19 control logic 10g, to an input of message buffer 20 orignation register 1 (MBORl)/ MBSW1 register 60q, 21 and to an input of IOIUCR register 60r; an output of ~2 MBOR0 register 60p is connected to an output of 23 MBOR1 register 60q and to an input of compare logic 24 60y; an output of MBSW0 register 60p is connected to 25 the output of MBSWl register 60q, to a further input 26 of error detection logic 60m of the storage control 27 logic 10g, and to the CPU EXT INTERRUPTS line; an 28 output of the IOIUCR register 60r is connected to a 29 further input of compare logic 60y, an output of 30 compare lo~ic being connected to some input 31 terminals of MIS register 60t; an output of MIS 32 register 60t is connected to an input of AND gate 33 60u, a further input of AND gate 60u being connecteA 34 to another output of IOIUCR register 60r; an output 35 of AND gate 60u is connected to the CPU EXT 36 INTERRUPTS line; an input of an IUSW register 60~ is 37 connected outside the IOIU logic 10e to an output of 38 a control logic 60n, a further output of control , 39 logic 60n being connected to the STG CTLS line ofll 40 control bus 10h, and the STG DV line of the control 41 bus 10h; the control logic 60n is also connected to 42 an output terminal of the error detection logic 60m; 43 . . ~

.

g~
the control logic 60n is also connected to the 3 following lines of the control line group lOn3: 4 ADPT CMD TIME, ADPT DATA VALID, IOIC BUSY, IOIC ACK, 5 ADPT sUS CHECX; the control logic 60n is further 6 connected, outside the IOIU logic lOe, to the 7 arbiter logic lOi, the arbiter logic lOi being 8 connected to the following additional lines of the g control line group lOn3: OP END, I/O REQ, I/O GRANT; lO
the IUSW register, inside the IOIU logic lOe, is ll connected at its output to the following remaining 12 line of the control line group lOn3: EIS BIT 4. 13 A description of the functional operation of the 15 storage controller, including the IOIU lOe and the 16 storage control logic lOg, will set forth in section 17 (v) of this specification and in the following 18 paragraphs of section (iii) of this specification 19 entitled "The Adapter bus lOn": (1) Processor Bus 20 Operation (PBO) message operations - copy operations 21 and load operations, (2) memory operations - read ,~2 from storage, write to storage, and read modify 23 write to storage, and (3) message acceptance24 operations. 25 (iii) The Adapter Bus lOn 28 In figure 19, an IOIC lOj-lOm is an interface30 between the asynchronous SPD BUS lOt-lOw and the 31 synchronous ADAPTER BUS lOn. The Adapter Bus lOn is 32 the synchronous interface between the I/O Interface 33 Unit (IOIU) lOe and four IOIC's lOj-lOm. There may 34 be up to sixteen IOICs used in this system. The 35 adapter bus lOn comprises an a~apter address data 36 (A/D) bus lOnl, a key status (K/S) bus lOn2, and a 37 control line group lOn3. 38 The Adapter Address/Data (A/D) Bus lOnl is a 36 bit, 40 tri-state bi-directional bus, consisting of 4 bytes 41 with parity. 42 The Key/Status 1K/S) Bus lOn2 is a 6 bit, tri-state 3 bi-directional bus, consisting of 5 data bits with 4 parity. S

As illustrated in figure 19, the control line group 7 lOn3 of each IOIC includes 6 lines used to control 8 the direction of data flow, handshaking and error 9 information. They are: 10 Adapter Command Time 12 Adapter Data Valid 13 Adapter Bus Check 14 IOIC ~cknowledge 15 IOIC Busy 16 External Interrupt Summary Bit 4 (EIS 4) 17 The control line group lOn3 of each IOIC also 19 includes: 20 two request lines, namely, IOIC REQ and IOIC CMD 22 REQ; 23 a grant line, namely, IOIC GRANT; and 24 an operation end line, termed OP END EIS 5. 25 Referring once again to figure 19, the adapter 27 address data (A/D) bus lOnl is a physical part o~ 28 the adapter bus lOn. The following paragraphs 29 describe the individual bytes which comprise the 30 adapter A/D bus lOnl: 31 Adapter Bus Byte O is active from TO to TO and 35 contains the 'Storage Command' the cycle after an 36 IOIC grant has been given. It contains data 37 ; a~ter a storage write command for up to eight 38 cycles. It contains the 'PBO Adapter Command' at 39 ADAPTER COMMAND TIME when receiving a PBO command 40 from the IOIU. It contains data when ADAPTER 41 DATA VALID is active for a storage read. The 42 `` ~2~ 4 IOIC will clock ~he data from the Bus using the 3 T2 Clock. 4 ADAPTER A/D BUS BYTE l 6 Adapter Bus Byte l is active from T0 to T0 and 8 contains the Storage Address the cycle after an 9 IOIC GRANT has been given. It contains data 10 after a storage write command for up to eight 11 cycles. It contains the 'I/O Command' at ADAPTER 12 COMMAND TIME when receiving a PBO command from 13 the IOIU. It contains data when ADAPTER DATA 14 VALID is active for a storage read. The IOIC lS
will clock the data from the Bus using the T2 16 Clock. 17 Adapter Bus Byte 2 is active from T0 to T0 and 21 contains the Storage Address the cycls after an 22 IOIC GRANT has been given. It contains data 23 after a storage write command for up to eight 24 cycles. It contains the 'PRiority level and IOIC 25 address' at ADAPTER COMMAND TIME when receiving a 26 PBO command from the IOIU. It contains data when 27 ADAPTER DATA VALID is active for a storage read. 28 The IOIC will clock the data from the Bus using 29 the T2 Clock. 30 Adapter Bus Byte 3 is active ~rom T0 to T0 and 34 contains the Storage Address the cycle after an 35 IOIC GRANT has been given. It contains data 36 after a storage write command for up to eight 37 cycles. It contains the 'Destination address' at 38 ADAPTER COMMAND TIME when receiving a PBO command 39 ; from the IOIU. It contains data when ADAPTER DATA 40 VALID is active for a storage read. The IOIC 41 will clock the data from the Bus using the T2 42 Clock. 4 EN986033 _ 45 _ Referring to figure 19, the adapter bus lOn 3 comprises the key status (K/S) bus lOn20 4 Referring to figure 22, the key status bus bit 6 layout is illustrated. 7 The Key Status (K/S) Bus lOn2 is active from TO to 9 TO following the receipt of an IOIC GRANT. It will 10 contain the S/370 key on bits 0-3 if in 370 11 emulation or it must contain zero's if in Native 12 mode. Bit 4 if active, will cause the storage 13 address received from the Adapter Bus lOnl and 14 clocked into the Command/Address register 60i to be 1~
added to a value of zero by the adder 6Ok. If bit 4 16 is inactive, it will cause the address in the 17 CMD/ADDR Register 60i to be added to the value in 18 the S/370 Offset Register 60j. The resultant19 address from the adder 60k is the address presented 20 on the Storage Bus lOf. In Native mode bit 4 has no 21 effect since the offset will be equal to zero. ~2 During Message Acceptance operations, the Key/Status 23 bus bits 0-3 contain the message priority value. ~4 Except for the time when the IOIC drives the bus, 2~
the IOIU drives the bus and presents Status. The 26 Status bits 0-1 are sensed once for Command status 27 on the second cycle after the IOIC GRANT, and then 2~
during each ADAPTER DATA VALID cycle for a Read 29 opexation, or on the fourth cycle after the last 30 write data cycle for a Write operation. 31 In figure 22, a key bit layout, associated with the 33 key bus portion of the key status bus lOn2, and a 34 status bit layout, associated with the status bus 35 portion of the key status bus lOn2, is presented. 36 The status bus bits have a specific meaning in terms 37 of the status of commands and the status of data on 38 the bus. Figure 22 sets forth the status of39 commands (COMMAND STATUS) and the status of data 40 (DATA STATUS) for the first two bits of the status 41 bus, the remaining bits also having a specific 42 , , ' .

- ~z~

meaning as outlined in figure 22 and in the 3 following parayraphs: 4 COMMAND STATUS BIT MEANING: 7 Bits 0-1: equal to '00' means that everything is 9 good and the storage operation is proceeding; 10 equal to '01' means the address given is invalid 11 (Invalid Address); equal to '10' means the Key 12 given is not correct for the address given 13 (Protection Violation); equal to 'll' means that 14 the command given is not valid (Unit Check). 15 Bit 2 indicates that a parity check has occurred 17 on the A/D Bus with the Command and Address or on 18 the data cycle following the command. It could 19 also mean that there was a parity check on the 20 K/S Bus during the command cycle. (Unit Check) 21 Bit 3 indicates that the IOIU clocks have stopped 23 and that the operation in progress will be 24 unpredictable and should be repeated. (Not 25 Ready) 26 Bit 4 indicates that the Message Buffer is Not 28 Available and is a result of the "OR" of MBSW0 29 register 60p (of figure 20) bits 28,29,or 31, or 30 MBSW1 register 60q bits 28,29,or 31. If active, 31 it signals the storage operation will not be 32 done. This bit is only significant for a Message 33 Acceptance operation. (Buffer Not Available) 34 Bit 5 will maintain odd parity for the K/S Bus. 36 DATA STATUS BIT MEANING: 38 The I/O Status Register 60e contains the40 following bit meaning and is gated to the 41 Key/Status Bus 10n2 by the Storage Controller at 42 "

EN986033 _ 47 _ , .

all times except the cycle following an IOIC 3 GRANT when the bus is used for Key information. 4 Bits 0-1: equal to '00' means that the data being 6 received is good; equal to '01' means the data 7 being received is bad and not reliable (Unit 8 Check-Storage Error); equal to '10' or '11' are 9 reserved and should be ignored. 10 Bit 2 indicates that a parity check has occurred 12 on the A/D Bus with data from the IOIC buffers. 13 (Unit Check) 14 Bit 3 indicates that the IOIU clocks have stopped 16 and that the operation in progress will be 17 unpredictable and should be repeated. (Unit 18 Check) 19 Bit 4 has no valid meaning at thi~ time.21 Bit 5 will maintain odd parity for the K/S Bus. 23 Referring to figure 19, the adapter bus 10n includes 25 a control line group lOn3. ~ 26 The control line group 10n3 comprises the following 28 signal lines~ 1 29 ADAPTER COMMAND TIME - The Adapter command time 31 signal is active from T0 to T0 and is driven by 32 the IOIU. This signals all IOIC's to sample the 33 Adapter A/D Bus at T2 and determine if the PBO 34 command is for them. If a match of the select 35 field and the IOIC's address occurs, then either 36 an IOIC ACKNOWLEDGE or IOIC BUSY must be given on 37 the second cycle after ADAPTER COMMAND TIME. 38 Absence of a response will cause IUSW Register 39 60v bit 29 to activate which in turn forces the' 40 summary bit 31 active which activates EIS bit 4. 41 :

..
~ EN986033 - 48 -. .
. .

ADAPTER DATA VALID - The Adapter data valid 3 signal is active from T0 to T0 and is driven by the IOIU. This signal indicates that the Adapter 5 A/D Bus bus should be sampled for data and that 6 the Status Bus should be checked to see if the 7 data is good and no error conditions exist. 8 ADAPTER BUS CHECK - The Adapter Bus Check line is 10 an open collector signal which is driven by the 11 IOIC from T0 to T0 on the following cycle after 12 the receipt of bad parity on the Adapter A/D Bus. 13 Parity is checked on the Adapter A/D Bus during 14 ADAPTER COMMAND TIME and the following data 15 cycle. The Adapter Bus Check signal is only valid 16 for PBO's. 17 IOIC ACKNOWLEDGE - The IOIC Acknowledge signal is 19 active from T0 to T0 and is driven by the IOIC on -- 20 the second cycle following the ADAPTER COMMAND 21 TIME cycl~. It signals that the selected IOIC has 22 received the PBO command with no parity check and 23 will do the operation. 24 IOIC BUSY - The IOIC Busy signal is active from 26 T0 to T0 and is driven by ~he IOIC on the second 27 cycle following the ADAPTER COMM~ND TIME cycle. 28 It signals that the selected IOIC has received 29 the PBO command with no parity check but is 30 unable to complete the operation at the present 31 time. 32 EIS BIT 4 (I/O EXCEPTION) - The EIS Bit 4 3~
interrupt signal will siynal exceptional 35 conditions that occur during the e~ecution of SP~ 36 Bus commands. It is the dynamic signal created 37 ~rom the logical OR o~ the IOIC STATUS WORD 38 (ICSW) Status Summary Bit 28 from each of the 39 IOIC's. ICSW Bit 28 is a summary bit indicating 40 the occurrence of an error or other event on the 41 SPD I/O Bus which the IPU needs to handle. EIS 4 42 will remain active until all sources are reset to 43 :

EN986033 _ 49 _ ;

zero by Reset ICSW Under Mask instructions. This 3 signal is also present if the IOIU Status Reg 60v 4 summary bit 31 is active. 5 OPERATION END EIS BIT 5 - The Operation End EIS 7 5 interrupt signals the completion of an 8 abnormally completed operation. It is the 9 dynamic signal created from the logical AND of 10 the MESSAGE ORIGINATION STATUS WORD (MOSW) 11 Operation End Bit 0 and MOSW Status Summar~ Bit 12 2. Each IOIC sends a separate OPERATION END EIS 5 13 signal to the IOIU Operation End Summary Register 14 60w. These 4 bits are "OR"ed and result in the 15 External Interrupt Bit 5 being active. The MOSW 16 bit 2 is a summary bit indicating abnormal status 17 which the IPU will need to har.dle when the 18 operation ends. OPERATION END EIS 5 is on until 19 MOSW Bit 2 is reset to zero by executing a Move 20 MOSW PBO where the OPERATION END bit 0 is equal 21 to one . 22 IOIC REQUEST - The IOIC Request signal is active 24 from T2 to the T2 following the reception of an 25 IOIC GRANT and is driven to the IOIU by each IOIC 26 by a separate line. It signals the IOIU that the 27 IOIC has a normal I/O Request for use of the 28 Adapter Interface to obtain access to Storage. A 29 normal I/O Request is mutually exclusive with the 30 Cycle Steal Request from the same IOIC. 31 IOIC CMD REQUEST - The IOIC Command Request is 33 active from T2 to the T2 Eollowing th reception 34 of IOIC GRANT and is driven to the IOIU by each 35 IOIC by a separate line. It signals the IOIU that 36 the IOIC has a top priority I/O Request for use 37 of the Adapter Interface to obtain access to 38 Storage. It is used only for four or eight byte 39 requests needed for the next CCW. If used for any 40 other purpose, it may result in performance 41 degradation in the other IOIC's. An IOIC CMD 42 EN986033 _ 50 _ $~
Request is mutually exclusive with a normal I/O 3 Request from the same IOIC. 4 IOIC GRANT - The IOIC Grant signal is active from 6 T1 to T1 and is driven by the arbiter 10i of 7 figure 1 to each IOIC on a separate line. This 8 signal tells the IOIC that its request has been 9 granted and to drive its Command, Address and Xey 10 to the Adapter Interface the next T0 to T0 which 11 is IOIC Command Time. 12 A functional description of the operation of the 14 adaptor bus 10n will be set forth in the following 15 paragraphs with reference, initially, to figure 19 16 of the drawings. 17 There are three main uses for the ADAPT~R BUS l9 interface. 20 1. Processor Bus Operation (PBO) message~2 operations - transfer of Processor Bus23 Operation (PBO) information; 24 2. Memory Operations - transfer of IOIC data to 25 or from Memory; and 26 3. Message Acceptance Operations - transfer of 27 I/O Message information to Memory. ~ 28 Each of these three main uses are fully described in 30 the following numbered paragraphs. 31 1. PBO MESSAGE OPERATIONS: A Processor Bus 33 Operation (PBO) is any operation, based on the 34 execution o~ a particular instruction, originating 35 from the IPU 10a. A list of valid PBO instructions 36 executed by the IPU 10a for the purpose of using 37 IOIC's for operations on the adaptor bus 10n and the 38 SPD bus 10t-10w are illustrated in figure 21. 39 Processor Bus Operations originate in the IPU l~a 1 40 and are relayed to the IOIU lOe via the Data Cache 41 10c on the Storage Bus 10f. At the receipt of a PBO 42 request, the Storage Control logic 10g requests the 43 ~, 7~
Storage Bus 10f, by activating the PBO request line 3 7 of figure 1 and waits for a grant from the arbiter 4 logic 10i. When both the Data Cache 10c and the 5 Storage Control 10g receive t~le PBO grant line from 6 the Arbiter 10i, the Data Cache sends information, 7 which it received from the IPU lOa via the A~bus, on 8 the Storage sus 10f, to the A register 60c of the 9 Storage Control logic 10g of figure 20. During the 10 next cycle, the Data Cache 10c sends information, 11 which it received from the IPU 10a via the D-bus, to 12 the B register 60d of storaye control logic 10g of 13 figure 20. 14 There are two types of PBO operations to the IOIC: 16 A. Copy operations; and 18 B. Load operations. 19 A. Copy operations: 21 Refer to figure 32 for a timing diagram of the Copy 23 PBO operation. 24 During copy operations, data is sent back to the 26 IOIU from the IOIC on a third PBO cycle. There are 27 three cycles during a copy PBO operation: 28 (1) Adapter COMMAND TI~E cycle, 30 (2) DATA VALID cycle, and 31 (3) RETURN DATA cycle. 32 The adapter COMMAND TIME cycle occurs from T0 to T0 34 on the cycle following the IOIC Grant. The contents 35 of the A-Register 60c of the storage controller 10g 36 of figure 20 are gated onto the Adapter Bus 10n to 37 the IOIC durin~ the this cycle. This data 38 represents the destination select (DESTSEL) 39 information clocked into Dest Select Register 20h in ~0 figure 3. 41 7~

The DATA VALID Cycle is the next cycle. During this 3 cycle, the contents of the s--Register 60d are 4 clocked onto the adapter bus lOn to the IOIC for 5 storage in the Selector Buffex 20e. 6 The RETURN DATA cycle is the last cycle of the PBO 8 sequence. In response to the A-register 60c and 9 B-register 60d information, the selected IOIC10 10j-lOm will gate data, corresponding to the ll A-register and B-register information, onto the 12 Adapter Bus 10n to the B-register 60d in the IOIU 13 10e. The data will, in turn, be transferred back to 14 the IPU 10a via the storage bus 10f and the data 15 cache 10c in response to a subsequent successful - 16 request for access to the storage bus using the PBO 17 REQUEST line. The selected IOIC will also send the 18 IOIC ACKNOWLEDGE signal or the IOIC BUSY signal to 19 the IPU. 20 ..
If IOIC ACRNOWLEDGE signal is not received from the 22 IOIC, bit 29 of the IOIU STATUS Word Register 60v 23 will be set, which in turn sets the summary bit 31 24 causing External Interrupt Summary bit 4 to be 25 activated. If IOIC BUSY is received, bit 30 of the 26 IUSW will be set which also sets the summary bit 31 27 causing EIS bit 4 to be activated. 28 B. Load operations: 30 Refer to figure 31 for a timing diagram of the Load 32 PBO operation. 33 Load PBO's follow the same sequence as the Copy PBO 35 operation, with the exception that, during the third 36 cycle, the IOIC ACKNOWLEDGE signal is transmitted 37 back to the IPU, but no data is transferred.38 Figure 21 provides a list of valid PBO commands~ ' 40 2. MEMORY OPERATIONS: Memory Operations on the ~2 Adapter Bus always originate in the IOIC. There are 43 EN986033 ~ 53 _ 3~
three types of memory co~mands that the IOIC sends 3 to the Storage Control 10g of figure 1: Read, Write, and Read Modify Write (RMW). Read takes data 5 from the Common Storage Facility 10d and sends it to 6 the IOIC. ~rite takes data ~rom the IOIC and puts 7 it in the Storage Facility 10d. Read Modify Write 8 takes data from the IOIC and puts it in the Storage 9 Pacility 10d but, first, an 8 byte read operation is 10 performed, followed by a merge of the new data to be 11 written. 12 Refer to figure 21A for the valid memory commands 14 which the IOIC sends to the s~orage control 10g of 15 figure 1. 16 There are three main types of memory commands in 18 figure 21A: READ from STORAGE, WRITE to STORAGE, 19 and READ MODIFY WRITE to STORAGE. Each of the three 20 main types of memory commands are described in 21 further detail in the following paragraphs. ~2 A. READ from STORAGE 24 Refer to figure 27 for a timing diagram of the 26 I/O Read Operation. 27 !
IOIC COMMAND TIME: The Adapter A/D Bus Byte 0 29 contains the Read Command for 1,2,4,6 or 8 30 words of data and is clocked into the CMD/ADDR 31 Register 60i of the Storage Controller 10g of 32 figure 20 from an IOIC. Figure 21A details 33 the valid commands which may be used. The 34 Adapter A/D Bus Bytes 1-3 contain the starting 35 address for the storage read and is clocked 36 into the storage controller 10g from the IOIC. 37 If the I/O Key Register 60f bit 4 is inactive, 38 the address in the CMD/ADDR Register 60i will 39 be added by Adder 60k to the S370 Offset 40 Register 60j value prior to the Storage 41 Command Time. This resultant address is the 42 address presented to the Key Stack Array 6Oh. 43 EN986033 - 54 _ The data read from the Key Stack into the Key 3 Data Register 60g wil~ then be compared to the g Key received in the I/O Key Register 60f. If 5 it satisfies the Key compare operation, the 6 Storage operation proceeds, however, if a 7 Protection Check or an Invalid Address Check 8 occurs the operation is halted and the error 9 status is sent from the Error Detection Logic 10 60m to the I/O Status ~egister 60e where it is 11 driven to the Key/Status Bus 10n2. 12 ADAPTER DATA VALID: After sending the Command 14 and Address to the storage controller 10,g (and 15 ultimately to storage facility 10d), the IOIC 16 waits for the data from storage. The data 17 received on the Storage Bus 10f is clocked 18 into the Data In Register 60a and relayed to 19 the Adapter A/D Bus 10nl on the next cycle. 20 Storage Data Valid signal is also delayed one 21 cycle and becomes ADAPTER DATA VALID. Adapter 2~2 Data Valid will indicate when each word of 23 data transferred is to be loaded into the IOIC 2g Data Buffer. Note: Data cycles may not be 25 consecutive if extended ECC retry is'attempted 26 by the Storage. ' ' 27 "
STATUS TIME: The read status from the I/O 29 Status Register 60e of figure 20 is sent to 30 the IOIC at the same time data is transferred 31 with Adapter Data Valid. 32 B. WRITE to STOR~GE ' 34 Refer to figure 28 for a timing diagram of the , 36 I/O Write Operation. 37 :' IOIC COMMAND TIME: The ~ddress/Data Bus Byte 0 39 contains the Write Command for 2,g,6 or 8 'i 40 words of data. Bytes 1,2 and 3 contain the 41 starting address for the storage write. The 42 Key/StatUs Bus contains the storage protect 43 EN986033 - 55 _ key. The beginning cycle is identical to that 3 of a Read Command. The data immediately 4 follows the Command Address cycle. 5 DATA CYCLES: The cycles which follow 7 immediately after the IOIC Command Time cycle 8 contain the data to be written in Storage. 9 The data is byte aligned and must be in 10 multiples of 8 bytes and must be within the ll appropriate boundaries, i.e., a 32 byte 12 request must start on a 32 byte boundary. The 13 data is loaded into the Data In Register 60a 14 and transferred to the Data Out Register 60b 15 on the following cycle. From here the data is 16 sent out on the Storage Bus 10f. This delay 17 of data by two cycles, allows the Key check 18 operation to take place and the new address 19 generated to be gated to the Storage Bus 10f 20 at STORAGE COMMAND TIME. 21 STATUS TIME: The write status from the IOIU is 23 sent to the IOIC on the fourth cycle after the 24 last data valid cycle. Note: ADAPTER DATA 25 VALID line is not used when doing a write. 26 C. READ MODIFY WRITE to STORAGE " 28 Refer to figure 29 for a timing diagram of the~ 30 I/O RMW Operation. 31 IOIC COMMAND TIME: The Address/Data Bus Byte 0 33 contains the Write Command for 1 to 7 bytes of 34 data. Bytes 1,2 and 3 contain the starting 35 address for the storage write. The Key/Status 36 Bus contains the storage protect key.37 DATA CYCLES: The 2 cycles which follow 39 immediately after the IOIC Command Time cycle 40 contain the data to be written in Storage. 41 The data is byte aligned and must be on an 8 42 byte boundary. The first word transferred '43 will end up in the Data Out Register ~Ob, 3 while the second word trans~erred will end up 4 in the Data In Register 60a. The data is sent 5 out on the Storage Bus twice, once ~uring the 6 Read operation and then during the Write 7 operation. This allows the Data Cache 10c to 8 modify the Cache during the read portion of 9 the Read Modify Write operation if the data is 10 presently in the cache and the data has been 11 modified prior to this access. 12 STATUS TIME: The write status from the IOIU is 14 sent to the IOIC on the fourth cycle after 15 ADAPTER DATA VALID line comes active.16 3. MESSAGE ACCEPTANCE OPERATION: Message 18 Acceptance Operations on the Adapter Bus look just 19 like a Write to Storage. The difference is as 20 follows: the IOIC does not send an address to the 21 IOIU; instead, it puts a message priority value on 22 the key status (K/S) Bus 10n2, which is clocked into 23 I/O Key Register 60f. This priority value is used 24 to select Message Buffer Origination Register 0 60p 25 or Message Buffer Origination Register 1 60q which 26 provides the address to the storage bus at Storage 27 Command Time. 28 A. MESSAGE ACCEPTANCE to STORAGE 30 Refer to figure 30 for a timing diagram of the I/O 32 Message Acceptance Operation. 33 IOIC CO~MAND TIME: The Address/Data Bus Byte 0 35 contains the Command code point of X'OA'. Bytes 36 1,2 and 3 contain good parity. The Key/Status 37 Bus contains the message priority value.38 DATA VALID: The 4 cycles which follow immediately 40 after the IOIC Command Time cycle contain the 41 following information to be written in Storage: 42 2~7~
A/D bus contents during Select Cycle on the 3 SPD bus. 4 A/D bus during the first Data Cycle on the SPD 5 bus. 6 A/D bus during the second Data Cycle on the 7 SPD bus.
Message Acceptance Status Word tMASW). 9 (iv) The SPD I/O Bus 10t-10w 12 In figure 19, the spd I/O bus 10t-10w comprises an 14 address data bus 10tl, a command status bus 10t2, an 15 origin destination bus 10t3, and a control line 16 group 10t4. The control line group 10t4 includes 17 }~QUEST BUS, ACKNOWLEDGE BUS, BUS GRANT, MONITOR 18 CLOCK, BUS CLEA~, BOARD SELECT, to arbiter BCU 50, 19 and MASTER STEERING (MST), SLAVE READY, MASTER 20 SELECT ~MSEL), and POWER ON RESET, to thP 21 adapter/SPD bus control logic 30 and 40. 22 The SPD I/O Bus is the asynchronous interface 24 between the IOIC and the I/O Bus Units (IOBU). It 25 consists of three buses, thirteen control lines and 26 three signal lines for polling. The Address/Data 27 Bus is a 36 bit, tri-state bi-directional bus, 28 consisting of 4 bytes with parity. The 29 Command/Status Bus is a 9 bitl tri-state 30 bi-directional bus, consisting of 1 byte with 31 parity. The Origin/Destination Bus is a 6 bit, 32 tri-state bi-directional bus, consisting of 5 bits 33 plus parity. The control line group is broken down 34 into ~our groups. They are: 35 1. TAG LINES 37 Master Steering 39 Master Select 40 Slave Ready 41 2. DIRECT SELECTION LINES 43 ..

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Card Select 3 Board Select 4 3. ARBITRATION LINES 6 Request Bus 8 Request Priority 0-2 9 Acknowledge Bus 10 Acknowledge Bus Pol In/In' 11 Acknowledge Bus Pol Out 12 Bus Grant 13 4. CONTROL LINES 15 Bus Clear 17 Monitor Clock 18 Power On Reset 19 In figure 19, the SPD bus 10t-10w comprises an 21 address data bus 10tl. The following paragraphs~2 will provide the address data bus 10tl signal 23 descriptions. 24 ADDRESS DATA BUS SELECT CYCLE: The A/D Bus is 26 driven by the bus master and must be valid prior 27 to Master Select and remain valid until Slave 28 Ready. When the IOIC is master it drives the29 data from the Select Data Buffer to the A/D Bus. 30 When the IOIC is slave it stores all four bytes 31 of data from the A/D Bus in Data BuEfer 0, byte 0 32 in the Key BufEer, and bytes 1-3 in the Address 33 Register or the Diagnostic Buffer. 34 ADDRESS DATA BUS DATA CYCLE (WRITE): The A/D Bus 36 is driven by the ~us master and must be valid 37 prior to Master Select and remain valid until 38 Slave Ready. When the IOIC is master it drives 39 the data from the Message Buffers to the A/D Bus. 40 When the IOIC is slave it stores the data fxom 41 the A/D Bus in the Data Buffers. 42 .

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EN986Q33 - 59 _ ADDRESS DATA BUS DATA CYCLE (READ): The A/D Bus 3 is driven by the bus slave and must be valid 4 prior to Slave Ready and remain valid until the 5 deactivation of Master Select. When the IOIC is 6 master it stores the data from the A/D Bus in the 7 Message Buffers. When The IOIC is slave, it 8 drives the A/D BUS with the ICCR Status Register 9 or with the Diagnostic Bu~fer. 10 In figure 19, the SPD bus 10t-10w comprises a 12 command status ~C/S) bus 10t2. 13 SELECT CYCLE: the C/S Bus is driven by the bus 15 master and must be valid prior to Master Select 16 and remain valid until Slave Ready. When the 17 IOIC is master it drives bits 5-7 and 11-15 of 18 the Command Register to the C/S Bus.19 Refer to figure 25 for a description of the C/S 21 bus command bits. 22 DATA CYCLE: the C/S Bus is driven by the bus 24 slave and must be valid prior to Slave Ready and 25 remain valid until the deactivation of Master 26 Select. When the IOIC is master, it stores the 27 status from the C/S Bus in the MOSW Status 28 Register. 29 Refer to figure 26 of a description of the C/S 31 bus status bits. 32 In figure 19, the SPD bus 10t-10w comprises an SPD 34 origin destination bus 10t3. 35 ORIGIN/DESTIN~TION BUS SELECT CYCLE: The O/D Bus 37 is driven by the bus master and must be valid 38 prior to Master Select and remain valid until 39 Slave Ready. When the IOIC is master it drives 40 bits 27-31 of the Command Register to the O/D 41 Bus. 42 . .

ORIGIN/DESTINATION BUS DATA CYCLE (NORMAL): The 3 O~D Bus is driven by the bus master with its 4 address so the slave will know the origin 5 address. The master's origin address must be 6 valid prior to Master Select and remain valid 7 until the activation of Slave Ready of each data 8 cycle; and the O/D bus value must be the same for g each data cycle of a bus operation. 10 ORIGIN/DESTINATION BUS DATA CYCLE (DIRECT): The 12 O/D Bus is driven by the bus slave with its 13 address so that the BCU can put the address in 14 the MOSW Status Register. The slave address must 15 be valid prior to Slave Ready and remain valid 16 until the deactivation of Master Select.~ 17 In figure 19, refer to the control line group 10t4. 19 The SPD bus 10t-10w compxises the following tag 20 lines, which are a part of the control line group 21 10t4: 22 l. MASTER SELECT (MSEL) 24 SELECT CYCLE: The MSEL line indicates the start 26 of a bus operation cycle. In response to Bus 27 Grant, MSEL indicates bus mastership by an IOBU. 28 MSEL indicates validity of the A/D Bus, the C/S 29 Bus, and the O/D Bus. MSEL is interlocked with 30 Slave Ready and Acknowledge Bus. 31 DATA CYCLES: MSEL indicates validity of the buses 33 driven by the bus master and is interlocked with 34 Slave Ready. 35 2. SLAVE READY ~RDY) 37 SELECT CYCLE: The RDY line response to MSEL 39 indicates that information on the A/D Bus, the 1l 40 C/S Bus, and the O/D Bus has been received. 41 .
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DATA CYCLES: A RDY response to MSEL indicates 3 that the information sent by the Master has been received and indicates validity of information 5 being sent to the Master. 6 3. MASTER STEERING (MST~ 8 SELECT CYCLE: The MST line is activated by the 10 bus master and received by the bus arbiter. ll DATA CYCLES: The deactivation of MST by the bus 13 master is used to indicate that the current bus 14 operation is complete and that Bus Grant may be 15 activated to start a new operation. ~ 16 Still referring to figure 19, the SPD bus 10t-10w 18 comprises the following direct selection lines which 19 are a part of the control line group 10t4. 20 1. CARD SELECT (CS) 22 SELECT CYCLE: The CS line used in conjunction 24 with Board Select indicates selection when doing 25 direct selection. The CS line is an input26 required by all IOBU's other that the BCU. The 27 source of the CS line is a different A/D Bus line 28 (from bit position 0-15) for each IOBU card 29 location. For example, A/D Bus bit 0 for the 30 first card location, bit 2 for the second and so 31 on. 32 2. BOARD SELECT ~BS) i 34 SELECT CYCLE: The BS line used in conjunction 36 with Card Select indicates selection when doing 37 direct selection. The BS line is an input38 required by all IOBU's other that the BCU. The 39 source of the BS line is a driver on each board 40 which decodes A/D Bus bits 29-31 to determine if 41 the board select line should be activated. For' 42 ' .

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~2;~37~
example, A/D Bus bits 29~31 all zero the IOIC 3 will drive BS. 4 In figure l9, the SPD bus 10t-10w comprises the 6 following arbitration lines which are a part of the 7 control line group 10t4. 8 1. REQUEST BUS (REQB) 10 The REQB line is activated by IOBUs and received 12 by the bus arbiter when services of the SPD Bus 13 are required by the IOBU. 14 2. REQUEST PRIORITY 0-2 (REQP0-2) 16 The REQP0-2 lines are priority level requests 18 associated with the bus request indicated by 19 REQB. Four levels of priority are possible with 20 REQB and REQP0 being the highest and REQB with no 21 priority lines active being the lowest. An IOBU ?~2 which has REQB active must compare its priority 23 with the level indicated on the REQPn lines and 24 if it has a lower priority it must propagate the 25 poll. 26 3. ACKNOWLEDGE BUS (ACKB) , 28 The ACKB line from the bus arbiter indicates the 30 beginning of arbitration for the next bus master. 31 The IOBU uses ACKB to sample its requests with 32 REQPn and determine if it will propagate the poll 33 when ABPI and ABPI' are active. 34 4. ACKNOWLEDGE BUS POLL IN/IN' ¦ABPI,ABPI') 36 The ABPI and ABPI' lines are required by all 38 IOBUs to support arbitration. Each IOBU provides 39 internal termination for ABPI and ABPI' which 1 40 allows the removal of an IOBU from a serial 41 string without breaking the propagation path. 42 7~
5. ACKNOWLEDGE BUS POLL OUT ~ABPO) 3 The ABPO line is an output required by all IOsUs 5 to support arbitration. The ~sPo line is activated by an IOBU when ACKB is active and its 7 request is inactive or lower in priority than 8 other requests and ABPI and ABPI' are active. 9 6. BUS GRANT (BUSG) 11 The BUSG line is activated by the bus arbiter to 13 establish a bus master for the next operation. 14 Bus Grant signals the IOBU that stopped the 15 serial poll that it is bus master for one bus 16 operation. Activation of MSEL with BUSG active 17 indicates the start of the select cycle to all 18 other IOBUs. BUSG is deactivated after MSEL is 19 deactivated. 20 In figure 19, the SPD bus 10t-10w comprises control 22lines, a part of control line group 10t4. ~ 23 1. BUS CLEAR (BC) 25 The Bus Clear line is driven by the BCU 50 and 27 causes the following actions: , 28 An IOBU in an operation will immediately stop 30 that operation and deactivate all buses and 31 tags; 32 All other IOBUs will deactivate all buses and 34 tags while Bus Clear is active. 35 2. MONITOR CLOCK (MC) 37 The Monitor Clock line is driven by the BCU and 39 is activated following the detection of a timei 40 out. Monitor Clock is an input to all IOBUs and 41 signals them to collect status. 42 .

~9 ~"~ 'Jrb ~
3. POWER ON RESET (POR) 3 The POR line is active for all power on and off 5 sequences for a power domain. POR is driven by 6 the power supply associated with the power 7 domain. The following actions occur with POR: 8 Arbitration is suppressed; 10 IOBU addresses are set to zero; and 11 Deactivate drivers by putting tristate drivers 12 in high impedance state and the other drivers 13 in the inactive state. 14 A functional description of the SPD bus 10t-10w will 16 be set forth in the following paragraphs with 17 reference, initially, to figure 1 and figure 19 of 18 the drawings. Figure 1 is needed to visualize the 19 relationship between the SPD bus and other IOBUs 20 10p-10s. Figure 19 is needed to visualize the 21 structure of the SPD bus 10t-10w. ~ 22 ' There are two basic SPD I/O Bus operations: (l) 24 Storage Operations, and (2) Unit Operations. Each 25 of these operation will be discussed in detail in 26 the following paragraphs. ; 27 1. STORAGE OPERATIONS on the SPD I/O BUS transfers 29 packets of one to thirty-two bytes of data between 30 the IO~U 10p-10s and common storage facility 10d. A 31 packet consists of one select cycle and from one to 32 eight data cycles. The IOIC, in this 33 implementation, is always the slave during Storage 34 Operations. A storage sequence is indicated by bit 35 0 of the SPD command being equal to zero. Bit 1 36 being on indicates a write and bits 2-7 plus one is 37 the number of bytes to be transferred. 38 Refer to figure 23 for a table of SPD storage l' 40 commands. 41 , STORAGE WRITE to STO~AGE 43 .

~37~

SELECT CYCLE: The Master I/O Bus Unit (IOBU) puts 3 information on the O/D Bus 10t3, the C/S Bus 10t2 4 and the A/D Bus 10tl. The O/D Bus 10t3 contains 5 the address of the IOIC which is X'00'. The C/S 6 Bus 10t2 contains the Write command plus the 7 number of bytes of data to be transferred. The 8 A/D sus lOtl contains the Key in byte 0 and the 9 starting common storage facility address in bytes 10 1,2, and 3. 11 DATA CYCLES: The Master ItO Bus Unit (IOBU) puts 13 its address on the O/D Bus 10t3 and a word of 14 byte aligned data on the A/D Bus 10tl. The size 15 of the packet of data can cause up to eight Data 16 Cycles. The IOIC buffers the data in the IOIC 17 DATA BUFFERS until the whole packet of data has 18 been transferred from the IOBU Master. The IOIC 19 generates common storage facility commands and 20 transfers the data from the the buffers to 21 storage. The IOIC puts the completion status on 2~2 the C/S Bus 10t2 after the data has been 23 transferred to the Common Storage Facility 10d 29 and storage status has been received by the IOIC. 25 , .
STORAGE READ from STORAGE 27 .
SELECT CYCLE: The Master I/O Bus Unit (IOBU) puts 29 information on the O/D Bus 10t3, the C/S Bus 10t2 30 and the A/D Bus 10tl. The O/D Bus 10t3 contains 31 the address of the IOIC which is X'00'. The C/S 32 Bus 10t2 contains the Read command plus the 33 number of bytes of data to be transferred. The 34 A/D Bus 10tl contains the ~ey in byte 0 and the 35 starting common storage facility address in bytes 36 1,2, and 3. 37 . .
DATA CYCLES: The Master I/O Bus Unit (IOBU) puts 39 its address on the O/D Bus 10t3. The IOIC l' 40 generates an common storage facility command and 41 receives data from storage and buffers it in the 42 IOIC DATA BUFFERS. The IOIC puts a word of byte 43 ~ . .

~L2~7~
aligned data from the buf~ers on the A/D Bus 10tl 3 after it has received the data and status from the Common Storage Facility 10d. The size of the 5 packet of data can cause up to eight Data Cycles. 6 The IOIC also puts the completion status on the 7 C/S Bus 10t2 during the last Data Cycle. 8 2. UNIT OPERATIONS provide a means of 10 communications between IOBUs without having to 11 utilize storage. Vnit Operations will always have 12 one select cycle and two data cycles. A unit 13 operation sequence is indicated b~ bit 0 of the SPD 14 command being equal to oneO Bit 1 being on indicates 15 a write and bit 2 on indicates direct select. Bits 16 3-7 are the unit operation command code. 17 Refer to figure 24 for a table of SPD bus unit 19 operation commands. 20 .
UNIT W~ITE transfers 8 bytes of data from the IOBU ~2 Master to the IOBU Slave. 23 SELECT CYCLE: The Master puts information on the 25 O/D Bus 10t3, the C/S Bus 10t2 and the A/D Bus 26 10tl. The O/D Bus 10t3 contains the address of 27 the Slave and the C/S Bus 10t2 contains the write 28 command. The A/D Bus 10tl contains 4 bytes of 29 machine depenclent data. 30 DATA C~CLES: The Master puts its address on the 32 O/D Bus 10t3 and data on the A/D Bus 10tl both 33 cycles. The Slave puts its completion status on 34 the C/S Bus 10t2 at the end of the last Data 35 Cycle. 36 UNIT READ transfers 8 bytes of data from the IOBU 38 Slave to the IOBU Master. 39 SELECT CYCLE: The Master puts information on the 41 O/D Bus, the C/S Bus and the A/D Bus. The O/D Bus 42 contains the address of the Slave and the C/S Bus 43 ~.

" ~3~
contains the read command. The A/D Bus contains 4 3 bytes of machine dependent data.

DATA CYCLES: The Master puts its address on the 6 O/D Bus. The Slave puts data on the A/D Bus both 7 cycles and its completion status on the C/S Bus 8 at the end of the last Data Cycle. 9 UNIT WRITE DIRECT transfers 8 bytes of data from the ll IOIC Master to the IOBU Slave. The Board Select and 12 Card Select lines, of the control line group 10t4, 13 are used to select the IOBU Slave. 14 SELECT CYCLE: The IOIC Master puts information on 16 the O/D Bus, the C/S Bus and the A/D Bus. The O/D 17 Bus contains the Slave address for a write 18 command and the C/S Bus contains the write 19 command. The A/D Bus contains the card and board 20 select data. 21 DATA CYCLES: The IOIC Master puts data on the A/D 23 Bus both cycles. The Slave puts its address on 24 the O/D Bus and its completion status on the C/S 25 Bus at the en~ of the last Data Cycle. 26 i UNIT READ DIRECT transfers 8 bytes of data from the 28 : IOBU Slave to the IOIC Master. The Board Select and 29 Card Select lines are used to select the IOBU Slave. 30 SELECT CYCLE: The Master puts information on the 32 O/D Bus, the C/S Bus and the A/D Bus. The O/D Bus 33 contains good parity and the C/S Bus contains the 34 read command. The A/D Bus contains the card and 35 board select data. 36 DATA CYCLES: The IOBU Slave puts its address on 38 the O/D Bus. The Slave puts data on the A/D Bus 39 both cycles and its completion status on the C/S 40 Bus at the end of the last Data Cycle. 41 ~7~

An SPD bus MESSAGE ACCEPTANCE OPERATION is like Unit 3 Write and the IOIC is always the slave. The SPD Op 4 Code is C0-CE and the IOIC will send the data to an 5 IPU Message Buffer in storage. 6 SELECT CYCLE: The Master IOBU puts '00' on the 8 O/D Bus, 'CX' on the C/S Bus and the A/D Bus 3 contains 4 bytes of machine dependent data which 10 is put into the first IOIC DATA BUFFER. 11 DATA CYCLES: The Master IOBU puts its address on 13 the O/D Bus and data on the A/D Bus both cycles. 14 The IOIC buffers the two words of A/D Bus data in 15 the second and third IOIC DATA BUFFERS and puts 16 the Message Acceptance Status Word tMASW) in the 17 fourth IOIC DATA BUFFER. The IOIC sends an 'OA' 18 IPU Common Storage Facility command to the IOIU 19 followed by the four words in the data buffers. 20 The IOIU knows the next address of the IPU 21 Message Buffer and stores the data. The IOIC puts 22 the completion status on the C/S Bus after the 23 data has been transferred to the Common Storage 24 Facility 10d and storage status has been received 25 by the IOIC. ~ 26 In the following paragraphs, a description of the 28 arbitration scheme practiced by the BCU 50 is set 29 forth. In practicing the arbitration scheme, the 30 BCU 50 receives requests for access to an SPD bus 31 (one of 10t-10w) from an IOIC (one of 10j-lOm) or 32 from one or more IOBUs 10p-10s. The BCU 50 will 33 determine which one of the IOICs or the IOBUs will 34 be granted access to the SPD bus. 35 ~eferring to figure 18a, another schematic of the 37 IOIC 10j-lOm, including BCU 50, is illustrated in 38 conjunction with four other IOBUs 10p-10s. In 39 figure 18a, an IOIC includes SPD bus arbiter BCU 50. 40 Other IOBUs are also illustrated. The IOIC is 41 connected to a number of card slots in which circuit 42 cards are disposed, namely, card slots 1, 2, 3, and 43 ~2~
4. Slot 1 has priority over slot 2, by virtue of 3 its position, slot 2 having priority over slot 3, by 4 virtue of its position, etc. The following buses 5 are connected to each of the circuit cards in each 6 card slot as indicated in figure 18a: the REQ BUS, 7 the REQ P0, the REQ Pl, and the REQ P2. The 8 ~ollowing additional buses of figure 3, are 9 connected to each of the circuit cards: the C/S bus - 10 10t2, the O/D bus 10t3, and the A/D bus 10tl. The 11 bus arbiter BCU 50 is disposed within the IOIC, the 12 arbiter having a pin O. Each circuit card in each 13 card slot 1 through 4 have pins I, I', and O. Pin I 14 and pin I' are not connected to an external active 15 source but are pulled on by an internal active 16 source. Pin O of slot 1 is connected to pin I of 17 slot 2 and to pin I' of slot 3. Pin O of slot 2 is 18 connected to pin I of slot 3 and to pin I' of slot 19 4. Pin O of slot 3 is connected to pin I of slot 4, 20 etc. 21 A functional description of the arbitration scheme 23 practiced by the SPD bus arbiter BCU 50 will be 24 described in the following paragraphs with reference 25 to figure 18a of the drawings. 26 Pin I and pin I' are pulled high by an internal 28 source in the IOBU because they are not connected to 29 an external source. Circuit card 1 then looks at 30 the status of its REQ BUS pin, REQ P0 pin, REQ P1 31 pin, and its REQ P2 pin when the acknowledge bus 32 (ACKB) signal is activated by the arbiter in the BCU 33 50. If its REQ BUS pin is high, it then looks to 34 the status of its other pins: REQ P0, REQ P1, and 35 REQ P2. If the other pins are high, and circuit 3~
card 1 did not cause these other pins to go high, 37 circuit card 1 will defer to the next card in slot 2 38 or 3 by turning on its Acknowledge Bus Poll Out 0 39 (ABPO 0) in figure 18a. Circuit card 2 of slot 2' 40 will look to its REQ BUS pin, and REQ P0, REQ P1, 41 and REQ P2 pins. If its REQ BUS pin is high, and 42 its REQ P0, REQ Pl, and/or REQ P2 pin is high, but 43 EN936033 _ 70 -~Z~ 4 circuit card 2 did not cause the REQ P0, REQ Pl, and 3 REQ P2 pins to go high, ~ircuit card 2 will defer to 4 the next card in slot 3 or 4 by turning on its ABPO 5 (0~ in figure 18a. Assume that circuit card 3 of 6 slot 3 examines its pins, and discovers the REQ BUS 7 pin is high, the RE~ P0 pin is high, the REQ Pl pin 8 is high, and the REQ P2 pin is high. Assume that 9 circuit card 3 of slot 3 caused its REQ P0, REQ P1, 10 REQ P2 pins to go high. Therefore, circuit card 3 11 of slot 3 (one of the IOBUs attached to the SPD bus) 12 gets access to the SPD bus. 13 TIMEOUTS are set by the BCU when an IOBU fails to 15 ; complete an operation within a specific perio~ of 16 time. There are two kinds of timeouts. 17 Bus Idle Timeout will occur i~ there is a request 19 on the SPD Bus and, after arbitration, there is 20 no response to the request by the Master turning 21 on MASTER STEERING and M~STER SELECT control 2 lines. 23 Bus Operation Timeout will occur if an SPD Bus 25 operation starts but does not complete by turning 26 ; off MASTER STEERING control line. 27 DIRECT SELECTION operations can only originate from 29 the BCU. Direct selection commands are unit 30 operations used to communicate with IOBU's which do 31 not have addresses assigned. It is through the 32 direct select commands that the BCU finds out who is 33 on the bus and then writes an address to that IOBU. 34 ERROR RECOVERY is performed by the BCU through the 36 use of the MONITOR CLOCR and BUS CLEAR control 37 lines. 38 Figures 27 to 32 illustrate timin~ sequence diagrams 40 for the adapter bus, the diagrams illustrating how 41 different adapter bus 10n interface lines interact 42 ~L2~7~
.

and the number of cycles required for each 3 operation. 4 Figures 33 to 39 illustrate timing sequence diagrams 6 for the SPD bus, the diagrams further illustrating 7 how the different SPD bus interface lines interact, 8 and illustrate the tag sequences required for each 9 operation. 10 (v) Functional description of the SPD bus, IOIC, 13 Adapter bus, and Storage Controller operating in 14 combination 15 A functional description of the operation of the SPD 17 bus 10t-10w, input output interface controller 18 (IOIC) 10j-lOm, the adaptor bus 10n, and the Storage 19 Controller 10e, 10g operating in combination will be 20 described in the following paragraphs with reference 21 to figures 1-39 of the drawings. ~2 1. COPY TYPE PROCESSOR BUS OPERATIONS (PBO) TO AN 24 IOIC 10j-lOm 25 A. Copy MOSW 27 The Message Origination Status Word ~MOSW) of figure 29 5 of an addressed IOIC is sent to the IPU 10a and 30 the contents of the MOSW is not changed. 31 A PBO operation to an IOIC starts when the IOIU 10e 33 of figure 1 transmits to the IOICs "ADAPTER COMMAND 34 TIME" to tell all the IOIC's that the ADAPTER A/D 35 BUS 10nl of figure 19 contains an IOIC PBO Command. 36 See figure 32 for the applicahle timing sequence. 37 The adapter bus control logic 30 of figure 10 PBO 38 Sequencer 30c loads the PBO command from the ADAPTER 3~
A/D BUS 10nl into the Destination Select Registeri 40 20h of figure 3 and figure 4, and the IOIC Match 41 logic 30a of figure 10 compares the PBO address with 42 the IOIC Hardware Address. If the addresses match, 43 ~2~
the PBO Facility logic 30~ of figure 10 decodes the 3 Pso Command determining that it is a 'DA' command (see figure 21). Then, the PBO facility logic 30b 5 sets the status register 20g controls so that, on 6 the third cycle of the P~O, the data in the MOSW 7 register of figu.re 5 will be gated to the ADAPTER 8 A/D BUS lOnl. Also, on the third cycle, the IOIC 9 Match logic 30a of figure 10 will send IOIC 10 ACKNOWLEDGE if the PBO address and a IOIC hardware 11 address matched. 12 (CONTINUED ON PAGE 74) 7~
B. Move MOSW 3 The Message Origination Status Word (MOSW) register 5 of figure 5, of the addressed IOIC, is sent to the 6 IPU 10a, and, if the Operation End bit is on 7 (MOSW ( 0 ) =1 ), then the remalning bits in the MOSW are 8 set to zero. If the Op End bit is off (MOSW(0) =0), 9 then the MOSW of figure 5 is not changed. 10 A PBO operation to an IOIC 10j-lOm starts when the 12 IOIU 10e transmits ADAPTER COM~ND TIME to the IOICs 13 to tell all the IOIC's that the ADAPTER A/D BUS 10nl 14 of figures 3 and 19 contains an IOIC PBO Command. 15 See figure 32 for the applicable timing sequence. 16 The adapter bus control logic 30 of figure 10 PBO 17 Sequencer 30c loads the ADAPTER A/D BUS 10nl into 18 the Destination Select Register 20h of figure 3 and 19 the IOIC Match logic 30a of figure 10 compares the 20 PBO address with the IOIC ~ardware Address. I~ the 21 addresses match, the PBO Facility logic 30b of 22 figure 10 decodes the Adapter Command to find that 23 it is a 'D8' (see figure 21) and then sets the 24 status register 20g controls so that, on the third 25 cycle of the PBO, the data in the MOSW register of 26 figure 5 will be gated to the ADAPTER A/D BUS 10nl. 27 Also, on the third cycle, the IOIC Match logic 30a 28 of figure 10 will send ~OIC ACKNOWLEDGE if the PBO 29 address and a IOIC hardware address matched. After 30 the MOSW register of figure 5 has been sent to the 31 IPU 10a, the PBO Facility logic 30b of figure 10 32 checks the Op End bit and, if it is on, resets the 33 rest of the MOSW bits to zero. 34 2. LOAD TYPE PBO'S TO IOIC 36 A. Load Message Buffer Reg 1 38 The Message Buffer Register 1 (MBRl) 20b of figure 3 40 is loaded with four bytes of data from the IPU 10a. 41 If the Message Origination facility is busy, that 42 is, if bit 1 of the MOSW register of figure 5 is a 43 .

. EN986033 - 74 - ;

~Z97~
binary 1 (MOSW(l)=l), the message buffer register 3 20b is not loaded. 4 A PBO operation to an IOIC starts when the IOIU 10e 6 of figure 1 sends "ADAPTER COMMAND TIME" to all 7 IOICs in order to tell the IOIC's that the ADAPTER 8 A/D BUS 10nl contains an IOIC PBO Command (See 9 figure 31 for the timing sequence). The adapter bus 10 control logic 30 PBO Sequencer 30c loads thell contents of the ADAPTER A/D BUS lOnl into the 12 Destination Select Register 20h of figure 3 (and 13 figure 4) and the IOIC Match logic 30a of figure 10 14 compares the PBO address with the IOIC Hardware 15 Address and checks for SPD Busy. If the addresses 16 match and the spd bus is not busy~ the PBO ~acility 17 logic 30b decodes the PBO Command to find that it is 18 a '9E'(see figure 21) and then sets the message 19 buffer 20b controls so that, on the second cycle of 20 the PBO, the data on the ADAPTER A/D BUS 10nl will 21 be set into the MBRl buffer 20b of figure 3. On the 22 third cycle of the PBO, the IOIC Match logic 30a of 23 figure 10 will send IOIC ACKNOWLEDGE to the IOIU 10e 24 if the PBO address and a IOIC hardware address 25 matched or IOIC BUSY if the address matched and the 26 Message Origination facility (MOSW) is busy.27 B. Reset ICSW under mask 29 In this operation, the contents of the Selector 31 Buffer 20e of figure 3 are "ones complemented" and 32 then ANDed with the bits of the IOIC Status Word 33 (ICSW) register of figure 8 within the status 34 registers 20g of figure 3. 35 A PBO operation to an IOIC starts when the IOIU 10e 37 transmits "ADAPTER COMMAND TIME" to the IOICs to 38 tell all the IOIC's that the ADAPTER A/D BUS 10nl of 39 figure 3 and 19 contains an IOIC PBO Com~and. Seel 40 figure 31 for an applicable timing sequence. The 41 adapter bus control logic 30 of figure 10 PBO 42 Sec3uencer 30c loads the ADAPTER A/D BUS 10nl into 43 EN986033 _ 75 _ ~Z~9~
the Destination Select Register 20h of figure 3, and 3 figure 4, in the first PBO cycle, and into the 4 Selector Buffer 20e of figure 3 in the second cycle. 5 The IOIC Match logic 30a of figure 10 compares the 6 PBO address with the IOIC Hardware Address. If the 7 addresses match, the PBO Facility logic 30b of 8 figure 10 decodes the Adapter Command to find that 9 it is a '99'(see figure 21) and then sets the status 10 register 20g controls so that, after the second 11 cycle, contents of the Selector suffer 20e of figure 12 3 are "ones complemented" and then ANDed with the 13 bits in the ICSW of figure 8. Only the bits on in 14 the Selector Buffer 20e will have their 15 corresponding bits in the ICSW reset to zero. On the 16 third cycle of the PBO, the IOIC Match logic 30a 17 will send IOIC ACKNOWL~DGE to the IOIU 10e if the 18 PBO address and a IOIC hardware address matched. 19 3. UNIT OPERATION PROCESSOR BUS OPER~TIONS (PBO) TO 21 IOIC 2~2 A. Unit Operation Write 24 This instruction requests a unit write operation on 26 the specified SPD I/O bus (one of buses 10t-10w). 27 If the Message Origination facility is busy, that 28 is, MOSW(1)=1, there i5 no change in the state of 29 the IOIC. 30 A PBO operation to an IOIC starts when the IOIU 32 transmits "ADAPTER COMMAND TIME" to the IOICs to 33 tell all the IOIC's that the ADAPTER A/D BUS lOnl 34 contains an IOIC PBO Command. See figure 31 for the 35 applicable timing sequence. The adapter bus control 36 logic 30 PBO Sequencer 30c of figure 10 loads the 37 ADAPTER A/D BUS 10nl into the Destination Select 38 Register 20h of figure 3, and figure 4, in the ~irst 39 PBO cycle and into the Selector Buffer 20e in thel 40 second cycle. The IOIC Match logic 30a of figure 10 ~1 compares the PBO address with the IOIC Hardware 42 Address and checks for SPD Busy. If the addresses 43 .
. EN986033 - 76 -~Z~7~

match and the SPD bus is not busy, the Pso Facillty 3 logic 30b of figure 10 decodes the Adapter Command 4 to find that it is a '96'(See figure 21) and then, 5 if the Message Origination Facility is not busy, 6 uses the load command buffer controls to move the 7 Selector suffer 20e of figure 3 to the Select Data 8 Buffer 20f of figure 3 and the Dest Select Register 9 20h to the Com~and Register 20i of figure 3. On the 10 third cycle of the Pso, the IOIC Match logic 30a 11 will send IOIC ACKNOWLEDGE ~o the IOIU 10e if the 12 PBO address and a IOIC hardware address matched or 13 IOIC BUSY if the address matched and the Message 14 Origination facility is busy. The PBO Facility 30b 15 of figure 10 sends a request to the SPD Bus Control 16 logic 40 of figure 2 which accepts this instruction 17 and then resets MOSW bits 0,8, and 27-31 of figure 18 5. The Message Origination facility becomes busy 19 (MOSW(l)=1). The IOIC SPD Master Control unit 40a 20 of figure 12 sends a REQB for a SPD bus operation to 21 the BCU 50 of figure 2. The Master Control unit 40a 22 takes the ACKB from the BCU 50 and, if no other IOBU 23 has higher priority, it blocks the ACKB from going 24 out to the SPD Bus and waits for BUSG. When the 25 Master Control unit 40a receives BUSG, it starts the 26 SPD Unit Write operation select cycle (See figure 35 27 for the SPD bus sequence) by driving the SPD A/D Bus 28 10tl, C/S Bus 10t2, O/D Bus 10t3 of figure 19, and 29 Master Steering (MST) of control line group 10t4. 30 The Select Data Buffer 20f is sent to the SPD A/D 31 Bus 10tl, the SPD bus command field of the Command 32 Register 20i to the C/S Bus 10t2, and the 33 destination field of the Command Register 20i to the 34 O/D Bus 10t3 of figure 19 (See figure 4 for a 35 description of the Dest Sel Register 20h which is 36 equal to the data in the Co~nand register 20i). 37 After the data on the buses settles down, the Master 38 Control 40a drives MSEL telling the slave IOBU that 39 the bus data is valid. The slave IOBU tells the IOIC 40 to continue by raising RDY. The master control 40a 41 drops MSEL and stops driving the buses. After MSEL~ 42 drops, the BCU 50 drops BUSG and the slave IOBU 43 EN986033 _ 77 _ drops RDY to end the select cycle. The first data 3 cycle starts when the Master Controller 40a dri~es 4 the A/D Bus with the data in Message Buffer 1 and 5 the O/D Bus with the IOIC address '00. Next, the 6 Master Control 40a sets the CiS Bus to receive and, 7 after the buses settle, raises MSEL to indicate that the bus data is valid. The slave drives the C/S Bus 9 with status (figure 26~ if there is an error and, 10 after waiting for the bus to settle, raises RDY. ll The master control 40a drops MSEL and stops driving 12 the A/D Bus. The slave drops RDY and stops driving 13 the C/S Bus to end the first data cycle. The second 14 data cycle starts when the Master Controller 40a 15 drives the A/D Bus with the data in Message Buffer 16 2. After the A/D Bus settles, the Master Controller 17 40a raises MSEL to indicate that the bus data is 18 valid. The slave drives the C/S Bus with ending 19 status or error status if there was an error and, 20 after waiting for the bus to settle, raises RDY. The 21 master 40a drops MSEL and stops driving the A/D Bus 2~2 and O/D Bus. The slave drops RDY and stops driving 23 the C/S Bus and then the Master Control drops MST. 24 The MOSW receives the ending status from the C/S Bus 25 which causes the Op End (MOSW(0)) bit to come on and 26 the Busy (MOSW(1)) bit to turn off to end the 27 operation. 28 B. Unit Operation Read 30 This instruction requests a unit read operation on 32 the specified SPD I/O bus. If the Message 33 Origination facility is busy (MOSW(1)=1), there is 34 no change in the state of the IOIC. 35 A PBO operation to an IOIC starts when the IOIU 37 sends ADAPTER COMMAND TIME to tell all the IOIC's 38 that the ADAPTER A/D BUS contains an IOIC PBO 39 Cor~and. (See figure 31 for timing sequence). The 40 adapter ~us control logic PBO Sequencer 30c loads 41 the ADAPTER A/D BUS into the Destination Select 42 Register 20h in the first PBO cycle and into the 43 g~
Selector Buffer 20e in ~he second cycle. The IOIC 3 Match logic 30a compares the PBO address with the 4 IOIC Hardware Address and checks for SPD Busy. If 5 the address match and the SPD bus is not busy, the 6 PBO ~acility logic 30b decodes the Adapter Command 7 to find that it is a '94'(fi~ure 21) and then, if 8 the Message Origination is not busy, uses the load 9 command buffer controls to move the Selector Buffer 10 20e to the Select Data Buffer 20f and the Dest ll Select Register 20h to the Command Register 20i. On 12 the third cycle of the PBO, the IOIC Match logic 30a 13 will send IOIC ACKNOWLEDGE if the PBO address and a 14 IOIC hardware address matched or IOIC BUSY if the 15 address matched and the Message Origination facility 16 is busy. The PBO Facility 30b sends a request to 17 the SPD Bus Control logic 40, which accepts this 18 instruction and then resets MOSW bits 0,8, and 19 27-31. The Message Origination facility becomes 20 busy (MOSW(1)=1)~ The IOIC SPD Master Control unit 21 40a sends a REQB for a SPD bus operation to the BCU 22 50. The Master Control unit 40a takes the ACXB from 23 the BCU 50 and, if no other IOBU has higher 24 priority, it blocks the ACKB from going out to the 25 SPD Bus and waits for BUSG. When the Master Control 26 unit 40a receives BUSG, it starts the SPD unit Read 27 operation select cycle (See figure 37 for the SPD 2~
bus sequence) by driving the SPD A/D Bus 10tl, C/S 29 Bus 10t2, O/D Bus 10t3 of figure 19, and MST. The 30 Select Data Buffer 20f is sent to the SPD AiD Bus 31 10tl, the SPD bus command field of the Command 32 Register 20i to the C/S Bus 10t2, and the 33 destination field of the Command Register 20i to the 34 O/D Bus. After the data on the buses settles down, 35 the Master Control ~Oa drives MSEL telling the slave 36 IOBU that the bus data is valid. The slave IOBU 37 tells the IOIC to continue by raising RDY. The 38 master control 40a drops MSEL and stops driving the 39 buses. After MSEL drops, the BCU drops BUSG and the 40 slave drops RDY to end the select c~cle. The first 41 data cycle starts when the Master Controller 40a 42 drives the O/D Bus 10t3 with the IOIC address '00. 43 EN986033 _ 79 _ Next, the Master Control 40a sets the A/D Bus 10tl 3 and the C/S Bus 10t2 to receive and, a~ter the O/D 9 Bus 10t3 settles, raises MSEL to indicate that the 5 data is valid. The slave IOBU drives the A/D Bus 6 10tl with data which is put in the Message Buffer 1 7 ~see figure 19) and the C/S sus 10t2 with status lf 8 there is an error. After waiting for the bus to 9 settle, the slave Iosu raises RDY. The master 10 control 40a drops MSEL after buffering the data in 11 the MBRl buffer. T~e slave IOBU drops RDY and stops 12 dxiving the A/D BUS 10tl and C/S Bus 10t2 to end the 13 first data cycle. The second data cycle starts when 14 the Master Controller 40a raises MSEL to indicate 15 that the master is ready for more data. The slave 16 IOBU drives the A/D Bus 10tl with data which is put 17 in the Message Buffer 2 (of figure 19) and the C/S 18 Bus 10t2 with ending status or error status if there 19 was an error and, after waiting for the buses to 20 settle, raises RDY. The master 40a drops MSEL after 21 buffering the data in the MBR2 buffer (of figure 19) ~2 and stops driving O/D Bus 10t3. The slave IOBU 23 drops RDY and stops driving the A/D Bus 10tl and C/S 24 Bus 10t2 and then the Master Control 40a drops MST. 25 The MOSW of figure 5 receives the ending status from 26 the C/S Bus 10t2 which causes the Op End (MOSW(0)) 27 bit to come on and the Busy bit (MOSW(1)) to turn 28 off to end the operation. 29 C. Unit Operation Write Direct 31 This instruction requests a unit write direct 33 operation on the specified SPD I/O bus (one of 34 10t-10w). If the Message Origination facility is 35 busy (MOSW(l)=l), there is no change in the state of 36 the IOIC. 37 A PBO operation to an IOIC starts when the IOIU 10e 39 sends "ADAPTER COMMAND TIME", which tells all the 40 IOIC's that the ADAPTER A/D BUS 10n contains an IOIC 41 PBO Command (See figure 31 for timing sequence). 42 The adapter bus control logic 30 PBO Sequencer 30c 43 EN986033 - 8~ -~L2~
loads the ADAPTER A/D BUS 10n into the Destination 3 Select Register 20h of figure 3 in the first PBO 4 cycle and into the Selector Buffer 20e in the second 5 cycle. The IOIC Match logic 30a of figure 10 6 compares the PBO address with the IOIC Hardware 7 Address and checks for SPD Busy. If the addresses 8 match and the SPD bus is not busy, the PBO Facility 9 logic 30b decodes the Adapter Co~nand to find that 10 it is a '97' (figure 21) and then, if the Message 11 Origination is not busy, uses the load co~nand 12 buffer controls to move the Selector Buffer 20e to 13 the Select Data Buffer 20f and the Dest Select 14 Register 20h to the Command Register 20i. On the 15 third cycle of the PBO, the IOIC Match logic 30a 16 will send IOIC ACKNOWLEDGE if the PBO address and a 17 IOIC hardware address matched or IOIC BUSY if the 18 address matched and the Message Origination facility 19 is busy. The PBO Facility 30b sends a request to 20 the SPD Bus Control logic 40 which accepts this 21 instruction and then resets MOSW bits 0,8, and 22 27-31. The Message Origination facility becomes 23 busy (MOSW(l)-l). The IOIC SPD Master Control unit 24 40a of figure 12 sends a REQB for an SPD bus 25 operation to the BCU 50. The Master Control unit 26 40a ta~es the ACKB from the BCU 50 and, if no other 27 IOBU has higher priority, it blocks the ACKB from 28 going out to the SPD Bus and waits for BUSG. When 29 the Master Control unit 40a receives BUSG, it starts 30 the SPD Unit Write Direct operation select cycle 31 (See figure 36 for the SPD bus sequence) by drivin~ 32 the SPD A/D Bus 10tl, C/S Bus 10t2, O/D Bus 10t3, of 33 figure 19, and MST. The Select Data Buffer 20f is 34 sent to the SPD ~jD Bus 10tl, the SPD bus co~nand 35 field of the Co~nand Register 20i to the C/S Bus 36 10t2, and the destination field of the Command 37 Register 20i to the O/D Bus 10t3. The BCU 50 38 decodes bits 29-31 of the A/D Bus 10tl for zeros to 39 drive Board Select. After the data on the buses i 40 settles down, the Master Control 40a drives MSEL 41 telling the slave IOBU that the bus data is valid. 42 The slave IOBU is in a card slot that sees both the 43 soARD SELECT and the CARD SELECT lines in all actlve 3 condition. The slave IOBU tells the IOIC to continue by raising RDY. The master 40a drops MSEL 5 and stops driving the buses. A~ter MSEL drops, the 6 BCU 50 drops BUSG and the slave IOBU drops RDY to 7 end the select cycle. The first data cycle starts 8 when the Master Control 40a drives the A/D BUS 10tl 9 with the data in Message Buffer l [figure 19). 10 Next, the Master Control 40a sets the C/S Bus 10t2 11 and O/D Bus 10t3 to receive and, after the buses 12 settle, raises MSEL to indicate that the bus data is 13 valid. The slave IOBU drives the C/S Bus 10t2 with 14 status (see figure 26) if there is an error and the 15 O/D Bus 10t3 with its address. After waiting for 15 the buses to settle, the slave IOBU raises RDY. The 17 ,master 40a puts the O/D Bus 10t3 data in byte 3 of 18 the MOSW, drops MSEL and stops driving the A/D Bus 19 10tl. The slave IOBU drops RDY and stops driving the 20 C/S Bus 10t2 to end the first data cycle. The 21 second data cycle starts when the Master Controller ~2 40a drives the A/D Bus 10tl with the data in Message 23 Buffer 2. After the A/D Bus 10tl settles, the 24 Master Controller 40a raises MSEL to indicate that 25 the bus data is valid. The slave IOBU drives the 26 C/S Bus 10t2 with ending status, or error status if 27 there was an error, and, after waiting for the bus 28 to settle, raises RDY. The master control 40a drops 29 MSEL and stops driving the A/D Bus 10tl. The slave 30 IOBU drops RDY and stops driving the O/D Bus 10t3 31 and the C/S Bus 10t2; and, then , the Master Control 32 40a drops MST. The MOSW receives the ending status 33 from the C/S Bus 10t2 which causes the Op End 34 (MOSW(0)) bit to come on and the Busy bit (MOSW(l)) 35 to turn o~f to end the operation. 36 4. SPD UNIT OPERATION TO IOIC 38 , .
A. Message Acceptance Operation ~I 40 This instruction is an SPD Unit Write operation from 42 an IOBU 10p-10s to an IOIC 10j-lOm. The message 43 .
..

. . , received from an Iosu 10p-lOs is buffered in the 3 IOIC 10j-lOm and then sent to the IOIU 10e for 4 storage. 5 An SPD operation to an IOIC 10j-lOm starts when the 7 IOBU 10p-lOs of figure 1 sends a REQs to the BCU 50 8 (See figure 39 for SPD bus sequence). The BCU 50 of 9 figure 11 ~and figure 2~ raises ACKB to start the 10 bus polling and then raises BUSG when the SPD Bus is 11 free to start another operation. The IOBU that 12 raised the REQB captures the poll and, when it sees 13 BUSG, starts the select cycle. The IOBU drives the 14 A/D Bus 10tl, C/S Bus 10t2, O/D Bus 10t3 of figure 15 19 and master steering (MST) of the control line 16 group 10t4. After the data on the buses settles 17 down, the IOBU drives MSEL telling the IOIC Slave 18 Control unit 40b of figure 12 that the data is 19 valid. The Slave control 40b decodes the 'C0' 20 command from the C/S Bus 10t2 and matches on '00' 21 from the O/D Bus 10t3. The command on the C/S Bus 22 10t2 is put in the MASW, a status register 20g of 23 figure 3 and figure 6; the data on the A/D Bus 10tl 24 is put in the first Data Buffer 20a; and A/D Bus 25 10tl bits 0-5 in the Key Buffer 20c. Then, the IOIC 26 raises RDY to tell the IOBU to continue. During 27 this time, the IOBU drops REQB and the BCU drops 28 ACKB. The IOBU, seeing RDY, drops MSEL and stops 29 driving the buses. After MSEL drops, the IOIC drops 30 RDY and the BCU 50 of figure 11 drops BUSG to end 31 the select cycle. The first data cycle starts when 32 the IOBU drives the A/D Bus 10tl with the data and 33 the O/D Bus 10t3 with its address and, after the 34 buses settle, raises MSEL to indicate that the bus 35 data is valid. The slave control 40b puts the data 36 fro~ the A/D Bus 10tl into the second Data Bu~fer 37 20a and from the O/D Bus 10t3 into the MASW register 38 of figure 6. The slave control 40b drives the C/S, 39 Bus 10t2 with status if there is an error and, after 40 waiting for the bus to settle, raises RDY. The IOBU 41 10p-10s drops MSEL and stops driving the A/D Bus 42 10tl. The IOIC slave control unit 40b of figure 12 43 . . , 79~
drops RDY and stops driving the C/S Bus 10t2 to end 3 the first data cycle. The second data cycle starts 4 when the IOBU drives the A/D Bus 10tl with the data 5 and, after the bus settles, raises MSEL to indicate 6 that the bus data is valid. The slave control 40b 7 puts the data from the A/D Bus 10tl into the third 8 Data Buffer 20a. Wow that the IOIC has all of the 9 message, the Slave Control unit 40b turns the 10 operation over to the Adapter sus Controls 30 of 11 figure 2 and holds the SPD Bus until the Adapter 12 controls 30 give the Slave control unit 40b final 13 status. The Adapter Bus Control 30 storage op 14 controller 30d of figure 10 raises IOIC REQUEST and 15 then waits for IOIC GRANT. When the controller 30d 16 receives IOIC GRANT, it drives the K/S Bus lOn2 and 17 the Adapter A/D Bus 10nl from T0 to T0 of the next 18 cycle (See figure 30 for timing sequence). The Key 19 bus 10n2 of figure 19 contains the message~priority 20 value, and byte zero of the Adapter A/D bus 10nl 21 contains 'OA', which is the Message Acceptance 22 command. When the storage controller logic 10g (see 23 figure 20) receives the command and address on the 24 cycle following the IOIC GRANT, it gates the 25 information from the ADAPTER BUS 10nl into the 26 CMD/ADDR register 60i. The message priority on the 27 ; KeytStatus Bus 10n2 during this same cycle 1s 28 clocked into the I/O KEY reg 60f. This message ~ 29 priority value will determine which Message Buffer 30 Offset Register 60p or 60q will be used for this 31 message. The adclress contained in the selected 32 message buffer will be gated to the storage bus 10f 33 at STORAGE COMiMAND TIME. The command 'OA' wi.ll be 34 changed to an '88' which is a sixteen byte write 35 operation. On the second data cycle, the data in 36 the DATA IN register 60a, will be clocked into the 37 DATA OUT register, while the data from the ADAPTER 38 BUS 10nl is clocked into the DATA IN register. This 39 sequence will continue for four cycles. On the i 40 third cycle, SI'ORAGE COMMAND TIME (one of the 41 storage control 10h signals) will be driven as well 42 as the I/O REQUEST TO D-CACHE signal. This I/O 43 ,. ~ ..

., :
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REQUEST TO D-CACHE signals the data cache to gatë 3 the command and address into its logic so that a 4 search of the cache can be made to see if the data 5 being updated exists within the cache and to see if 6 the data within that line has been modified. If the 7 data exists but has not been modified, the cache 8 will invalidate that line of data and allow the 9 storage operation to be done in the memory card. If 10 however, the data does exist and the data within 11 that line has been modified, the data cache will use 12 the data received on data cycles following the 13 command to modify the e~isting data in the cach~. 14 All data gated to the storage bus 10f by the storage 15 controller 10g is gated from the DATA OUT register 16 60b. Meanwhile the selected memory card is in the 17 process of accessing the storage location addressed 18 by the address given in bytes 1-3 on the command l9 cycle. On each cycle following the transmission of 20 data to the storage card, the INPUT PARITY line will 21 indicate whether an error was detected, and if 22 active, will be gated to the ERROR DETECTION LOGIC 23 60m, and then relayed to the I/O STATUS register 24 60e. At the end of the storage operation, the 25 appropriate message buffer offset register will be 26 incremented to the next quad word address. The 27 storage op controller 30d puts the first three Data 28 Buffers 20a on the Adapter A/D Bus 10nl from T0 To 29 T0 during the next three data cycles. On the fourth 30 data cycle, the storage op controller 30d puts the 31 MASW register of figure 6 (a part of the status 32 registers 20g of figure 3) on the Adapter A/D Bus 33 10nl from T0 to T0, and, then, waits four cycles to 34 get the final write status from the IOIU 10e on the 35 Status Bus 10n2. The Slave Control unit 40b of 36 figure 12 receives the final status from the Adapter 37 Bus Controls 30 and puts the ending status on the 38 C/S Bus 10t2. After waiting for the bus to settle, 39 the slave control 40b raises RDY to tell the master 40 control 40a o~ figure 12 that the Message Acceptance 41 operation in the IOIC is complete. The IOBU drops 42 MSEL and then stops driving the AiD Bus 10tl and the 43 O/D Bus 10t3. When the slave IOIC sees MSEL drop, 3 it drops RDY and stops driving the C/S Bus 10t2. The 4 Iosu master can now drop MST which ends the 5 operation. 6 B. Read Wrap Operation 8 This instruction is a SPD Unit Read operation from 10 an IOBU 10p-10s to the IOIC. The data received from 11 the IOsU during the select cycle is buffered in the 12 IOIC, and, then, for the purpose of checking the 13 operation of the spd bus, the data received from the 14 IOBU is put back on the A/D Bus 10tl for 15 transmission back to the IOBU during the data 16 cycles. ~ 17 An SPD operation to an IOIC starts when thé IOBU 19 sends a REQB to the BCU 50 (See figure 37 for SPD 20 bus sequence). The BCU 50 raises ACKB to start the 21 bus polling and then raises BUSG when the SPD Bus is 2~2 free to start another operation. The IOBU that 23 raised the REQB captures the poll, and, when it sees 24 BUSG, starts the select cycle. The IOBU drives the 25 A/D Bus 10tl, C/S Bus 10t2, O/D Bus 10t3 and master 26 steering (MST) of the control line group 10t4. 27 After the data on the buses settles down, the IOBU 28 drives master select ~MSEL) of the control line 29 group 10t4 telling the IOIC Slave Control unit 40b 30 that the data is valid. The Slave control 40b 31 decodes the '9F' command from the C/S Bus 10t2 and 32 matches on '00' Erom the O/D Bus 10`t3. The data on 33 the ~/D Bus 10tl is put in the Diagnostic Buffer 20j 34 of figure 3, then, the IOIC r~ises RDY to tell the 35 IOBU to continue. During this ti~e, the IOBU drops 36 REQB and the BCU 50 drops ACKB. The IOBU, seeing 37 RDY, drops MSEL and stops driving the buses. After 38 MSEL drops, the IOIC drops RDY and the BCU 50 drops 39 BUSG to end the select cycle. The first data cycle 40 starts when the IOBU drives the O/D Bus 10t3 with 41 its address, and, aftex the buses settle, raises 42 aster select (MSEL) of control line group 10t4 to 43 ~2~
indicate that the bus data is valid. The slave 3 control 40b of fi~ure 12 drives the A/D Bus 10tl 4 with the data stored in ~he Diagnostic Buffer 20j 5 and the C/S Bus 10t2 with status (see figure 26), if 6 there is an error, and, after waiting for the bus to 7 settle, raises RDY. The IOBU drops MSEL after 8 receiving the A/D sus 10tl. The IOIC slave control 9 unit ~Ob of figure 12 drops RDY and stops driving 10 the A/D Bus 10tl and C/S BUS 10t2 to end the first ll data cycle. The second data cycle starts when the 12 IOBU raises MSEL to tell the IOIC slave to continue. 13 The slave control 40b drives the A/D sus 10tl again 14 with data stored in the Diagnostic Buffer 20j and 15 the C/S Bus 10t2 with ending status or error status, 16 if there was an error. After waiting for the bus to 17 settle, the slave control 40b raises RDY to tell the 18 master control 40a of figure 12 that the Read Wrap 19 operation in the IOIC is complete. The IOBU (one of 20 10p-10s) drops master select (MSEL) and then stops 21 driving the O/D Bus 10t3. When the slave IOIC sees 22 MSEL drop, it drops RDY and stops driving the A/D 23 Bus 10tl and the C/S Bus 10t2. The IOBU master can 24 now drop MST which ends the operation. 25 " .
5. SPD STORAGE OPERATION TO IOIC 27 A. Write 32 Bytes Memory Operation 29 This instruction is a SPD Storage Write operation 31 from an IOBU (one of 10p-10s) to the IOIC 10j-lOm. 32 The data received from the IOBU is buffered in the 33 IOIC and then senk to the IOIU 10e for storage. 34 An SPD operation to an IOIC starts when the IOBU 36 sends a REQB to ~he BCU 50 (See figure 33 for SPD 37 bus sequence). The BCU 50 raises ACKB to start the 38 bus polling and then raises BUSG when the SPD Bus is 39 free to start another operation. The IOBU that i 40 raised the REQB captures the poll; and, when it sees 41 BUSG, starts the select cycleO The IOBU drives the 42 A/D Bus 10tl, C/S Bus 10t2, O/D Bus 10t3 and master 43 ~2~9~D~

steering (MST) of control line group 10t4. After 3 the data on the buses settles down, the IOBU drives 4 master select ~MSEL) of control line group 10t4 5 telling the IOIC Slave Control unit 40b that the 6 data is valid. The Slave control 40b decodes the 7 '5F' command from the C/S Bus 10t2 and matches on 8 '00' from the O/D Bus 10t3. The data on the A/D suS g 10tl is put in the Address Register 20d of figure 3 10 and A/D Bus 10tl bits 0-5 in the Key Buffer 20c. 11 Then, the IOIC raises RDY to tell the IOBU to 12 continue. During this time, the IOsU drops REQB and 13 the BCU 50 drops ACKB. The IOBU, seeing RDY, drops 14 MSEL and stops driving the buses. After MSEL drops, 15 the IOIC drops RDY and the BCU 50 drops BUSG to end 16 the select cycle. The first data cycle starts when 17 the IOBU drives the A/D Bus lOtl with the data and 18 the O/D Bus 10t3 with its address and, after the 19 buses settle, raises MSEL of the control line group 20 10t4 to indicate that the bus data is valid. The 21 slave control 40b of figure 12 puts the data from 22 the A/D Bus 10tl into the first Data Buffer 20a. 23 The slave control 40b drives the C/S Bus 10t2 with 24 status (see figure 26) if there is an error and, 25 after waiting for the bus to settle, raises RDY. 26 The IOBU drops MSEL and stops driving the A/D Bus 27 10tl. The IOIC slave control unit 40b drop~s RDY and 28 stops driving the C/S Bus 10t2 to end the first data 29 cycle. The second thru seventh data cycles are all 30 like the ~irst data cycle and they put the data in 31 the secon~ thru seventh Data Buffers. During the 32 data cycles, the Storage Opcode Translator unit 40c 33 oE figure 12 takes the '5~' command (see figure 23) 34 and generates a '90' Memory Opcode and stores it in 35 byte 0 of the Address Register 20d of figure 3. The 36 eighth data cycle starts when the IOBU drives the 37 A/D Bus 10kl with the data and, after the bus 38 settles, raises MSEL of control line group 10t4 to 39 indicate that the bus data is valid. The slave i 40 control 40b puts the data from the A/D Bus 10tl into 41 the eight Data Buffer 20a. Now that the IOIC has 42 all of the data, the Slave Control unit 40b turns 43 the operation over to the Adapter Bus Controls 30 3 and holds the SPD Bus until the Adapter bus controls 4 30 give the Slave controls 40b final status. I'he 5 Adapter Bus Control 30 storage op Controller 30d 6 raises IOIC REQUEST and then waits for IOIC GRANT 7 from IOIU 10e. When the controller receives IOIC 8 GRANT, it drives the K/S Bus 10n2 and the Adapter 9 A/D Bus 10nl from T0 to T0 o~ the next cycle. The 10 Key bus 10n2 contains the 370 key and the Adapter 11 A/D bus 10nl contains the first Address Register 12 20d. Byte 0 of the Address Register 20d is the 13 memory command (figure 21A) and bytes 1-3 are the 14 starting memory address. When the storage~ -~ 15 controller logic 10g (see figure 20) receives the 16 command and address on the cycle following the IOIC 17 GRANT, it gates the in~ormation from the ADAPTER BUS 18 10nl into the CMD/ADDR register 60i. The Key data 19 present on the Key/Status Bus 10n2 during this same 20 cycle is clocked into the I/O KEY reg 60f. The 21 cycle following the command and address will contain 22 the first data sent on the ADAPTER BUS 10nl and is 23 clocked into the DATA IN reg 60a. Simultaneously 24 during this second cycle, the address in the 25 C~D/ADDR register 60i is added to the 370 OFFSET 26 register 60j if the I/O KEY register bit 4 is zero. 27 If bi.t 4 is a one, then a zero value is substituted 28 for the 370 OFFSET value. The result of the29 addition irom ADDER 60k is gated to the KEY STACK 30 ARRAY 60h which acldresses the key ~alue for that 31 memory address requested. The output of the key 32 stack is gated into the the KEY DATA register 60g. 33 The key data in the ~EY DATA register 60g is now 34 compared to the key in the I/O KEY register 60f, by 35 the ERROR DETECTION LOGIC 60m. If the key is 36 acceptable the status gated to the I/O STATUS 37 ; register 60e will indicate good status. Otherwise, 38 a protection check indication will be set into the 39 register. On the second data cycle, the data in the 40 DATA IN register 60a, will be clocked into the DATA 41 OUT register, while the data from the ADAPTER BUS 42 10nl is clocked into the DATA IN register. This 43 :

97~
sequence will continue for as many cycle as 3 necessary, determined by the opcode received on the 4 command cycle in byte 0 of the CMD/ADDR register 5 60i. Assuming no error conditions exist, the 6 resultant address from the ADDER 60k is placed on 7 the Storage suS 10f bytes 1-3 during this same 8 cycle. Byte 0 of the Storage Bus will be driven 9 with the value ln the CMD/ADDR register 60i. Figure 10 21A lists the code points used for each length of 11 data transfer. During this cycle, STORAGE COMMAND 12 TIME (one of the storage control 10h signals) will 13 be driven as well as the I/O REQUEST TO D-CACHE 14 signal. This I/O REQUEST TO D-CACHE signals the 15 data cache to gate the command and address into its 16 logic so that a search of the cache can be made to 17 see if the data being updated exists within the 18 cache and to see if the data within that line has 19 been modified. If the data exists but has not been 20 modified, the cache will invalidate that line of 21 t data and allow the storage operation to be done in 22 the memory card. If however, the data does exist 23 and the data within that line has been modified, the 24 data cache will use the data received on data cycles 25 following the command to modify the existing data in 26 the cache. One exception to this procedure exists, 27 and that is , if the write operation is 32 bytes, or 28 a full line within the cache, the data cache will 29 ` not write the data. Instead it invalidates the line 30 within the cache and allows the write to memory. 31 This means that a reference to this data by the IPU 32 will cause the line to be refetched into the cache. 33 All data gated to the storage bus 10f by the storage 34 controller 10g is gated from the DATA OUT register 35 60b. Meanwhile the selected memory card is in the 36 process of accessing the storage location addressed 37 by the address given in bytes 1--3 on the command 38 cycle. On each cycle following the transmission of 39 data to the storage card, the INPUT PARITY line will 40 indicate whether an error was detected, and if 41 active, will be gated to the ERROR DETECTION LOGIC 42 60m, and then relayed to the I/O STATUS register 43 .

60e. The Storage OP Controller 30d puts the eight 3 data Buffers 20a on the Adapter A/D Bus 10nl from T0 4 To T0 during the next eight data cycles~ After the 5 eighth data c~cle, the storage controller 30d waits 6 four cycles to get the final write status from the 7 IOIU on the Status Bus. The Slave Control unit 40b 8 receives the final status from the Adapter sus 9 Controls 30 and puts the ending status on the C/S 10 Bus 10t2. After waiting for the bus to settle, the 11 slave control 40b raises RDY to tell the master 12 control 40a that the Storage Write operation in the 13 IOIC is complete. The IOBU drops master select 14 (MSEL) of control line group 10t4 and then stops 15 driving the A/D Bus 10tl and the O/D Bus 10t3. When 16 the slave control 40b of the IOIC sees MSEL drop, it 17 drops RDY and stops driving the C/S Bus 10t2. The 18 IOBU master control 40a can now drop master steering 19 (MST) of control line group 10t4 which ends the 20 operation. 21 B. Read 32 Bytes Memory Operation 23 , .
This instruction is an SPD Storage Read operation 25 from an IOBU (one of 10p-lOs) to the IOIC (one of 26 10j-lOm). The data read from the IOIV 10e is 27 buffered in the IOIC and then sent to the IOBU. 28 An SPD operation to an IOIC starts when the IOBU 10e 30 sends a REQB to the BCU 50. The BCU 50 raises ACKB 31 to start the bus polling and then raises BUSG when 32 the SPD Bus is free to start another operation. The 33 IOBU that raised the REQB captures the poll and, 34 when it sees BUSG, starts the select cycle. The IOBU 35 drives the ~/D Bus 10tl, C/S Bus 10t2, O/D Bus 10t3 36 and master steering (MST) oE the control line group 37 10t4. A~ter the data on the buses settles down, the 38 IOBU drives master select (MSEL) of the corltrol line 3g group 10t4 telling the IOIC Slave Control unit 40bl 40 that the data is valid. The Slave control 40b 41 decodes the 'lF' cornmand ~see figure 23) from the 42 C/S Bus 10t2 and matches on '00' from the O/D Bus 43 , :

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~2~

10t3. The data on the A/D Bus 10tl is put in the 3 Address Register 20d of figure 3 and A/D Bus 10tl 4 bits 0-5 in the Key Buffer 20c. Then, the IOIC 5 raises RDY to tell the IOBU to continue. During 6 this time, the IOBU drops REQB and the BCU 50 drops 7 ACKB. The IOBU, seeing RDY, drops MSEL and stops 8 driving the buses. After MSEL drops, the IOIC drops 9 RDY and the BCU 50 drops BVSG to end the select 10 cycle. The first data cycle starts when the IOBU 11 drives the O/D Bus 10t3 with its address and, after 12 the buses settle, raises MSEL of control line group 13 10t4 to indicate that the bus data is valid. The 14 slave control 40b decodes the command; the Storage 15 Opcode Translator unit 40c of figure 12 takes the 16 'lF' command and generates a 'D0' Memory Opcode and 17 stores it in byte 0 of the Address Register 20d. 18 Now that the IOIC knows that this a storage read 19 operation, the Storage Op Controller 30d turns the 20 operation over to the Adapter Bus Controls 30 and 21 holds the SPD Bus until the Adapter controls 30 give 22 the Slave controls 40b DATA VALID, indicating that 23 the data is on the Adapter A/D Bus 10nl. The24 Adapter Bus Control 30 storage op controller 30d 25 raises IOIC REQUEST and then waits for IOIC GRANT. 26 When the controller 30d receives IOIC GRAN'r, it 27 drives the K/S Bus 10n2 and the Adapter A/D Bus 10nl 28 from T0 to T0 of the next cycle. The Key bus 10n2 29 contains ~he 370 key and the Adapter A/D bus 10nl 30 contains the first Address Register 20d. Byte 0 of 31 the Address Register 20d is the memory command (see 32 figure 21A) and bytes 1-3 are the starting mernory 33 address. When the storage controller logic 10g (see 34 figure 20) receives the command and address on the 35 cycle following the IOIC GRANT, it gates the 36 information from the ADAPTER BUS 10nl into the 37 CMD/AD~R register 60i. The Key data present on the 38 Key~'Status Bus 10n2 during this same cycle is 39 clocked into the I/O KEY reg 60f. The cycle ' 40 following the command and address will contain the 41 first data sent on the ADAPTER BUS 10nl and is , 42 clocked into the DATA IN reg 60a. In the case of a 43 12~79~

read operation, any data maybe sent with good 3 parity. Simultaneously during this second cycle, 4 the address in the CMD/ADDR register 60i is added to 5 the 370 OFFSET register 60j if the I/O KEY register 6 bit 4 is zero. If bit 4 is a one, then a zero value 7 is substituted for the 370 OFFSET value. The result 8 of the addition from ADDER 60k is gated to the KEY g STACK ARRAY 60h which addresses the key value for 10 that memory address requested. The output of the 11 key stack is gated into the the KEY DATA register 12 60g. The key data in the KE~ DATA register 60g is 13 now compared to the key in the I/O KEY register 60f, 14 by the ERROR DETECTION LOGIC 60m. If the key is 15 acceptable the status gated to the I/O STATUS 16 register 60e will indicate good status. Otherwise, 17 a protection check indication will be set into the 18 register. As~uming no error conditions exist, the 19 resultant address from the ADDER 60k is placed on 20 the Storage Bus 10f bytes 1-3 during this same 21 cycle. Byte 0 of the Storage Bus will be driven ~2 with the value in the CMD/ADDR register 60i. Figure 23 21A lists the code points used for each length of 24 data transfer. During this cycle, STORAGE COMMAND 25 TIME (one of the storage control 10h signals) will 26 be driven as well as the I/O REQUEST TO D-CACHE 27 signal. This I~O REQUEST TO D-CACHE signals the 28 data cache to gate the command and address into its 29 logic so that a search of the cache can be made to 30 see if the data being fetched exists within the 31 cache and to see if the data within that line has 32 been modified. If the data exists but has not been 33 modified, the cache will allow the data to be 34 accessed from the memory card. If however, the data 35 does exist and the data within that cache line has 36 been modi~ied, the data cache will send a signal ~IT 37 & MODIFIED to the storage controller 10g on the 38 cycle following the command time. Receipt of this 39 siynal will cause the storage controller 10g to 1 40 activate the STOR~GE DISABLE signal (part of the 41 storage controls 10h). This will cause the memory 42 card belng accessed to disable its drivers on the 43 EN986033 - 93 _ storage bus 10f and allow the data cache to send the 3 data requested on the storage bus upon receipt of 4 the DATA CACHE GATE DATA signal. A11 data gated to 5 the storage bus 10f by either the memory card or the 6 cache will be gated into the DATA IN register and 7 relayed to the Adapter Bus 10nl on the next cycle 8 from T0 to T0. Refer to timing diagram for storage 9 read operations on figure 27. Any error status 10 received during STORAGE DATA VALID cycles on the 11 storage control lines 10h, will be gated to the 12 error detection logic 60m and relayed to the I/O 13 status register 60e, for transmission during data 14 cycle corresponding to the error. When ADAPTER DATA 15 VALID comes on, for eight cycles, the storage op 16 controller 30d will take the data from the Adapter 17 A/D Bus 10nl and put it i~ the eight Data Buffers 18 20a at T2 time, and will accumulate the read status 19 from the IOIU 20e on the Status Bus at each T2. Now 20 that the IOIC has all of the data, the ~dapter Bus 21 Control unit 30 turns the operation back over to the 2~2 SPD Slave Control Unit 40b. The slave control 40b 23 drives the A/D Bus 10tl with the data in the first 24 Data Buffer 20a and the C/S Bus 10t2 with status 25 ~see figure 26) if there is an error. After waiting 26 for the bus to settle~ the slave IOIC raises RDY. 27 The master IOBU drops MSEL after receiving the data. 28 The slave control 40b drops RDY and stops driving 29 the A/D Bus 10tl and C/S Bus 10t2 to end the ~irst 30 data cycle. I'he second through the seventh data 31 cycles start when the master IOBU raises MSEL to 32 indicate that the it is ready for more data. The 33 slave control 40b drives the A/D Bus 10tl with data 34 from the second thru seventh Data Bu~fers 20a and 35 drives the C/S Bus 10t2 with status i~ there is an 36 error. After waiting for the bus to settle, the 37 slave IOIC (slave control unit 40b) raises RDY. The 38 master IOBU drops MSEL after receiving the data. 39 The slave control 40b drops RDY and stops driving 40 the A/D Bus 10tl and C/S Bus 10t2 to end the data 41 cycle. The eighth data cycle starts when the master 42 IOBU raises MSEL to indicate that the it is ready 43 , EN986033 _ 94 _ for more data. The slave control unit 40b drives 3 the A/D Bus 10tl with data from the eighth Data 4 Buffer 20a and drives the C/S sus 10t2 with ending 5 status or error status, if there was an error, and, 6 after waiting for the buses to settle, raises RDY. 7 The mastex Iosu drops MSEL after receiving the data 8 and stops driving O/D Bus 10t3. The slave control g unit 40b drops RDY~ stops driving the A/D Bus 10tl 10 and the C/S Bus 10t2. The IOBU master can now drop 11 MST which ends the operation. 12 C. Write 6 Bytes Read Modify Write Operation14 This instruction is a SPD Storage Write operation 16 ~rom an IOBU (one of 10p-10s) to an IOIC (one o~ 17 10j-lOm). The data received from the IOBU is 18 buffered in the IOIC and then sent to the IOIU 10e 19 using read modify write command for storage.20 An SPD operation to an IOIC starts when the IOBU ~2 sends a REQB to the BCU 50. The BCU 50 raises ACKB 23 to start the bus polling and then raises BUSG when 24 the SPD Bus (one of 10t-10w) is free to start25 another operation. The IOBU that raised the REQB 26 captures the poll and, when it sees BUSG, starts the 27 select cycle. The IOBU drives the A/D Bus 10tl, C/S 28 Bus 10t2, O/D Bus 10t3 and master steering (MST) of 29 the control line group 10t4 o~ figure 19. After the 30 data on the buses settles down, the IOBU drives 31 master select ~MSEL) of the control line group 10t4 32 telling the IOIC Slave Control unit 40b that the 33 data is valid. The Slave control 40b decodes the 34 '45' command from the C/S Bus 10t2 and matches on 35 '00' from the O/D Bus 10t3. The data on the A/D Bus 36 10tl is put in the Address Register 20d and A/D Bus 37 10tl bits 0-5 in the Key Bu~fer 20c. Then, the IOIC 38 raises RDY to tell the IOBU to continue. During 39 this time, the IOBU drops RE~B and the BCU 50 drops 40 ACKB. The IOBU, seeing RDY, drops MSEL and stops 41 driving the buses. After MSEL drops, the IOIC drops 42 RDY and the BCU 50 drops BUSG to end the select 43 EN986033 95 _ ~25~
cycle. The first data cycle starts when the IOBU 3 drives the A/D sus 10tl ~ith the data and the O/D 4 Bus 10t3 with i-ts address and, after the buses 5 settle, raises MSEL to indicate that the bus data is 6 valid. The slave control 40b puts the data from the 7 A/D Bus 10tl into the even Data Buffer 20a pointed 8 to by the address. The slave control 40b drives the 9 C/S sus 10t2 with status (see figure 26) if there is 10 an error and, after waiting for the bus to settle, 11 raises RDY. The IOBU drops MSEL and stops driving 12 the A/D Bus 10tl. The IOIC slave control 40b drops 13 RDY and stops driving the C/S Bus 10t2 to end the 14 first data cycle. While the data cycles are in 15 process, the Storage Opcode Translator unit 40c of 16 figure 12 takes the '45' comman, generates a 'B8' 17 Memory Opcode, and stores it in byte 0 of the 18 Address Register 20d. The second data cycle starts 19 when the IOBU drives the A/D sus 10tl with the data 20 and, after the bus settles, raises MSEL to indicate 21 that the bus data is valid~ The slave control 40b 22 puts the data from the A/D Bus 10tl into the odd 23 Data Buffer 20a pointed to by the address. Now that 24 the IOIC has all of the data, the Slave Control unit 25 40b turns the operation over to the Adapter Bus 26 Controls 30 and holds the SPD Bus until the Adapter 27 controls 30 give the Slave control unit 40b final 28 status. The Adapter Bus Control 30 storage op 29 controller 30d raises IOIC REQUEST and then waits 30 for IOIC GRANT. When the controller 30d receives 31 IOIC GRANT, it drives the K/S Bus 10n2 and the 32 Adapter A/D Bus 10nl from T0 to T0 of the next 33 cycle. The Key bus 10n2 contains the 370 key and 34 the Adapter A/D bus 10nl contains the first Address 35 Register 20d. Byte 0 of the Address Register 20d is 36 the memory command (see figure 21A) and bytes 1-3 37 are the starting memory address. The controller 30d 38 puts the two Data Buffers 20a on the Adapter A/D Bus 39 10nl from T0 To T0 during the next two data cycles. 40 When the storage controller logic 10g (see figure 41 20) receives the command and address on the cycle 42 following the IOIC GRANT, it gates the information 43 , from the ADAPTER BUS 10nl into the CMD/ADDR register 3 60i. The Key data present on the Key/Status Bus 4 10n2 during this same cycle is clocked into the I/O 5 KEY reg 60f. The cycle following the command and 6 address will contain the first data sent on the 7 ADAPTEX BUS 10nl and is clocked into the DATA IN reg 8 60a. Simultaneously during this second cycle, the 9 address in the CMD/ADDR register 60i is added to the 10 370 OFFSET register 60j if the I/O KEY register bit 11 4 is zero. If bit 4 is a one, then a zero value is 12 substituted for the 370 OFFSET value. The result of 13 the addition from ADDER 60k is gated to the KEY 14 STACR ARRAY 60h which addresses the key value for 15 that memory address requested. The output of the 16 key stack is gated into the the KEY DATA register 17 60g. The key data in the KEY DATA register 60g is 18 now compared to the key in the I/O KEY register 60f, 19 by the ERROR DETECTION LOGIC 60m. If the key is 20 acceptable the status gated to the I/O STATUS 21 register 60e will indicate good status. Otherwise, 22 a protection check indication will be set into the 23 registerO On the second data cycle, the data in the 24 DATA IN register 60a, will be clocked into the DATA 25 OUT register, while the data from the ADAPTER BUS 26 10nl is clocked into the DATA IN register. Assuming 27 no error conditions exist, the resultant addxess 28 from the ADDER 60k is placed on the Storage Bus 10f 29 bytes 1-3 during this same cycle. Byte 0 of the 30 Storage Bus will be driven with the value x'F8' 31 which is the first cycle command of the two step 32 Read Modify Write storage operation. During this 33 cycle, STORAGE COMMAND TIME (one of the storage 34 control 10h signals) will be driven as well as the 35 I/O REQUEST TO D-CAC~E signal. This I/O REQUEST TO 36 D-CACHE signals the data cache to gate the command 37 and address into its logic so that a search of the 38 cache can be made to see if the data being updated 39 exists within the cache and to see if the data 40 within that line has been modified. If the data 41 exists but has not been modified, the cache will 42 invalidate that line of data and allow the storage 43 EN986033 ~ 97 -operation to be done in the memory card. If 3 however, the data does exist and the data within that line has been modified, the data cache will use 5 the data received on the two cycles following the 6 command to modify the appropriate data within the 7 specified cache line. The first data cycle 8 information sent by the storage controller 10g is 9 gated from the DATA OUT register 60b. The second 10 data cycle information sent by the storage 11 controller 10g is ga-ted from the DATA IN register 12 60a. These two data cycles are not clocked into 13 the memory cards. Meanwhile the selected memory 14 card is in the process of accessing the storage 15 location addressed by the address given in bytes 1-3 16 on the command cycle. After three access cycles 17 have passed, the storage card will send the STORAGE 18 DATA VALI~ signal, which indicates the access has 19 finished, the double word of data is in its data 20 register and is now ready to accept the write 21 portion of the two cycle RMW storage operation. The ~2 cycle following the receipt of STORAGE DATA VALID, 23 signals the storage controller to send the STORAGE 24 COMMAND TIME signal again and also gate the address 25 again on bytes 1-3 of the storage buss 10f. Byte 0 26 will now contain the x'B8' command which is still in 27 the CMD/ADDR register 60i. The next two cycles 28 following the command will contain first the data in 29 the DATA OUT register 60b, followed by the data in 30 the DATA IN register 60a. On each cycle following 31 the transmission of data to the storage card, the 32 INPUT PARITY line will indicate whether an error was 33 detected, and if active, will be gated to the ERROR 34 DETECTION LOGIC 60m, and then relayed to the I/O 35 STATUS register 60e. After the second data cycle, 36 the storage op controller 30d of figure 10 waits for 37 DATA VALID from the IOIU 10e and then counts four 38 cycles to get the final write status from the IOIU 39 10e on the Status Bus. The Slave Control unit 40b 40 receives the final status from the Adapter Bus 41 Controls 30 and puts the ending status on the C/S 42 Bus 10t2. After waitin~ for the bus to settle, the 43 slave control 40b raises RDY to tell the master 3 control 40a that the Storage Write operation in the 4 IOIC is complete. The IOBU drops MSEL and then 5 stops driving the A/D Bus 10tl and the O/D Bus 10t3. 6 When the slave IOIC (slave control unit 40b) sees 7 MSEL drop, it drops RDY and stops driving the C/S 8 Bus 10t2. The Iosu master control unit 40a can now 9 drop MST which ends the operation~ 10 The invention being thus described, it will be 12 obvious that the same may be varied in many ways. 13 Such variations are not to be regarded as a 14 departure from the spirit and scope of the 15 invention, and all such modifications as would be 16 obvious to one skilled in the art are intended to be 17 included within the scope of the following claims. 18 .
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EN986033 ~ 99 _

Claims (32)

1. A system for interconnecting a high speed bus and a low speed bus including an interface section and a main section, said interface section adapted to join said low speed bus to said main section of said system, said interface section comprising address and data communication means attached to the main section of said system for conducting address information or data information between said low speed bus and said main section of said system;
command and status communication means attached to the main section of said system for conducting command information or status information between said low speed bus and said main section of said system; and origin and destination communication means attached to the main section of said system for conducting origin address information or destination address information between said low speed bus and said main section of said system.

2. The interface section of claim 1, further comprising:

control communication means attached to the main section of said system for conducting control information between said low speed bus and said main section of said system.

3. The interface section of claim 2, wherein said low speed bus is an asynchronous bus.

4. The interface section of claim 1, wherein said address and data communication means conducts key information between said low speed bus and said main section of said system during a select cycle of a storage write to storage operation or a storage read from storage operation, said address and data communication means conducting a word of data between said low speed bus and said main section of said system during a data cycle of said storage write to storage operation or said storage read from storage operation.

5. The interface section of claim 4, wherein said command and status communication means conducts write command information and a number of bytes of data during a select cycle and completion status during a subsequent data cycle of a storage write to storage operation, said command and status communication means conducting read command information and a number of bytes of data during a select cycle and completion status during a subsequent data cycle of a storage read from storage operation.

6. The interface section of claim 5, wherein said origin and destination communication means conducts said destination address information during a select cycle and an address of said system representing said origin address information during a subsequent data cycle of a storage write to storage operation, said origin and destination communication means conducting said origin address information during a select cycle and an address of said system representing said destination address information during a subsequent data cycle of a storage read from storage operation.

7. The interface section of claim 1, wherein said address and data communication means conducts data information between said low speed bus and said main section of said system during a unit write operation or a unit read operation.

8. The interface section of claim 7, wherein said command and status communication means conducts a write command during a select cycle of a unit write operation and a read command during a select cycle of a unit read operation, said command and status communication means conducting a completion status during a subsequent data cycle of the unit write operation and the unit read operation.

9. The interface section of claim 8, wherein said origin and destination communication means conducts said destination address information during a select cycle and conducts an address of said system representing said origin information during a subsequent data cycle of a unit write operation, said origin and destination communication means conducting an address of said system representing said destination address information during a select cycle and conducting said origin address information during a subsequent data cycle of a unit read operation.

10. The interface section of claim 9, wherein said system is a master during said unit read operation and said unit write operation.

11. The interface section of claim 21 wherein said address and data communication means conducts said control information during a select cycle of a unit write direct operation and a unit read direct operation and conducts data during a data cycle of said unit write direct operation and said unit read direct operation.

12. The interface section of claim 11, wherein said command and status communication means conducts a write command during a select cycle of a unit write direct operation and conducts a completion status during a data cycle of the unit write direct operation.

13. The interface section of claim 12, wherein said origin and destination communication means conducts an address of said device during a select cycle and a data cycle of a unit write direct operation.

14. The interface section of claim 1, wherein:

said address and data communication means conducts data during a data cycle of a message acceptance operation;

said origin and destination communication means conducts an address of said system during said data cycle of said message acceptance operation;
and said command and status communication means conducts a completion status following the conducting of said data via said address and data communication means during said data cycle of said message acceptance operation.

15. The interface section of claim 2, wherein said control. communication means comprises:

tag communication means for conducting a first portion of said control information between said low speed bus and said main section of said device, said tag communication means including, a master steering signal line means for conducting control information indicating possession of said low speed bus, a master select signal line means for conducting control information acknowledging the placement of data on said low speed bus and the validity of said data, and a ready signal line means for conducting control information acknowledging receipt of said data placed on said low speed bus and communicating a possible intent to conduct further data via said low speed bus.

16. The interface section of claim 15, wherein said control communication means further comprises:

card select communication means for conducting a second portion of said control information; and board select communication means for conducting a third portion of said control information, said address and data communication means conducting said second portion of said control information associated with the card select communication means and conducting said third portion of said control information associated with the board select communication means during a select cycle of a unit write direct operation and a unit read direct operation.

17. The interface section of claim 16, wherein said control communication means further comprises:

arbitration communication means for conducting arbitration signals which request access to said low speed bus by said device, determine priority of access to said low speed bus by said system, and grant access to said low speed bus by said system.

18. The interface section of claim 17, wherein said control communication means further comprises:

control line communication means including a bus clear line means for conducting a bus clear signal thereby causing said system to cease operation when said bus clear line means is active.

19. The interface section of claim 18, wherein said control line communication means includes a monitor clock line means includes a monitor clock line means for conducting a monitor clock signal which causes said system to collect status in the event a timeout has occurred during the use of said low speed bus.

20. A method of performing a storage operation in conjunction with a main store over a first bus which interconnects a controller device to at least one input output bus unit (IOBU), said controller device being connected to said main store via a second bus, said first bus including an address data bus, a command status bus, and an origin destination bus, comprising the steps of:

transmitting information between said IOBU and said controller device via said first bus, a first part of said information being transmitted between said IOBU and said controller device via said address data bus of said first bus, a second part of said information being transmitted between said IOBU and said controller device via said command status bus of said first bus, a third part a said information being transmitted between said IOBU and said controller device via said origin destination bus of said first bus; and writing said information from said controller device to said main store or reading said information from said main store to said controller device via said second bus.

21. The method of claim 20, wherein, during a select cycle of a write to storage operation, said first part of said information includes key information and starting main store address information, the transmitting step including the step of transmitting said key information and said starting main store address information from said IOBU to said controller device via said address data bus of said first bus.

22. The method of claim 21, wherein, during said select cycle of said write to storage operation, said second part of said information includes a write command and a number representing the number of bytes of data to be stored in said main store, the transmitting step including the step of transmitting said write command and said number of bytes of data from said IOBU to said controller device via said command status bus of said first bus.

23. The method of claim 22, wherein, during said select cycle of said write to storage operation, said third part of said information includes an address of said controller device, the transmitting step further including the step of transmitting said address of said controller device from said IOBU to said controller device via said origin destination bus of said first bus.

24. The method of claim 20, wherein, during a data cycle of a write to storage operation, said first part of said information includes a word of data, the transmitting step including the i step of transmitting said word of data from said IOBU to said controller device via said address data bus.

25. The method of claim 24, wherein, during said data cycle of said write to storage operation, said third part of said information includes an address of said IOBU, the transmitting step including the step of transmitting said address of said IOBU from said IOBU to said controller device via said origin destination bus.

26. The method of claim 25, wherein said controller device buffers said word of data until said word of data is received from said IOBU, said controller device generating storage commands and transferring the word of data to said main store, said controller device receiving data status information from said main store when said word of data is received by said main store; and wherein during said data cycle of said write to storage operation, said second part of said information includes completion status information, the transmitting step including the step of:
transmitting said completion status information from said controller device to said IOBU via said command status bus of said first bus when said word of data has been transferred to said main store and said data status information has been received by said controller device from said main store.

27. The method of claim 20, wherein, during a select cycle of a read from storage operation, said first part of said information includes key information and starting main store address information, the transmitting step comprising the step of transmitting said key information and said starting main store address information from said IOBU to said controller device via said address data bus.

28. The method of claim 27, wherein during the select cycle of the read from storage operation, said second part of said information includes a read command and a number representing the number of bytes of data to be read from said main store, the transmitting step including the step of transmitting the read command and the number representing the number of bytes of data from said IOBU to said controller device via said command status bus.

29. The method of claim 28, wherein, during the select cycle of the read from storage operation, said third part of said information includes an address of said controller device, the transmitting step including the step of transmitting said address of said controller device from said IOBU to said controller device via said origin destination bus.

30. The method of claim 20, wherein, during a data cycle of a read from storage operation, said third part of said information includes an address of said IOBU, the transmitting step including the step of transmitting said address of said IOBU from said IOBU to said controller device via said origin destination bus of said first bus.

31. The method of claim 30, wherein said controller device generates a storage command and receives a word of data from said main store in response thereto, said controller device temporarily buffering said word of data therein; and wherein during the data cycle of the read from storage operation, said first part of said information includes said word of data, the transmitting step including the step of transmitting said word of data from said controller device to said IOBU via said address data bus of said first bus.

32. The method of claim 31, wherein, during the data cycle of the read from storage operation, said second part of said information includes completion status information, the transmitting step including the step of transmitting said completion status information from said controller device to said IOBU via said command status bus after said word of data is transmitted from said controller device to said IOBU.