CA1297998C

CA1297998C - Interconnection system for integrated circuit chips

Info

Publication number: CA1297998C
Application number: CA000573801A
Authority: CA
Inventors: Louis Edmond Chall, Jr.
Original assignee: Loral Aerospace Corp
Current assignee: Lockheed Martin Tactical Systems Inc
Priority date: 1987-11-06
Filing date: 1988-08-04
Publication date: 1992-03-24
Anticipated expiration: 2009-03-24
Also published as: EP0315792A2; CA1319204C; CA1319205C; EP0315792B1; DE3853764T2; JP2727204B2; DE3853764D1; EP0315792A3; CA1319203C; CA1319202C; JPH01150348A; US4858072A

Abstract

ABSTRACT

A novel packaging system for VLSI circuits allows low-cost construction and maintenance of complex high density high-performance devices with low power requirements. The devices can be individually created by software means from a small selection of standardizable IC chips by disposing a plurality of chips in leadless chip carriers in a mosaic on a substrate, and configuring them by software to selectively communicate with other chips of the mosaic or even to individually change their operating function. The immediate juxtaposition of the chip carries in the mosaic eliminates transmission line data skew, and also allows considerable savings in chip space and power requirements by dispensing with interconnection drivers, receivers and bonding pads. The chip carrier mosaics may be assembled into modules suitable for plug-in connection to an interconnecting backplane to create even larger devices, and individual modules can be dynamically tested in their high-performance mode by configuring one or more modules as test modules and either plugging them into modules to be tested or making them a permanent part of the device's module array.

Description

INTERCONNECTION SYSTEM FOR TNTEGRATED CIRCUIT c~nPS

Field of the Inven~ion This invention rel~tes to integrated circuits, and more particul~rly to a p~ck~ging system which eliminates the .Idverse effects of long transrnission lines and of the resulting data skew, and which allows a wide variety of very l~rge scale integrated circuits for very high performance electronic devices to be built from a small selection of standard modules containing only a few types of 1 0 standard chips.

Back~round of the Invention The proliferation of VLSI (very large scale integration) chips for the rniniaturization of complex electronic equipment has brought about new kinds of problems which tend to defeat the advantages of VLSI technology. Among others, these problems include: 1) the large number of terminals associated with VL,SI
chips produces complex, expensive circuit board layouts and long interconnection lirles which in turn cause skew problems and require high power consuming, heat-generating drivers; 2) a failure in any part of the chip usually makes the whole chip inoperative; and 3) the vast number of specialized chips available on the market results in uneconomical short runs and makes it difficult for designers to keep up with what the market has to ofter.
Prior art in this field includes U.S. Patent No. 3,611,317 which deals with printed circuit board layouts but does not teach elimination of long IC interconnections nor a universal board configuration; U.S. Paterlt No. 4,107,760 which shows a flat peripheral heat sink for a circuit board which does not encounter the thermal expansion compensation problems solvecl by this invention; U.S.
Patent No. 4,246,597 which shows an add-on device for cooling a multi-chip mod~lle; IJ.S. Paten~ No. 4,296,~56 which deals with a lligh-bandwidth IC package but does not sllow the leadless I/0 serial data connection scheme of tllis invention; U.S. Patent No. ~,398,208 which deals with an IC package tllat uses ~ multilayer substrate but does not have the leadless interconnection feature of this invention;

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U.S Patent No. 4,437,141 which deals with outside-world connections for large terminal count IC chips; U.S. Patent No. 4,484,21~ which deals Wit}l a flexible mounting support for immersion cooling of wafer scale IC's; U.S. Patent No. 4,~89,363 which deals with a cooling 5 method not suited to high density IC packaging; U.S Patent No.
4,549,200 which deals with a multi-level modul~r approach not suited to the leadless packaging of this invention; U.S. Patent No.
4,5~ 1,746 which relates to a stacked chip array; and U.S. Patent No.
4,578,697 which deals with a packaging method using printed-10 circuit-type interconnections.
I

Summarv of the Invention The invention overcomes the problems of the prior art by providing a packaging scheme that uses standardizable modules carrying planar mosaics of many integrated circuit chips which may be selected from a very small variety of standardizable IC chips. The individual chips, which are leadlessly interconnected and have no need for high-powered drivers, are then combined by software techniques into large-scale arrays of any desired configuration, in which the interface and communications, protocol are standardized for all chips. Modules can in turn be interconnected by fiber optic and electrical connectors to create very high perform;lnce electronic devices of any desired size and architecture which can be tested on a module-by-module basis.
The multiple chip interfaces provide fault tolerance capability. Because the C}lip mosaic providcs many possible paths from one chip to another, eacJl mosaic can easily be programmed to take a defective C}lip out of the circuit with little or no effect on the overall device.
3 0 The individual C}lipS are mounted on leadless carriers which can take various geometric forms; althoug}l hexagons are preferred, the carrier geometry of this invention is equally applicable to squares, rectangles or any ot}-er carrier shapes which have a plurality of sides interfacing with sides of several adjacent carrier chips.

~129~7~9~3 The le~dless interconnection scheme of this invention is made possible in part by providing, in conjunction with each set of leadless interconnections, a serializing/deserializing interface which greatly reduces the number of intcrconnections needed from chip to S chip. In the preferred embodiment of the invention, each set of interconnections requires only three connection pads: a high-speed incoming data connection pad, a high-speed outgoing data connection pad, and a low-speed bidirectional configur;ltion signal connection pad. The serializing/deserializing interfaces are preferably formed of gallium arsenide for high-speed operation.
Another aspect of the invention is the provision of highly effective cooling means in the form of a corrugated sheet of thermally and electrically conductive material w;th interdigitated slots. When the sheet is soldered to a ground plane of the module, the slots allow the sheet to accommodate the different expansion coefficient of the ground plane substrate. At the same time, the electrical conductivity of the sheet enhances the power-carrying capacity of the ground plane.

Brief Description of the ~rawin~
Fig. 1 is ~ perspective, partially cut away view of a module rack having a backplane and carrying a plurality of the process modules of this invention, one of the modules being partially pulled out to show detail;
Fig. 2 is an enlarged perspective view, partially cut away, of a single process module;
Fig. 3 is a plan view of an alternative embocliment of tlle module of Fig. 2;
Fig~ 4 is a detail cut-away perspective view of a portion of the circuit board assembly of the module of Fig. 2;
Fig. 5 is a bottom perspective view of a single chip carrier of the module of Fig. 2;
Fig. 6 is a top plan view of the chip carrier of Fig.
showing details of portions o~ the chip;
Fig. 7 is a vertical section along line 7-7 of Fig. 6;

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Fig. 8 is a detail vertical section through a chip carrier and the substrate of the module of Fig. 2 ~long a diameter of the chip carrier;
Fig. 9 is a plan view of the circuit board substrate at the 5 connection between two adjacent chip carriers;
Fig. 10 is a plan view of a portion of a mosaic of chip carriers, with their caps removed, on the module of Fig. 2;
Fig. 11 is a block di~gram of the configuration circuitry of the chip of Fig. 6; and Figs. 12a through 12d illustrate various possible mosaics of chip carriers.

Description of the Preferred Embo~iment Fig. 1 shows a module rack 20 in which any number of process modules 22a, 2~b through 22n may be plugged into the female connectors 21 a backplane 24 by male connectors 21 to form a specific electronic device. The baclcplane 24 contains the fiber optic and electric interconnections (not shown) necessary to connect each of the modules 22a through 22n to one or more of the other modules 22a through 22n in such a manner as to crcate whatever hard-wired array of modules 22 the particular device may require.
The end 25 of each module opposite the backplane 24 is equipped with a set of fiber optic and female electrical connectors which allows a test module (not shown) structurally similar to the modules 22 but software-configured as a test module to be plugged into it end-to-end for the dynamic testing of each individu;ll module.
Due to the extremely high operatin~ specds of which the system of this invention is capable, conventional test equipmcnt may not be suitable. Instead, Icnown data may be generated by the device, and 3 0 the data stored in the test module as a result thereof may be used as a diagnostic tool in evaluating the performance of the tested module.
~Iternatively, one or more of the modules 22a though 22n may be programmed to function as permanent test modules connectable to appropriate evaluation equiptnent.
~n individual process module 22 of this invention is shown in more detail in Fig. 2. The module 22 consists of a pair of '79~8 parallel circuit boards 26, 28 which are reflow soldered to a heat sink structure 30.
The heat sink structure 30 preferably consists of a corrugated, highly heat-conductive and electrically conducti~e material which has a large number of interdigitated saw kerfs or apertures 32 formed therein to allow -for the dif~erent S coefficien~ of expansion of the circuit boards 26, 28 in the vertical direction in Figure 2. ~ir or coolant can flow through the heat sink structure 30 in the direction of arrows 33, and out of the Figure 1 rack through ventilation grille 35 or other suitable circulation means. The heat sink structure also provides additional current-carrying capacity for the ground plane 60 (Figure 4)of the circuit boards 26, 28.
As best shown in Figure 2, the circuit boards 26, 28 carry a mosaic of hexagonal chip carriers 36 (eighty-one per board in the embodiment shown in Figure 2). The chip carriers 36 are shown in more detail in Figs. S through 7. As best illustrated in Figure 10, the individual chip carriers 36 of the mosaic 34 are placed in immediate adjacency to each other (typically less than 0.1 mm apart).
They are interconnected by reflowing solder from microstrips 38 (Fig. 9) into the generally cylindrical tube 40 -formed by the opposing semi cylindrical connection pads 42 of adjacent chip carriers 36.
Coming back to Figure 1, a clriver strip 44 may be placed at each end of the mosaic 34 to contain the receivers and drivers Eor the outside-worlclfiber optic connectors 46 and electrical connectors 48 locatecl in the Eemale and male connector blocks S0, 52, respectively. Alternatively, the Eiber optic drivers and receivers may be incorporated in speckll chip carriers 36 which are part oE the mosaic 34 but which mllst then be place(l in specitic positions arld speciEic orientations to match positions Eor optical fibers in the circ~lit boarcls 26, 28. Six Eiber optic connectors 46 and six electrical connectors 48 have been shown in Figure 2 for clrawing clarity, but it will be llnderstood that their nllmber may vary as dictatecl by design consiclerations.
Altho~lgh the invention has so Ear been described in terms ot card-like modules 22 (Figs. 1 and 2) suitable for insertion into a rack 20 for plug-in connection to a backplane 24, the modules of this invention may be carried out in other configurations such as, ~29~9~

for example, the circularly configured module 70 of ~ig. 3. In th,lt configuration, the fiber optic and eleetric~l connectors (not shown~ of the module 70 may be on the rim of moclule 70 or at some other convenient loc~tion.
The circuit boards 26, 28 are shown in more detail in Fig.
4. Each of the boards 26, 28 consists of two insul~ting layers 54, ~6 preferably composed of aluminum nitride whieh separate a pair of conductive ground planes 58, 60 *om a conductive power plane 62.
In the center of eacll chip position of the mosaic 34 (Fig. 2), the ground plane 58 is eut out to allow a solder pad 64 eleetrically connected to the power plane 62 to protrude through the ground plane 58. The ground plane 60 is soldered to the heat sink 30, and the solder pads 64 are preferably centered (line 65) along the solder lines (indicated by dot-dash line 67 in Fig. ~) connecting the heat sink 30 and the ground plane 60 on each side of the module 22. The ground planes 5 ~, 60 are connected to eaeh other by connector pins 66.
Figs. 5 throu~h 7 illustrate the leadless chip carriers 36 which form the mosaic 3~. In the preferred embodiment, the chip carriers 36 are hexagonal in shape because a hexagonal mosaic is efficient and easy to assemble (and also tends to align itself during reflow soldering), but other mosaics may also be used as shown in Figs. 12a through 12d.
In this respect, it should be noted that from an assembly point of view, the c)rientation of any indivicl~lal el1ip earrier 36 is immaterial, as its connection pad sc,ts 72 will always matell the positions of every adjaeent earrier's eonnection pad sc,ts. The same is true of the arrangement of Fig. 12a (which however requires eight connection pad sets per carrier instead of six); that of Fig. 12b (in 3 0 wlliell eae}l earrier has only two possible orientations); ancl that of Fig. 12c (in whieh eaeh chip can communicate with only four otller ehips instead of six). By contrast, in the arrangement of Fig. 12d, two oP the fol~r possible orientations of any carrier would result in a mismateh, so that more care woulcl have to be exereised in assembly.
3 5 Returning now to Fig. 5, the ehip carrier 36 ineludes a tray-shaped body 73 for reeeiving an integrated eireuit ehip. As a ~L2~317~

matter of gener.ll reference, the body 73 m.ly h~ve a di~meter on the order of one centimeter. As seen from ~he bottom in Fig. 5, the body 73, which is preferably m~de of aluminum nitride, has a met~llic ground plate 7~ which is reflow soldered to the ground plane 58 (Fig.
5 4) of the module 22. The ground plate 74 is spaced from the semicylindrical metallic connection pads ~2 which ex~end upwardly from the base. It is also cut out in the center to form a metallic power connector plate 76 which is reflow soldere~ to the power pad 64 of Fig. 4. Connections 78, 80 (Fig. 7) extend from the ground plate 74 and power connector plate 76 through the body 73 to appropriate contacts on the integrated circuit chip die 82 mounted in the cavity of body 73.
As shown in Fig. 8, a ring-shaped depression 84 formed in body 73 op~osite a similar depression 86 in the substrate 54 of the eircuit board 26 or 28 (Fig. 4) is preferably provided to prevent solder from flowing across the gap between ground plate 74 and power connector 76.
Fig. 6 shows the details of the chip die 82 and its interconnection with the connection pad sets 72. The die 82 carries in its center a processorl, memory, or other function circuit 88 capable of being statically and dynamically configured, through multiplexers and electronic switches, to receive data from a selected set of connection pad sets 72, carry out a computational function, and transmit data through the same or another selected set of connection pad sets 72. If the circuit 88 is to serve merely as a transit path for the data without performing any computntional function, multiplexers in the cireuit 88 can be set to route clata directly from one set of connection pad sets 72 to another with min;mum delay.
The manner in which this is done will be discussed in more detail in 3 0 the description of Fig. 11. In the preferred embod;ment of the invention, each connection pad set 72 eontains three eontacts ~2 (Fig.
5), one of whieh handles ineoming high-speed data, another outgoing high-speed data, and the third bidirectional slow-speed configuration signals .
Surrounding the function circuit ~8 are a voltage impedanee interface 90 with contacts 92 for the slow-speed static 7~gl3 configuration input/output 94 of Figure 11, and a high-speed data interface 96 which serves as the data input/output 98, 100 of Figure 11. The high-speed data circuitry carries clock and data signals simultaneously for each connection pad set 72 (at which the arrows indicate the direction of signal travel), the interface 96 S carries a corresponding set of contacts including an input contact 102 and an output contact l 04. In accordance with one aspect of the invention, the interface 96 also carries a serializing shift register 106 and a deserializing shift register 108 for each set of interconnections 72. If the fimction circuit ~38 is a parallel device, as it would usually be in high-density high performance systems, serializing thechip-to-chip connections allows the number of connection pads 42 in each set of interconnections 72 to be reduced to a rnanageable number, considering the smallphysical size of the chip carriers 36.
For high-performance ~levices, it is desirable to form at least the high-speed interEace 96 and possibly the function circuit 88 of gallium arsenide1,5 alone, or of gallium arsenide grown on a silicon base. The silicon provides a superior thermal path for heat transfer out of the circuit die 82. For lower speed devices, however, silicon alone would be a satisfactory mater;al.
In accordance with conventional integrated circuit chip construction, the leads 110, shown schematically in Figure 6, are embodied in a lead frame 112(Figure 7) which is assembled with the die 82 and carrier body 73 by a conventional tape a~ltomated bonding assembly process. A separator 114(~igure 7~and cap :LL6 complete the assembly Oe chip carrier 36.
Figures 9 and 10 illustrate the assembly Oe the chip carriers 36 into the mosaic 34. The carriers 36 are placed into the mosaic 34 asstlown in Figure 10, with a gap ot about 0.1 mm between them to perrnit inspection ot the solclerconnections. Underneath each set oE connection pad sets 72, the ground plane 58 is cut out as shown at 117 in E;igure 9 to form the solder-covered electrically isolatecl microstrips 38. When the cElrriers 36 Elre in place and the moclule 22 is retlow soldered, the solder erom strips 38 rises in the cylinclrical tube 40 formed by opposing connection pads 42 and joins them together both physically and electrically. At the same time, as seen , : :

~L2~ 8 in Fig. ~, the c~rrier's ground pl:~te 74 and power connector plate 76 ~re mechanic~lly and electrically joined to the ~round plane 58 ;lnd power pad 64, respectively, of the circuit board 26 or 28.
Fig. 11 shows, in block form7 the organiz.ltion of eacll chip 82. In accordance with tl~e invention, the operation of the module 22 involves both ~ st~tic ~nd a dynamic s~lection of the configur~tion of each Cllip 82. Slow-speed st~tic configuration selection signals are applied to each chip 82 through its six contacts 92 (Fig. 6~. These signals establish the basic configuration of tlle mosaic 34 (usually done during initialization on power-up starting from a known interface) by defining paths which data signals follow as they progress through the mosaic 34. Amon~ other things, this arrangement allows the static configuration of the mosaic 34 to be changed from time to time to route data around any chips 82 which might be defective, without taking the module 22 out of service.
Dynamic configuration of the chip 82 is accomplished by the received high-speed data itself. Each of the six input contacts 102 of the interface 96 (Fig. 6) is connected at the data input 98 of Fig. 11 to a separate receiver 122 which can be connected to any one of the deserializing shifts registers 108 or drivers 142 to bypass the function circuit 88) by multiplexers 124. The multiplexers 124 are statically configured by the reconfiguration control 126 over lines 128. The shift registers 108 are statically configured by the control 126 over lines 130, and the data received by them is in turn used to operate the eontrol 126. dynamically over lines 132.
The function circuit 88 can be both dynamically and statically configured by control 126 over lines 134 to change tlle operational architecture of circuit 88 as desired. At the output of circuit 88, the serializing registers 106 interact with control 126 as do shift registers 108, but over lines 136 and 138, respectively, for static and dynamic reconfiguration. The output multiplexers 140 are static.llly configured by control 126 via lines 141 to connect any given serializing register 106 or receiver 122 to an output driver 142 associatecl witll an output contact 104 (Fig. 6) of the output interface 100 (or with one of the multiplexers 124 of Fig. 11 for reentry into function circuit 88).

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It will be seen that the present invention prov;des a packaging scheme which allows low-cost manufacture and m~intenance of highly complex, yet low-power high perform~nce devices requiring only a small selection of simple, inexpensive 5 standardi~ed components which can be quickly configured into any desired form by software alone. In another aspect, the invention provides a communication scheme and a high-performance processor architecture, all based on controlling the configuration of multiple standarizable chips by software techniques. At the same time, the 10 system of this invention eliminates the problem of data skew and delay in VLSI deviccs by eliminating leads between chip carriers, and makes the devices built with the inventive system easy to test and repair, sometimes without even taking them out of service.
The leadless architecture of the module of this invention 15 permits a power reduction of up to 90% per chip, while the omission of interconnection drivers, receivers and bonding pads saves on the order of 55% of the normally required chip space. The ability of the chip carrier to accomodate up to 1.5 W per chip is thus adequ;lte to house chips which would normally dissipate seven to ten watts, or 20 even up to fifteen watts.

Claims

1. A leadless interconnection system for integrated circuits, comprising:
a) a substrate for supporting chip carriers;
b) a plurality of chip carriers mounted on said substrate adjacent to each other, each of said carriers including:

i) a carrier body having a geometric shape such that said carriers may be disposed on said substrate to form a mosaic;

ii) connection pads so arranged on the periphery of said geometric shape of said body that when said carriers are disposed in said mosaic, each connection pad is immediately adjacent to a corresponding connection pad of another carrier of the mosaic;

iii) an integrated circuit chip mounted on said carrier body;

iv) said chip, carrier and mosaic being so configured as to allow said chip to selectively transmit and receive data to and from a chip on any adjacent carrier through said connection pads; and c) immediately adjacent ones of said connection pads being electrically connected to each other without the use of intervening wires or leads formed on said carrier.

2. The system of Claim 1, in which said substrate is a circuit board having a conductive ground plane and a conductive power plane separated by an insulating layer, said power plane being electrically connected to a first portion of the underside of said chip carriers, and said ground plane being electrically connected to a second portion of the underside of said chip carriers.

3. The system of Claim 2, in which said first portion is surrounded by said second portion.

4. The system of Claim 2, in which the material of said insulating layer and the material of said chip carrier body is aluminum nitride.

5. The system of Claim 2, in which said circuit board includes a second conductive ground plane separated from said power plane by a second insulating layer on the opposite side of said power plane from said first-named ground plane, and an electrically conductive heat sink conductively bonded to said second ground plane.

6. The system of Claim 5, in which said ground planes are electrically connected through said insulating layers.

7. The system of Claim 5, in which said heat sink includes a corrugated sheet of heat-conductive material, said sheet having interdigitated elongated apertures therein to compensate for the differing heat expansion coefficients of said heat sink material and said substrate.

8. The system of Claim 2, in which said body carries on its underside a ground plate and a power connector plate connected to said chip, said ground plate and power connector plate being electrically and mechanically connected to said ground plane and said power plane, respectively.

9. The system of Claim 8, in which said ground plate surrounds said power connector plate.

10. The system of Claim 1, in which said chip carriers have a geometric shape and connection pad disposition such that their orientation in the mosaic is immaterial.

11. The system of Claim 10, in which said chip carriers are hexagonal, and said connection pads are located in the center of each side of said hexagon.

12. The system of Claim 10, in which said chip carriers are rectangular, and each carrier has two sets of connection pads on each long side, and one set of connector pads on each short side.

13 13. The system of Claim 10 in which said chip carriers are square, and each carrier has two sets of connection pads located on each side.

14. The system of Claim 10, in which said chip carriers are square, and each carrier has one set of connection pads located in the center of each side.

15. The system of Claim 1, in which said body is made of aluminum nitride.

16. The system of Claim 1, in which said connection pads are conductive, substantially semicylinclrical indentations, individually connected to said chip, in the periphery of said carrier body.

17. The system of Claim 16, in which said substrate carries solder-coated insulated microstrips extending across each pair of said corresponding connection pads, so that upon flow soldering, solder rises in the cylindrical space defined by said corresponding connection pads to electrically and mechanically connect said corresponding connection pads.

18. The system of Claim 1, in which said chip includes:
i) a function circuit; and ii) interface means surrounding said function circuit for connecting said function circuit to said connection pads.

19. The system of Claim 18, in which said function means include slow speed bidirectional circuitry and high-speed unidirectional data circuitry, simultaneously carrying clock and data and said interface means include a slow-speed interface and a high-speed interface.

20. The system of Claim 19, in which said high-speed interface includes shift registers for serializing and deserializing data.

21. The system of Claim 19, in which said high-speed interface is formed of a material taken from the group consisting of gallium arsenide, gallium arsenide on silicon and silicon.

22. The system of Claim 18, in which said function circuit is formed of a material taken from the group consisting of gallium arsenide, gallium arsenide on silicon, and silicon.

23. The system of Claim 1, in which said chip includes:
i) a function circuit; and ii) configuration means for selectively switching, in response to external configuration signals, said function circuit to receive and transmit configuration and data signals from and to selected ones of said connection pads.

24. The system of Claim 23 in which said configuration means include static configuration means for configuring said chip in response to slow-speed configuration signals, and dynamic configuration means for configuring said chip in response to high-speed data signals.

25. The system of Claim 23, in which said configuration means have the additional capability of configuring the circuitry of said function circuit to change its operating characteristics.

26. The system of Claim 1, in which said chips have parallel inputs and outputs, and said chips include serializing/deserializing circuit means for converting said parallel inputs and outputs into single line serial inputs and outputs at said connection pads.