CA1311063C - Digital signal processor - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

The present invention improves a digital signal processor, more particularly, calculation methods for motion compensation in reduceing a required amount of calculations when an amount of distortion between a last frame block and a current frame block; in processing a direct memory access at a higher efficiency; in processing a subdivided data calculation at a higher speed; in processing a branch instruction occurring in the pipeline process at a higher efficiency; and in processing an interruption occurring in a repeat process operation at greater convenience, and furthermore in reducing a required amount of calculations through minimum distortion searching processes hierarchized.

Description

BACKGROUND OF THE INVENTION
Field of the Invention The present invention relates to a digital signal processor capable of performing an arithmetic processing of mainly a signal series.
SUMMARY OF ~HE INVENTION
The present invention has been made in an attempt to solve the above-described problems, and therefore has an object to provide a digital signal processor in which the number of the distortion calculations is reduced and simultaneously an amount of calculation is reduced by outputting a minimum distortion and a block number of a minimum distortion block, so that the processing time can be efficiently reduced.
In accordance with one aspect of the invention there is provided a digital signal processor comprising:
an instruction memory for previously storing control means to instruct various internal operations as an instruction word; an internal data memory for storing calculation data; a calculator for performing various calculations on at least one data read from the internal data memory in accordance with the instruction word read from the instruction memory; an accumulator for accumulating an output from the calculator; an accumulating register for holding an output from the accumulator; a ~, 13~ 1063 minimum distortion register for holding a minimum distortion; a minimum distortion position register for holding a number of a block having said minimum distortion; a block counter for holding a number of a block under distortion calculation; a comparator for comparing an output value of the accumulatGr with a value of said minimum distortion register every cycle while, in order to detect the minimum distortion among M blocks (M
being a positive integer) of a data series, the distortion calculation is performed on a k-th block (1 S k < M, "k"
being an integer) of M blocks of the da~a series; and, an instruction execution controlling unit for executing the control means upon decoding the instruction word supplied from the instruction memory.
In the digital signal processor according to the invention, during the accumulating operation, a comparison is made between the accumulated data and minimum distortion at every cycle. When the comparison result exceeds over the minimum distortion, the accumulation is forcibly accomplished. The update of the minimum distortion and update of ~he block number are performed for the block where the accumulation has been normally accomplished. As a result, a required calculation amount is reduced and the processing time is efficiently utilized.
Also, another object of the present ", ~, . .

lnvention is to provide a hig}l-speed digital signal processor having a simpler circuit arrangernent and flexibilities.
To achieYe the above-described object, a digital signal processor according to the present invention comprises:
an instruction execution control unit for controlling operations such as decoding and calculating of an instruction word which is read ~0 from an instruction memory in a predetermined order;
a calculation unit for performing various calculations on two input data which have been transferred from a data bus;
an internal data memory for storing a calculation result which has been transferred via a data output bus;
an external data memory connecting unit for reading data from an external data memory to said data bus and for writing the data on said data output bus into said external data memory, by using values output from an address generating unit which generates one output address value and two input address values in yarallel for said calculation unit;
a direct memory transfer bus for connecting one port of said internal data mernory to 1 3 t 1 063 sai~ e~.ternal data memory connecting unit; and, a direct data memory transfer control unit for inputting and outputting the data in units of block between said external data memory connecting unit and said internal data memory via said direct memory transfer bus, independent of the internaL operation controlled by said instruction execut.ion control unit.
In accordance with the digital signal yrocessor of the invention, from an address terminal in the external data memory connecting unit, both an upper address and lower address can ~e output in two machine cycles, and the two-dimensional block transfer can be performed without decreasing the ef~iciency of the internal calculation by employing the DMA bus in the direct dat.a ~nemory transfer control unit. With an employment of the mode register and direct data memory control register, the external address ZO output format and connecting memory in program and direct data memory transmission can be independently set, so that, for instance, the small region at the hig~l-speed memory can be accessed in t~le program, and the large region at the low-speed memory can be accessed in DMA.
.A further object of the present invention is to provide digital signal processor in which a re~uired calculation amount can be reduced to 1/2 and less in a case tilat the data precision is enough of a half and less of a data size at its maximum, so that the calculation capabilities can be increased and higher speed calculation can be realized.
To achieve the above object, a digital signal processor is characterized in that when the required data precision is smaller than, or equal to a half of the data size at maximum thereof, the input data is at first multiplied in parallel by the multiplier circuit, and then, the resultant data is shifted as to execute the arithmetic operation. By this arrangement of the multiplier circuit, the calculation speed can be irlcreased.
Then, in the multiplier circuit of the digital signal processor according to the invention, the data of the half upper bit side of the input data and also the half lower bit side thereof are regarded as independent data, these multiplications are parallel-processed in four channels, the shift process, or zero set process with respect to the respective resultant data is performed, and thereafter the addition or s~btraction on the resultant data is executed, so that the calculation on the plural channels can be executed by the same hardware at a speed two times higher than the normal.
~ still another object of the invention is to provide a digital signal processor capable of performing a comparison process without interrupting a continuous process even while a series of continuous processing operation is e~ecuted, whereby a branch processing operation can be realized at a better efficiency.
To achieve the above-described object, a digital signal processor according to the invention comprises:
a control circuit including a program counter for address-controlli.ng a fetched instruction;
a data memory for inputting/outputting data:
and, a data decision unit for selecting one of an output from an arithmetic calculator within a calculating unit, an output from a logical shifter, and an output from a multiplier in parallel with an operation of the calculating unit, for simultaneously comparing the selected output data with tllreshold values of "n" in number (n being an integer not less than 1); for judging in which region said output data is present among data regions that are subdivided into (n + 1) regions by sald ~ reshold values of "n" in number based upon comparison results of "n" in number; for sequentially comparing said comparison result with region limiting conditions of "m" in number (m being an inte~er less than 1) for designating a preset data region and for outputting branch address information corresponding to a consistent region limiting condition among preset branch addresses of "m" in number corresponding to said region limiting conditions of "m" in number in case of one of said conditions is consistent, or for output.ting a signal which indicates discreyancy in all of said conditions in case of all of said conditions of "m" in number are discrepant.
In accordance with the data decision unit of the present invention, the paralleL-comparison processing is performed between a plurality of thresllold values and the outputs from the multiplier unit per machine cycle, and also a specific branch destination is selected from a plurality of branch destinations in accordance with the comparison results, so that ~ithout interupting the continuous process, the continuous comparison decision can be performed. ~5 a result, a complex brancll processing operation can be controlled at the higher efficiency.
It is another object of the invention to ~ 7 --provide a digital signal processor in WhiCIl lowering t~le process speed and increasing the step number of instructions are suppressed, and perfect returnillg from a interuption is secured by restoring the respective register values which have been preserved at the start of the interruption.
To achieve the above-described object, a digital signal processor according to the present invention comprises:
a plurality of register preserving memories for preserving each of register data when the interruption is performed;
an interruption controlling unit for correctly transferring data to ~ach of said ~5 registers at returning from the interrupting operation, and for controlling the complete recovery from the interrupting operation by restarting executions by remaining repeat numbers even after returning from the interruption which has occurred on the way to repeat processing; and, an interruption enable controlling unit for forming an interruption inhibiting period to inhibit a H/W interruption other than the interruyting process.
2S In the register preserving memories according to the invention, when the interruption is carried out, the register values of the t3~ 1063 respec~ive registers are written after the previously ex~ecuted instruction is accomplislled.
In the interruption controlling unit, the register values which have been written into said register preserving memories are restored to the respective registers at the end of the interrupting oyeration, and t.he repeat instruction can be executed by the remaining repeat numbers after returning from the interruption which has occurred even during the repeat. instruction execution. Further, the enable control unit can improve the data processing capabilities of the digital signal processor by employing the interruption inhibiting period during which the e.~ternal interruption is inhibited in the course of waiting the memory subjected to the e~ternal datz memory access, and in the course of decoding and executing a branch instruction, a return instruction, and a software interrupt instruction.
It is further an object of the invention to obtain a motion compensation calculating method by which a calculation amount can be lowered without de~rading the detecting performance of the minimum distortion block, and a simple and co~pact llard-ware can be realized.

g _ In accordance with another aspect of the invention there is provided a motion compensation calculating method for detecting a block and a motion vector of the ~loc~
having a mini.mum distortion obtained by calculating an inter-pattern analogy between each of blocks in a previously input fram~ and respective blocks of digital image data of a presently input frame, said blocks into which said presently input frame of the digital image data composed of a plurality of frames sequentially input in a time series, is divided, said method comprising the steps of: setting a first motion vector search range of which size is predetermined and of which center is located at a position of an input data block to be encoded within the previously input frame; equally subdividing this first search range into a plurality of regions; arranging a group of first search motion vectors of n in number (n being a positive integer) in the respective regions at a coarse density; calculating, as an intra-range-distortion value, a sum of distortion values, each of which representing an inter pattern analogy between the input data block and a block data of a position pointed by the respective motion vectors of n in number; detecting a region where the intra-range-distortion value becomes minimum within the first search region; setting as a minimum distortion region, a region where a distortion amount within this region becomes minimum; setting, a second motion vector search range of which size is smaller than that of the first search range and of which center is located at a position of the minimum intra-region distortion value region; arranging a group of second search motion vectors at a higher density within the second search range; and, detecting a most analogous blocX
to the input data block through a minimum distortion calculation based upon the group of second search motion vectors, whereby both the block with this minimum distortion and the motion vector thereof can be used as a final prediction signal and a final motion vector respectively.
In accordance with the motion compensation calculating method of the present invention, the motion vector search range is subdivided into a plurality of lS search small-regions, a plurality of blocks to be searched are allocated at the low density to every regions, the region where a sum of the distortion amounts between the blocks becomes minimum with respect to the motion vectors to be calculated, is detected as a minimum distortion region. Furthermore, with respect to this minimum distortion region, the limited search range is set as the high density blocks to be searched, from which the motion vector is detected. At first, a search operation of a position expected to exist a minimum distortion block can be estimated at high precision by comparing the distortion amount in units of region, and thereafter, the high-density motion vector search operation is carried out within the regicn so as to maintain the higher detecting precision under suppressing the calculation amount.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a schematic block diagram of a first conventional digital signal processor;
Fig. 2 illustrates a relationship of data blocks;
Fig. 3 is a flowchart for explaining a detecting operation of a minimum distortion effected in the conventional processor shown in Fig. l;
Fig. 4 illustrates an amount of distortion calculations performed in the conventional processor;
Fig. 5 is a schematic block diagram of a second conventional digital signal processor;
Fig. 6 is an access timing chart of an external data memory employed in the second conventional digital signal processor;
Fig. 7 ls a block diagram of a DSSP chip employed in a third conventional digital signal processor;
Fig. 8 is a flowchart of a conventional sum-of-product process;
Fig. 9 is a flowchart of the conventional complex number multiplication process;
Fig. 10 is a flowchart of the conventional binary tree search vector quantizing process;
Fig. 11 is a block diagram of a fourth conventional digital signal processor;

Fig. 12 is a flowchart of the continuous calculating process containing the data decision in the fourth conventional digital signal processor;
Fig. 13 is a block diagram of a fifth conventional digital signal processor;
Fig. 14 is a timing chart for explaining the normal interrupting operation effected by the fifth conventional digital signal processor;
Figs. 15 and 17 are explanatory diagrams for a conventional tree search type movement compensation calculation method;
Fig. 16 is a schematic block diagram of an image encoding transmission apparatus where a normal interframe encoding process has been performed;
Fig. 18 is a diagram for explaining a conventional tree search type motion compensation calculating method;
Fig. 19 is a block diagram of a digital signal processor according to a first preferred embodiment of the present invention;
Fig. 20 is a flowchart for representing an operation of a minimum distortion detection effected in the first embodiment;
FigO 21 is a diagram for representing a distortion calculating amount according to the invention;
Fig. Z2 is a schematic block diagram for showing a digital signal processor according to a second preferred embodlment of the invention;

Fig. 23 is a block diagram for representiny an arrangement of a direct data transfer controlling unit shown in Fig. 22;
Fig. 24 is a diagram for showing DMA transfer regions in an internal data memory and an external data memory;
Fig. 2S i5 a diagram for representing a register arrangement example for setting external data memory access methods of a programmed transfer and a DMA
transfer;
Fig. 26 is a timing chart in case that the external data memory is accessed by the programmed and DMA
transfer;
Fig. 27 is a timing chart of the external data memory access in an external data memory connecting unit shown in Fig. 22;
Fig. 28 is a detailed circuit diagram of a multiplier circuit of a digital signal processor according to a third preferred embodiment of the invention;
Figs. 29a, 2~b are state diagrams of shifters and others for representing operation contents of a double precision multiplication and a single precision parallel multiplication;
Fig. 30 is a state diagram of shifters and others for representing operation contents of an n-bit data parallel sum-of-product calculation;
Fig. 31 is a flowchart of representing the calculation flow in Fig. 30;

Fig. 32 is a state diagram of shifters and o~e~ 63 for illustratiny operation contents of a single precision comple~ number calculation;
Fig. 33 is a flowchart for explaining the calculation flow in Fig. 32;
Fig. 34 is a state diagram of shifters and others for representing operation eontents of the binary tree search vector quantizing calculation;
Fig. 35 is a flowchart for showing the calculation flow in Fig. 34;
Fig. 36 is a diagram for explaining a data multiplexing ~ormat in the data memory;
Fig. 37 is a schematic bloek diagram of a digital signal proeessor as a whole aeeording to a fourth preferred embodiment of the invention;
Fig. 38 is a block diagram of an internal arrangement of a data decision unit;
Fig. 39 is a block diagram for showing an internal arrangement of a eondition deeision unit:
Fig. 40 is a diagram for explaining one example of data region deeision;
Fig. 41 is a diagram for explaining conditional data representative of a braneh eondition;
Fig. 42 is a flowchart of the eontinuous calculation process containing the data decision;
Fig. 43 is a bloek diagram of a digital signal proeessor aeeording to a fifth preferred embodiment of the in~ention; - 15 -:

Fig. 44 is a timing chart for explaining the normal interruption operation of the present invention;
Fig. 45 is a timing chart for explaining the interruption operation during the repeat instruction execution of the invention;
Fig. 46 is a diagram for explaining a motion compensation calculating method according to a preferred embodiment of the invention; and, Fig. 47 is a flowchart for explaining the motion vector detecting process.
Description of the Prior Art Fig. 1 is a schematic block diagram of an arrangement of a first conventional digital signal processor which has been described in "A 50nS FLOATING-POINT SIGNAL PROCESSOR VLSI", p. 401, ICASSP 86, 1986. It should be noted that for the sake of simplicity, only required blocks are illustrated in Fig. 1.
In Fig. 1, reference numeral 1 indicates aninstruction memory for storing an instruction word; 2 denotes a program counter for outputting an address of the instruction memory 1 to an output path 51; 3 represents an instruction execution control unit for decoding the instruction word supplied from the instruction memory 1 via an output path 52, and for outputting a control signal via an ou~put path ~3 to the program counter 2, a calculation unit and the like;
4 is an internal data memory for storing calculation ''~.;'~ '' data; ~ represents a data bus for transferring data read out from the internal data memory 4 via the output path 54; 6a denotes a multiplier unit for performing multiplication on input data supplied from the data bus 5 via an output path 55; 7 indicates an accumulator for performing an accumulating operation; 8 represents an accumulating register for holding an accumulation result; and reference numeral 9 indicates a repeat count.er for repeating the same instruction at.
plural times.
Furthermore, reference numeral 63 indicates an input/output path for connecting the repeat counter g and the data bus 5; 64 represents a selector for inputting the data which has been supplied via the output path 56 from the multiplier unit 6a, and the data which has been supplied from the data bus 5 via the output path 57 thereinto and for supplying output data via the output pth 58 to the accumulator 7; 65 denotes a selector for inputting the output data which has been supplied from the data bus 5 and the output data which has been supplied from the accumulating register 8 therein, and for supplying the output data via the output path 61 to the accumulator; and reference numeral 66 is an ~utput pat.h for transmitting a control signal of the repeat counter 9.

An operation of the above-described digital signal processor will now be described. In response to the address output from the program counter 2 via the output path 51, the instruction word read from the instruction memory 1 is input via the output path 52 to the instruction execution control unit 3. 8ased upon the decoded instruction, the instruction execution control unit 3 controls the operations by sending the control signal via the output path 53 to various sections.
The internal data memory 4 reads at most two pieces of data to the data bus 5 via the output path 54, and the multiplier 6a outputs the multiplication results with respect to two pieces o~ input data which has been supplied from the data bus 5 via the output path 55. The selector 64 selects either the output data which has been supplied from the multiplier 6a via the output path 56, or the output data which has been supplied from the data bus 5 via the output path 57. The selector 65 selects either the output data which has been supplied from the data bus 5 via the output path 59, or the output data which has been supplied from the accumulating register 8 via the output path 60.
The accumulator 7 adds th~ output data which has been supplied from the above-described .;

selector 64 via the output path 58, to the output data which has been supplied from the selector 65 via t.he output path 61. The calculation result of the accumulator 7 is written via the output path ~2 into the accumulating register 8.
It should be noted that the same instruction such as the above-described accumulation is carried out in such a manner that in accordance with t~he out.put data which has been supplied from the data bus 5 via the input/output path 63, the number preset in the repeat counter 9 can be repeated.
In accordance with the above-described arrangements, Fig. 3 shows a flowchart for explaining such an operation that a block which has a minimum distortion with respect to a block "A" of a certain data series, is detected among search blocks of m in number as shown in a data relationship diagram of Fig. 2.
An amount of distortion is calculated by equation 1:

dk = ~ (Ykh ~ xh) '' ' (l) h-l where, the block A is: x = ( x1, x2 .... , xw) the search blocks are: Yk =( Ykl,Yk2~ Ykw ) k = 1 ~ M

"M" and "~1" are fixed integers.
That is to say, with respect to the output data of xh~ Y1h which have been read from the data memory 4 of the respective blocks, the accumulating calculations are performed by the number of the data (steps ST 11, ST 12), the distortion comparison is performed afte M numbers of the respecti~e block's distortions are obtained, and thereafter a minimum distortion and a block number thereof are obtained (step ST 13).
In this case, the digital signal processor having the arrangement shown in Fig. 1 requires both the comparison and update process by "M" times in order to perform a sum-of-product calculation within one machine cycle, where an amount of calculation becomès (W x M) times for the sum-of-product process, and furthermore M times for both the minimum distortion and the block number thereof are needed. As a result, a processing time ZO required for the calculations becomes t x (M x W +
M), where t is one machine cycle.
Since the conventional digital signal processor has been arranged with the above-described constructions, when, for instance, a ~5 block having a minimum distortion is detected among blocks having a certain data series and "M" pieces of search blocks, distortions for all of "M" pieces -- ~ O

,, ~

of blocks are calculated, ~hese distortions are compared with each other, and then a block number (position) of a minimum distortion is detected. As a result, there are drawbacks that an amount of calculations becomes very large and a required processing time is considerably long.
Fig. 5 is a schematic block diagram of the d.igital signal processing processor disclosed in "A 50nS FLOATING-POINT SIGNAL PROCESSOR VLSI", P.401, Proceedings of ICASSP 86, 1986. It should be noted that for the sake of simplicity, only necessary blocks are shown in Fig. 5.
In the bloc~ diagram of Fig. 5, reference numeral 1 denotes an instruction memory for storing an instruction word; 3 indicates an instruction execution control unit for controlling various operations of decoding the instruction word and calculations; 5 is a data bus for mutually connecting the following sections with each other and for mainly performing a data transmission; 4 is an internal data memory for storing the calculation data; 6 represents a calculating unit for performing various calculations with respect to two pieces of data which have been transferred from the data bus 5; 8 denotes an address generating unit capable of generating at most 3 addresses at the same time; 10 represents an external data memory ~31 1063 connec,i~g unit for controlling the read/write operations to an external data memory (not shown);
78 is an external address bus, 79 denotes an external data bus; 80 indicates an external device control signal bus; 81 is a serial port (referred to as an "SIO" hereinafter) for performing a serial data transmission between external devices (not shown in detail); and, reference numeral 82 denotes a direct data memory transfer control unit treferred to as a "DMAC" hereinafter) for controlling a direct data memory transfer (referred to as a ~DMA~ hereinafter) between SIO 81 and external data memory connecting unit 10.
Fig. 6 illustrates a timing chart of external data memory accessing operations of the digital signal processor shown in Fig. 5. Fig. 6a is a read timing chart and Fig. 6b is a write timing chart. In Figs. 6a and 6b, reference numeral 291 is an external address terminal; 292 represents a strobe signal for controlling the read timing supplied from the external data memory; 293 is an external data terminal; and, 294 represents a strobe signal for controlling write timing to the external data memory.
An operat1On of the digit~l signal processor will now be described. In Fig. 5, the instruction word of the designated address is read , -- 1, out from the instruc~ion memory 1, and input via an input/output path 201 to the instruction execution control unit 3. The control signal and data which have been decoded by the instruction execution control unit 3 are transferred via an output path 202 to the data bus 5.
In response to this control signal, calculation data from the internal data memory 4 to the data bus s is read via an output path 203, the data from the data bus 5 is input via an output path 204 to the calculation unit 6, the calculating process and calculation result at the calculation unit 6 is output via an output path 205 to the data bus 5, the data sent from the data bus 5 to the internal data memory 4 is written via an output path 206, and various operations such as the external data memory access are controlled.
Both the address of the input data from the internal data memory 4 to the calculation unit 6 and the writing address of the output data from the calculation unit 6 to the internal data memory 4 are controlled by the address generating unit 8 having three systems of address generators. This address generating unit 8 generates the address with the readable/wrltable data input from the data bus s via an input/output path 210, controls the internal data memory 4 and the external data memory connection unit 10 in response to the data which has been output via output paths 208 and 209, and determines the input data and output data write destination -to the calculation unit 6.
When, on the other hand, data is set to a specific register of DMAC 82 via the data bus 5 and a path (not shown), DMA is initialized.
Once DMA is initialized, all of operations other than the DMA transfer are in~terrupted, and the data transfer is carried out from SIO 81 to the external data memory connection unit lQ via the output path 208 and data bus 5.
The transfer word number is set into the specific register of DMAC 82 in response to the instruction which has been previously output via the output path 201. As the settable transfer word numbers, a selection is made to only 64, 128, 256 and 512 words.
A description will now be made to Fig. 6.
When the readout operation of the external data memory is carried out as shown in Fig. 6a, an RE
terminal of the external device control signal bus 80 becomes active for l machine cycle, the strobe signal 292 informs the external device of the data readout, and the address data is output from the external address bus 78 for 1 machine cycle.
Furthermore, the data read from the external device is fetched at the trailing edge of the sarne cycle.
When the writing operation of the external data memory as shown in ~ig. 6b is carried out, a WE terminal of the external device control signal bus 80 becomes active for 1 machine cycle, the data writing operation is announced to the external device, the address data is output from the external address bus 78 and the write data is output from the external data bus 79 for one machine cycle.
Since the second conventional digital signal processor is arranged as described above, the following problems exist:
a), Since no direct data transfer is carried out between the internal data memory and external data memory, the processing efficiency of the internal calculation is lowered.
b). When the external data memory is accessed by way of the direct data transfer, the address of the external data memory is simple increasing se~uence and the transfer word number cannot be arbitarily designated, so that it is difficult to directly transfer the two-dimensional block data.
c). Since the internal calculation of the processor is interrupted when the direct data transfer is carried out, the processing efficiency of the internal calculation is extremely lowered.

d). Sir~ce tlle external address output is fixed at 12 bits the accessing region of the external data memory is narrow.
Fig. 7 is a schemtic block diagram of the conventional digital signal pr-Jcessor (referred to as a DSP hereinafter) chip employed in the digital signal processor disclosed in IEEE ICASSP 86 publications on page 401 A 50nS FLOATING-POINT
SIGN~L P~OCESSOR VLSI . It should be noted tllat for the sake of simplicity only necessary blccks are illustrated in Fig. 7. In Fig. 7 reference numeral 1 indicates a program memory for storing a microprogram by which all of processes of DSP are performed; 3 indicates a control circuit for controlling the executions of various processes such as fetching and decoding of the microprogram of t~le program memory l reading of data calculation and writing of calculation results; 4 represents 2-port data memory capable of storing 2n bits (Sl is a positive integer) data as the data size also of simultaneously reading two pieces of data and also of writing one piece of data; 8 indicates an address generating unit for generating an address for the data memory 4; reference numerals 301 and 302 represent selectors; reference numeral 303 a multiplier circuit for performing a multiplication process and adding/subtracting ,~

~31 1063 process with respect to two pieces of data X and Y
which are simultaneously read from the data memory 4 and supplied via the respective selectors 301 and 302; reference numeral 6 is a calculation unit for performing an arithmetic operation and accumulation with respect to the above-described two pieces of data or resultant data by the multiplier circuit 303, and, reference numeral 5 indicates a data bus for transferring ~oth the above-described two pieces of data X and Y, and the resultant data ~y the calculation unit 6 between the calculation unit 6 and data memory 4.
An operation of the digital signal processor will now be described. First of all, an overall operation of DSP shown in Fiy. 7 will be described. That is, the address generating unit 8 generates the address with respect to the data memory 4 so as to supply to this data memory 4. Thereafter when the data is read out, two pieces of data are simultaneously read out from the data memory 4, and then supplied via the respective selectors 301 and 302 to the multiplier circuit 303 or calculation unit 6 as the data X and Y. At this time, the multiplier circuit 303 performs the multiplication process on these data X and Y, and also sum-of-product processes on the multiplication result, and finally supplies the resultant data to the calculation unit 6. Then, the calculation unit 6 perform such an arithmetic calculating process that sun~ation, subtraction, and bit manipulation are execu~ed to this resultant data or the above-described two pieces of data X and ~, and alsosupplies the resultant data to the data memory 4 ~ia the data bus 5 for writing. The above-described series of processing operations are performed by such a pipeline process that the control circuit 3 reads the microprogram which has been stored in the program memory 1, the instruction is decoded by the control circuit 3, and the control signal 31 is output to the respective circuits.
Then, in case that a sum-of-product calculation, a complex number calculation, and a binary three search vector quantizin~ calculation are executed in such a DSP, descriptions of a required machine cycle number will now be made.
(1) ~ sum-of-product calculation.
Fi~. 8 shows a calculation flow of a sum-of-product calculation. That is, at first, in a step ST 21, an initialization is executed. Namely, an address for the data memory 4 is set, and a loop number is sèt in the multiplier circuit 303 and 2S calculation unit 6. Then, in a step ST 22, the sum-of-product calculation is performed in one machine cycle. In a next step ST 23, a decision process is ~ 28 made whether or not a count value of the repeat coun~er is equal to zero. In other words, a decision process whether or not the repeat calculations are executed M times which have been set in the previous initialization step, has been performed.
In this case, if the calculation result of the sum-of-product calculation output from the calculation unit 6 is assumed to be "Z~, this llZ~
will be expressed as follows:

M

Z = 1 1 (Xi x Yi) .... (2) It should be noted that input data series X and Y
are defined by:

X = (Xl~ Xn)~ arld Y = (Yl, ~ Yn Since two pieces of data read from the data memory 4, multiplication, and accumulatian of the multiplied results are pipeline-processed, an amount of required calculations becomes M machine cycles per one output data when the loop numbers "M" are sufficiently great. Thus, this is the same in the case that the data size is equal to "n"
bits.

(2). Complex number calculation.
Fig. 9 illustrates a calculation flow of a complex number calculation. That is to say, in a step ST 31, an initialization is carried out similar to t~le above-described step ST 21. In a subsequent step ST 32, and next step ST 33, a calculation on a real number part and a calculation on an imaginary number part are separately executed in two machine cycles respectively. In a next step ST 34, a decision is made whether or not the count value of the loop counter is equal to zero. In other words, a decision is made whether or not the calculations have been performed M times which have been set in the initialization.
In this case, if the input data X and Y
are set to X = al + jaz, y = bl + ib2~
respectively, a multiplication between these complex numbers X and Y is as follows:
X X Y = (al x bl - a2 x b2) + j~al X b2 + a2 X bl) As a result, the calculations on the real number part and imaginary number part are executed in the two steps of ST 32 and ST 33. Accordingly, an amount of required calculation becomes five machine cycles per one output data.

(3). Binary tree search vector quantizing calculation.
Fig. lO represents a calculation flow for explaining a binary tree search vector quantizing calculation. The function of this binary tree - ~ 30 ~

131 ~06~

search is to perform a matching calculation between an input vector "x", and two output vectors 'yO"
and "Y1 at a certain search stage so as to detect an output vector containing a smaller matching distortion, and is to repeat such a matching calculation operation on two output vectors located at a stage below the detected vectors.
As the above-described matching calculation, a vector inner product is utilized.
~ssuming that an element number of a vector is "k", a matc~ling distortion quantity is defined as follows:

k O x Yo =i~l (xl x Yo1) --- (4) dl x Y~ (Xl x Yll) '''' (5) where X = Xl, .,., X
Yo = Yo 1 ' ' ' ' ' Yo Yl = Yll~ Yl As a consequence, at steps ST 42 and 43, ~do~ and "d1" are calculated. In the subsequent step ST 44, a comparison is made between "do'1 and "dl". Then, the process is advanced to the subsequent process. ~ccordingly, an amount of required calculation per one stage is equal to (2k + 5) machine cycles.

Since t~3e third conventional digital signal processor is arranged as described above, even in case that the required data precision is enough of a half of a data size at its maximum, an amount of various calculations required is equal to that of the data precision with respect to the data size at its maximum. As a result, the calculation capabilities of the digital signal processor per se cannot be sufficiently utilized.
Fig. 11 is a schematic block diagram of the conventional digital signal processor (referred to as a "DSP" hereinafter) disclosed in, for instancee, ~A 50nS FLOATING POINT SIGNAL PROCESSOR
V~SI", on page 401, IEEE, ICASSP86. It should be noted tllat for the sake of simplicity, only necessary blocks are represented in Fig. 11.
In DSP shown in Fig. 11, reference numeral 1 indicates a program memory; 3 is a control circuit for controlling data transfer, calculation, branching and so on 31 represents an output path for outputting a control signal from the controL circuit 3; 404 indicates an output path from the control circuit 3 to the program memory 1;
405 is an output path from the program memory 1 to the controL circuit 3; 4 denotes a data memory; 6 indicates a calculation unit including a multiplier, an arithmetic calculator, a shifter, an ~ ~ - 32 -accumulatar and so on; 5 is a data bus; 409 represents output paths from the data memory ~ to tlle data bus 5, and from the data bus 5 to the calculation unit 6; and, reference numeral 4lC
denotes output paths from the calculation unit 6 to the data bus 5 and from t~le data bus 5 to the data memory 4.
The operations of DSP will now be described. The basic operations of DSP is cont~olled based upon the program read from the prograrn memory 1, by the control circuit 3.
Furtllerlnore, the data read from the data memory 4 is subjected to a series of processing operations such as the instruction fetch, the decoding, data reading, calculation, and calculation result writing on inputting the data into the calculation unit ~.
~ hen the same instruction is consecutively performed by way of the pipeline processing, one instruction may be approximately performed within one machine cycle. As a consequence, in case that a single instruction is repeatedly executed, the process speed may be increased more if the process is more consecutively executed.
However, if a specific condition is satisfied with the caLculation resuLts, the _ 33 -~ollowing branching process is required in the ~ranching program. Tllat is, in such a branching program, an intermediate check point is introduced in a routine, and the consecutive execution is once interrupted so as to judge a condition before the consecutive execution process is completed, and urther a comparison is made between the calculation result data and the specific data.
Thus, based upon the comparison result, the branching process is executed.
Fig. 12 is a process low for performing an intermediate check while a series of consecutive execution is processed, The results of the calculation process is compared with a threshold value (steps ST 51 and 52). Thereafter, a decision is made whether or not an interrupt condition is satisfied (step ST 53~. If YES, then this process is completed. If NO, another decision is made whether or not the final data is accomplished (step 2~ ST 54). If NO, then the process is returned to the previous step ST 51 in which the above-described operation is repeated. To the contrary, if YES, then this process is ended.
In a motion compensating process of an image encoding method, a difference absolute value accumulation is employed for a pattern matching so as to detect a minimum pattern. when, for instance, a value which is now accumulated exceeds over a minimum value, the rernaining accumulation is waste of time. In such a case, the process is advanced to the next routine for the sake of efficiency.
To this end, it is useful to perform the intermediate check to some extent. ~lowever, the various processes of comparisons and decisions, and also interruptions of the process accompany a loss of time, Further, according to the conventional ~SP, it is possible to only judge the conditions on t~e positive or negative decision of the data.
hen a comparison of a size is needed between the data and the specific threshold value, a subtraction is once carried out between the data in question and the threshold value, and thereafter, a decision can be performed based upon this subtraction result, resulting in a lower processing efficiency of DSP.
If there are a plurality of comparison thresllold values, the processing efficiency is moreover lowered. For instance, in case that the process sorts are subdivided into plural numbers ~n in number), the comparisons between the data in question and ~n-l) threshold values, and the branching instructions based upon the comparison results are required. At least a loss of (n-l) x 2 t3t 1063 machine cycles occurs.
Since t~le fourth conventional digital signal processor is so constructed, the processing efficiency is lowered because of the following reasons That is, in case that the branching process is carried out depending upon the calculation results or intermediate calculation results, the process is interrupted during the consecutive processing steps, and the subtractions and also the comparison processes are executed.
Fig. 13 is a simplified schematic block diagram of a audio signal processor (DSSPl) which has been represented in Japanese Telecommunication Institute, symposium publication No. S10-1 in 1986.
In the audio signal processor shown in Fig. 13, reference numeral 1 denotes an instruction memory into which instruction words have been stored; 3 represen~s an instruction execution control unit for controlling various operations such as decoding of the instruction word and calculations; and 2 indicates a program counter for holding an instruction address; 504 is an PC stack far preserving a return address used in the subroutine process and interruption procèss.
This PC stack 504 preserves an instruction address 531 output from the program counter 2 just before the interruption process, until the process is ,. , ,- - 36 -accomplished. Reference nurneral 505 indicates a sequence control unit for controlling the entire operation of the processor: S06 is a repeat control unit for performing a counting operation between the sequence control unit 505 and itself during the loop/repeat operation; 9 is a repeat counter for count.ing a repeat number during the execution of the repeat instruction; 508 is a program bus for transferring the decoded control data; 5 represents a data bus for transferring main data; 510 is a bus interface register for connecting the program bus and data bus 5; 4 represents a data memory for storing.calculation data; 6 indicates a calculation processing circuit for performing arithmetic operations such as addition, subtraction, multiplication, and division; 513 is an interruption control unit for starting the interrupting process; 514 is an external interrupt request signal; and, reference numeral 515 denotes an external interrupt. acknowledgement signal.
An operation of DSPl will now be described, ~n general, a signal processor has a pipeline structure in order to increase a processing speed. For instance, in the signal processor as shown in Fig. 13, the structure thereof is 3-stage pipeline. Accordingly, the following description is made based upon the pipeline processing.
In a first stage of the pipeline, an instruction word 511 which is designated by an instruction address 531 output from the program counter 2 is read from the instruction memory 1 and thell input into the instruction execution control unit 3.
In a second stage of the pipeline, both the control signal and data decoded by the instruction execution control unit 3 are transferred to the corresponding parts.
In a third stage of the pipeline, various operations are controlled. That is, the calculation data 512 are read from the data memory 4 to the data bus 5 in response to the control signal, and written from the data bus S into the data memory 4, and furthermore processed in the calculation unit 6.
The interruption control unit 513 has a 3-level interrupt function other than RESET. RESET
not only resets the program counter 2, but also initializes control registers such as a status register (SR), a flag register (FR~, an interruption, and a ~us control.
An interrupt 0 (INTR0~ is non-maskable, and the program counter 2 is set to an address "1 when an INTR0 signal is input.

~ 38 -~ n interrupt l (INTRl) is maskable, and is masked when RESET, INTR0, or INTRl is accepted, or by being designated in the program. A release of masking is executed by the program. Whell this interrup~ion is accepted, the program counter Z is set to an address "2n.
~ n interruption 2 (INTR2) is maskable, and corresponds to a normal interruption having an acknot~ledgement function.
When RESET, INTR0, INTRl, and INTR2 are accepted, or it is set by the program, INTR2 is masked. ~ release of masking is performed by the program. when an interruption request signal is accepted, an acknowledgement signal (INTR2) is output, and then an address "3 is set to the program counter 2.
~ n instruction word which will be executed after the normally executed instruction word, has been stored in an address which is defined by adding 1 to the instruction address 531 w}lere the normally executed instruction word has been stored.
In the first stage of the pipeline the instruction address 531 output from the program counter 2 is added by "+1" in the adder so as to produce an address defined by adding the instruction address 531 to "1".

In general, in the processor ha~ing a pipeline structure, a delay may be caused by this pipeline until the instruction has been executed.
As shown in Fig. 14, in a machine cycle of time period Tn, the ~ l interrupt request signal 514 is input into the interruption control unit 513.
In response to the above-described input, when the external interrupt acknowledgement signal 515 is output from the interrupt control unit 513, an instruction word designated by an instruction address PC(n) is read out. Since the interrupt signal has been received, the instruction word which llas been stored in an "n" address of the instruction execution control unit 3 at the machine cycle of time period (Tn~l), is invalidated, and it is substituted by no operation instruction (nop).
The program counter 2 is set to an address "3" at the machine cycle of time period Tn, whereby an interruption process is performed. The process cannot be completely recovered from the interruption process because the executivns of the instruction words designated by PC(n-l) and PC(n) have not yet accomplished, and operations of the program counter 2 and the various key registers are interrupted not preserved, before the underruption process i5 executed.
Since the conventional digital signal 1 3 1 ~ ~6~

processor having the above-described pipeline structu~e is so arranged above, the correct data before the interruption cannot be guaranteed when the external interruption is executed while the normal instruction is performed. ~Jhen the interruption is executed during the repeat operation, tlle remaining repeat instruction is not executed. This causes the process efficiency to be lowered in the image si~nal processing field where the external ~ interruption is e,Yecuted, and a large ~uantity of data is processed at a high speed so as to obtain a correct calculation result.
Fig. 15 is an explanatory diagram of the conventional motion-compensation calculating rnethod lS which is described in, for instance, "A METHOD OF
INTERFRAME ENCODING BY EMPLOYING MOTION
COMPENSATION/B~CKG~OUND PREDICTION", publication of ~lectronic Telecommunication Institute, '85/1 Vol.
J68-B No. 1, pages 77 to 84 by H. KORODA: N.
TAKEK~WA and ~l. HASHIMOTO. In particular, this diagram shows an entixe search type method. In Fig, lS, reference numeral 603 indicates a presently input block having a bloc~ size of Q 1 x Q 2 used for compencating a motion of a position in the presently input frame; and 604 indicates a motion vector search range for representing a range of (Ql + 2m) and (Q2 + 2n) - 41 ~

1 3 ~ 1 063 wllere a ~lock is located. This block is matching-processed with the presently input block 603 in the previously input frame.
In this case, the number "M" of the S search blocks i5 expressed by:
~ l = (2m ~ 1) x (2n + 1) -~~ (6) The search range is defined by a range of -m to ~m pixels in the horizontal direction and a range of -n to ~n pi~els in the vertical direction.
The motion compensation is executed at a predetermined sized block unit by obtaining a prediction signal approximate to the presently input frame data while utilizing a inter-frame correlation ~etween the presently input frame data and previously input frame data in the inter-frame encoding transmission method. Then, a block having a minimum inter-block-distortion quantity against a presently input block 603 within a presently input frame data, is searched among the motion vector Z0 search range 604 within a previously input frame data and obtained a motion vector and a prediction signal. Tllis block corresponds to a bloc~ having the highest correlation with the presently input block 603 with a calculation method such as a sum-of-absolute-difference calculation.
Fig. 16 is a schematic block diagram of an image encoding transmission apparatus where a general inter-frame encoding process is performed.
In Fig. 16, reference numeral 601 denotes an input signal of image data constructed of a plurality of sequential frames in a time series; 602 denotes a motion compensation unit for obtaining a prediction signal by calculating approximation of a correlation between a presently input block 603 of the input signal 601 and a motion vector search range 604 given as a previously input signal 601;
reference numerals 605 and 606 are prediction signals output from the motion compensation unit 602; 607 is an encoding unit for encoding a difference signal bet~een the input signal 601 and prediction signal 606 so as to output a motion compensated signal; 608 denotes a decoding unit for decoding the motion compensated signal which has been encoded in the encoding unit 607; and, reference numeral 609 indicates a frame memory for adding the signal from the decoding unit 607 to the prediction signal 606 from the motion compensation unit 602 so as to obtain reproduced data to be stored therein, and also for giving the motion vector search range 604 to the motion compensation unit 602.
In the image encoding transmission apparatus with the above-described arrangement, an operation thereof will now be described with reference to an explanatory diagram of Fig. 17.
The configuration shown in Fig. 16 has functions as follows: each of inter-block distortions between the presently input block "x"
603 with a size of e, x ~2 at a specific position within the presently input frame and the respective blocks of M in number within the motion vector search range 604 of the previously input frame, is calculated; and a minimum value of these distortions, i.e., a relative position of a minimum distortion block "y" indicated by the minimum distortion, with respect to the position of the presently input block 603, is searched as a motion vector; so that a signal "ymin" of this block is output as a generated prediction signal 605. Then, ~31 1063 in the frame inter-frame encoding transmission, the prediction signal can be produced even at the reception side by transmitting the motion vector information at the reception side.
Assuming now that the number of the motion vectors "V" to be searched within a given motion vector search range 604 is "M" (an integer not less than 2). In case that a sum-of-absolute-differences is employed as a distortion quantity between the previous frame block at the position of the specific motion vector "V" and the presently input block, an amo~nt of distortion is calculated by:

Di = ~ ¦ yiP - xP¦ .... (7) P,l It should be noted that the input block is x = (xl, x2, ---, xL), the block to be searched is yi = (yil, yi2, ---, yiL), and i = 1 to M, L is equal to el x e2. Thus, the motion vector V is obtained by:
V = Vi (min di ¦ i = 1 - M) .... (8) Then, a calculation amount S1 of this case is obtained by the following equation when the sum-of-absolute-differences calculation needs "a"
machine cycles and the comparison process needs "b"
machine cycles.
Sl = L x M x a + M x b .... (9) In case that, for instance, a = 1 machine cycle, b = 2 machine cycles, e1=8, e2=8, m=8, and n=8, then L=64, M=289, and;
S1 ~ 19,000 ........................ (10) machine cycles. This is very large value in view of the hardware arrangement. The high-speed calculation system such as the pipeline pxocessing has been used in accordance with the frame cycle of the image signal.
However, it is a great problem to lower quantities of the hardware. In accordance with Japanese KOKAI (Laid-open) Patent Application No. 63-181585, for instance, entitled: "AN
APPARATUS FOR MOTION COMPENSATION INTER-FRAME
ENCODING OF A TV SIGNAL", it has been proposed a method or calculating a tree search type motion ~ .., 13~ 1063 compensation so as to reduce an amount of calculations. Fig. 18 is an illustration for explaining a method of a motion compensation calculation. There are arranged first blocks " O "
of low density at equal intervals to be searched within the motion vector search range 604. When a block " O " giving the minimum distortion is detected, second blocks " ~ " to be searched are positioned within a narrow region with this block " O " as a center thereof. In this narrow region, a block " ~ " giving the minimum distortion is detected. Furthermore, third blocks " ~ " to be searched are set within another region with this block " 0 " as a center thereof so as to detect a blocX " ~ " giving the minimum distortion.
Finally, the block " ~ " giving the minimum distortion within the motion vector search range 604 is specified.
An amount of the calculations "S2" in this case is expressed by:
S2 = (9 x L x a + 9 x b) x 3 .... (11).

~31 1063 As a result, under the same conditions as the above, it becomes S ~ 1,800 .... (12) machine cycles.
Although a quantity of calculation according to this tree search type motion compensation calculating method becomes small, the capability to detect the minimum distortion block is lowered as compared with that of the full search type motion compensation calculating method. That is to say, there are considerable possibilities that at the matching process of the first search operation with the low density, a selection is made on such a block of which position is apart from that of the correct block having the minimum distortion. As a consequence, there are many cases that the calculation result cannot reach the expected minimum distortion amount and gives a decision of no correlation, resulting in a lower efficiency.
Since the conventional motion compensation calculating method has been so arranged in above, a calculation amount becomes great if the fall , . ,~

~ 31 ~ 3 searching operation with high reliability in the motion compensation calculating is employed, so that a large scaled arrangement of the hardware is required. On the other hand, if the calculation amount is reduced by way of the tree searching method, the detectability of the minimum distortion block is lowered. As a consequence, there are problems of the erroneous detections and insufficient efficiency.
DETAILED DESCRIPTION OF THE PREFERRED
EMBODIMENTS
A description will be made on a first preferred embodiment of the present invention with reference to drawings.
Fig. 19 is a schematic block diagram of a digital signal processor according to the invention. It should be noted that same reference numerals may be employed for denoting the same or similar components shown in Fig. 1 and no further explanation thereof is made.
In Fig. 19, reference numeral 110 is a minimum distortion register for holding a minimum distortion; 111 is a comparator for comparing a value of ~he mil7imuln di6~0r~ioll register 110 wit]
an vu~put oi accumulator 7 and for outputting a comparison resul~ to an instruction execution controlliny unit 3; reference nwneral 112 is a block counter for representing a block number WhiC}I
no~ performs accumulation; and 113 indicates a minimum dist.ortion position register for holding a block nulllber having the minimum distortion.
Furthermore, reference numeral 101 indicates an input/output pass between the data bus 5 and block eounter 112; 102 is an output path from the minimum distortion position register 113 to the data bus 5; 103 is an output path for supplying an increlnent control signal from the instruction lS e~ecution controlling Urlit 3 to the bloek eounter 112; 104 is an output path for announcing the eornparison result of comparator 111 to the instruction execution controlling unit 3; 105 represents an output path for supplying the output data of the accumulator 7 to the eomparator 111, 106 represents an output path for supplying the data of the minimum distortion register 110 to the comparator 111; 10 represents an update path from the accumulating register 8 to the minimum distortion register 110; and, 108 indicates an updata path from the block counter 112 to the minimum distortion position register 113.

~ ig, 2() is a flowchart for explairling an oper~t-iorl to obtain a block number and a distortion correspollding to a minimum distortion among blocks of "~1" in number by employing the digital siynal processor shown in Fig. 19.
In response to an address output from the program counter 2, an instruction word is read from the instruction memory 1 and input into the instruction execution controlling unit 3 via an output path 52. Based on a decoded instruction, the instruction execution controlling unit 3 sends a control signal to the various circuit portions so as to control them.
In case that the decoded instructior corresponds to the instruction of the minimum distortion detection which is accompanied by aCCUIIIUlatiOllS such as the difference absolut.e value accumulation and sum of products, the data transfer of the read data from the data memory 4 to the data bus 5, the data trarlsfer of at the most two pieces of output data from the data bus 5 to the calculator G, and the data transfer of accumulation result from the accwnulator 7 by using the output data of the calculator 6 and the output data of the accumulating register 8 ~step ST 101).
On the other hand, the accumulation result which is supplied via the output path 105 ~rancl-led frolll tlle output path 62 of the accwnulator 7 is corrlpared with the output data which is supplied from the minirnum distortion register 110 via the output path 106, by the comparator 111 every cycle (step ST 102).
The comparison result obtained by the comparator 111 is transferred to tne instruction execution controlling unit 3 every cycle. wherl the accumulation result of the accumulator 7 is greater than the value of the minimum distortion register 110, namely if YES, then the accumulation is interrupted to clear the repeat counter 9 to "0"
and simultaneously to increment the value of the block counter 112 in response to the irlcrement control signal derived from the instruction execution controlling unit 3, and then, the process is advanced to the next step ~steps ST 103) and 104~.
When the accwnulation operation is carried out by the number set in the repeat counter 9, and the accumulation is normally accomplished, the value of the accumulating register 8 is written and updated into the minimum distortion register 110 (step ST 105): the value of the block counter 112 is written and updated in the minimum distortion position register 113 (step ST 106), and the block counter 112 is incremented by tlle incre~llerlt control signal 103 (step ST 107~.
~ Ihen the minimum distortion block with respe~t to a block "~" of a certain data series is detected among "M" pieces of blocks "Yi" to ~e searclled in accordance with the above-descri~ed processiny operation, assuminy the number of the accumulatious for a K-th block is "~k" (~c is an inteyer, 1 ~ ~k ~ w), the sum-of-products process is perforlned by ~ ~k~ and both the minimum k=1 distortion and tlle ~lock number of the minimum distortion are obtained si.multaneously with the accumulatiorl. ~s a result, neither comparison nor update yrocessing is required to obtained this minimum distortion and the n\inimum distortion block nwnber. ~s shown in Fig. 21, the calculation processiny time is shortened only to t x ( ~ W~c).
It should be noted that although the difference square summation has been employed as the distortion calculation according to the above preferred embodiment, either difference absolute values or inner products may be utilized.
~ lso, the above-described criterion for the comparator is "whether or not the accumulated output from the accumulator exceeds over the value of the minimum distortion register", however, another criterion may be made to be "whet}ler the accumulal:ed output from the accumulator exceeds over, o~ is e~ual to the value of the mioimum distortion register".
~ ~escription of a second preferred embodilr)ent of the invention will now be made.
Fig. 22 is a schematic block diagram of a digital signal yrocessor according to the present invention. It should be noted that the same reference numerals will be employed for denoting the same or similar circuit elements shown in Fig.
5 and no further explanation thereof will be made.
In tlle processor shown in Fig. 22, reEerence numeral ~3 indicates a mode register for setting the access method of the external data memory; ~4 indicates an output bus for outputting tlle calculation result; and ~5 is a direct data transfer bus.
Furthermore, reference numeral 211 is an input/outyut path of the data from the data bus 5 to the mode register 33; 212 is an output path of the control signal rom the mode register 83 to the external data memory connecting unit 10: 263 indicates an input/output path of the data from the direct data memory transfer bus ~5 to the data memory 4; 264 indicates an inyut/output path o the data between the direct data memory transfer bus 35 and external data memory connecting unit 10; and refererce nurneral 265 indicates an output path of the data from ~he data output bus 84 to the external data mernory connecting uni-t 10.
~ ig. 23 is a schem~tic block diagram of an arrangement of D~l~C ~2 ernployed in Fig. 22. In Fig. 23, reference numeral 231 indicates a frame horizontal size reyister (dmfhr) for representing a horizontal s:ize of a two-dimensional address space (dornain); 232 denotes a block horizontal size register (dmbhr) for representing a horizontl size of a rectangular portion within the two-dimensional address space: 233 denotes a block start address register (dmbsr) for indicating a head address of the exterrlal data memory to execute a DMA transfer;
234 represents an internal memory start address register (dmssr) for indicating a head address of the in~.erllal data rnemory to execute the DMA
transfer 235 represents a word register (drnwcr) to indicate the number of words of the D~A transfer;
236 indicates a D~IAC register (dmcr) for selecting an external address output mode at the DMA
transfer and the external memory; 237 is a DMA
address calculation unit; and reference numeral 238 is a DM~ transfer controlling unit to control the DMA transfer.
Furthermore, reference numeral 271 is an input/output path of the frame horizontal size ~31 1063 re~ister 231; 27Z i5 an input/output path of the block ~lorizorl~al size reigster 232 273 indicates all inE~u~/out~)u~ ~ath of the block start address register 233 274 is an input/output path of the inl-ernal melllory start address register 234; 275 is an input/output path of the word register 235 and reference numeral 276 is an input/output path of ~-he Dl~lAC register 236.
ln addition, reference nurneral 277 indicates an output path for the internal data melllory address of the DMA transfer from the DMA
address calculation unit 237; 278 is an output patl for ~he ext-ernal data memory address of the Dl~lA
transfer from the D~A address calculation unit 237;
and 279 denotes an output path for outputting the control signal such as a DMA transfer word number from the D~5A transfer controlling unit 238 to the DMA a~dress calculating unit 237.
Fig. 24 illustrates an example of a transfer region of the DMA trarlsfer performed betweell the internal data memory 4 and external data melnory 241 by DMAC 82 shown in Fig. 23.
Fig. 25 is a diagram for illustrating bit arrangements of the DMCA register 236 shown in Fiy.
23 and the mode register 83 showrl in Fig. 22. In Fig. 25, symbol "A" denotes preliminary bits, symbol "B" indicates a first bit of an address .3 6 3 out.put mode and symbol C indicates a zeroth bit of a memory connection mode.
Fig. 2G illustrates a timing example where the external data memory is accessed by the programs and DM~ s.
~ n operation of the digital signal processor will now ~e described. The instruction word read from the instruction memory 1 is input to the instruction execution controlling unit 3 via the input/output path 201. In response to the control signal decoded by this instruction execution controlling unit 3 the calculation data from the internal data memory 4 to the data bus 5 is read via the output path 203 whereas the data from the data bus 5 is input to the calculation unit 6 via tlle output path 204. The calculation processing result at t.he calculating unit 6 is output to the data output bus 84 via the out.put path 205 the data from the data output path 206 is written to the internal data memory 4 and also the data from the data output bus 84 is written into the external dat.a memory connecting unit 10 via the output path 265.
Both the address of the input data which has been input from the internal data memory 4 via the output path Z0~ and a write destination address of the internal data memory 4 of the output dat.a wllich llas been ou1E)ut from the calculation unit 6 via t-he output path 205 to the data output bus ~4, are controlled ~y tlle address generating unit havilly three~line address generators.
S The a~dress generating unit ~ generates addresses by using readable/writable data which has sup~lied from the data bus 5 via the input/output path 210, and controls of the internal data memory 4 and external data memory connecting unit 10 are ~erformed by USill9 the data output via the output path 20~ and 209, respectively, so as to determine the write destinations of tlle input data and output data to the calculating unit 6.
The access mode of the external data memory 241 by means of the external data memory connecting unit 10 is determined by a value which has been set via the data bus 5 into the mode register ~3 in accordance Wit21 the instruction word read from the instruction memory 1.
W2~en, on the other hand, the data is set into the s~ecific register of DMAC ~2 via the data bus 5 based upon tlle above-described instruction word, the DM~ transfer is initialized. The external data memory connecting unit 10 is controlled by DMAC ~2 independently to carry out the data transfer between the internal data memory 4 and external data memory 241 via the input/output - 5~ -1 3t 1 063 ~a~hs 263 and 2~4 and direct. data transfer bus 85.
Tlle D~A transfer controlling unit 23B
performs an initialization of the DM~ transfer by means of the data which has been set in the DIIA
address calculating unit 237 via the data bus 5.
The D~ address calculating unit 237 generates a two-dimellsional block address 278 with respect to the address of the external data memory 241 and also an ascending one-dimensional address 277 wit~
respect to the internal data memory 4 based upon the values of the frame horizontal siæe register 231 block horizontal size register 232 block start ad~ress register 233 and internal memory start address register 234.
In the DMA transfer controlling unit 238 when the DM~ transfer word number which has been set in the word register 235 is ended a termination signal is sent to the DMA address calculating unit. 237.
2~ As shown in Fig. 24 the above-described DMA transfer can be performed between arbitrarily rectangular regions (k-line x l-column in Fig. 24) of the external data memory Z41 from the arbitrary address (address "t in Fig. 24) and of the internal data memory 4 from the arbitrary address (address S in Fig~ 24).
~s shown in Fig. 25 when both the zeroth 1 3 ~ 1 063 ~its of the mode register ~3 and Dr~C register 23~, wllich in~icate the mernory connecting mode are 0 i~- is a t~ai.ting mode waiting until the read/write colllL)le~ioll signal frorn the e~ternal device is S detected duriny the use of the low-speed memory.
To tlle contrary whell the zeroth bit indicating t.he melllory conllecting mode is '1", it is such a mode tllat after the lower bits of the address are output the read and write operat:ions are accomplislled in one machine cycle.
W}len t.he i-irst bit whicll indicates the address ~utput mode is "0" both the upper and lower bit.s of the address are output in two machine cycles, ~hereas when this bit is '1 only the lower bits of the address are output in one mac}line cycle.
By independently setting tl~e mode register ~3 and DMAC register 236 the external memory access from the program and DMA can be independently carried out.
In Fig. 26, there is shown an access tirming example of the external data mernory 241 in case that "1" are set as the address output mode and as tile memory connecting mode in the mode register ~3 shown in ~ig. 25 and 0 are set as the address output mode and as the memory connecting mode in Dr~AC register 23~.

~ G0 -ihe access to the external data memory 241 froln ~M~C ~2 is accomplished by detecting the read/wri~e complet:ioll signal from the external ~evice in case of the low speed memory (n' machine cycles in Fig. 26) whereas the external data memory access from t:he program is completed in 1 machirle cycle in case of the high speed memory.
The external data memory access by DMA is contilluously performed unless the external data memory access is effected by the program. Then when tlle external data memory access is executed by the program the access operation by DMAC ~2 is interrupted and after the access operation by the program is accomplished the process is restarted.
Fig. 27 is a timing chart of the external data memory access (read out) in the external data memory connecting unit 10 shown in Fig. 22. It should be noted that same reference numerals will be employed for denoting the same or similar circuit elements shown Fig. 6, and no further explarlat iOII thereof is made.
In Fig. 27, reference numeral 251 is a signal for controlling upper address timings when the address is output (referred to as an A~IE );
252 is a signal for controlling lower address timings when the address is output (referred to as an ALE ~; 253 indicates a signal for announcing to the external device whether or not the external data mernory access is executed by the processor or DMA (referred to as a "PJD"); and reference numeral 254 is a read/write completion signal from the external device (referred to as a "DTACK").
When the high speed memory shown in Fig.
27(a) is used, A~IE 251 is asserted in the first machine cycle and also the upper address is output from an external address terminal 291 of the address bus 73, both ALE 252 and ~E 292 are assert-ed in the second machine cycle, and the data from an external data terminal 293 of an external data memory 241 is fetched at the trailing edge of the second machine cycle.
When the low speed memory as shown in Fig. 27(b) is used, AllE 251 is asserted in the first machine cycle and also the upper address is output from the external address terminal 291 of the address bus 78, both ALE 252 and RE 292 are asserted in the second machine cycle, RE 292 is negated and the data from the external data terminal 292 of the external data memory 241 is fetched at the trailing edge of a cycle where the external device asserts DTACK 254. Furthermore, ALE 252 is negated at the trailing edge of the cycle where DTACK 254 negated.
As above-described, the external data melnory connecting unit 10 has the following fea1-ure.s .
(a). rhe co~ ectilly unit 10 includes two address output modes ~o the external data memory. In one address output mode both the upper and lower addresses are oul-put in two machine cycles so t~hat all oE external data memory regions can be accessed. In the other address output mode the lower address is output only in one machine cycle so that the specific region of the external data memory 241 can be accessed at a high speed. These two modes are changed by the value of the mode register set by an instruction.
(b). lt is possible to connect two types of external data memory 241. One is the high speed memory where after the lower address is output, the read/write operation is accomplished in one machine cycle. The other is the low speed memory where it is waited until the read/write completion signal from the external device is detected. These two types are changed by the value of the above-described mode register.
The direct data memory transfer unit has the following features.
~c). In accordance with the direct memory control register set by an instruction the above-described two address output modes and two types of external data memory connections are available indepen~en1:
iroln the external data memory access by an internal instructiol1 based upon the value of the mode regis1-er.
(d~. T~le address designa~ion with respect to the external data rmemory connecting unit is so arranged in a manner that the rectangular portion of k-lines by l-colurnns (k, l are integers) in the two-dimensional address space of m-lines by n-columns (m, n are positive integers) are sequentially designated. The address with respect to the internal data memory is designated from an arbitrary starting address in an ascending order, and t}1e two-dimensional data transfer is performed between the external data memory and internal data mernory. Further, when the data transfer is commenced, the transfer direction and transfer data nwnber are designated by an instruction, so that the data input/output and internal calculation process with the external data memory are executed in parallel in units of rectangular block of k-lines by l-columns.
It should be noted that in the abo~e-described preferred embodiment, a description was made that the number of the external address terminals was 16 bits, however other terminal numbers may be utilized.

It should also be noted that since there is no relationsl1ip between the essential poin1-s of t:he inver~t~ion and de~ailed speciEications of the above-described preferred embodiments, t~1e cvntents oE t:~1e inveIltiorl are not rest.ricted tl1ereto.
A third preferred embodilnent of the inventiol1 will now be described with reference to the drawings. Fig. 28 is a concre-te arrangement of a multiplier circuit 303 according to the third preferred embodirnent of the invention. In principle, the circuit arrangement of DSP according to the invention is the same as that of the conventional one described in Fig. 7. Ilowever, the arrangelnent of the mult.iplier circuit 303 is mainly different, II1 Fig. 28, reference numeral 320 ir1dicates a register A as a first 2n-bit sized regist.er, for inputting data X among two pieces of data X and Y which are simultaneously read out from the data memory 4; 321 is a register B as a second 2n-bit. sized register, for inputting t.he data Y;
reference numerals 322 and 323 represent upper n-~its of the data X (referred to as "data ~l") set in the register A and lower n-bits thereof ~referred to as "data ~0") respectively; 324 and 325 denote upper n-bits (referred to as "data Bl") oE the data Y set in the register B, and lower n-~i~s ~lereof (referre~ to as "data sO"): 32~, 327, 32~ alld 329 represent a first mul~iplier (referred t-o as an "~IPYl"), a second rnultiplier (reterred to as an "MPY2"), a third rnultiplier (referred to as an "MPY3") and a fourth multiplier (referred to as an "MPY4 " ) for multiplying the data Al and Bl; the data ~0 and Bl: the data Al and B0; and the data ~0 and B0 in parallel, respectively; reference nurnerals 33U, 331, 332 and 333 represent a first shifter (referred to as a "shiEter 1"), a second shifter (referred to as a "shifter 2"), a third shifter ~referred to as a "shift:er 3") and a fourth shift.er (referred to as a "shift,er 4") for performing a sl-ift process or zero set in accordance wit.h a microprogram in the program memory 1 with respect to the outputs from MPYl, MPY2, MPY3 and MPY4, respect.ively; 334, 335, 336 and 337 are output data from t.he first to fourth shifters 30 to 33, resyectively; 338 and 339 denote a first arithmetic calcul.ator (referred to as an "AUl") and a second arithrrletic calculator (referred to as an "~IJ2") for inputting therein the outputs from the shifters 1 and 4 or the shifters 2 and 3, respectively, and for surnrning or subtracting these outputs in accordance with the microprogram; and reference nurneral 34~ indicates a third arithmetic calculator for inputting therein the outputs from AUl and AU2 alld for. ~umllliny or subtracting these oul:puts in acco~-dance with 1:he microprograrn so as to output the final calculation resultant data of 4n-bits to the calculating unit 6.
~n operation will now be described. The data input:/output in -t~e data memory 4, and various calculation processes at the multiplier circuit 303 and calculating circuit 6 as shown in Fig. 7 in detail, are executed in such a manner that the control circuit 3 reads the microprogram in the program lllelllory l, the instructions thereof are decoded, and the pipeline process is carried out in response to the control signal based on the decoded instructions. Where, the data size is 2n-bits at a maximum size, the resultant n-bit data will be referred to as single precision data, and 2n-bit data will be referred to as double precision data.
The multiplication system instructions based upon the microprogram include various instructions, such as a double precision multiplication (2n-bits x 2n-bits) for multiplying 2n-bit data with each other, a single precision multiplication (n-bits x n-bits) for multiplying n-bit data with each other, a single precision sum-of-products, a single precision complex nurnber multiplication, and a binary tree vector quantizing multiplication.

1 ~1 1 0~3 llowever in this case in the multiplier circuit 3~3 shown in Fig. 2~ each par~ thereof will ~e operated in response to t}le control signal corresponding to the sorts of the above instructions as follows. That is two pieces of data simultaneously read from the data memory 4 are supplied to the multiplier circuit 303 via the select-ors 301 and 302 the data X is set into the register ~ and the data Y is set into the register B. It should be noted that both the data X and Y
are 2-~it sized data at the maximum value.
lhe upper n-bit data ~1 of the data X and lower n-bit data ~0 thereof which have been set into the register A are supplied to MPY 1 MPY 3 or MPY 2 MPY 4 respectively. Also the upper n-bit data Bl and lower n-bit data B0 of the data Y WtliC}I
have been set into the register ~ are supplied to MPY 1 MPY 2 or MPY 3 MPY 4 respectively. As a consequence, MPY 1 multiplies the data A1 by Bl MPY 2 multiplies the data A0 by Bl, MPY 3 multiplies the data ~1 by B0 an~ MPY 4 multiplies the data ~0 by B0 in parallel and the respective 2n-bit sized resultant data are supplied to the shifter 1 shifter 2 shifter 3, and shifter 4. As to the resultant data input into the respective shifter 1 to shifter 4 the shift process or zero set process is carried out in accordance with sorts - 6~ -~f the ins~ructiorl. T~lus, the output data 334 to 337 of 4n-bits derived from the respective shifters 1 to ~ are input into AUl and AU2.
AUl performs the swmnation or subtraction on the data from the shifters 1 and 4 and the resultant data is supplied to kU3. AU2 performs the summation or subtraction on the data from the shifters 2 and 3 and supplies the resultant data to Au3 AU3 furthermore executes the summation or subtraction on the data derived from AUl AU2 and thereafter sends the resultant data as the 4n-bit final calculation resultant data to the calculation unit 6.
A description of a required amount of calculation on the various calculating modes will now be made.
(1). A double precision multiplication.
Fig. 29(a) represents a diagram for showing operation contents of the shifters 1 to 4 and AUl to AU3 in this case. That is in the shifter 4 the shift value 0 is processed and the n-bit left shift process is performed in the shifters 2 and 3 further 2n-bit left shift process is performed in the shifter 1. In ~U2 the summation is carried out the summation is executed in AUl and the sw~nation is performed in AU3 whereby the double precision multiplication is performed. In this 131 t~63 case, a re~uired amount of calculation is l machine cycle per l d~ta, which is the same as that. of t.he collvelltional ap~aratus.
( 2 ) . A single precision parallel multiplication.
In Fig. 29(b), there are shown the opera1-ion cor1tents of the shifters l to 4 and AUl to AU3 in this case. In this case, it should be not:ed taht as the single precision data, two pieces of data have been previously stored in the data melTIory 4 having 2n-bit data sizes, by way of tile multlplex as shown in Fig. 36. Then, both the multiplication result (Al x Bl ) on the upper n-bit input data, and multiplication result (A0 x BU) on the lower n-bit input data are obtained with the respective MPY l and MPY 4. Thereafter, the shift value 0 is processed in the shifter 4, the 0-set is performed in the shifters 3 and 2, and the 2n-bit shift is carried out in the shifter l. Then, additions on the data are performed in AUl, AU2, and AU3, so that the single precision multiplication results are multiplexed into a resultant 4n-bit data as an upper 2n-bit and lower 2n-bit data. In this case, the required calculation amount becomes 0.5 machine cycles per l data, which is at a speed of two times higher than that of the conventional apparatus.
(3). A single precision parallel sum-of-product calculation.
~ 'ig. 30 illustrates the operation contents of this calculation. Fig. 31 shows an calcula-tior1 flow. Also, in this case, the single precision data has been rnultiplexed as shown in Fig. 36. After the initiali~ation is set at the step ST ~31; in the parallel surn-of-product calculatios~ process of step ST 332, the following processes are executed. That is, the shift value 0 is processed for the multiplication result (A0 x B0) of t.he lower n-bit data of two pieces of input.
data in 1-he shift.er 4; "0" set is performed in the shiEters 3 and 2; the shift process of the shift value "0" are perfonned wit.h respect to the multiplication result (Al x Bl) of the upper n-bit ir- the shifter l. In AUl, a addition of (A0 x so) + (Al x Bl) is carried out. In AUl, a addit:ion of (U + 0) is effected, and further another addition of (A0 x B0) + (Al x Bl~ + 0 is performed in AU3.
As a result, an accumulation value of two single-mult.iplication-resultant-data is obtained. Then, this accwnulation value is furthermore accumulated in the post-staged calculating unit 6 by M/2 times repeatedly by way of the process defined by the step ST 333. Thus, the sum of products containing M pieces of data are executed. In this case, a required calculation amount becomes 0.5 machir1e ~ycles per 1 oul:put data, which is at a speed of t~o limes higl~er t.hall that of the conventional calcul.a ~ iOIl .
(4). ~ single precision complex nwnber calculation.
In Fig. 32, there are shown the operation contents of this calculation. In Fig. 33, there is SIIOWIl a calculation flow t~lereof. In this case, it.
is assumed that a real number part multiplexed into t.he upper n-bits and an imaginary number part multiplexed into the lower n-bits of data have been stored in the data memory 4. ThUS, after the init.ialization defined by the step ST 341 has been effect:ed, the complex nwnber calculating process of step ST 342 is performed as follows. As shown in Fi~. 32, a 2n-bit left shift operation is performed in the shifter 4 for the multiplication result (A0 x B0); a shift value "0" is processed for (Al x B0) in the shifter 3: a shift value "0" is processed for tA0 x B1) in the shifter 2; a 2n-bit left shift operation is performed for tA1 x Bl) in the shifter 1. Then, a subtraction of tA1 x B1 - A0 x B0) is perfonned in AU1, an addition of tA1 x B0 ~ A0 x B0) is effected in AU2, and anot.her addition of tAl x Bl - A0 x B0) ~ tAl x B0 ~ A0 x B1) is carried out in AU3. As a result, the resultant data is ob~ained in such a form that the real number yart of the complex number multiplicat.ion result is multiplexed into an upper 2n-bits, and the imayi1~ary nwl1~er part 1-1~ereof is multiplexed into a lower 2n-bi~~s. In this case, a re~uired calculat.ion amount becomes l machine cycle per l da1.a, which is five times higher than the convent:ior1al calculation speed.
(5). ~ binary tree retreive vector quantization calculation.
Fig. 34 shows an operation contents of tl~is calculation, and Fig. 35 represents an operatio1) flow 1-hereof. In this case, it is assumed that one of two pieces of input data has been stored in the data memory 4 by a multiplexed forma1- every element of the binary tree search vectors.
An element of vector "y0" is stored in the upper n-bits of one input data "A", an element of vector "Yl is stored in the lower n-bits thereof; and an element of vector "x" is stored in the lower n-bits of the other input data "B".
Thus, in a step ST 3S2, a "0" shift is performed for the multiplication result ~A0 x B0) in the shifter 4; a "0" shift is performed for the multiplication result (Al x B0) in the shifter 3; a "0" set is done in the shifters 2 and l. ~lso, an output from the shifter 4 is subtracted from an output from the shifter 3 in AUl the output from the shlf~-er 3 is added to an output from the shlfter 2 in ~U2; and an output from ~Ul is added to an output from AU2 in A~3. ~s a result, the resultar1t data (Yol x x~ Yll l) multiplier circuit 303 is obtained, an accumulation is performed in the post-staged calculating unit 6, and this accumulation is repeated by k times corresponding to the element nw11ber, so that the following resultant data are obtained:

~ ¦ ( Yoi X Xi ) - ( Yli i ~ }

k k i~-l(Yi Xi) - ~i (Yli x Xi) 0 i .... (13) wllere do: an inner product between the reference vector "yO" and input vector "x".
di: an inner product between the reference vector "Yi" and input vector "x".
Tllen, in a step ST 353, a matching decision is made by judging whether or not the above-described accumulated value (do - dl) is positive or negative. Thus, a required calculation amount per one sta~e becomes ~k + 4) machine cycles, which are approximately at a speed of two times higher than that of the conventional apparatus.
It should be noted that in the above-descL:ibed preEerred embodilnerlt ~U1 to ~U3 are employed as 1-he aritllmetic calculators and a mere adder may ~e utilized for ~U2 and ~U3.
~ description of a fourtll preferred embodiment according to the invention will now be made. In Fig. 37 it should be noted that sarne reference nulllerals will be employed Lor denoting the same or simiLar circuit elements shown in Fig.
11 and a further explanation thereof is omitted.
In Fig. 37 reference numeral 411 indicates a data decision device; 412 denotes an input/output path for conrlecting the data bus 5 and data decision device 411; and 413 denotes an output path from the calculating unit 6 to the data decision device 411.
Fig. 38 is a block diagram of an internal arrangement of the above-described data decision device 411. In Fig. 38 reference nwlleral 415 is a threshold register group; 417 is a comparator group for comparing the calculation data with the threshold values 419 represents a condition decision device for judging the region of the calculatioll data based upon the comparator output so as to compare a branch condition with the decision result; 420 represents a condition register for holding the branch condition and address index information indicating a destination;

13t 1063 424 indicat-es an address register file for holding a l~lurality of destinated branch addresses correspondiny to the conditions of the condition register; 412 represents an input/output path and reference numerals 413, 414, 416, 418, 421 and 422 are outpu1- paths.
Fig. 39 is a block diagram of an internal arranyement of the condition decision device 419.
In Fiy. 39, reference numeral 426 indicates a region decision circuit: 428 is a condition comparing circuit; and reference numerals 418, 421, 422 and 427 are output paths.
~ n operation will now be described. In Fiy. 37, the data decision device 411 compares the data to be compared which is input from the calculating unit 6 via the output path 413, with "n" pieces of threshold values which are supplied from t-he previously set threshold value register group 415 via the output paths 416 in the comparator 417, and judges the data region of the data in question in the condition decision device 419 based upon "n" pieces of comparison results (comparison result is represented by one bit data of "O" or "1") supplied via the output path 418.
Fig. 40 represents an example where (n +
1) pieces of regions 0, ---, 4 into which the threshold values aO, ---, a9 divides, the colnpara~-or ou~pu~s and region decisiorl are shown.
In thls case, a specific bit is set to "1" in accor~ance with the region number.
Tlle region decision circuit 426 of tlle 5 conditioll decision device 419 iudges the region of the data based upon the cornparator outputs which are supplied from the comparator group 417 via the output paths 418, and outputs to the output path 422 an index signal indieating the reyion. The 10 condition eomparing eireuit 428 outputs to the output path 422 an address index indieating a brancllir)g address when the condition is satisfied by comparing this region index signal with the condition signal which has been supplied from the 15 condition register 420 via the output path 421.
Fig. 41 illustrates one example of a format of the eondition signal stored in the eondition register 420. In Fig. 41, symbols f0 to f4 denote a region "o" designation flag to a region 20 4 designation flag, eaeh of whieh beeomes "1" at the designation, and "0" at the non-designation.
plurality of conditions 1 to m ean be designated, a priority ordex of the conditions to be compared is set, and these conditions are sequentially 25 eompared. Onee a eondition is satisfied, an address index signal is output from the eondition decision device 419 via the output path 422.

Into the address register file 424, a plurali~:y of brarlcll addresses corresponding to the respec~-ive conditions have been stored, arld the brallcll address signal is output to the output path 414 based upon the address index signal supplied from ~he condition decision device 419 via the output path 422. As a consequence, based upon the output address value, the control circuit 3 performs the branch operation by setting a count value of the program counter built therein to this address value.
In case that all of conditions are not satisfietl, the above-described address index signal is "OFF", and also the address signal output from the address register files 424 is "OFF", and the count value of the program counter points a next instruction address.
As to the data supplied from the calculating Ullit 6 via the output path 413, which is to be chec1ced by this data decision device 411, one of OlltpUtS from tlle arithmetic calculator, multiplier, accurtlulator within the calculating unit 6 is defined by the instruction such as the mode setting operation, and a check is made by the data decision device 411 every machine cycle, so that a loss of the processing time required for comparing the data with the data regions can be prevented.

I'ig. 42 represents a continuous processirlg flow containing an intermediate check.
First-, initializations such as a selection o~
objects to be cornpared, a threshold value data set, a branc}l address set, and a branch condition set, are performed (step ST 401). Then, both calcuLation process and condit:ion decision process are repeatedly performed in parallel via t:he process data loop by the number of processing data, and the addresses A to C are output when the condi~ions 1 to 3 are satisfied.
~ eferring now to drawings, a fifth preferred embodiment of the present invention will be described.
Fig. 43 is a block diagram of the digital signal processor according to the fifth preferred embodiment of the invention. It should be noted that in Fig. 43, same reference nwnerals will be employed for denoting the same or similar circuit elemellts shown in Fig. 13, and therefore, no further explanation is made. In Fig. 43, reference nurneral 516 represents a register preserving memory for preserving the ~ata store~ in the respective registers during the execution of the interruption;
517 is a repeat flag register (rfr) for representing that the repeat instruction is under execution; 513 represents a repeat flag stack ~ 79 -t31 1063 (rfsk) func~-i.oning as a memory for preserving data w~len t-he illterrupt-ion is accepted, 519 denotes a rear repeat counter (rch) for holding a number of an ini~-ial value of repea1-ing; and 520 indicates an illterrupt enable controlling unit for performing an automa-tic disable process of interruptions when the interruption is initialized.
The register preserving memory 516 ~lolds properly register values of registers needed to preserve for an interrupt processing routine. ~nd, ttle interrup~ enable controlling unit 520 inhibits automatically a ~/W interrupt during an access to t.he external data memory and during executions of a branc}l instruction, return instruction, and S/W
interrupt instruction~
Referring now to Fg. 43, a H/W interruption process operation will be described. When the interruption is demarlded in an external device, the external device announces an occurrence of -the interruption request to the interruption controlling unit 513 in response to the interruption reguest signaJ. 514.
Upon accepting the interruption, the interruption request is output from the interrup~ion cont.rolling unit 513 to the sequence controlling unit 505. Upon receipt of this int.erruption request, a non-operation instruction is se~ o ~he instruction execution controlling unit 3, an~ ~he up~a1:e operation of the program counter 2 is pro1libite~.
Thereafter, an interruption acknowle~gemerlt signal 515 is sent from the interruption controlling unit 513 to the external ~evice, and in principle, the 1~ interruption is prol1ibited duri11g the interrupt operation.
It should be understood that it is lU substituted by such an instruction that no operation is made in the sequence controlling unit 505. Other interruptions than the interruption under processing, e.g., executions on the memory wait cycle during access of the external data memory, and also decoding of branch instructions, return instructions, and S/W interrupt, are automatically disabled by the interrupt enable controlling unit 520.
Upon receipt of the interruption instruction, the non-operation instruction is set to the instruction execution controlling unit 3, the count ~alue of the program counter 2 is automa~ically pushed in the PC stack 504 and also an interrupt address is set to this program counter.
In case of the interrupt operation during the repeat operation, it is furthermore required to -- ~1 --t31 ~063 s~ore a condition of a repeat flag register 517.
Tlle regis~er value of the repeat flag register 517 is au~omatically preserved into the repeat flay stack 51~ in order to accept the interruption instruction even during the execution of the repeat instruc-t iOI- .
The preserving operation of the register values of the registers used in the interrupt processing routine, is carried out at the destinated interrupt address by a register preserving instruction (push). The return operation froln the interrupt operation is effected in response 1:o a return instruction Irti). Before the execution of this return instruction the register values obtained before the interrupt process routine are set into the respective registers in response to a register value return instruction (pop) at the destinated interrupt address.
Thereafter, the return instruction is executed to return from the interrupt operation.
In this case, the count value of the program counter 2 is poped from the PC stack 504, the non-operation instruction is set to the instruction execution controlling unit 3, and thereafter, the register value of the repeat flag register 517 is restored from the repeat flag stack 51~.

- ~2 -Fi~J. 44 is a timirlg chart for explaining ~ e rlormal interrupt- operation. ~ig. 45 is another tilnirlg c~l~rt- for explaining the interrupt operation during tlle repeat instruction execution. ~t the second stage of 1:he repeat instruction, a reyister value "1" is set in t:he repeat flag register 517, and "1" is su~tracted from the counter value of the rear repeat counter 519 so as to perform the repeat settiny operation At this time, at ttle first stage of the instruction word designated by the instructi~n address PC (n + 1), the program counter 2 is not updated. Also, at 1:he second stage, when "1" has been set in the repeat flag register 517, "1" is subtracted from the count value of the rear repeat counter 519 so as to test whether or not it is equal to "0". If zero, this instruction is perormecl.
Once t.he interrupt request is accepted, the non-operation instruction is set to the inst.ruction execution controlling unit 3, the register value of the repeat flag register 517 is preserved to the repeat flag stack 518 and also PC
(n + 1) is preserved to the PC stack 504. Then, after the interruption, the count value of the repeat counter 9 is preserved to the register preserving memory 516 in response to the register 1 3t 1 063 prese:rvil~g instruction.
sefore the interrupt process routine is accomplisiled, both the preserved count value of the repea~- counter 9 and t.he respective register values are set illtO the respective registers in response to t.lle register value return instruction. In case of return from the interrupting operation, the instruction address PC (n + 1) is poped from the program counter staclc 504 to the program counter 2 in response to t.he S/~J return instruction, and also the non-operation instruction is set as a subsequent inst.ruction to the instruction execution controlling unit 3. Thereaft.er, the data before the interruption is poped from the repeat flag stack 51~ to the repeat flag register 517~
As a result, since "1" has been set in the repeat. flag register 517, the count value of the repeat counter 9 is subtrated by "1" to become "1"
and the repeat instruction is again executed.
2~ In the external 1l/~ interrupt operation, the processor can be corllpletely returned by processing the interruption instructions as explained above in the preferred embodiment even when the normal interruption and repeat instruction are executed.
As a result, it can prevent the processor processing efficiency from being lowered.
It should be noted that the repeat - ~4 -opera~iorl number was four in the above-described preferred embodirnent while t:he interrupt operation was execute~ durirlg the repeat operation. Ilowever, according to the invention, since the system can be completely returned from the interrupt opera-tion even just after the execu~ion o~ the repeat instruction and just before the execution thereof, the interrupt operation may be arbitrarily performed in any operations other than the inhibit period of the interruption~
Also, since there is no relationship between the essential feature of the present inventioll and the detailed specifications of the above-described preferred embodiment, the above-described descriptions do not limit the contents ofthe invention.
Referring now to figures, another preferred em~odiment o~ the invention will be described. Fig. 46 is an explanatory diagram on a motioll compensation calculating method according to a preferred embodiment of the invention, and Fig.
47 is a flowchart for explaining a detecting process of motion vector. In Fig. 46, reference numeral 610 is a seaxch small-regions into which a motion vector search range 604 is equally divided 611 represents motion vectors whose distortion amounts are to be calculated and which are arranged - ~5 -ill an e~uidis~arlce within the search small-region 610; 612 denotes a minilrium distortion region where a summat-ion ~ ~he in~er-~loclc distortion amounts of the motion vect:ors 611 which have been positioned in t-he search small-region 610: and 613 represents a limited search range having the moving vec~ors whose distortions are to be calculated disposed at a higher density.
Fiy. 46a illustrates a region decision step. ~s illustrated, the complete motion vector search range 604 is equally subtlivided into a plurality of search small-regions 610. It is assumed that a total number of these search small-regions 610 is "~". In the respective search small-regions 610, there are equally arranged the motion vectors 611 whose distortions are to be calculated at a coarse density. ~t this time, it is assumed that a total nwtlber of these motion vectors 611 to be distortion-calculated is "e". ~n amount of inter-block distortion 'ldqll (q = 1 to e) between the block of the position of this motion vector 611 and the presently input block 603 is calculated (step ST 601) and a total thereof is assumed as an intra-region distortion amount "Dj"
(j = 1 to R) of this search small-region 610.
In this case, since the following equation (14) is satisfied, i.e., - ~6 -131 ~063 e e L
Dj = ~ xp - yiP¦ ....
~ =1 q=1 P=l a calculation arnunt per one search small-region 610 is expressed in units of machine cycle as follows:
(~ x L x a) .... (15) The above-defined calculation is carried ou~, over all the search small-regions 610 so as to de~ect a minimum distortion reyion 612 having a miIliInum intra-region distortion amount "D min"
(step ST 602). At this time, a calculation amount is equal to:

((e x L x a) x R + R x ~) .... (16) Then, as illustrat,ed on the moving vector detecting st.ep in Fig. 46(b), the limited search range 613 having a size of K1 x K2 with the minimum distortion region 612 obtained in the region decislon step as a center is set, and the motion vectors to be searched at the higher density are positioned within this search range 613 (step ST
603). A calculation amount within this limit.ed 2U search range 613 is obtalned by summing the following items (17) and (13).
((kl x k2) x L x a) .... (17) (kl x k2) x b .... (1~) 'I'he item (18) is obtained by the comparison process.
Assuming that the total number " R" of the search small-regions 610 is equal to nine (9), the nunlbel- e of the motion vectors 611 to be calcu:lat-ecl wi1^hill t:he search small-region 610 i5 e(lual to four (4): and the values of kl and also k2 in the limit:ed search range 613 are equal to six (G) total calculation amount is defined in UllitS
oE machine cycle as follows:
S = ( (e x L. x a) x R + R x b ) + (kl x k2) x L x a + (kl x K2) x b ~ 4.~00 ...- (19) ~s a consequence, the resultant calculation amount is reduced t.o approximately 1/4 of a calculation amourlt of full searching.
It should be noted that although the range limitat.ion by the searching operation at a low density was one stage in the above-described preferred embodiment, a plurality of stages may be utilized for limiting the search ranges.
~ lso, the difference absolute value sullllnatioll was utilized for t.he distortion calculat.ion in t.he above-described preferred embodiment. a difference square summation may be utilized.

- ~8 -

Claims (28)

1. A digital signal processor comprising:
an instruction memory for previously storing control means to instruct various internal operations as an instruction word;
an internal data memory for storing calculation data;
a calculator for performing various calculations on at least one data read from the internal data memory in accordance with the instruction word read from the instruction memory;
an accumulator for accumulating an output from the calculator;
an accumulating register for holding an output from the accumulator;
a minimum distortion register for holding a minimum distortion;
a minimum distortion position register for holding a number of a block having said minimum distortion;
a block counter for holding a number of a block under distortion calculation;
a comparator for comparing an output value of the accumulator with a value of said minimum distortion register every cycle while, in order to detect the minimum distortion among M
blocks (M being a positive integer) of a data series, the distortion calculation is performed on a k-th block (l <k <M, "k" being an integer) of M blocks of the data series; and, an instruction execution controlling unit for executing the control means upon decoding the insatruction word supplied from the instruction memory.

2. A digital signal processor as claimed in claim 1, wherein said control means includes program means in which an accumulation is interrupted when the output value from the accumulator exceeds the value of said minimum distortion register in progress of the accumulation, the process is advanced to an instruction of a subsequent address or an instruction of a designated address, and when the accumulation is completed, the value of said accumulating register is written into said minimum distortion register and the block number held in said block counter is written into said minimum distortion position register.

3. A digital signal processor as claimed in claim 1, wherein said control means includes program means in which an accumulation is interrupted when the output value of said accumulator is equal to the value of said minimum distortion register in progress of the accumulation, the process is advanced to an instruction of a subsequent address or an instruction of a designated address, and when the accumulation is completed, the value of said accumulating register is written into said minimum distortion register and the block number held in said block counter is written into said minimum distortion position register.

4. A digital signal processor as claimed in claim 2 or 3, further comprising a repeat counter to which an accumulation number stored in said internal data memory is set and referred by said control means.

5. A digital signal processor comprising:
an instruction memory for previously storing an instruction word to define various internal operations;
an instruction execution control unit for controlling operations such as a decoding and calculation of said instruction word read from said instruction memory in a predetermined order;
a calculation unit for performing various calculations on two input data transferred from a data bus and from an internal data memory storing calculation data;
a data output bus for transferring a calculation result derived from said calculation unit to said internal data memory;
an address generating unit for generating 2-input and 1-output data in parallel to said calculation unit;
an external data memory connecting unit for reading and writing the data between an external data memory and said data bus in response to values output from said address generating unit;
a mode register for setting an access method of said external data memory;
a direct memory transfer bus for connecting one of ports of said internal data memory to said external data memory connecting unit; and a direct data memory transfer control unit for inputting and outputting the data in units of block between said external data memory connecting unit and said internal data memory via said direct memory bus, in independence of the internal operation controlled by said instruction execution control unit.

6. A digital signal processor as claimed in claim 5 wherein said more register includes an address output mode unit for holding information to select one of first and second modes, said first mode outputting both an upper address and a lower address to said external data memory, and said second mode outputting only the lower address thereto; and, a memory connecting unit for holding selection information whether or not a read/write completion signal is handled between said external data memory and itself.

7. A digital signal processor as claimed in claim 6, wherein said direct data memory transfer control unit includes;
a frame horizontal size register connected to said data bus for representing a horizontal size of a two-dimensional address space;
a block horizontal size register for representing a horizontal size of a rectangular portion in the two-dimensional address space;
a block start address register for indicating a head address of said external data memory;
an internal memory start address register for representing a head address of said internal data memory;
a word register for indicating a transfer word number;
a DMAC register for selecting an external address output mode and an external memory connection mode;
a DMA address calculation unit for performing an address calculation of said external data memory; and, a DMA control unit for performing a direct memory access transfer.

8. A digital signal processor as claimed in claim 7, wherein said DMA address calculation unit includes:
means for generating a two-dimensional block address supplying to said external data memory and a one-dimensional address supplying to said internal data memory, based upon the respective values which have been set in said frame horizontal size register, block horizontal size register, block start address register, and internal memory address register.

9. A digital signal processing processor claim 8, wherein said DMAC register includes:
an address output mode unit for holding selection information to select one of first and second modes in response to data supplied from said data bus, said first mode outputting both an upper address and a lower address to said external data memory, and said second mode outputting only the lower address thereto; and, a memory connecting unit for holding selection information whether or not a read/write completion signal is handled between said external data memory and itself.

10. digital signal processor as claimed in claim 9, wherein said external data memory connecting unit includes:
changing means for inputting/outputting data between said direct data transfer bus and said external data memory in case that the address of said external data memory is designated by said direct data memory transfer control unit, and for inputting/outputting data between said external data memory and one of both the data bus and the data output bus when the address of said external data memory is designated by said address generating unit.

11. A digital signal processor as claimed in claim 10, wherein said external data memory connecting unit further includes:
mode setting means for changing an address mode output to said external data memory in accordance with a set value of said mode register or said address output mode unit of the DMAC
register, and for changing such a condition that the read/write completion signal is input or not in response to said set value of said mode register or said memory connecting unit of the DMAC register.

12. A digital signal processor as claimed in claim 11, wherein said external data memory connecting unit includes:

means for interrupting data input/output operations between said direct data transfer bus and itself in case that a request to access to said external data memory is generated by said calculation unit during inputting/outputting data between said external data memory and said direct data transfer bus, and for executing inputting/outputting data between said external data memory and one of both said data bus and said data output bus.

13. A digital signal processor including a program memory for storing a microprogram; a control circuit for performing a fetch of said microprogram in said program memory, decoding, data reading, a calculation and writing of a calculation result in parallel pipelining; a data memory capable of storing 2n-bis data-sized data, and simultaneously reading out two data; an address generating unit for generating addresses for said data memory; a multiplier circuit for performing a multiplication, addition or subtraction between the two data read simultaneously from said data memory;
a calculation unit for performing an arithmetic calculation or accumulation with respect to said two data or resultant data of said multiplier circuit; and, a data bus for transferring said two data and the resultant data from said calculation unit, wherein said multiplier circuit comprises:
a first register and a second register for holding one and the other of said two data respectively;
a first multiplier to a fourth multiplier provided in accordance with four combinations respectively among two upper-side bits and two lower-side bits of the two data held in said first and second registers, for performing four multiplications respectively in parallel;
a first shifter to a fourth shifter provided in accordance with said first to fourth multipliers respectively, for performing four shift or zero-set processes respectively in parallel in response to said microprogram as to the respective resultant data from said first to fourth multipliers;
a first arithmetic calculator for receiving both outputs from said first and fourth shifters to perform an addition or subtraction process in response to said microprogram;
a second arithmetic calculator for receiving both outputs from said second and third shifters to perform an addition or subtraction in response to said microprogram; and, a third arithmetic calculator for receiving both outputs from said first and second arithmetic calculators to perform an addition or subtraction in response to said microprogram, so as to supply 4n-bit output data to said calculation circuit.

14. A digital signal processor as claimed in claim 13, wherein said microprogram includes:
control means for controlling said first to fourth shifters and said first to third arithmetic calculators in response to respective sorts of calculations to be executed.

15. A digital signal processor as claimed in claim 14, wherein said control means includes:
double precision multiplying means for shifting contents of said second and third shifters to the upper side by lower-side bits, for shifting a cotent of said first shifter to the upper side by a data length, and for instructing said first to third arithmetic calculation units to perform addition processes respectively.

16. A digital signal processor as claimed in claim 14 or 15, wherein said control means includes:
single precision parallel multiplying means for setting all contents of said second and third shifters to zero, for shifting a content of the first shifter to the upper side by the data length; and for instructing said first to third arithmetic calculation units to perform addition processes respectively.

17. A digital signal processing processor as claimed in claim 14 or 15, wherein said control means includes:
single precision parallel sum-of-product means for setting all contents of the second and third shifters to zero, and for instructing said first to third arithmetic calculation units to perform addition processes respectively

18. A digital signal processing processor as claimed in claim 14 or 15, wherein said control means includes:
single precision complex number calculating means for shifting each of contents of said first and fourth shifters to the upper side by the data length when a real number part is set to upper side bits of respective values which have been set to said first and second registers, and when an imaginary number part is set to lower side bits of the respective values which have been set to said first and second registers, and for instructing said first arithmetic calculation unit to perform a subtraction process, said second and third arithmetic calculation units to execute addition processes respectively.

19. A digital signal processor as claimed in claim 14 or 15, wherein said control means includes:
a binary tree search vector quantization calculating means, in case that a first vector element is set to the upper side bits of said first register, a second vector element is set to the lower side bits of said first register, and a third vector element is set to the lower side bits of said second register, for setting all contents of said first and second shifters to zero for instructing said first arithmetic calculating unit to perform a subtraction process and each of said second and third arithmetic calculating units to perform addition processes respectively, and for constructing said calculating unit to accumulate an output value of said third arithmetic calculating unit so as to judge whether the accumulated value is positive or negative.

20. A digital signal processing processor in which a built-in microprogram is fetched and decoded, data is read and calculated in accordance with a content of the microprogram, and calculation result data is written as a basic operation, comprising:
a control circuit including a program counter for an address control of a fetched instruction;

a data memory for inputting/outputting data; and, a data decision device for selecting one of an output from an arithmetic calculator within a calculating unit, an output from a logical shifter, and an output from a multiplier in parallel with an operation of the calculating unit; for simultaneously comparing the selected output data with n-threshold values (n being a positive integer); for deciding said output data to exist in which region among (n+1) regions into which a data region is subdivided by said n-threshold values based upon these n-comparison results; and for sequentially comparing this resultant region with m-region limiting conditions (m being a positive integer) which are set previously to designate a present data region; so as to output, when one of said conditions is coincident, branch address information corresponding to said coincident region limiting condition among m-branch addresses which are set previously corresponding to said m-region limit conditions , or so as to output a signal representative of incoincidence of all the conditions when all of the m conditions are incoincident, characterized in that said control circuit updates said program counter based upon said branch address information output from said data decision device so as to generate an instruction address of a destination branch or adds "1" to said program counter based upon said incoincident signal output from said data decision device so as to generate a subsequent instruction address.

21. A digital signal processor as claimed in claim 20, wherein said data decision device includes;
a register group storing said threshold values;
a comparator for comparing calculation data with said threshold value output from said register group;
a condition decision device for comparing an output value of said comparator with a branch condition;
a condition register for holding said branch condition and index information representative of a destination; and an address register file for holding a destination address corresponding to said address index information.

22. A digital signal processor as claimed in claim 21, wherein said condition decision device includes:
a region decision circuit for storing information on a relationship between the output value of said comparator and a region; and, a condition comparing circuit for outputting said address index information when the condition is satisfied by comparing a region index signal output from said region decision circuit with the branch condition.

23. A digital signal processor comprising:
An instruction memory for previously storing an instruction word instructing various internal operations;
an instruction execution controlling unit for controlling various operations such as a calculation designated by said instruction word;
a data memory for storing calculation data;
a calculation unit for performing a calculation designated by said instruction word for said calculation data so as to output a calculation result and a condition;
a program counter for holding an instruction address;
a PC stack for preserving a count value of said program counter while the interruption operation is executed;
a repeat counter for counting a repeat number during an execution of a repeat instruction;

a repeat flag register for instructing that said repeat instruction is under execution;
a repeat flag stack for preserving a register value of said repeat flag register during the interruption operation;
a register preserving memory for preserving the respective register values and said count value of the repeat counter during the interruption operation;
an interrupt controlling unit for outputting an interrupt request signal to said instruction execution controlling unit upon receipt of an interruption operation, and for outputting an interrupt permit signal to an interrupt destination; and, an interrupt enable controlling unit for prohibiting a H/W interrupt operation during a wait cycle of external-data-memory accessing, and during decoding/executing an instruction of branch, return, or S/W interrupt.

24. A digital signal processor as claimed in claim 23, wherein said instruction execution controlling unit includes;
pipeline controlling means which contains:
a first stage for fetching said instruction word;

a second stage for decoding the instruction word fetched by said instruction execution controlling unit; and, a third stage for outputting a calculation result and a condition of said calculation unit based upon data obtained by decoding said instruction word.

25. A digital signal processor as claimed in claim 24, further comprising a rear repeat counter where the count value is subtracted at said second stage.

26. A motion compensation calculating method for detecting a block and a motion vector of the block having a minimum distortion obtained by calculating an inter-pattern analogy between each of blocks in a previously input frame and respective blocks of digital image data of a presently input frame, said blocks into which said presently input frame of the digital image data composed of a plurality of frames sequentially input in a time series, is devided, said method comprising the steps of:
setting a first motion vector search range of which size is predetermined and of which center is located at a position of an input data block to be encoded within the previously input frame;

equally subdividing this first search range into a plurality of regions;
arranging a group of first search motion vectors of n in number (n being a positive integer) in the respective regions at a coarse density;
claculating as an intra-range-distortion value a sum of distortion values, each of which representing an inter-pattern analogy between the input data block and a block data of a position pointed by the respective motion vectors of n in number;
detecting a region where the intra-range-distortion value becomes minimum within the first search region setting as a minimum distortion region, a region where a distortion amount with in this region becomes minimum;
setting, a second motion vector search range of which size is smaller than that of the first search range and of which center is located at a position of the minimum intra-region distortion value region;
arranging a group of second search motion vectors at a higher density within the second search range; and, detecting a most analogous block to the input data block through a minimum distortion calculation based upon the group of second search motion vectors, whereby both the block with this minimum distortion and the motion vector thereof can be used as a final prediction signal and a final motion vector respectively.

27. A motion compensation calculating method as claimed in claim 26, wherein the distortion calculation is carried out by a difference absolute value summation.

28. A motion compensation calculating method as claimed in claim 26, wherein the distortion calculation is carried out by a difference square summation.