CA1312134C - Cell switching system of asynchronous transfer mode - Google Patents
Cell switching system of asynchronous transfer modeInfo
- Publication number
- CA1312134C CA1312134C CA000595717A CA595717A CA1312134C CA 1312134 C CA1312134 C CA 1312134C CA 000595717 A CA000595717 A CA 000595717A CA 595717 A CA595717 A CA 595717A CA 1312134 C CA1312134 C CA 1312134C
- Authority
- CA
- Canada
- Prior art keywords
- packet
- buffer
- packets
- broadcast
- output lines
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/104—Asynchronous transfer mode [ATM] switching fabrics
- H04L49/105—ATM switching elements
- H04L49/108—ATM switching elements using shared central buffer
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/20—Support for services
- H04L49/201—Multicast operation; Broadcast operation
- H04L49/203—ATM switching fabrics with multicast or broadcast capabilities
Abstract
ABSTRACT OF THE DISCLOSURE
A fixed-length packet switching system, in which fixed-length packets (cells) each composed of a header portion and a data portion are received from a plurality of input lines, and after conversion of the header portions, the received packets are transmitted onto selected ones of output lines designated by their header portions. The system includes a buffer memory having a first buffer area composed of a plurality of subsidiary areas for accumulating cells correspondingly to the output lines, and a second buffer area for accumulating broadcast cells to be transmitted to selected ones of the plurality of output lines; a packet reading circuit for reading the cells from the buffer area successively corresponding to the output lines and for reading the broadcast cell from the second buffer area at a predetermined frequency;
and a broadcast control circuit for reproducing a plurality of broadcast cell from the broadcast cell read from the second buffer area and for transmitting the plurality of reproduced broadcast cells, instead of the cells read from the first buffer area, onto the output lines.
A fixed-length packet switching system, in which fixed-length packets (cells) each composed of a header portion and a data portion are received from a plurality of input lines, and after conversion of the header portions, the received packets are transmitted onto selected ones of output lines designated by their header portions. The system includes a buffer memory having a first buffer area composed of a plurality of subsidiary areas for accumulating cells correspondingly to the output lines, and a second buffer area for accumulating broadcast cells to be transmitted to selected ones of the plurality of output lines; a packet reading circuit for reading the cells from the buffer area successively corresponding to the output lines and for reading the broadcast cell from the second buffer area at a predetermined frequency;
and a broadcast control circuit for reproducing a plurality of broadcast cell from the broadcast cell read from the second buffer area and for transmitting the plurality of reproduced broadcast cells, instead of the cells read from the first buffer area, onto the output lines.
Description
BACKGROUND OF THE INVENTION
The present invention generally relates to cell switching systems and, more particularly, relates to a cell switching system using an asynchronous transfer mode which is a mode for realizing a broad-band multimedia switching system.
Prior art switching systems will be discussed hereinbelow in conjunction with the drawings.
SUMMARY OF THE INVENTION
The aforementioned problems are caused by the two characteristics of the conventional system as follows.
(1) The buffer memory for storing cells is periodically updat~d regardless of existence of input cells.
The present invention generally relates to cell switching systems and, more particularly, relates to a cell switching system using an asynchronous transfer mode which is a mode for realizing a broad-band multimedia switching system.
Prior art switching systems will be discussed hereinbelow in conjunction with the drawings.
SUMMARY OF THE INVENTION
The aforementioned problems are caused by the two characteristics of the conventional system as follows.
(1) The buffer memory for storing cells is periodically updat~d regardless of existence of input cells.
(2) Copies of the address designated for a broadcast cPll are stored in the queues.
It is therefore an object of the present invention to provide a packet switching system in which the capacity of the buffer memory for storing cells or packets can be used efficiently.
It is another object of the invention to provide a packet switching system which is suitable particularly for switching broadcast cells.
In order to attain the foregoing objects, the cell switching system according to the present invention has a feature in that writing of cells in the buffer memory is .~
1 3 ~ 2 1 ~ ~
carried out only when cells are inputted and that in the case of a broadcast cell, a cell body and an address are stored during buffering in the switching system so that necessary number o~ copies of the broadcast cell are generated when the broadcast cell is transmitted.
In accordance with one aspect of the invention there is provided a packet switching system in which a plurality of fixed-length reception packets each composed of a header portion and a data portion are received respectively through a plurality of input lines, and each of the reception packets is selectively transmitted onto one of a plurality of output lines as a transmission packet after conversion of the header portion of the reception pacXet, said packet switching system comprising: first interface means connected to said plurality of input lines, for receiving a serial signal of packets inputted from each of said input lines, and for outputting each of said packets with its header portion and data portion separated from each otheri buffer memory means divided into a plurality of buffer areas corresponding to said output lines, for storing said header-portion converted packets correspondingly to said output lines; packet writing means connected to both of said first interface means and said buffer memory means, for generating converted hPader portions to be given to respective transmission packets in accordance with the contents of the header portions of the respective reception packets outputted from said first interface means, ~2~ 3-~
and for writing said transmission packets each composed of the converted header portion and the data portion of the corresponding reception packet outputted from said first interface means into said respective buffer areas corresponding to the output lines through which said transmission packets are to be ouputted respectively by individually generating in a sequence plural writing addresses corresponding to storage locations in said respective buffer areas; packet reading means connected to said buffer memory means, for reading said transmission packets out of said buffer areas of said buffer memory means in a first-in first-QUt manner by successively accessing said buffer areas; and second interface means connected between said buffer memory means and said plurality of output lines, for converting said transmission packets respectively read out of said buffer areas of said buffer memory means into serial signals respectively and for transmitting said respective serial signals onto said output lines corresponding to said buffer areas from which said transmission packets are read out.
Another aspect of the invention is as follows.
To realize a switching function of broadcast mode in which one and the same input cell is transmitted onto a plurality of output lines, broadcast cells are accumulated in a broadcast cell buffer area which serves as a first-in first-out memory in the same manner as the output-line-corresponding buffer memory area. Each broadcast cell is read from the ~, ~2:~3~
broadcast cell buffer area at a predetermined frequency and accumulated in a broadcast cell register. For example, with logical channel number (LCN~ contained in the header of the thus read~out cell as an address, an output line number for indicating the output line to which the cell is transmitted is read ~rom an output line indication table and accumulated in an output line indication register. By transmitting the broadcast cell into an output interface circuit at a predetermined timing corresponding to the contents of the output line indication register, copies of the broadcast cell, instead of ordinary cells read from the buffer memory, can be transmitted to the plurality of output lines.
According to the present invention, even in the case where broadcast cells are concentrately inputted in the switching system, all the cells can stand by the transmission of the broadcast cell in the buffer memory as far as the total throughput in the switching system or throughput in e~ery output line does not exceed a predetermined limit of output throughput. Accordingly, the probability that queuing of input cells cannot be carried out because of the resource occupation of the queues by the broadcast cell is reduced, so that the loss probability of cells by the concentration of broadcast cells can be reduced remarkably compared with the conventional system.
'~4 The foregoing and other objects, advantages, manner of operation and novel features of the present invention will be understood from the following detailed description wh~n read in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a diagram showing an example of the construction of the whole of a conventional switching system;
Fig. 2 is a view of the construction of an ATM cell;
Fig. 3 is a diagram showing an example of the construction of the whole of the ATM switching system according to the present invention;
Fig. 4 is a detailed diagram of the broadcast control circuit 131 depicted in Fig. 3;
Fig. 5 is a view for explaining the output line indicating register 133 depicted in Fig. 4;
Fig. 6 is a view for explaining in detail the broadcast cycle designating register 422 depicted in Fig. 4;
Fig. 7 is a diagram showing an example of the construction of the phase synchronization circuit 103 depicted in Fig. 3;
Fig. 8 is a diagram showing an example of the input register 104 depicted in Fig. 3;
~ igs. 9A and 9B are views for explaining the function of the input register 104;
~A
, r,, ~
Figs. lOA and lOB are views for explaining the function of the output register 125 depicted in Fig. 2;
Fig. 11 is a timing chart showing the operation of the input reyisters 104 to 106; and Fig. 12 is a timing chart showing the operation of the output registers 125 and 126.
A cell switching system of asynchxonous transfer mode (hereinafter referred to as "ATM cell switching system") having such a configuration as disclosed in 10 Japanese Patent Publication JP-A-59-13599 is known. The principle of operation of the ATM cell switching system of the JP-A-59-13599 will be described briefly with reference to Fig. 1. In the following description, each cell (which is also called '~packet") 10 to be switched is assumed to have a 15 fixed length of 35 bytes composed of a 3-byte header 12 and a 32-byte user data 11 as shown in Fig. 2. The header 12 includes a logical channel number for identifying the logical channel to which the cell belongs. Cell switching is executed by identifying the destination of the cell at every switching 20 node on the basis of the LCN.
The above-mentioned values of the respective byte lengths of the entire cell, the header and the data are determined for the sake of convenience of explanation, while those values are not determined on the basis of the basic 2S principle of the present invention.
A
Fig. 1 shows a basic construction o~ the conYentional ATM cell switching system provided with 32 input lines 201a - 201n and 32 output lines 217a - 217n. Such a cell 10 as shown in Fig. 2 is periodically applied to each of the 32 inputs 201a to 201n synchronously with each other.
The respective input cells are converted from serial data into parallel data by means of a multiplexer circuit 203 so that the respective headers of the input cells are multiplexed and transferred onto a line 204 and the respective user data of the input cells are multiplexed and transferred onto a line 205. The line 204 is used for transferring parallel data of 24 bits (3 bytes) and the line 205 is used for transferring parallel data of 256 bits (32 bytes). The user data is written in an input-line-corresponding buffer memory 206 while the address of the user data is designated by an output line 208 of a counter 207. In this example, the output from the counter 207 is composed of 9 bits in which the upper 5 bits are used for designating any one of the input lines 201a to 201n. The buffer memory 206 has a memory capacity for 16 cells corresponding to each of the input linesO The lower 4 bits of the counter 207 are used for designating the cell address successively. Accordingly, the buffer memory 206 operates to successively store cells 10 periodically applied through the input lines into addresses designated by the counter 207, so that writing of cells in the whole cell area of the buffer memory 206 is perfected by 16 periods.
~1 3 ~ 2 ~ ~ ~
Thereafter, writing of cells is performed periodically so that new cells are successively overwritten in the area where old cells have been written. Accordingly, unless a cell stored in the buffer is read out of the buffer within 16 periods so as to be sent out through a switching system, the old cell will be lost in the switching system because a new cell will be overwritten on the old cell.
on the other hand, the headers 12 of respective cells 10 are fed to a header converter circuit 209 through the line 204. For example, the header converter circuit 209 may be constituted by a memory table. The memory table is read by an address determined by a co~bination of the LCN contained in the header of a cell and the number of the input line through which the cell is applied, 50 that routing data of the header, that is to say, an output line number and an LCN (generally, different from the LCN contained in the input header) for identifying the cell on the output line, are fed onto lines 210 and 211, respectively. The output line number on the line 210 is composed of 32 bits which respectively correspond to the output lines. The output line number indicates the fact that the cell will be transmitted to the output lines corresponding to the bit position where the bit takes '~1".
The LCN appears on the line 211 in synchronism with the writing of the user data of the cell in the input-line-corresponding buffer memory 2061 and written into a cell areaof the buffer memory together with the user data.
~ i ' q j ~
The address of the buffer memory 206 where the cell has been written is fed to a group of output queues 212a to 212n through the line 208 and stored in one output queue designated by the output line number. The output queues 212a 5 to 212n correspond to the output lines 217a to 217n, so that the address on the buffer memory 206 for one cell to be outputted is stored in the corresponding one of the output, queues for corresponding one of the outpu~ lines. Those output queues 212a to 212n are successively designated by the output of the counter 207 so that the contents of the buffer memory 206 are read out corresponding to the successively designated contents of the output queues, that is, addresses, and outputted to a line 215. Accordingly, cells to be transferred onto the output lines 217a - 217n exist on the line 215 in the multiplexed form. Those multiplexed cells are demultiplexed through a demultiplex circuit 216 and then the demultiplexed cells are respecti~ely correspondingly transferred onto the 32 output lines 217a to 217n.
The aforementioned ATM switching system however requires a switching function for broadcast mode. The broadcast mode is a mode in which one cell inputted through an input line is outputted onto a plurality of output lines. In the case of the conventional system as shown in ~ig. 1, one and the same address of the buffer memory 206 is written in the plurality of output queues by putting "l" in a plurality of bit positions on the line 210. As a result, one and the ,~
~ 3~
same address can be read from the plurality of output queues when the cell is to be outputted, and accordingly, the one and same cell can be transferred onto the plurality of output lines.
In this case, it is a matter of course that the respective broadcast cells have not only one and the same under data but also one and the same contents o~ the header.
Accordingly, call control must be carried out on the assumption that the broadcast cells on the respective output lines ha~e one and th~ same LCN.
The a~orementioned convention~l switching system has a problem that the quantity of hardware in the memory constituting the address queues 212a - 212n becomes large. In particular, when priority, for example, classified by service classes, is established in handling cells in ATM switching, queues must be set as classified by service classes, so that the quantity of hardware is more increased.
Further, in cell transmission in the broadcast mode, a broadcast cell is stored with one and the same address as the buffer memory 206, in each of the queues through which the broadcast cell is to be transmitted. Accordinyly, a problem arises in that the capacity of the queues for storing cells belonging to other LCNs is reduced. For example, in the example shown in Fig. 1, it is a necessary and sufficient condition that the output queues have an address storage capacity for 16 periods, that is, for 16 cells, because the input-line-corresponding buffer memory 206 is always updated or overwritten with the passage of time of 16 periods or more.
Accordingly, for example, in the case where 16 broadcast cells ko be transmitted onto all the output lines are inputted in one period, all the queues are occupied by those broadcast cells so that other input cells become lost because of existence of no vacant ~ueues.
Even if the number of cells inputted in several periods befor~ and after the period in which 16 broadcast cells are inputted is not so large that the total throughput in the switching system for the short duration or the throughput in every output line is within a limit of output throughput~ lost cells may occur in case of instantaneous concentration of broadcast cells. This is a serious problem in the traffic performance of the switching system. To solve these problems by the conventional system construction, both the capacity of the queues 212a to 212n and the capacity of the input-line-corresponding buffer memory 206 must be increased. However, a disadvantage arises in that efficiency in use of the memory is lowered, because the increased portion of the buffer memory is not used when there is no concentration of broadcast cells.
Referring to Fig. 3, there is shown the configuration of an embodiment of the switching system according to the present invention, which has 32 input lines lOla - lOln and 32 output lines 130a - 130n for switching 35-byte fixed-length cells in the same manner as the convantional system as shown in Fig. 1. A phase synchronization circuit 103 and input registers 104, 105 and 106 are provided to carry out a function equivalent to 3 ~
1 that of the multiplexer circuit 203 shown in Fig. 1.
The construction and operation of the phase synchroniza-tion circuit 103 and the input registers 104, 105 and 106 will be described in detail later~ In this embodiment, input cells are converted from serial data into parallel data by the phase synchronization circuit 103 and the input registers 104 to 106 in the same manner as the conventional system. Then, the respective headers of the cells are multiplexed and transmitted onto a line 107 and the respective user data of the cells are trans-mitted onto a line 108. The header is fed to a header conversion circuit 109 and converted, by the header conversion circuit 109, into routin~ information, that is to say, an output line number, to be fed onto a line 110 and LCN on the output line to be fed onto a line 111.
The user data fed onto the line 108 is written, together with the LCN, into an idle area in the output-line-corresponding buffer memory area preliminarily designated in the buffer memory 112 corresponding to the routing information on the line 110. The routing information on the line 110 is composed of 6 bits, in which 5 bits are used for designating one of the 32 output lines 130a - 130n and the remaining 1 bit is used as a broadcast cell indication bit. In this embodiment, all the broadcast cells are always written in a broadcast buffer memory 113 regardless of the destination ~f those cells.
Addresses for writing into and reading out of ~ 3 ~
1 the buffer memories 112 and 113 are designated by write counters (WCNT) 114a to 114m and read counters (RCNT) 116a to 116m, respectively. 33 write counters and 33 read counters are provided corresponding to 32 output-line buffer memory areas and one broadcast buffer memory, so that an address for writing a cell into or an address for read-ing it from a buffer memory area corresponding to the aforementioned sections is designated. Each of those counters makes a counting-up or increment operation whenever a writing or reading operation is carried out.
In the case of writing operation, the output of one counter selected from the 33 write counters 114a to 114m by a selector 118 appears on a line 119 so that an address in the buffer memory 112 or 113 is designated by combination of the output on the line 119 with the routing information on the line 110.
In the case of output of cells from the switch-ing system, the output signals from the read counters 116a to 116m are successively selected by a selector 121 in accordance with the output value from a control counter 119 and successively transmitted onto a line 122. The output signals of the read counters 116a to 116m, together with the output value of the counter 119 obtained on the line 120, are given as read addresses to a buffer memory 112 or a broadcast buffer memory 113. The header portion and the user data portion contained in the data read from the buffer memory 112 or 113 are transmitted to lines 123 and 124, respectively. Then the header portion 3 ~
1 and the user data portion are transmitted onto selected one of the output lines 130a to 130n through output registers 125 and 126 and a selector 128. The output registers 125 and 126 and the selector 128 have a function equivalent to that of the demultiplexer circuit 216 of Fig. 1. The construction and operation of the output registers 125 and 126 and the selector 128 will be described in detail later.
The output from the control counter 119 is distributed into various parts of the switching system through a line 120 to thereby determine the sequence and timing for the periodic operation of the whole swit~hing system.
In the following, a broadcast cell output method in the switching system is described. When a broadcast cell is read from the buffer memory 113, copies of the broadcast cell are generated by a broadcast control circuit 131 by the number equal to that of the output lines through which broadcast is to be carried out, and the copies of the broadcast cell are transmitted onto those output lines respectively.
The construction of the broadcast control circuit 131 is shown in Fig. 4.
In Fig. 4 the reference numeral 400 designates a data (broadcast cell) read from the buffer memory. The data 400 is equivalent to a combination of the data obtained on the lines 123 and 124 shown in Fig. 3. In Fig. 4, the reference numeral 133 designates an output ~ ~ ~ 2 z ~ ~
1 line from the output line indicating table memory 132 shown in Fig. 3. The reference numeral 120 designates the output line from the control counter 119 as already shown in Fig. 3. The reference numeral 135A designates broadcast cycle indication information as a part (10 bits) of the output line 135 from a call processor 134 shown in Fig. 3. The reference numeral 136 designates an input line to the output registers 125 and 126. The reference numeral 137 designates a buffer memory read enable signal. Register write-timing signals 4~6, 427 and 428 are generated from a timing signal generation circuit (not shown in Fig. 3) for generating various control timing signals necessary for the switching system on the basis of the output signal of the control counter 119.
The broadcast cell 400 read from the braodcast buffer memory 113 is accumulated in a broadcast cell register 412. In this case, the header portion of the broadcast cell has been fed to the output line indicating table memory 132 shown in Fig. 3. Output line indication information of 32 bits is read from the output line indicating table memory 132 while the LCN contained in the header portion is used as a read address. The read results are accumulated in an output line indicating register 413 shown in Fig. 4 through the signal line 133. As shown in Fig. 5, the output line indication information is composed of 32 bits, in which ssme bits corresponding to the output lines to which the broadcast L ~ ~ J !~
1 cell needs to be transmitted have "1", remainder bits corresponding to the output lines to which the broadcast cell does not need to be transmitted have "0".
The timing for reading cells from the output-line buffer areas of the buffer memory 112 is designatedby the output 120 from the control counter 119. The output 120 is decoded by a control count decoder 414, so that the value on each of lines 415a to 415n is turned to "1" in the timing corresponding to the corresponding output line. The data on those lines 415a to 415n, together with the corresponding bits o~ the output line indicating register 413, are applied to AND gates 417a to 417n. An OR gate 419 performs logical OR of the output signals from the ~ND gates 417a to 417n. When the output from the OR gate 419 is "1", a bus output gate 42G is opened to thereby feed the contents of the broadcast cell register 412 onto the line 136. When the output from the OR gate 419 is "1", the output from a gate 421 takes 1l0l- SO that a signal for inhibiting reading of the buffer memory 112 i5 fed onto the line 137.
The output from the control counter 119 changes periodically so that the reading from the respective buffer areas of the buffer memory 112 corresponding to the 32 output lines is designated successively in the order of the output line number and then the reading from the broadcast memory 113 is designated upon comple-tion of the reading from the buffer memory area correspond-ing to the 32th output line. Upon completion of the reading 1 from the broadcast memory 113, the output from the eontrol counter 119 returns to its initial state so as to designate the reading from the buffer memory area corresponding to the first output line again. The period of from the reading of the broadcast cell to the reading of the cell to be transmitted onto the 32th output line is defined as one cycle. A broadcast cycle designating register 422 shown in ~ig. 4 is provided to designate thë cyele in which the reading of the broadcast cell from the buffer memory 113 and the transmission of the broadcast cell onto output lines are to be carried out. The broadcast cycle designating register 422 is constituted by a cyclic shift register which makes a shifting operation whenever one cycle is terminated, as shown in Fig. 6. Each bit of the shift register 422 corresponds to one cycle. The shift register 422 changes its bits eyelically so that the contents of the first bit are shifted to the second bit, the contents of the second bit are shifted to the third bit~ and the contents of the last bit (the 10th bit in the example of Fig. 6) are shifted to the first bit. The output of the first bit of the shift register 422 is fed to a line 423 to thereby control the output signals from the AND gates 417a to 417n and an AND gate 425.
In the eycle (braodcast eycle) where the first bit of the shift register 422 takes "1", each of the lines 424 and 423 in Fig. 4 respeetively takes "1" when the value of the eontrol counter 119 indicates the 1 read-enable state of the broadcast buffer memory 113, so that the output from the AND gate 425 for performing logical AND of the values of the lines 424 and 423 takes "1". Accordingly, the output from the gate 421 takes "1" to thereby feed a buffer memory read enable signal to the line 137, so that the broadcast cell existing in an address in the broadcast buffer memory 113 indicated by the read counter 116m is read and accumulated in the broadcast register 412. The broadcast cell thus accumulated in the broadcast register 412 is transmitted onto the output lines corresponding to the bits of "1"
in the output line indicating register A13, at predetermined timing designated by the control count decoder 414, as already mentioned above. Cells read from the buffer memory 112, instead of the broadcast cell, are transmitted onto the output lines corresponding to the bits of "0" in the output line indicating register 413 even within the broadcast cycle. In the cycle where the first bit of the broadcast cycle designating register is "0", all the output signals from the AND gates 417a to 417n and 425 take "0".
Accordingly, the buffer memory read enable signal on the line 137 takes "1" when the output-line-corresponding buffer memory 413 designated by the control counter 1~9 and, on the other hand, the signal takes "0" when the broadcast buffer memory is designated. Accordingly, the contents of the output-line-corresponding buffer memory 112 are transmitted to all the output lines but the broadcast cell is not transmitted. Further, reading from ~ 2:~3~
1 the broadcast buffer memory 113 is not carried out so that the contents of the broadcast cell register 412 are kept. It is apparent from the above description that the frequency of broadcast cell transmission is determined by the contents of the broadcast cycle designating register 422. If the all the contents of the register 422 are set to "0", no broadcast cell is trans-mitted. In the cycle where "1" is fed to the line 423, the broadcast cell is transmitted preferentially.
Accordingly, the degree of priority of the broadcast cell increases as number of bits of "1" increases in the broadcast cycle designating register 422. When all the bits of the resister 422 are "1", the priority is highest.
The call processor 134 determines a pattern to be written in the broadcast cycle designating register 422, consider-ing factors such as a broadcast call set state, a used band and the like. Although Fig. 4 shows the case where the broadcast cycle designation information (pattern) is composed of 10 bits, it is to be understood that the number of bits can be suitably selected in accordance with the determination of the frequency of broadcast cell transmission.
In the following, a switching input portion which is constituted by the phase synchronization circuit 103 and the input registers 104, 105 and 106, and a switching output portion which is constituted by the output registers 125 and 126 and the selector 128 shown in Fig.
3 are described.
1 Fig. 7 shows an example of the detailed construc-tion o the phase synchronization circuit 103. The phase synchronization circuit 103 performs the phase synchroniza-tion so that the respective phases of the input cells received from the respective input lines lOla to lOlm are shifted successively one byte by one byte. The phase synchronization circuit 103 is composed of 32 shift units 500a to SOOn provided corresponding to the input lines, and a control circuit 510 for controlling the operation of the shift units 500a - 500n.
For example, the shift unit 500a has a shift register 501 for receiving an input cell in the form of a serial signal from a data line lOa of the input line lOla, a tap selector 502 for selecting one of taps provided corresponding to the bits of the shift register to thereby transmit the input cell onto an output line Dl, and a decoder 503 for designating the tap to be selected by the tap selector 502. A synchronous signal lla for indicating the head of each input cell and an input cell transfer clock signal 12a are given to the decoder 503. The current position of the input head bit in the shift register 501 is grasped by counting the transfer clock. When an output timing signal 511 is given from the control circuit 510, the decoder 503 generates a selection signal corresponding to the count value, and the tap selector 502 selects one of the taps corresponding to the position of the head bit of the input cell. As a result, the input cell is serially transmitted ~- 3 ~ a 3 ~
1 onto the output line Dl in synchronization with the output timing. A shift register 504 for receiving a header having a data length o~ 3 bytes and a gate 505 for controlling transmission of parallel output signals from the shift register 504 to the line 107 are provided on the output line from the tap selector 502. The gate 505 is opened by a timing signal 512 from the control circuit 510 so that the header portion of each cell i5 transmitted onto the line 107. The control circuit 510 feeds the timing signals (511, 512) to each of the shift units 500a - 500n through the control signal lines 510a - 510n respectively in the condition that the respective phases of the timing signals are shifted successively one byte by one byte. Accordingly, the input cells with their phases shifted successively one byte by one byte are transmitted to the respective output lines Dl to D32, and, on the other hand, the header portions of the respective input cells are successively transmitted onto the line 107.
Fig. 8 shows the construction of an embodiment of the input register 104. Other input registers 105 and 106 have the same construction as the input register 104. The input register 104 is composed of one-byte serial=to-parallel conversion circuits (S/P circuits) 25 600-1 to 600-32 connected to the output lines Dl to D32 from the phase synchronization circuit lQ3, l-byte memory cells Ml_l to M32_35 arranged in the form of a matrix having 32 rows and 35 columns, a write address decoder 610, ~2~ ~4 1 a read address decoder 620, and a control circuit 640.
The output from each respective S/P circuit 600-Q is made to be data written in the 35 memory cells M~ 1 to MQ 35 in the corresponding Q-th row. The data read from those memory cells are fed to an ou~put register 630 through corresponding column-direction lines.
The write address decoder 610 decodes the count value 641 given from the control circuit 640 to thereby generate write signals Wl to W66 successively. The write signal Wl is generated at the timing when the S/P
circuit 600-1 connected to the output line Dl transmits the first byte of the first input cell, so that the aforementioned one-byte data is written in the memory cell Ml 1 The write signal W2 is generated at the timing when the S/P circuit 600-2 connected to the output line D2 transmits the first byte of the second input cell, so that the first one-byte data of the second input cell is written in the memory cell M2 1 and, at the same time, the second one-byte data of the first input cell is written in the memory cell Ml 2. In short, write signals are successively generated in the same manner as described above while the memory cell access position is shifted in order. In the case of the 32th write signal W32, the 32nd one-byte data of the first input cell is written in the memory Ml 3~, the 31st one-byte data of the second input cell is written in the memory M2 31~ ~ and the first one-byte data of the 32th input cell is written in the memory cell M32_1. In the case of the 33rd write 1 signal W33, the 33rd one-byte data of the first input cell is writ-ten in the memory Ml_33, the 32nd one-byte data of the second input cell is written in the memory M2 32~ and the second one-byte data of the 32nd input cell is written in the memory cell M32 2 In the case of the last 66th write slgnal W66, the 35th one-byte data of the 32nd input cell is wri-tten in the memory M32 35 On the other hand, the reading of data from these memory cells is carried out by read signals Rl to R32 generated from the read address decoder 620. Those read signals are successively generated corrresponding to the count value 642 from the control circuit 640. The read signal Rl makes access to one-row memory cells Ml 1 to Ml 35 at once. Similarly, the read signals R2 to R32 respectively make access to memory cells of one row which corresponds to one input cell (from the second input cell to the 32nd input cell). Thus, 35-byte (280~bit) data per input cell unit can be successively read into the register 630 from which 32-byte (256 bits) user data portion is outputted to the line 108.
Figs. 9A and 9B are views showing models of the function of the aforementioned register 10~. In the write mode, as shown in Fig. 9A, 32-byte parallel input cell data blocks are written successively in the positions shifted one byte by one byte. In the read mode, as shown in Fig. 9B, a 35-byte data block for each input cell, for example, a data block 910 having 35 bytes of from "0101" to "3501", is read at once as shown.
3 ~
1 The other input registers 105 and 106 have the same function as the input register 104. As will be described later, those three input registers 104, 105 and 106 are switched so as to be used successively to thereby constitute an input buffer of three input planes.
Fig. 11 is a timing chart showiny the relation between writing data into and reading data from the input registers 104 to 106. In Fig. 11, register numbers #1 to #4 correspond to the input registers 104 to 106, and terminal numbers 1 to 32 correspond to the input lines lOla to lOln and the output lines Dl to D32 from the phase synchronization circuit 103. In each of the registers, a write cycle and a read cycle are repeated alternately.
Since the input cells have been successively fed to the input registers while successively shifting one byte by one byte as shown by oblique lines, if the time (cycle) required for writing the one-byte data is represented by a symbol "B", the cycle of 35B is required for writing one-cell data and the cycle of 66B is required for writing 32-line input cells. In this embodiment, the next input cell (for example, A23 from the line through which writing of an input cell (for example, Al) in the first input register 104 (#1) is terminated is written in the second input register 105 (#2). When the writing of the input cell A2 is terminated, the next input cell (for example, A3) is written in the third input register 106 (#3). The further next input cell (for example, A4) is written in the first input register 104 (#1) again.
~ 2~ ~
1 In short, the input registers are used by turns. As a result, the idle time of 39B can be provided between the point of time when writing of 32 input cells in one input register is terminated and the point of time when writing of next input cells is started. If data are read by one cell per cycle from the input register in which writing is terminated, the time of 32B is required for reading all the 32 cells~ Accordingly, the idle time of 39B after the termination of input cell writing is used in each register so that all input cells can be successively read and written in the buffer memories 112 and 113. Data read from the buffer memories 112 and 113 are transmitted to the output lines 103a to 103n through the output registers 125 and 126 and the selector 128.
Writing of data into the output register 125 (or 126) is carried out so that one-cell data of 35 bytes read from the buffer memory are written into an address corresponding to the output line in the form of a parallel data block 920 composed of data of from "0132"
to i'3532" as shown in Fig. 10A. When the time required for writing one-cell data is represented by lB, the time of 32B is required for writing 32-line cells into one output register. On the other hand, reading of data from the output register is carried out so that 32-byte data blocks (for example, block 930 composed of data from "0101" to "0132" as shown in FigO 10B) formed by taking one byte from the head of each cell are successively ~ 3 ~
1 accessed in parallel to read all the data for the time of 35B. The 32-byte data read from the output register are converted into serial signals by the selector 128, so that the serial signals are transmitted to the output lines 130a to 130n.
By staggering write cycles and read cycles in the output registers 125 (#1) and 126 (#2) as shown in Fig. 12, writing of cell data from the buffer memory and reading of cell data from the output registers into the selector can be carried out respectively continuously.
In the output register side, it is not necessary to shift the timing of cell transmission onto the lines successively one byte by one byte unlike in the input register side.
According to the present invention, cells transmitted in the ATM switching system are merely ac-cumulated in the buffer memory without requiring address queues unlike in the prior art. Accordingly, hardware for queuing is not required. Further, according to the invention, queues do not need to be provided for every service class, in the case where service classes are provided for handling cells within the ATM switching system. Accordingly, in this case, the advantage in reduction of hardware becomes greater.
It is therefore an object of the present invention to provide a packet switching system in which the capacity of the buffer memory for storing cells or packets can be used efficiently.
It is another object of the invention to provide a packet switching system which is suitable particularly for switching broadcast cells.
In order to attain the foregoing objects, the cell switching system according to the present invention has a feature in that writing of cells in the buffer memory is .~
1 3 ~ 2 1 ~ ~
carried out only when cells are inputted and that in the case of a broadcast cell, a cell body and an address are stored during buffering in the switching system so that necessary number o~ copies of the broadcast cell are generated when the broadcast cell is transmitted.
In accordance with one aspect of the invention there is provided a packet switching system in which a plurality of fixed-length reception packets each composed of a header portion and a data portion are received respectively through a plurality of input lines, and each of the reception packets is selectively transmitted onto one of a plurality of output lines as a transmission packet after conversion of the header portion of the reception pacXet, said packet switching system comprising: first interface means connected to said plurality of input lines, for receiving a serial signal of packets inputted from each of said input lines, and for outputting each of said packets with its header portion and data portion separated from each otheri buffer memory means divided into a plurality of buffer areas corresponding to said output lines, for storing said header-portion converted packets correspondingly to said output lines; packet writing means connected to both of said first interface means and said buffer memory means, for generating converted hPader portions to be given to respective transmission packets in accordance with the contents of the header portions of the respective reception packets outputted from said first interface means, ~2~ 3-~
and for writing said transmission packets each composed of the converted header portion and the data portion of the corresponding reception packet outputted from said first interface means into said respective buffer areas corresponding to the output lines through which said transmission packets are to be ouputted respectively by individually generating in a sequence plural writing addresses corresponding to storage locations in said respective buffer areas; packet reading means connected to said buffer memory means, for reading said transmission packets out of said buffer areas of said buffer memory means in a first-in first-QUt manner by successively accessing said buffer areas; and second interface means connected between said buffer memory means and said plurality of output lines, for converting said transmission packets respectively read out of said buffer areas of said buffer memory means into serial signals respectively and for transmitting said respective serial signals onto said output lines corresponding to said buffer areas from which said transmission packets are read out.
Another aspect of the invention is as follows.
To realize a switching function of broadcast mode in which one and the same input cell is transmitted onto a plurality of output lines, broadcast cells are accumulated in a broadcast cell buffer area which serves as a first-in first-out memory in the same manner as the output-line-corresponding buffer memory area. Each broadcast cell is read from the ~, ~2:~3~
broadcast cell buffer area at a predetermined frequency and accumulated in a broadcast cell register. For example, with logical channel number (LCN~ contained in the header of the thus read~out cell as an address, an output line number for indicating the output line to which the cell is transmitted is read ~rom an output line indication table and accumulated in an output line indication register. By transmitting the broadcast cell into an output interface circuit at a predetermined timing corresponding to the contents of the output line indication register, copies of the broadcast cell, instead of ordinary cells read from the buffer memory, can be transmitted to the plurality of output lines.
According to the present invention, even in the case where broadcast cells are concentrately inputted in the switching system, all the cells can stand by the transmission of the broadcast cell in the buffer memory as far as the total throughput in the switching system or throughput in e~ery output line does not exceed a predetermined limit of output throughput. Accordingly, the probability that queuing of input cells cannot be carried out because of the resource occupation of the queues by the broadcast cell is reduced, so that the loss probability of cells by the concentration of broadcast cells can be reduced remarkably compared with the conventional system.
'~4 The foregoing and other objects, advantages, manner of operation and novel features of the present invention will be understood from the following detailed description wh~n read in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a diagram showing an example of the construction of the whole of a conventional switching system;
Fig. 2 is a view of the construction of an ATM cell;
Fig. 3 is a diagram showing an example of the construction of the whole of the ATM switching system according to the present invention;
Fig. 4 is a detailed diagram of the broadcast control circuit 131 depicted in Fig. 3;
Fig. 5 is a view for explaining the output line indicating register 133 depicted in Fig. 4;
Fig. 6 is a view for explaining in detail the broadcast cycle designating register 422 depicted in Fig. 4;
Fig. 7 is a diagram showing an example of the construction of the phase synchronization circuit 103 depicted in Fig. 3;
Fig. 8 is a diagram showing an example of the input register 104 depicted in Fig. 3;
~ igs. 9A and 9B are views for explaining the function of the input register 104;
~A
, r,, ~
Figs. lOA and lOB are views for explaining the function of the output register 125 depicted in Fig. 2;
Fig. 11 is a timing chart showing the operation of the input reyisters 104 to 106; and Fig. 12 is a timing chart showing the operation of the output registers 125 and 126.
A cell switching system of asynchxonous transfer mode (hereinafter referred to as "ATM cell switching system") having such a configuration as disclosed in 10 Japanese Patent Publication JP-A-59-13599 is known. The principle of operation of the ATM cell switching system of the JP-A-59-13599 will be described briefly with reference to Fig. 1. In the following description, each cell (which is also called '~packet") 10 to be switched is assumed to have a 15 fixed length of 35 bytes composed of a 3-byte header 12 and a 32-byte user data 11 as shown in Fig. 2. The header 12 includes a logical channel number for identifying the logical channel to which the cell belongs. Cell switching is executed by identifying the destination of the cell at every switching 20 node on the basis of the LCN.
The above-mentioned values of the respective byte lengths of the entire cell, the header and the data are determined for the sake of convenience of explanation, while those values are not determined on the basis of the basic 2S principle of the present invention.
A
Fig. 1 shows a basic construction o~ the conYentional ATM cell switching system provided with 32 input lines 201a - 201n and 32 output lines 217a - 217n. Such a cell 10 as shown in Fig. 2 is periodically applied to each of the 32 inputs 201a to 201n synchronously with each other.
The respective input cells are converted from serial data into parallel data by means of a multiplexer circuit 203 so that the respective headers of the input cells are multiplexed and transferred onto a line 204 and the respective user data of the input cells are multiplexed and transferred onto a line 205. The line 204 is used for transferring parallel data of 24 bits (3 bytes) and the line 205 is used for transferring parallel data of 256 bits (32 bytes). The user data is written in an input-line-corresponding buffer memory 206 while the address of the user data is designated by an output line 208 of a counter 207. In this example, the output from the counter 207 is composed of 9 bits in which the upper 5 bits are used for designating any one of the input lines 201a to 201n. The buffer memory 206 has a memory capacity for 16 cells corresponding to each of the input linesO The lower 4 bits of the counter 207 are used for designating the cell address successively. Accordingly, the buffer memory 206 operates to successively store cells 10 periodically applied through the input lines into addresses designated by the counter 207, so that writing of cells in the whole cell area of the buffer memory 206 is perfected by 16 periods.
~1 3 ~ 2 ~ ~ ~
Thereafter, writing of cells is performed periodically so that new cells are successively overwritten in the area where old cells have been written. Accordingly, unless a cell stored in the buffer is read out of the buffer within 16 periods so as to be sent out through a switching system, the old cell will be lost in the switching system because a new cell will be overwritten on the old cell.
on the other hand, the headers 12 of respective cells 10 are fed to a header converter circuit 209 through the line 204. For example, the header converter circuit 209 may be constituted by a memory table. The memory table is read by an address determined by a co~bination of the LCN contained in the header of a cell and the number of the input line through which the cell is applied, 50 that routing data of the header, that is to say, an output line number and an LCN (generally, different from the LCN contained in the input header) for identifying the cell on the output line, are fed onto lines 210 and 211, respectively. The output line number on the line 210 is composed of 32 bits which respectively correspond to the output lines. The output line number indicates the fact that the cell will be transmitted to the output lines corresponding to the bit position where the bit takes '~1".
The LCN appears on the line 211 in synchronism with the writing of the user data of the cell in the input-line-corresponding buffer memory 2061 and written into a cell areaof the buffer memory together with the user data.
~ i ' q j ~
The address of the buffer memory 206 where the cell has been written is fed to a group of output queues 212a to 212n through the line 208 and stored in one output queue designated by the output line number. The output queues 212a 5 to 212n correspond to the output lines 217a to 217n, so that the address on the buffer memory 206 for one cell to be outputted is stored in the corresponding one of the output, queues for corresponding one of the outpu~ lines. Those output queues 212a to 212n are successively designated by the output of the counter 207 so that the contents of the buffer memory 206 are read out corresponding to the successively designated contents of the output queues, that is, addresses, and outputted to a line 215. Accordingly, cells to be transferred onto the output lines 217a - 217n exist on the line 215 in the multiplexed form. Those multiplexed cells are demultiplexed through a demultiplex circuit 216 and then the demultiplexed cells are respecti~ely correspondingly transferred onto the 32 output lines 217a to 217n.
The aforementioned ATM switching system however requires a switching function for broadcast mode. The broadcast mode is a mode in which one cell inputted through an input line is outputted onto a plurality of output lines. In the case of the conventional system as shown in ~ig. 1, one and the same address of the buffer memory 206 is written in the plurality of output queues by putting "l" in a plurality of bit positions on the line 210. As a result, one and the ,~
~ 3~
same address can be read from the plurality of output queues when the cell is to be outputted, and accordingly, the one and same cell can be transferred onto the plurality of output lines.
In this case, it is a matter of course that the respective broadcast cells have not only one and the same under data but also one and the same contents o~ the header.
Accordingly, call control must be carried out on the assumption that the broadcast cells on the respective output lines ha~e one and th~ same LCN.
The a~orementioned convention~l switching system has a problem that the quantity of hardware in the memory constituting the address queues 212a - 212n becomes large. In particular, when priority, for example, classified by service classes, is established in handling cells in ATM switching, queues must be set as classified by service classes, so that the quantity of hardware is more increased.
Further, in cell transmission in the broadcast mode, a broadcast cell is stored with one and the same address as the buffer memory 206, in each of the queues through which the broadcast cell is to be transmitted. Accordinyly, a problem arises in that the capacity of the queues for storing cells belonging to other LCNs is reduced. For example, in the example shown in Fig. 1, it is a necessary and sufficient condition that the output queues have an address storage capacity for 16 periods, that is, for 16 cells, because the input-line-corresponding buffer memory 206 is always updated or overwritten with the passage of time of 16 periods or more.
Accordingly, for example, in the case where 16 broadcast cells ko be transmitted onto all the output lines are inputted in one period, all the queues are occupied by those broadcast cells so that other input cells become lost because of existence of no vacant ~ueues.
Even if the number of cells inputted in several periods befor~ and after the period in which 16 broadcast cells are inputted is not so large that the total throughput in the switching system for the short duration or the throughput in every output line is within a limit of output throughput~ lost cells may occur in case of instantaneous concentration of broadcast cells. This is a serious problem in the traffic performance of the switching system. To solve these problems by the conventional system construction, both the capacity of the queues 212a to 212n and the capacity of the input-line-corresponding buffer memory 206 must be increased. However, a disadvantage arises in that efficiency in use of the memory is lowered, because the increased portion of the buffer memory is not used when there is no concentration of broadcast cells.
Referring to Fig. 3, there is shown the configuration of an embodiment of the switching system according to the present invention, which has 32 input lines lOla - lOln and 32 output lines 130a - 130n for switching 35-byte fixed-length cells in the same manner as the convantional system as shown in Fig. 1. A phase synchronization circuit 103 and input registers 104, 105 and 106 are provided to carry out a function equivalent to 3 ~
1 that of the multiplexer circuit 203 shown in Fig. 1.
The construction and operation of the phase synchroniza-tion circuit 103 and the input registers 104, 105 and 106 will be described in detail later~ In this embodiment, input cells are converted from serial data into parallel data by the phase synchronization circuit 103 and the input registers 104 to 106 in the same manner as the conventional system. Then, the respective headers of the cells are multiplexed and transmitted onto a line 107 and the respective user data of the cells are trans-mitted onto a line 108. The header is fed to a header conversion circuit 109 and converted, by the header conversion circuit 109, into routin~ information, that is to say, an output line number, to be fed onto a line 110 and LCN on the output line to be fed onto a line 111.
The user data fed onto the line 108 is written, together with the LCN, into an idle area in the output-line-corresponding buffer memory area preliminarily designated in the buffer memory 112 corresponding to the routing information on the line 110. The routing information on the line 110 is composed of 6 bits, in which 5 bits are used for designating one of the 32 output lines 130a - 130n and the remaining 1 bit is used as a broadcast cell indication bit. In this embodiment, all the broadcast cells are always written in a broadcast buffer memory 113 regardless of the destination ~f those cells.
Addresses for writing into and reading out of ~ 3 ~
1 the buffer memories 112 and 113 are designated by write counters (WCNT) 114a to 114m and read counters (RCNT) 116a to 116m, respectively. 33 write counters and 33 read counters are provided corresponding to 32 output-line buffer memory areas and one broadcast buffer memory, so that an address for writing a cell into or an address for read-ing it from a buffer memory area corresponding to the aforementioned sections is designated. Each of those counters makes a counting-up or increment operation whenever a writing or reading operation is carried out.
In the case of writing operation, the output of one counter selected from the 33 write counters 114a to 114m by a selector 118 appears on a line 119 so that an address in the buffer memory 112 or 113 is designated by combination of the output on the line 119 with the routing information on the line 110.
In the case of output of cells from the switch-ing system, the output signals from the read counters 116a to 116m are successively selected by a selector 121 in accordance with the output value from a control counter 119 and successively transmitted onto a line 122. The output signals of the read counters 116a to 116m, together with the output value of the counter 119 obtained on the line 120, are given as read addresses to a buffer memory 112 or a broadcast buffer memory 113. The header portion and the user data portion contained in the data read from the buffer memory 112 or 113 are transmitted to lines 123 and 124, respectively. Then the header portion 3 ~
1 and the user data portion are transmitted onto selected one of the output lines 130a to 130n through output registers 125 and 126 and a selector 128. The output registers 125 and 126 and the selector 128 have a function equivalent to that of the demultiplexer circuit 216 of Fig. 1. The construction and operation of the output registers 125 and 126 and the selector 128 will be described in detail later.
The output from the control counter 119 is distributed into various parts of the switching system through a line 120 to thereby determine the sequence and timing for the periodic operation of the whole swit~hing system.
In the following, a broadcast cell output method in the switching system is described. When a broadcast cell is read from the buffer memory 113, copies of the broadcast cell are generated by a broadcast control circuit 131 by the number equal to that of the output lines through which broadcast is to be carried out, and the copies of the broadcast cell are transmitted onto those output lines respectively.
The construction of the broadcast control circuit 131 is shown in Fig. 4.
In Fig. 4 the reference numeral 400 designates a data (broadcast cell) read from the buffer memory. The data 400 is equivalent to a combination of the data obtained on the lines 123 and 124 shown in Fig. 3. In Fig. 4, the reference numeral 133 designates an output ~ ~ ~ 2 z ~ ~
1 line from the output line indicating table memory 132 shown in Fig. 3. The reference numeral 120 designates the output line from the control counter 119 as already shown in Fig. 3. The reference numeral 135A designates broadcast cycle indication information as a part (10 bits) of the output line 135 from a call processor 134 shown in Fig. 3. The reference numeral 136 designates an input line to the output registers 125 and 126. The reference numeral 137 designates a buffer memory read enable signal. Register write-timing signals 4~6, 427 and 428 are generated from a timing signal generation circuit (not shown in Fig. 3) for generating various control timing signals necessary for the switching system on the basis of the output signal of the control counter 119.
The broadcast cell 400 read from the braodcast buffer memory 113 is accumulated in a broadcast cell register 412. In this case, the header portion of the broadcast cell has been fed to the output line indicating table memory 132 shown in Fig. 3. Output line indication information of 32 bits is read from the output line indicating table memory 132 while the LCN contained in the header portion is used as a read address. The read results are accumulated in an output line indicating register 413 shown in Fig. 4 through the signal line 133. As shown in Fig. 5, the output line indication information is composed of 32 bits, in which ssme bits corresponding to the output lines to which the broadcast L ~ ~ J !~
1 cell needs to be transmitted have "1", remainder bits corresponding to the output lines to which the broadcast cell does not need to be transmitted have "0".
The timing for reading cells from the output-line buffer areas of the buffer memory 112 is designatedby the output 120 from the control counter 119. The output 120 is decoded by a control count decoder 414, so that the value on each of lines 415a to 415n is turned to "1" in the timing corresponding to the corresponding output line. The data on those lines 415a to 415n, together with the corresponding bits o~ the output line indicating register 413, are applied to AND gates 417a to 417n. An OR gate 419 performs logical OR of the output signals from the ~ND gates 417a to 417n. When the output from the OR gate 419 is "1", a bus output gate 42G is opened to thereby feed the contents of the broadcast cell register 412 onto the line 136. When the output from the OR gate 419 is "1", the output from a gate 421 takes 1l0l- SO that a signal for inhibiting reading of the buffer memory 112 i5 fed onto the line 137.
The output from the control counter 119 changes periodically so that the reading from the respective buffer areas of the buffer memory 112 corresponding to the 32 output lines is designated successively in the order of the output line number and then the reading from the broadcast memory 113 is designated upon comple-tion of the reading from the buffer memory area correspond-ing to the 32th output line. Upon completion of the reading 1 from the broadcast memory 113, the output from the eontrol counter 119 returns to its initial state so as to designate the reading from the buffer memory area corresponding to the first output line again. The period of from the reading of the broadcast cell to the reading of the cell to be transmitted onto the 32th output line is defined as one cycle. A broadcast cycle designating register 422 shown in ~ig. 4 is provided to designate thë cyele in which the reading of the broadcast cell from the buffer memory 113 and the transmission of the broadcast cell onto output lines are to be carried out. The broadcast cycle designating register 422 is constituted by a cyclic shift register which makes a shifting operation whenever one cycle is terminated, as shown in Fig. 6. Each bit of the shift register 422 corresponds to one cycle. The shift register 422 changes its bits eyelically so that the contents of the first bit are shifted to the second bit, the contents of the second bit are shifted to the third bit~ and the contents of the last bit (the 10th bit in the example of Fig. 6) are shifted to the first bit. The output of the first bit of the shift register 422 is fed to a line 423 to thereby control the output signals from the AND gates 417a to 417n and an AND gate 425.
In the eycle (braodcast eycle) where the first bit of the shift register 422 takes "1", each of the lines 424 and 423 in Fig. 4 respeetively takes "1" when the value of the eontrol counter 119 indicates the 1 read-enable state of the broadcast buffer memory 113, so that the output from the AND gate 425 for performing logical AND of the values of the lines 424 and 423 takes "1". Accordingly, the output from the gate 421 takes "1" to thereby feed a buffer memory read enable signal to the line 137, so that the broadcast cell existing in an address in the broadcast buffer memory 113 indicated by the read counter 116m is read and accumulated in the broadcast register 412. The broadcast cell thus accumulated in the broadcast register 412 is transmitted onto the output lines corresponding to the bits of "1"
in the output line indicating register A13, at predetermined timing designated by the control count decoder 414, as already mentioned above. Cells read from the buffer memory 112, instead of the broadcast cell, are transmitted onto the output lines corresponding to the bits of "0" in the output line indicating register 413 even within the broadcast cycle. In the cycle where the first bit of the broadcast cycle designating register is "0", all the output signals from the AND gates 417a to 417n and 425 take "0".
Accordingly, the buffer memory read enable signal on the line 137 takes "1" when the output-line-corresponding buffer memory 413 designated by the control counter 1~9 and, on the other hand, the signal takes "0" when the broadcast buffer memory is designated. Accordingly, the contents of the output-line-corresponding buffer memory 112 are transmitted to all the output lines but the broadcast cell is not transmitted. Further, reading from ~ 2:~3~
1 the broadcast buffer memory 113 is not carried out so that the contents of the broadcast cell register 412 are kept. It is apparent from the above description that the frequency of broadcast cell transmission is determined by the contents of the broadcast cycle designating register 422. If the all the contents of the register 422 are set to "0", no broadcast cell is trans-mitted. In the cycle where "1" is fed to the line 423, the broadcast cell is transmitted preferentially.
Accordingly, the degree of priority of the broadcast cell increases as number of bits of "1" increases in the broadcast cycle designating register 422. When all the bits of the resister 422 are "1", the priority is highest.
The call processor 134 determines a pattern to be written in the broadcast cycle designating register 422, consider-ing factors such as a broadcast call set state, a used band and the like. Although Fig. 4 shows the case where the broadcast cycle designation information (pattern) is composed of 10 bits, it is to be understood that the number of bits can be suitably selected in accordance with the determination of the frequency of broadcast cell transmission.
In the following, a switching input portion which is constituted by the phase synchronization circuit 103 and the input registers 104, 105 and 106, and a switching output portion which is constituted by the output registers 125 and 126 and the selector 128 shown in Fig.
3 are described.
1 Fig. 7 shows an example of the detailed construc-tion o the phase synchronization circuit 103. The phase synchronization circuit 103 performs the phase synchroniza-tion so that the respective phases of the input cells received from the respective input lines lOla to lOlm are shifted successively one byte by one byte. The phase synchronization circuit 103 is composed of 32 shift units 500a to SOOn provided corresponding to the input lines, and a control circuit 510 for controlling the operation of the shift units 500a - 500n.
For example, the shift unit 500a has a shift register 501 for receiving an input cell in the form of a serial signal from a data line lOa of the input line lOla, a tap selector 502 for selecting one of taps provided corresponding to the bits of the shift register to thereby transmit the input cell onto an output line Dl, and a decoder 503 for designating the tap to be selected by the tap selector 502. A synchronous signal lla for indicating the head of each input cell and an input cell transfer clock signal 12a are given to the decoder 503. The current position of the input head bit in the shift register 501 is grasped by counting the transfer clock. When an output timing signal 511 is given from the control circuit 510, the decoder 503 generates a selection signal corresponding to the count value, and the tap selector 502 selects one of the taps corresponding to the position of the head bit of the input cell. As a result, the input cell is serially transmitted ~- 3 ~ a 3 ~
1 onto the output line Dl in synchronization with the output timing. A shift register 504 for receiving a header having a data length o~ 3 bytes and a gate 505 for controlling transmission of parallel output signals from the shift register 504 to the line 107 are provided on the output line from the tap selector 502. The gate 505 is opened by a timing signal 512 from the control circuit 510 so that the header portion of each cell i5 transmitted onto the line 107. The control circuit 510 feeds the timing signals (511, 512) to each of the shift units 500a - 500n through the control signal lines 510a - 510n respectively in the condition that the respective phases of the timing signals are shifted successively one byte by one byte. Accordingly, the input cells with their phases shifted successively one byte by one byte are transmitted to the respective output lines Dl to D32, and, on the other hand, the header portions of the respective input cells are successively transmitted onto the line 107.
Fig. 8 shows the construction of an embodiment of the input register 104. Other input registers 105 and 106 have the same construction as the input register 104. The input register 104 is composed of one-byte serial=to-parallel conversion circuits (S/P circuits) 25 600-1 to 600-32 connected to the output lines Dl to D32 from the phase synchronization circuit lQ3, l-byte memory cells Ml_l to M32_35 arranged in the form of a matrix having 32 rows and 35 columns, a write address decoder 610, ~2~ ~4 1 a read address decoder 620, and a control circuit 640.
The output from each respective S/P circuit 600-Q is made to be data written in the 35 memory cells M~ 1 to MQ 35 in the corresponding Q-th row. The data read from those memory cells are fed to an ou~put register 630 through corresponding column-direction lines.
The write address decoder 610 decodes the count value 641 given from the control circuit 640 to thereby generate write signals Wl to W66 successively. The write signal Wl is generated at the timing when the S/P
circuit 600-1 connected to the output line Dl transmits the first byte of the first input cell, so that the aforementioned one-byte data is written in the memory cell Ml 1 The write signal W2 is generated at the timing when the S/P circuit 600-2 connected to the output line D2 transmits the first byte of the second input cell, so that the first one-byte data of the second input cell is written in the memory cell M2 1 and, at the same time, the second one-byte data of the first input cell is written in the memory cell Ml 2. In short, write signals are successively generated in the same manner as described above while the memory cell access position is shifted in order. In the case of the 32th write signal W32, the 32nd one-byte data of the first input cell is written in the memory Ml 3~, the 31st one-byte data of the second input cell is written in the memory M2 31~ ~ and the first one-byte data of the 32th input cell is written in the memory cell M32_1. In the case of the 33rd write 1 signal W33, the 33rd one-byte data of the first input cell is writ-ten in the memory Ml_33, the 32nd one-byte data of the second input cell is written in the memory M2 32~ and the second one-byte data of the 32nd input cell is written in the memory cell M32 2 In the case of the last 66th write slgnal W66, the 35th one-byte data of the 32nd input cell is wri-tten in the memory M32 35 On the other hand, the reading of data from these memory cells is carried out by read signals Rl to R32 generated from the read address decoder 620. Those read signals are successively generated corrresponding to the count value 642 from the control circuit 640. The read signal Rl makes access to one-row memory cells Ml 1 to Ml 35 at once. Similarly, the read signals R2 to R32 respectively make access to memory cells of one row which corresponds to one input cell (from the second input cell to the 32nd input cell). Thus, 35-byte (280~bit) data per input cell unit can be successively read into the register 630 from which 32-byte (256 bits) user data portion is outputted to the line 108.
Figs. 9A and 9B are views showing models of the function of the aforementioned register 10~. In the write mode, as shown in Fig. 9A, 32-byte parallel input cell data blocks are written successively in the positions shifted one byte by one byte. In the read mode, as shown in Fig. 9B, a 35-byte data block for each input cell, for example, a data block 910 having 35 bytes of from "0101" to "3501", is read at once as shown.
3 ~
1 The other input registers 105 and 106 have the same function as the input register 104. As will be described later, those three input registers 104, 105 and 106 are switched so as to be used successively to thereby constitute an input buffer of three input planes.
Fig. 11 is a timing chart showiny the relation between writing data into and reading data from the input registers 104 to 106. In Fig. 11, register numbers #1 to #4 correspond to the input registers 104 to 106, and terminal numbers 1 to 32 correspond to the input lines lOla to lOln and the output lines Dl to D32 from the phase synchronization circuit 103. In each of the registers, a write cycle and a read cycle are repeated alternately.
Since the input cells have been successively fed to the input registers while successively shifting one byte by one byte as shown by oblique lines, if the time (cycle) required for writing the one-byte data is represented by a symbol "B", the cycle of 35B is required for writing one-cell data and the cycle of 66B is required for writing 32-line input cells. In this embodiment, the next input cell (for example, A23 from the line through which writing of an input cell (for example, Al) in the first input register 104 (#1) is terminated is written in the second input register 105 (#2). When the writing of the input cell A2 is terminated, the next input cell (for example, A3) is written in the third input register 106 (#3). The further next input cell (for example, A4) is written in the first input register 104 (#1) again.
~ 2~ ~
1 In short, the input registers are used by turns. As a result, the idle time of 39B can be provided between the point of time when writing of 32 input cells in one input register is terminated and the point of time when writing of next input cells is started. If data are read by one cell per cycle from the input register in which writing is terminated, the time of 32B is required for reading all the 32 cells~ Accordingly, the idle time of 39B after the termination of input cell writing is used in each register so that all input cells can be successively read and written in the buffer memories 112 and 113. Data read from the buffer memories 112 and 113 are transmitted to the output lines 103a to 103n through the output registers 125 and 126 and the selector 128.
Writing of data into the output register 125 (or 126) is carried out so that one-cell data of 35 bytes read from the buffer memory are written into an address corresponding to the output line in the form of a parallel data block 920 composed of data of from "0132"
to i'3532" as shown in Fig. 10A. When the time required for writing one-cell data is represented by lB, the time of 32B is required for writing 32-line cells into one output register. On the other hand, reading of data from the output register is carried out so that 32-byte data blocks (for example, block 930 composed of data from "0101" to "0132" as shown in FigO 10B) formed by taking one byte from the head of each cell are successively ~ 3 ~
1 accessed in parallel to read all the data for the time of 35B. The 32-byte data read from the output register are converted into serial signals by the selector 128, so that the serial signals are transmitted to the output lines 130a to 130n.
By staggering write cycles and read cycles in the output registers 125 (#1) and 126 (#2) as shown in Fig. 12, writing of cell data from the buffer memory and reading of cell data from the output registers into the selector can be carried out respectively continuously.
In the output register side, it is not necessary to shift the timing of cell transmission onto the lines successively one byte by one byte unlike in the input register side.
According to the present invention, cells transmitted in the ATM switching system are merely ac-cumulated in the buffer memory without requiring address queues unlike in the prior art. Accordingly, hardware for queuing is not required. Further, according to the invention, queues do not need to be provided for every service class, in the case where service classes are provided for handling cells within the ATM switching system. Accordingly, in this case, the advantage in reduction of hardware becomes greater.
Claims (7)
1. A packet switching system in which a plurality of fixed-length reception packets each composed of a header portion and a data portion are received respectively through a plurality of input lines, and each of the reception packets is selectively transmitted onto one of a plurality of output lines as a transmission packet after conversion of the header portion of the reception packet, said packet switching system comprising:
first interface means connected to said plurality of input lines, for receiving a serial signal of packets inputted from each of said input lines, and for outputting each of said packets with its header portion and data portion separated from each other;
buffer memory means divided into a plurality of buffer areas corresponding to said output lines, for storing said header-portion converted packets correspondingly to said output lines;
packet writing means connected to both of said first interface means and said buffer memory means, for generating converted header portions to be given to respective transmission packets in accordance with the contents of the header portions of the respective reception packets outputted from said first interface means, and for writing said transmission packets each composed of the converted header portion and the data portion of the corresponding reception packet outputted from said first interface means into said respective buffer areas corresponding to the output lines through which said transmission packets are to be ouputted respectively by individually generating in a sequence plural writing addresses corresponding to storage locations in said respective buffer areas;
packet reading means connected to said buffer memory means, for reading said transmission packets out of said buffer areas of said buffer memory means in a first-in first-out manner by successively accessing said buffer areas; and second interface means connected between said buffer memory means and said plurality of output lines, for conver-ting said transmission packets respectively read out of said buffer areas of said buffer memory means into serial signals respectively and for transmitting said respective serial signals onto said output lines corresponding to said buffer areas from which said transmission packets are read out.
first interface means connected to said plurality of input lines, for receiving a serial signal of packets inputted from each of said input lines, and for outputting each of said packets with its header portion and data portion separated from each other;
buffer memory means divided into a plurality of buffer areas corresponding to said output lines, for storing said header-portion converted packets correspondingly to said output lines;
packet writing means connected to both of said first interface means and said buffer memory means, for generating converted header portions to be given to respective transmission packets in accordance with the contents of the header portions of the respective reception packets outputted from said first interface means, and for writing said transmission packets each composed of the converted header portion and the data portion of the corresponding reception packet outputted from said first interface means into said respective buffer areas corresponding to the output lines through which said transmission packets are to be ouputted respectively by individually generating in a sequence plural writing addresses corresponding to storage locations in said respective buffer areas;
packet reading means connected to said buffer memory means, for reading said transmission packets out of said buffer areas of said buffer memory means in a first-in first-out manner by successively accessing said buffer areas; and second interface means connected between said buffer memory means and said plurality of output lines, for conver-ting said transmission packets respectively read out of said buffer areas of said buffer memory means into serial signals respectively and for transmitting said respective serial signals onto said output lines corresponding to said buffer areas from which said transmission packets are read out.
2. A packet switching system according to claim 1, in which said packet writing means has a plurality of counter means arranged so that each of the counter means performs an increment operation up to a maximum value coincident with the packet storage capacity of each of said buffer areas whenever a transmission packet is written in a corresponding one of said buffer areas, said packet writing means generating a first address for selecting one of said buffer areas corresponding to the contents of the header portion of each reception packet and generating, through one of said counter means selected by said first address, a second address for indicating the packet storage position within said selected buffer area.
3. A packet switching system according to claim 1, in which said packet reading means has a plurality of counter means corresponding to said buffer areas, means for generating a first address for successively selecting said buffer areas, and counter selector means for selecting one of said counter means in accordance with said first address, each of said counter means operating to perform an increment operation up to a maximum value coincident with the packet storage capacity of each of said buffer areas whenever a transmission packet is read from a corresponding one of said buffer areas, and so as to generate a second address for indicating the packet storage position within selected buffer area when said counter means is selected by said counter selector means.
4. A packet switching system according to claim 3, in which said second interface means has memory means composed of storage areas for storing transmission packets read from said buffer memory means into a storage area corresponding to said first address, and parallel output means for transmitting said transmission packets stored in said memory means onto each output line in order from the head bit thereof.
5. A packet switching system in which a plurality of fixed-length reception packets each composed of a header portion and a data portion are received respectively through a plurality of input lines, and each of the reception packets is selectively transmitted onto one of a plurality of output lines as a transmission packet after conversion of the header portion of the reception packet, and in which each reception packet is transmitted to selected ones of said output lines in the case where the reception packet is a broadcast packet, said packet switching system comprising:
first interface means connected to said plurality of input lines, for receiving packets inputted from each of said input lines, and for outputting each of said packets with its header portion and data portion separated from each other;
buffer memory means connected to said first interface means and having a first buffer area including a plurality of buffer areas corresponding to said output lines for accumulating the header-converted packets correspondingly to said output lines and a second buffer area for accumulating the header-converted broadcast packets to be broadcast to said selected ones of said plurality of output lines;
packet writing means connected to both of said first interface means and said buffer memory means, for generating converted header portions to be given to respective transmission packets in accordance with the contents of the header portions of the respective reception packets outputted from said first interface means, and for writing said transmission packets each composed of the converted header portion and the data portion of the corresponding reception packet outputted from said first interface means into said first or second buffer area in accordance with said contents of the header portions by individually generating in a sequence plural writing addresses corresponding to storage locations in said respective buffer areas;
packet reading means connected to said buffer memory means, for reading said transmission packets successively from said first buffer area of said buffer memory means correspondingly to said output lines and for reading said broadcast packet from said second buffer area of said buffer memory means at a predetermined frequency;
second interface means connected between said buffer memory means and said plurality of output lines, for temporarily storing said transmission packets successively read from said first buffer area of said buffer memory means and for transmitting said temporarily stored transmission packets parallelly onto said plurality of output lines; and broadcast packet generating means connected to operate in synchronism with said packet reading means for reproducing a plurality of broadcast packets from the broadcast packet read from said second buffer area of said buffer memory means and for supplying said plurality of reproduced broadcast packets, instead of the transmission packets read from said first buffer area, onto said second interface means at predetermined timing determined in accordance with the contents of the header portion of said broadcast packet.
first interface means connected to said plurality of input lines, for receiving packets inputted from each of said input lines, and for outputting each of said packets with its header portion and data portion separated from each other;
buffer memory means connected to said first interface means and having a first buffer area including a plurality of buffer areas corresponding to said output lines for accumulating the header-converted packets correspondingly to said output lines and a second buffer area for accumulating the header-converted broadcast packets to be broadcast to said selected ones of said plurality of output lines;
packet writing means connected to both of said first interface means and said buffer memory means, for generating converted header portions to be given to respective transmission packets in accordance with the contents of the header portions of the respective reception packets outputted from said first interface means, and for writing said transmission packets each composed of the converted header portion and the data portion of the corresponding reception packet outputted from said first interface means into said first or second buffer area in accordance with said contents of the header portions by individually generating in a sequence plural writing addresses corresponding to storage locations in said respective buffer areas;
packet reading means connected to said buffer memory means, for reading said transmission packets successively from said first buffer area of said buffer memory means correspondingly to said output lines and for reading said broadcast packet from said second buffer area of said buffer memory means at a predetermined frequency;
second interface means connected between said buffer memory means and said plurality of output lines, for temporarily storing said transmission packets successively read from said first buffer area of said buffer memory means and for transmitting said temporarily stored transmission packets parallelly onto said plurality of output lines; and broadcast packet generating means connected to operate in synchronism with said packet reading means for reproducing a plurality of broadcast packets from the broadcast packet read from said second buffer area of said buffer memory means and for supplying said plurality of reproduced broadcast packets, instead of the transmission packets read from said first buffer area, onto said second interface means at predetermined timing determined in accordance with the contents of the header portion of said broadcast packet.
6. A packet switching system according to claim 5, in which:
said first buffer area of said buffer memory means is composed of a plurality of subsidiary areas corresponding to said output lines, said packet reading means including means for effecting access to said subsidiary areas successively to thereby read transmission packets from said subsidiary areas one by one; and said broadcast packet generating means includes means for giving an inhibiting signal to said packet reading means when said packet reading means makes access to selected ones of said subsidiary areas corresponding to selected ones of said output lines determined in accordance with the contents of the header portion of said broadcast packet.
said first buffer area of said buffer memory means is composed of a plurality of subsidiary areas corresponding to said output lines, said packet reading means including means for effecting access to said subsidiary areas successively to thereby read transmission packets from said subsidiary areas one by one; and said broadcast packet generating means includes means for giving an inhibiting signal to said packet reading means when said packet reading means makes access to selected ones of said subsidiary areas corresponding to selected ones of said output lines determined in accordance with the contents of the header portion of said broadcast packet.
7. A packet switching system according to claim 5, further comprising means coupled to said broadcast packet generating means for designating the cycle in which said broadcast packet is read from said second buffer area by said packet reading means.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8290988A JP2667868B2 (en) | 1988-04-06 | 1988-04-06 | Cell switching system |
| JP63-82909 | 1988-04-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1312134C true CA1312134C (en) | 1992-12-29 |
Family
ID=13787382
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000595717A Expired - Lifetime CA1312134C (en) | 1988-04-06 | 1989-04-05 | Cell switching system of asynchronous transfer mode |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4947388A (en) |
| EP (1) | EP0336373B1 (en) |
| JP (1) | JP2667868B2 (en) |
| CA (1) | CA1312134C (en) |
| DE (1) | DE68928574T2 (en) |
Families Citing this family (115)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA1292053C (en) * | 1986-09-16 | 1991-11-12 | Yoshito Sakurai | Time-division channel arrangement |
| US6005867A (en) | 1986-09-16 | 1999-12-21 | Hitachi, Ltd. | Time-division channel arrangement |
| US5740156A (en) * | 1986-09-16 | 1998-04-14 | Hitachi, Ltd. | Packet switching system having self-routing switches |
| US7058062B2 (en) * | 1986-09-16 | 2006-06-06 | Hitachi, Ltd. | Packet switching system having self-routing switches |
| US6330240B1 (en) * | 1987-04-24 | 2001-12-11 | Hitachi, Ltd. | ATM cell switching system |
| JP2947956B2 (en) * | 1991-03-05 | 1999-09-13 | 株式会社日立製作所 | Switching system |
| US5365519A (en) | 1991-03-05 | 1994-11-15 | Hitachi, Ltd. | ATM switch1ng system connectable to I/O links having different transmission rates |
| USRE36716E (en) * | 1987-07-15 | 2000-05-30 | Hitachi, Ltd. | Switching system for switching cells having error detection apparatus |
| USRE36751E (en) * | 1987-07-15 | 2000-06-27 | Hitachi, Ltd. | ATM switching system connectable to I/O links having different transmission rates |
| JPH01270431A (en) * | 1988-04-21 | 1989-10-27 | Nec Corp | High-speed packet exchange switch |
| US5303236A (en) * | 1988-08-26 | 1994-04-12 | Hitachi, Ltd. | Signalling apparatus for use in an ATM switching system |
| US5101404A (en) * | 1988-08-26 | 1992-03-31 | Hitachi, Ltd. | Signalling apparatus for use in an ATM switching system |
| DE3840688A1 (en) * | 1988-12-02 | 1990-06-13 | Standard Elektrik Lorenz Ag | PACKAGE SWITCH AND INPUT CONVERSION UNIT HERE |
| US5072440A (en) * | 1989-03-01 | 1991-12-10 | Fujitsu Limited | Self-routing switching system having dual self-routing switch module network structure |
| JP2860661B2 (en) * | 1989-03-14 | 1999-02-24 | 国際電信電話 株式会社 | ATM switch |
| NL8900640A (en) * | 1989-03-16 | 1990-10-16 | At & T & Philips Telecomm | METHOD FOR TRANSMITTING DATA PACKAGES IN ATD (ASYNCHRONOUS TIME DIVISION) AND AN APPARATUS FOR APPLYING THIS METHOD |
| CA1320257C (en) * | 1989-04-20 | 1993-07-13 | Ernst August Munter | Method and apparatus for input-buffered asynchronous transfer mode switching |
| JP2677418B2 (en) * | 1989-06-22 | 1997-11-17 | 富士通株式会社 | ATM switch system switching method |
| US5210744A (en) * | 1989-06-28 | 1993-05-11 | Mitsubishi Denki Kabushiki Kaisha | Cell exchange apparatus |
| GB8915135D0 (en) * | 1989-06-30 | 1989-08-23 | Inmos Ltd | Message routing |
| GB8915137D0 (en) * | 1989-06-30 | 1989-08-23 | Inmos Ltd | Message routing |
| US5422881A (en) * | 1989-06-30 | 1995-06-06 | Inmos Limited | Message encoding |
| JP2964151B2 (en) * | 1989-07-03 | 1999-10-18 | 富士通株式会社 | Communication control method |
| JP2767910B2 (en) * | 1989-07-18 | 1998-06-25 | 日本電気株式会社 | Time-division communication path |
| US5271006A (en) * | 1989-07-19 | 1993-12-14 | Hitachi, Ltd. | Frame aligner and method and system for control thereof |
| WO1991002420A1 (en) * | 1989-08-09 | 1991-02-21 | Alcatel N.V. | Communication switching element and method for transmitting variable length cells |
| JP2907886B2 (en) * | 1989-09-14 | 1999-06-21 | 株式会社日立製作所 | Switching system |
| JPH03104451A (en) * | 1989-09-19 | 1991-05-01 | Fujitsu Ltd | Route changeover system for multi-stage link exchange system |
| US5182748A (en) * | 1989-10-20 | 1993-01-26 | Kokusai Denshin Denwa Co., Ltd. | Protocol conversion system |
| JPH03182140A (en) * | 1989-12-11 | 1991-08-08 | Mitsubishi Electric Corp | Common buffer type exchange |
| DE3942977A1 (en) * | 1989-12-23 | 1991-06-27 | Standard Elektrik Lorenz Ag | METHOD FOR RESTORING THE CORRECT SEQUENCE OF CELLS, ESPECIALLY IN AN ATM SWITCHING CENTER, AND OUTPUT UNIT THEREFOR |
| JP2781633B2 (en) * | 1990-01-10 | 1998-07-30 | 株式会社日立製作所 | Cell signal processing circuit and optical switch using the same |
| JPH03220836A (en) * | 1990-01-25 | 1991-09-30 | Nec Corp | Asynchronous transmission mode exchange |
| JP2701507B2 (en) * | 1990-02-13 | 1998-01-21 | 日本電信電話株式会社 | Cell loss rate estimation method, and call admission control device and buffer link design device using the same |
| WO1991013505A1 (en) * | 1990-03-02 | 1991-09-05 | Ascom Tech Ag | Control unit for the central store of an atm node |
| EP0447769A3 (en) * | 1990-03-12 | 1994-12-21 | Sel Alcatel Ag | Method and circuit arrangement for managing uniform unities and switching element |
| ATE127643T1 (en) * | 1990-03-14 | 1995-09-15 | Alcatel Nv | ATM-TYPE MULTIPLE-MODE SWITCHING ELEMENT AND SWITCHING NETWORK CONTAINING SAME. |
| JPH03268532A (en) * | 1990-03-19 | 1991-11-29 | Fujitsu Ltd | Broadcasting system for atm cell |
| JP2555906B2 (en) * | 1990-05-18 | 1996-11-20 | 日本電気株式会社 | ATM cell VCI conversion method |
| KR920009679B1 (en) * | 1990-06-27 | 1992-10-22 | 재단법인 한국전자통신연구소 | Fast atm cell synchronus switching system having switching memory |
| JP2909165B2 (en) * | 1990-07-27 | 1999-06-23 | 株式会社東芝 | Broadband communication network, end user terminal, communication network, broadband communication node, communication node, interface adapter, multipoint connection interface, multipoint connection control device and access unit |
| US6985487B1 (en) | 1990-07-27 | 2006-01-10 | Kabushiki Kaisha Toshiba | Broadband switching networks |
| US5379295A (en) * | 1990-07-31 | 1995-01-03 | Nec Corporation | Cross-connect system for asynchronous transfer mode |
| JPH04107027A (en) * | 1990-08-28 | 1992-04-08 | Fujitsu Ltd | Data transmission system |
| GB9019340D0 (en) * | 1990-09-05 | 1990-10-17 | Plessey Telecomm | An asynchronous transfer mode switching arrangement providing broadcast transmission |
| JP2821255B2 (en) * | 1990-09-12 | 1998-11-05 | 株式会社日立製作所 | Communication network connection device |
| JPH0799831B2 (en) * | 1990-10-08 | 1995-10-25 | 株式会社東芝 | Unit cell switch for ATM communication system |
| US5260937A (en) * | 1990-10-29 | 1993-11-09 | Dsc Communications Corporation | Power conserving technique for a communications terminal time slot interchanger |
| US5166926A (en) * | 1990-12-18 | 1992-11-24 | Bell Communications Research, Inc. | Packet address look-ahead technique for use in implementing a high speed packet switch |
| JP2600496B2 (en) * | 1990-12-20 | 1997-04-16 | 日本電気株式会社 | Cell phase transfer circuit |
| JP2947628B2 (en) * | 1991-03-11 | 1999-09-13 | 富士通株式会社 | Switch control device |
| US5361255A (en) * | 1991-04-29 | 1994-11-01 | Dsc Communications Corporation | Method and apparatus for a high speed asynchronous transfer mode switch |
| JP3074573B2 (en) * | 1991-06-18 | 2000-08-07 | 富士通株式会社 | Method and apparatus for testing VPI conversion function, and ATM cross-connect apparatus including the apparatus |
| JPH0548638A (en) * | 1991-08-15 | 1993-02-26 | Fujitsu Ltd | End to end congestion coping control processing system in atm network |
| US5291486A (en) * | 1991-08-19 | 1994-03-01 | Sony Corporation | Data multiplexing apparatus and multiplexed data demultiplexing apparatus |
| GB2289196B (en) * | 1991-08-19 | 1996-03-13 | Sony Corp | Data storing medium |
| JP3025068B2 (en) * | 1991-09-12 | 2000-03-27 | 富士通株式会社 | ATM switch path test method |
| US5398245A (en) * | 1991-10-04 | 1995-03-14 | Bay Networks, Inc. | Packet processing method and apparatus |
| US5287346A (en) * | 1991-10-16 | 1994-02-15 | Carnegie Mellon University | Packet switch |
| US5398235A (en) * | 1991-11-15 | 1995-03-14 | Mitsubishi Denki Kabushiki Kaisha | Cell exchanging apparatus |
| US5351243A (en) * | 1991-12-27 | 1994-09-27 | Digital Equipment Corporation | Monitor for packets on a communications network |
| WO1993020634A1 (en) * | 1992-04-06 | 1993-10-14 | Northern Telecom Limited | Method for atm switch core interface |
| GB9213273D0 (en) * | 1992-06-23 | 1992-08-05 | Digital Equipment Int | Efficient atm cell synchronization |
| JP3104429B2 (en) * | 1992-10-08 | 2000-10-30 | 株式会社日立製作所 | Common buffer type ATM switch having copy function and copy method thereof |
| US5345558A (en) * | 1992-11-23 | 1994-09-06 | Synoptics Communications, Inc. | Topology independent broadcast of cells in an ATM network or the like |
| GB2273224B (en) * | 1992-12-05 | 1997-01-22 | Netcomm Ltd | An ATM Cell switch suitable for multicast switching |
| KR960003505B1 (en) * | 1992-12-29 | 1996-03-14 | 재단법인 한국전자통신연구소 | Atm multiplexing processor |
| EP0606729A3 (en) * | 1993-01-11 | 1996-12-18 | At & T Corp | Asynchronous transfer mode (atm) expanded internal cell format. |
| DE69429200T2 (en) * | 1993-02-15 | 2002-07-18 | Mitsubishi Electric Corp | Data queuing device and ATM cell switching based on push and search |
| SE515422C2 (en) * | 1993-03-10 | 2001-07-30 | Ericsson Telefon Ab L M | Label management in parcel networks |
| US5469432A (en) * | 1993-08-26 | 1995-11-21 | Gat; Erann | High-speed digital communications network |
| US5802287A (en) * | 1993-10-20 | 1998-09-01 | Lsi Logic Corporation | Single chip universal protocol multi-function ATM network interface |
| US5446726A (en) * | 1993-10-20 | 1995-08-29 | Lsi Logic Corporation | Error detection and correction apparatus for an asynchronous transfer mode (ATM) network device |
| US5708659A (en) * | 1993-10-20 | 1998-01-13 | Lsi Logic Corporation | Method for hashing in a packet network switching system |
| US5452293A (en) * | 1994-01-27 | 1995-09-19 | Dsc Communications Corporation | Apparatus and method of transmitting call information prior to establishing a connection path |
| US5453979A (en) * | 1994-01-27 | 1995-09-26 | Dsc Communications Corporation | Method and apparatus for generating route information for asynchronous transfer mode cell processing |
| US5528592A (en) * | 1994-01-27 | 1996-06-18 | Dsc Communications Corporation | Method and apparatus for route processing asynchronous transfer mode cells |
| CA2143495A1 (en) * | 1994-03-21 | 1995-09-22 | Rasoul M. Oskouy | Method and apparatus for reordering incoming interleaved asynchronous transfer mode cells |
| CA2145017C (en) * | 1994-03-31 | 2000-02-15 | Masaru Murakami | Cell multiplexer having cell delineation function |
| JPH07321815A (en) * | 1994-05-24 | 1995-12-08 | Nec Corp | Shared buffer type atm switch and its multi-address control method |
| JP2699872B2 (en) * | 1994-06-01 | 1998-01-19 | 日本電気株式会社 | Data receiving device and buffer management method |
| JP2922118B2 (en) * | 1994-08-12 | 1999-07-19 | 沖電気工業株式会社 | ATM cell switch and ATM exchange |
| US5949781A (en) * | 1994-08-31 | 1999-09-07 | Brooktree Corporation | Controller for ATM segmentation and reassembly |
| JPH09162877A (en) * | 1995-12-06 | 1997-06-20 | Fujitsu Ltd | Buffer control system |
| JP2842522B2 (en) * | 1995-12-06 | 1999-01-06 | 日本電気株式会社 | ATM switch and control method thereof |
| JP3075163B2 (en) * | 1996-01-10 | 2000-08-07 | 日本電気株式会社 | Multiport frame exchange method |
| FI103545B (en) * | 1996-02-14 | 1999-07-15 | Nokia Telecommunications Oy | Manipulation of the ATM cell header field |
| US5841772A (en) * | 1996-03-07 | 1998-11-24 | Lsi Logic Corporation | ATM communication system interconnect/termination unit |
| US6373846B1 (en) | 1996-03-07 | 2002-04-16 | Lsi Logic Corporation | Single chip networking device with enhanced memory access co-processor |
| US5920561A (en) * | 1996-03-07 | 1999-07-06 | Lsi Logic Corporation | ATM communication system interconnect/termination unit |
| US5848068A (en) * | 1996-03-07 | 1998-12-08 | Lsi Logic Corporation | ATM communication system interconnect/termination unit |
| US6535512B1 (en) | 1996-03-07 | 2003-03-18 | Lsi Logic Corporation | ATM communication system interconnect/termination unit |
| US5982749A (en) * | 1996-03-07 | 1999-11-09 | Lsi Logic Corporation | ATM communication system interconnect/termination unit |
| US5689644A (en) * | 1996-03-25 | 1997-11-18 | I-Cube, Inc. | Network switch with arbitration sytem |
| US5754791A (en) * | 1996-03-25 | 1998-05-19 | I-Cube, Inc. | Hierarchical address translation system for a network switch |
| US5784003A (en) * | 1996-03-25 | 1998-07-21 | I-Cube, Inc. | Network switch with broadcast support |
| US5703875A (en) * | 1996-04-10 | 1997-12-30 | Hughes Electronics | Integrated control and data message network |
| US5794025A (en) * | 1996-05-09 | 1998-08-11 | Maker Communications, Inc. | Method and device for performing modulo-based arithmetic operations in an asynchronous transfer mode cell processing system |
| US5860148A (en) * | 1996-05-09 | 1999-01-12 | Maker Communications, Inc. | Asynchronous transfer mode cell processing system with cell buffer space gathering |
| US6128303A (en) * | 1996-05-09 | 2000-10-03 | Maker Communications, Inc. | Asynchronous transfer mode cell processing system with scoreboard scheduling |
| US6005871A (en) * | 1996-08-22 | 1999-12-21 | Telefonaktiebolaget Lm Ericsson | Minicell alignment |
| US5831980A (en) * | 1996-09-13 | 1998-11-03 | Lsi Logic Corporation | Shared memory fabric architecture for very high speed ATM switches |
| US5959993A (en) * | 1996-09-13 | 1999-09-28 | Lsi Logic Corporation | Scheduler design for ATM switches, and its implementation in a distributed shared memory architecture |
| US6829240B1 (en) * | 1996-11-27 | 2004-12-07 | Mindspeed Technologies, Inc. | System for, and method of, ATM segmentation and re-assembly of cells providing streaming data |
| US6493347B2 (en) | 1996-12-16 | 2002-12-10 | Juniper Networks, Inc. | Memory organization in a switching device |
| US5850398A (en) * | 1996-12-30 | 1998-12-15 | Hyundai Electronics America | Method of scheduling data cell transmission in an ATM network |
| US6452939B1 (en) * | 1998-03-24 | 2002-09-17 | Samsung Electronics Co., Ltd. | ATM interface device with double header conversion |
| KR20000018716A (en) * | 1998-09-04 | 2000-04-06 | 윤종용 | Method for interface between rate adaptation processing part and board messenger processing part of wireless data communication processing apparatus |
| US20040071139A1 (en) * | 2002-10-10 | 2004-04-15 | Burnett Charles James | Method and apparatus for efficient administration of memory resources in a data network tester |
| US8059629B1 (en) | 2004-03-27 | 2011-11-15 | Dust Networks, Inc. | Digraph network timing synchronization |
| US7961664B1 (en) | 2004-03-27 | 2011-06-14 | Dust Networks, Inc. | Digraph network subnetworks |
| US7529217B2 (en) * | 2004-03-27 | 2009-05-05 | Dust Networks, Inc. | Low-power autonomous node for mesh communication network |
| US7881239B2 (en) * | 2004-03-27 | 2011-02-01 | Dust Networks, Inc. | Low-powered autonomous radio node with temperature sensor and crystal oscillator |
| US7420980B1 (en) * | 2004-03-27 | 2008-09-02 | Dust Networks, Inc. | Digraph network superframes |
| US8194655B2 (en) * | 2004-08-05 | 2012-06-05 | Dust Networks, Inc. | Digraph based mesh communication network |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE430288B (en) * | 1982-02-24 | 1983-10-31 | Ellemtel Utvecklings Ab | TELECOMMUNICATION SYSTEM FOR TRANSFER OF DATA INFORMATION BY A DIGITAL EXCHANGE |
| FR2538976A1 (en) * | 1982-12-29 | 1984-07-06 | Servel Michel | SYSTEM FOR SWITCHING SYNCHRONOUS PACKETS OF FIXED LENGTH |
| FR2538984A1 (en) * | 1982-12-30 | 1984-07-06 | Devault Michel | SWITCH FOR MULTIDEBIT DIGITAL NETWORK WITH ASYNCHRONOUS TIME SWITCH ADAPTED TO VIDEOCOMMUTATIONS |
| US4630258A (en) * | 1984-10-18 | 1986-12-16 | Hughes Aircraft Company | Packet switched multiport memory NXM switch node and processing method |
| US4734907A (en) * | 1985-09-06 | 1988-03-29 | Washington University | Broadcast packet switching network |
| US4755986A (en) * | 1985-09-13 | 1988-07-05 | Nec Corporation | Packet switching system |
| GB8528891D0 (en) * | 1985-11-23 | 1986-01-02 | Int Computers Ltd | Data transmission system |
| FR2594615B1 (en) * | 1986-02-20 | 1988-06-17 | France Etat | DEVICE FOR DEMULTIPLEXING PACKETS OF A MAC / PACKET BROADCASTING SIGNAL |
| JPH0831877B2 (en) * | 1986-09-02 | 1996-03-27 | 日本電信電話株式会社 | Packet switch |
| EP0269803A3 (en) * | 1986-12-05 | 1990-03-07 | ANT Nachrichtentechnik GmbH | Circuit arrangement for switching pcm channels |
| JPH035994A (en) * | 1989-06-01 | 1991-01-11 | Nec Ic Microcomput Syst Ltd | Address selecting circuit |
-
1988
- 1988-04-06 JP JP8290988A patent/JP2667868B2/en not_active Expired - Fee Related
-
1989
- 1989-04-04 DE DE68928574T patent/DE68928574T2/en not_active Expired - Fee Related
- 1989-04-04 EP EP89105891A patent/EP0336373B1/en not_active Expired - Lifetime
- 1989-04-05 CA CA000595717A patent/CA1312134C/en not_active Expired - Lifetime
- 1989-04-05 US US07/333,282 patent/US4947388A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0336373A2 (en) | 1989-10-11 |
| EP0336373A3 (en) | 1992-03-18 |
| JPH01256246A (en) | 1989-10-12 |
| EP0336373B1 (en) | 1998-02-04 |
| DE68928574T2 (en) | 1998-10-01 |
| JP2667868B2 (en) | 1997-10-27 |
| DE68928574D1 (en) | 1998-03-12 |
| US4947388A (en) | 1990-08-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1312134C (en) | Cell switching system of asynchronous transfer mode | |
| US5875189A (en) | Method and apparatus for multicast of ATM cells | |
| KR0155554B1 (en) | Communication switching element and method for transmitting variable lenght cells | |
| AU703227B2 (en) | Connectionless communication system | |
| EP0156580B1 (en) | Data transmission system | |
| US5535197A (en) | Shared buffer switching module | |
| US4603416A (en) | (Time division multiplex) switching system for routing trains of constant length data packets | |
| US6611527B1 (en) | Packet switching apparatus with a common buffer | |
| EP0725555B1 (en) | Method and apparatus for manipulating an ATM cell | |
| EP0420493B1 (en) | Broadcast packet switch network | |
| AU673026B2 (en) | Hybrid ATM cell switching | |
| EP0413899B1 (en) | Packet switching system having bus matrix switch | |
| JPH022767A (en) | Packet exchanger | |
| EP0420492B1 (en) | packet switching network for multiple packet types | |
| US5875173A (en) | Communication control device and method for use in an ATM system operable in an ABR mode | |
| JPH03182140A (en) | Common buffer type exchange | |
| EP0612171B1 (en) | Data queueing apparatus and ATM cell switch based on shifting and searching | |
| US5805590A (en) | Switching device for digital data networks and asynchronous transfer mode | |
| CA2151180C (en) | Method and apparatus for multicast of atm cells | |
| US4922485A (en) | System for changing priority of packets of data | |
| US5343467A (en) | Space/time switching element having input/output circuits each separately switchable between two or more bit rates | |
| US5479398A (en) | Digital data concentrator | |
| US5475706A (en) | Bulk data transmission system | |
| US5910953A (en) | ATM interface apparatus for time-division multiplex highways | |
| EP0710047B1 (en) | Method and apparatus for multicast of ATM cells |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKLA | Lapsed |