CA1318360C - Apparatus for cancelling carrier phase jitters - Google Patents
Apparatus for cancelling carrier phase jittersInfo
- Publication number
- CA1318360C CA1318360C CA000606715A CA606715A CA1318360C CA 1318360 C CA1318360 C CA 1318360C CA 000606715 A CA000606715 A CA 000606715A CA 606715 A CA606715 A CA 606715A CA 1318360 C CA1318360 C CA 1318360C
- Authority
- CA
- Canada
- Prior art keywords
- phase
- signal
- jitter
- producing
- detected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
- H04L27/233—Demodulator circuits; Receiver circuits using non-coherent demodulation
- H04L27/2332—Demodulator circuits; Receiver circuits using non-coherent demodulation using a non-coherent carrier
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0024—Carrier regulation at the receiver end
- H04L2027/0026—Correction of carrier offset
- H04L2027/0032—Correction of carrier offset at baseband and passband
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0044—Control loops for carrier regulation
- H04L2027/0053—Closed loops
- H04L2027/0057—Closed loops quadrature phase
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0044—Control loops for carrier regulation
- H04L2027/0071—Control of loops
- H04L2027/0079—Switching between loops
- H04L2027/0081—Switching between loops between loops of different bandwidths
Abstract
ABSTRACT OF THE DISCLOSURE
A jitter cancelling apparatus include a carrier phase locked loop comprising first phase rotator for producing a first phase-rotated signal by effecting a first phase rotation of a received signal, using a first phase control signal; first phase detecting means for detecting a phase of the first phase-rotated signal and producing a first detected phase signal; and control means having a time constant for processing the first detected phase signal, to obtain the first phase control signal. A
predictive jitter canceller comprises second phase rotator for producing a second phase-rotated signal by effecting a second phase rotation of the first phase-rotated signal, using a second control signal; second phase detecting means for detecting a phase of the second phase-rotated signal and producing a second detected phase signal; and predicting means responsive to the first detected phase signal for obtaining the second control signal. Phase jitter measuring means are responsive to the first detected phase signal for producing a phase jitter frequency signal by measuring a frequency of a phase jitter of the received signal. Comparing means produce a first comparison result signal, when the phase jitter frequency signal is greater than a predetermined value and a second comparison result signal, when the phase jitter frequency signal is smaller than the predetermined value. Predicting means control means activate the predicting means in response to the first comparison result signal and deactivate the predicting means in response to the second comparison result signal.
A jitter cancelling apparatus include a carrier phase locked loop comprising first phase rotator for producing a first phase-rotated signal by effecting a first phase rotation of a received signal, using a first phase control signal; first phase detecting means for detecting a phase of the first phase-rotated signal and producing a first detected phase signal; and control means having a time constant for processing the first detected phase signal, to obtain the first phase control signal. A
predictive jitter canceller comprises second phase rotator for producing a second phase-rotated signal by effecting a second phase rotation of the first phase-rotated signal, using a second control signal; second phase detecting means for detecting a phase of the second phase-rotated signal and producing a second detected phase signal; and predicting means responsive to the first detected phase signal for obtaining the second control signal. Phase jitter measuring means are responsive to the first detected phase signal for producing a phase jitter frequency signal by measuring a frequency of a phase jitter of the received signal. Comparing means produce a first comparison result signal, when the phase jitter frequency signal is greater than a predetermined value and a second comparison result signal, when the phase jitter frequency signal is smaller than the predetermined value. Predicting means control means activate the predicting means in response to the first comparison result signal and deactivate the predicting means in response to the second comparison result signal.
Description
~31~360 The present invention relates to a data transmission system for transmitting data over telephone lines or similar analog lines and, more particularly, to a jitter cancelling apparatus for carrier phase control associated with a receiver of such a data transmission system.
In a data transmission system, signals usually undergo various types of deteriorations known as amplitude distortions, delay distortions, carrier ~requency offsets and carrier phase jitters while being transmitter over lines. Among them, the amplitude distortions and delay distortions are substantially time-invariant or, their variation in time is slow enough to allow such distortion~
to be compensated for by so-called automatic equalizers.
Carrier phase jitters, on the other hand, result in time-variant distortions and this kind of distortions have hitherto been absorbed by using phase locked loops (PLL).
The PLL circuit, however~ cannot sufficiently suppress phase jitters (especially, high-frequency jitters) unless the freguency band of the PLL is broadened to a width in the range of 200 hertz to 300 hertz. Such a broad loop band would deteriorate the signal-noise characteristic of the PLL, thereby worsening the resistivity to noise of the entire data transmission system.
A device for the suppression of phase jitters heretofore proposed is a jitter canceller system as disclosed in U.S. Patent 4,639,939. (Botaro HirosaXi et al) issued on January 27, 1987. The jitter canceller system uses a predictive filter, which is tuned to phase jitters, so as to cancel phase jitters superposed on a carrier wave. This prior art system can be implemented with a narrow-band PLL which is adapted to recover the carrier wave, thereby eliminating the deterioration of the resistivity to noise. However, a drawback of this jitter canceller system is that the predictive filter has to be scaled up in inverse proportion to the lower limit of phase ~ $
r 11 ~1 83~Q
jitter frequency to be suppressed. Should the system be designed to cope with jitters whose frequency is as ].ow as 20 hertz, the hardware scale would become excessively large and therefore imprActical.
It is therefore an object of the present invention to provide an apparatus for reducing phase jitters over a wide frequency range while reducing the hardware scale of the apparatus.
Accordingly, a jitter cancelling apparatus of the present invention comprises: (a) a carrier phase locked loop comprising: a first phase rotating means for producing a first phase-rotated signal by effectiny a first phase rotation of a received signal, using a first phase control signal; first phase detecting means for detecting a phase of the first phase-rotated signal and producing a first detected phase signal; and control means having a time constant for processing the first detected phase signal, to obtain said first phase control signal; ~b) a predictive jitter canceller comprising: second phase rotating means for producing a second phase-rotated signal by effecting a second phase rotation of the first phase-rotated signal, using a second control signal; second phase detecting means for detecting a phase of the second phase-rotated signal and producing a second detected phase signal; and predicting means responsive to the first detected phase signal for obtaining said second control signal; ~c) phase jitter measuring means responsive to the first detected phase signal for producing a phase jitter frequency signal by measuring a frequency of a phase jitter of the received signal; (d) comparing means for producing a first comparison result signal when the phase jitter frequency signal is greater than a predetermined value and producing a second comparison result signal when said phase jitter frequency signal is smaller than said predetermined value;
and (e) predicting means control means for activating said predicting means in response to the first comparison result ~11 8~
signal and deactivating said predicting means in response to the second comparison result signal.
The jitter cancelling apparatus of the present invention has a phase locked loop for su'ppressing phase jitters with a frequency lower than 50 hertz, a predicti~e jitter canceller ~or suppressing phase jitters wikh a fxequency higher than 50 hertz, and a control circuit for controlling the PLL and jitter canceller. The control circuit has a jitter frequency measuring circuit which renders the jitter canceller inoperative when the measured jitter frequency is lower than 50 hertz. When the measured jitter frequency is higher than 50 hertz, the control circuit sets up a PLL frequency band of 1 hertz so as to allow the jitters to be substantially cancelled by the jitter canceller.
The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description taken with the accompanying drawings in which:
Figure 1 is a block diagram showing an embodiment of the present invention;
Figure 2 illustrates a block diagram of a phase detector used in the jitter cancelliny apparatus of the present invention;
Figure 3 illustrates a block diagram of the loop filter o~ the present invention in detail; and Figure 4 illustrates a block diagram of the zero-cross counter.
In the drawings, the thick lines represent complex signals and the thin lines, real signals or control signals.
Referring to Figure 1 of the drawings, a jitter cancelling apparatus embodying the present invention is shown in a schematic block diagram. As shown, the apparatus ''Y~
has an input terminal 116 to which a complex baseband signal is applied, and a first phase rotator 101 which rotates the baseband signal by a first phase to produce a first phase-rotated signal. A second phase rotator 102 rotates the f irst phase-rotated signal by a second phase to output a second phase-rotated signal. A d:iscriminator 103 discriminates the second phase-rotated signal to produce a discriminated signal. A phase detector 104 detects the phase of the first phase-rotated signal on the basis of the output of the discriminator 103, i.e~, the discriminated signal and the first phase-rotated signal which is received from the phase rotator 101. The first phase signal, output by the phase detector 104, is multipli~d by a constant K1 or K2 (K1 > K2) in a multiplier 105, and then the resulting signal is smoothed by a loop filter 106. The filtered output of the loop filter 106 is integrated by an integrator 107. In response to the integrated phase, a trigonometric function generator 108 tlabelled as "ei~ ") generates a first phase ~1. The first phase i5 applied to the phase rotator 101 as stated earlier, so that the received signal is rotated according to the first phase.
The elements 101 and 103 to 108 ~orm a PLL. one of the constants K1 and K2 is selected by a selector 114, for setting up the loop gain of the PLL. In the illustrative embodiment, the loop gains K1 and K2 are selected to provide loop frequency bands of about 50 hertz and 1 hertz, respectively.
The detected phase from the phase detector 104 is also routed to a predictive filter 109 via a switch 115.
In response, the predictive filter 109 predicts a phase jitter. A trigonometric function generator 110 (labelled as "e;e ~) generates a second phase ~2 in response to the predicted phase jitter and applies it to the phase rotator 102. The phase rotator 102, therefore, rotates the first phase-rotated signal (as previously stated), according to the second phase. A phase detector 111 detects the phase 13~8~
of the second phase-rotated signal from the second phase~
rotated signal and tha discriminated signaL, the detected phase being applied to the predictive filter 109 as a control signal for adjustment of the filter coefficient.
The adjustment of the prediction filter 10~ coef~ici2nt ~E
se is known (i.e. it is described in the previously mentioned U.S. Patent 4,639,939 in detail).
In the illustrative embodiment o~ Figure 1, the predictive filter 109 has a number of taps N which is selected such that the minimum prediction frequency be about 50 hertz.
A zero-cross counter 112 counts the number of times that the phase signal from the phase detector 104 crosses the zero level within a predetermined period of time. Hence, the output of the zero-cross counter 112 is proportional to the frequency of the detect~d phase signal, i.e., the frequency of a phase jitter. A comparator 113 determines whether the output of the zero-cross counter 112 is greater or smaller than a threshold value TH which is representative of the frequency of 50 hertz.
When comparator 113 determines that the frequency of the phase jitter is higher than 50 hertz, the selector 114 selects K2 as a loop coefficient and, at the same time, closes the switch 115. In this condition, a loop frequency band of about 1 hertz is set up and the predictive filter 109 is activated, whereby the phase jitter is mainly suppressed by the phase rotator 102. Conversely, when the frequency of the phase iitter is lower than 50 hertz, the selector 114 selects K1 as a loop coefficient and opens the switch 115. Then, a loop band of about 50 hertz is set up and the predictive ~ilter 109 is deactivated, so that the phase jitter is suppressed by the phas~ rotator 101.
Referring to Figure 2, a speci*ic construction of the phase detector 104 or lll is shown. As shown, the phase detector 104 (111) has a terminal 201 for receiving the first ~second) phase-rotated signal from the phase 131~3~0 conjugate unit 203 for producing a complex conjuyate signal of the receive.d discriminated signal, a multiplier 204 for produciny a product of the first phase-ro-tated signal and the complex conjugate signal, and an imaginary part selector 205 for separating an imaginary part of the product.
~ssuming that the signal on the terminal 201 is x = ~e (1) and that the signal on the terminal 202 is ~ = re-i9 then the complex conjugate unit 203 modifies the equation (2) as ~ e-je (3) After multiplication of the signals represented by the equations (1) and (3) in the multiplier 204, the imaginary part selector 205 separates only the imaginary part y of the product. The imaginary part y is expressed as:
y = ~rm (re-ie . ~e~
= ~m (r~eJ(9-~) = ~sin (e - ê) ~ C (e - ~) (4) assuming that C - ~ ~ and e - e << 1.
Figure 3 indicates a specific construction of the loop filter 106. ln the figure, the loop filter 106 is implemented as an ordinary full integration type loop filter and has coefficient units 301 and 302, an integrator 3 ~ ~
implemented as an ordinary full integration type loop filter and has coefficient units 301 and 302, an integrator 304, and an adder 303. The transEer function of the loop ~ilter 106 is expressed as:
H ~j~) = a (1 ~
Figure 4 is a schematic block diagram showing a specific construction of the zsro-cross counter 1120 In the figure, the zero-cross counter 112 checks the signs of successive sampled values so as to count the transitions of the sign. Specifically, the zero-cross counter 112 comprises a sign bit detector 401 for detecting the sign of a signal, a flip-flop 402 to be set and reset on the basis of the detected sign and a counter 403 for counting outputs of the flip-flop 402.
Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without depar$ing from the scope thereof.
.
In a data transmission system, signals usually undergo various types of deteriorations known as amplitude distortions, delay distortions, carrier ~requency offsets and carrier phase jitters while being transmitter over lines. Among them, the amplitude distortions and delay distortions are substantially time-invariant or, their variation in time is slow enough to allow such distortion~
to be compensated for by so-called automatic equalizers.
Carrier phase jitters, on the other hand, result in time-variant distortions and this kind of distortions have hitherto been absorbed by using phase locked loops (PLL).
The PLL circuit, however~ cannot sufficiently suppress phase jitters (especially, high-frequency jitters) unless the freguency band of the PLL is broadened to a width in the range of 200 hertz to 300 hertz. Such a broad loop band would deteriorate the signal-noise characteristic of the PLL, thereby worsening the resistivity to noise of the entire data transmission system.
A device for the suppression of phase jitters heretofore proposed is a jitter canceller system as disclosed in U.S. Patent 4,639,939. (Botaro HirosaXi et al) issued on January 27, 1987. The jitter canceller system uses a predictive filter, which is tuned to phase jitters, so as to cancel phase jitters superposed on a carrier wave. This prior art system can be implemented with a narrow-band PLL which is adapted to recover the carrier wave, thereby eliminating the deterioration of the resistivity to noise. However, a drawback of this jitter canceller system is that the predictive filter has to be scaled up in inverse proportion to the lower limit of phase ~ $
r 11 ~1 83~Q
jitter frequency to be suppressed. Should the system be designed to cope with jitters whose frequency is as ].ow as 20 hertz, the hardware scale would become excessively large and therefore imprActical.
It is therefore an object of the present invention to provide an apparatus for reducing phase jitters over a wide frequency range while reducing the hardware scale of the apparatus.
Accordingly, a jitter cancelling apparatus of the present invention comprises: (a) a carrier phase locked loop comprising: a first phase rotating means for producing a first phase-rotated signal by effectiny a first phase rotation of a received signal, using a first phase control signal; first phase detecting means for detecting a phase of the first phase-rotated signal and producing a first detected phase signal; and control means having a time constant for processing the first detected phase signal, to obtain said first phase control signal; ~b) a predictive jitter canceller comprising: second phase rotating means for producing a second phase-rotated signal by effecting a second phase rotation of the first phase-rotated signal, using a second control signal; second phase detecting means for detecting a phase of the second phase-rotated signal and producing a second detected phase signal; and predicting means responsive to the first detected phase signal for obtaining said second control signal; ~c) phase jitter measuring means responsive to the first detected phase signal for producing a phase jitter frequency signal by measuring a frequency of a phase jitter of the received signal; (d) comparing means for producing a first comparison result signal when the phase jitter frequency signal is greater than a predetermined value and producing a second comparison result signal when said phase jitter frequency signal is smaller than said predetermined value;
and (e) predicting means control means for activating said predicting means in response to the first comparison result ~11 8~
signal and deactivating said predicting means in response to the second comparison result signal.
The jitter cancelling apparatus of the present invention has a phase locked loop for su'ppressing phase jitters with a frequency lower than 50 hertz, a predicti~e jitter canceller ~or suppressing phase jitters wikh a fxequency higher than 50 hertz, and a control circuit for controlling the PLL and jitter canceller. The control circuit has a jitter frequency measuring circuit which renders the jitter canceller inoperative when the measured jitter frequency is lower than 50 hertz. When the measured jitter frequency is higher than 50 hertz, the control circuit sets up a PLL frequency band of 1 hertz so as to allow the jitters to be substantially cancelled by the jitter canceller.
The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description taken with the accompanying drawings in which:
Figure 1 is a block diagram showing an embodiment of the present invention;
Figure 2 illustrates a block diagram of a phase detector used in the jitter cancelliny apparatus of the present invention;
Figure 3 illustrates a block diagram of the loop filter o~ the present invention in detail; and Figure 4 illustrates a block diagram of the zero-cross counter.
In the drawings, the thick lines represent complex signals and the thin lines, real signals or control signals.
Referring to Figure 1 of the drawings, a jitter cancelling apparatus embodying the present invention is shown in a schematic block diagram. As shown, the apparatus ''Y~
has an input terminal 116 to which a complex baseband signal is applied, and a first phase rotator 101 which rotates the baseband signal by a first phase to produce a first phase-rotated signal. A second phase rotator 102 rotates the f irst phase-rotated signal by a second phase to output a second phase-rotated signal. A d:iscriminator 103 discriminates the second phase-rotated signal to produce a discriminated signal. A phase detector 104 detects the phase of the first phase-rotated signal on the basis of the output of the discriminator 103, i.e~, the discriminated signal and the first phase-rotated signal which is received from the phase rotator 101. The first phase signal, output by the phase detector 104, is multipli~d by a constant K1 or K2 (K1 > K2) in a multiplier 105, and then the resulting signal is smoothed by a loop filter 106. The filtered output of the loop filter 106 is integrated by an integrator 107. In response to the integrated phase, a trigonometric function generator 108 tlabelled as "ei~ ") generates a first phase ~1. The first phase i5 applied to the phase rotator 101 as stated earlier, so that the received signal is rotated according to the first phase.
The elements 101 and 103 to 108 ~orm a PLL. one of the constants K1 and K2 is selected by a selector 114, for setting up the loop gain of the PLL. In the illustrative embodiment, the loop gains K1 and K2 are selected to provide loop frequency bands of about 50 hertz and 1 hertz, respectively.
The detected phase from the phase detector 104 is also routed to a predictive filter 109 via a switch 115.
In response, the predictive filter 109 predicts a phase jitter. A trigonometric function generator 110 (labelled as "e;e ~) generates a second phase ~2 in response to the predicted phase jitter and applies it to the phase rotator 102. The phase rotator 102, therefore, rotates the first phase-rotated signal (as previously stated), according to the second phase. A phase detector 111 detects the phase 13~8~
of the second phase-rotated signal from the second phase~
rotated signal and tha discriminated signaL, the detected phase being applied to the predictive filter 109 as a control signal for adjustment of the filter coefficient.
The adjustment of the prediction filter 10~ coef~ici2nt ~E
se is known (i.e. it is described in the previously mentioned U.S. Patent 4,639,939 in detail).
In the illustrative embodiment o~ Figure 1, the predictive filter 109 has a number of taps N which is selected such that the minimum prediction frequency be about 50 hertz.
A zero-cross counter 112 counts the number of times that the phase signal from the phase detector 104 crosses the zero level within a predetermined period of time. Hence, the output of the zero-cross counter 112 is proportional to the frequency of the detect~d phase signal, i.e., the frequency of a phase jitter. A comparator 113 determines whether the output of the zero-cross counter 112 is greater or smaller than a threshold value TH which is representative of the frequency of 50 hertz.
When comparator 113 determines that the frequency of the phase jitter is higher than 50 hertz, the selector 114 selects K2 as a loop coefficient and, at the same time, closes the switch 115. In this condition, a loop frequency band of about 1 hertz is set up and the predictive filter 109 is activated, whereby the phase jitter is mainly suppressed by the phase rotator 102. Conversely, when the frequency of the phase iitter is lower than 50 hertz, the selector 114 selects K1 as a loop coefficient and opens the switch 115. Then, a loop band of about 50 hertz is set up and the predictive ~ilter 109 is deactivated, so that the phase jitter is suppressed by the phas~ rotator 101.
Referring to Figure 2, a speci*ic construction of the phase detector 104 or lll is shown. As shown, the phase detector 104 (111) has a terminal 201 for receiving the first ~second) phase-rotated signal from the phase 131~3~0 conjugate unit 203 for producing a complex conjuyate signal of the receive.d discriminated signal, a multiplier 204 for produciny a product of the first phase-ro-tated signal and the complex conjugate signal, and an imaginary part selector 205 for separating an imaginary part of the product.
~ssuming that the signal on the terminal 201 is x = ~e (1) and that the signal on the terminal 202 is ~ = re-i9 then the complex conjugate unit 203 modifies the equation (2) as ~ e-je (3) After multiplication of the signals represented by the equations (1) and (3) in the multiplier 204, the imaginary part selector 205 separates only the imaginary part y of the product. The imaginary part y is expressed as:
y = ~rm (re-ie . ~e~
= ~m (r~eJ(9-~) = ~sin (e - ê) ~ C (e - ~) (4) assuming that C - ~ ~ and e - e << 1.
Figure 3 indicates a specific construction of the loop filter 106. ln the figure, the loop filter 106 is implemented as an ordinary full integration type loop filter and has coefficient units 301 and 302, an integrator 3 ~ ~
implemented as an ordinary full integration type loop filter and has coefficient units 301 and 302, an integrator 304, and an adder 303. The transEer function of the loop ~ilter 106 is expressed as:
H ~j~) = a (1 ~
Figure 4 is a schematic block diagram showing a specific construction of the zsro-cross counter 1120 In the figure, the zero-cross counter 112 checks the signs of successive sampled values so as to count the transitions of the sign. Specifically, the zero-cross counter 112 comprises a sign bit detector 401 for detecting the sign of a signal, a flip-flop 402 to be set and reset on the basis of the detected sign and a counter 403 for counting outputs of the flip-flop 402.
Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without depar$ing from the scope thereof.
.
Claims (2)
1. A jitter cancelling apparatus comprising:
(a) a carrier phase locked loop comprising:
a first phase rotating means for producing a first phase-rotated signal by effecting a first phase rotation of a received signal, using a first phase control signal;
first phase detecting means for detecting a phase of the first phase-rotated signal and producing a first detected phase signal; and control means having a time constant for processing the first detected phase signal, to obtain said first phase control signal;
(b) a predictive jitter canceller comprising:
second phase rotating means for producing a second phase-rotated signal by effecting a second phase rotation of the first phase-rotated signal, using a second control signal;
second phase detecting means for detecting a phase of the second phase-rotated signal and producing a second detected phase signal; and predicting means responsive to the first detected phase signal for obtaining said second control signal;
(c) phase jitter measuring means responsive to the first detected phase signal for producing a phase jitter frequency signal by measuring a frequency of a phase jitter of the received signal;
(d) comparing means for producing a first comparison result signal when the phase jitter frequency signal is greater than a predetermined value and producing a second comparison result signal when said phase jitter frequency signal is smaller than said predetermined value;
and (e) predicting means control means for activating said predicting means in response to the first comparison result signal and deactivating said predicting means in response to the second comparison result signal,
(a) a carrier phase locked loop comprising:
a first phase rotating means for producing a first phase-rotated signal by effecting a first phase rotation of a received signal, using a first phase control signal;
first phase detecting means for detecting a phase of the first phase-rotated signal and producing a first detected phase signal; and control means having a time constant for processing the first detected phase signal, to obtain said first phase control signal;
(b) a predictive jitter canceller comprising:
second phase rotating means for producing a second phase-rotated signal by effecting a second phase rotation of the first phase-rotated signal, using a second control signal;
second phase detecting means for detecting a phase of the second phase-rotated signal and producing a second detected phase signal; and predicting means responsive to the first detected phase signal for obtaining said second control signal;
(c) phase jitter measuring means responsive to the first detected phase signal for producing a phase jitter frequency signal by measuring a frequency of a phase jitter of the received signal;
(d) comparing means for producing a first comparison result signal when the phase jitter frequency signal is greater than a predetermined value and producing a second comparison result signal when said phase jitter frequency signal is smaller than said predetermined value;
and (e) predicting means control means for activating said predicting means in response to the first comparison result signal and deactivating said predicting means in response to the second comparison result signal,
2. A jitter cancelling apparatus comprising:
carrier phase locked loop means for suppressing a phase jitter included in a received signal to thereby produce a first jitter-suppressed signal;
jitter canceller means for predicting a phase jitter on the basis of the first jitter-suppressed signal and, in response to the predicted phase jitter, removing a phase jitter from said first jitter-suppressed signal;
phase detecting means for producing a detected phase signal by detecting a phase of the first jitter-suppressed signal;
phase jitter measuring means for producing a phase jitter frequency signal by measuring a frequency of a phase jitter of the received signal in response to the detected phase signal; and control means for rendering said jitter canceller inoperative in response to the phase jitter frequency signal.
carrier phase locked loop means for suppressing a phase jitter included in a received signal to thereby produce a first jitter-suppressed signal;
jitter canceller means for predicting a phase jitter on the basis of the first jitter-suppressed signal and, in response to the predicted phase jitter, removing a phase jitter from said first jitter-suppressed signal;
phase detecting means for producing a detected phase signal by detecting a phase of the first jitter-suppressed signal;
phase jitter measuring means for producing a phase jitter frequency signal by measuring a frequency of a phase jitter of the received signal in response to the detected phase signal; and control means for rendering said jitter canceller inoperative in response to the phase jitter frequency signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63185415A JP2658221B2 (en) | 1988-07-27 | 1988-07-27 | Phase control method |
| JP185415/1988 | 1988-07-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1318360C true CA1318360C (en) | 1993-05-25 |
Family
ID=16170388
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000606715A Expired - Fee Related CA1318360C (en) | 1988-07-27 | 1989-07-26 | Apparatus for cancelling carrier phase jitters |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US5128968A (en) |
| JP (1) | JP2658221B2 (en) |
| CA (1) | CA1318360C (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5299232A (en) * | 1992-03-26 | 1994-03-29 | Motorola, Inc. | Phase compensation method and apparatus |
| IT1255852B (en) * | 1992-10-09 | 1995-11-17 | Alcatel Italia | SYSTEM AND CIRCUIT FOR THE ESTIMATION OF THE CARRIER FREQUENCY OF A PSK NUMERIC SIGNAL |
| US5402443A (en) * | 1992-12-15 | 1995-03-28 | National Semiconductor Corp. | Device and method for measuring the jitter of a recovered clock signal |
| US5422917A (en) * | 1993-01-04 | 1995-06-06 | Novatel Communications Ltd. | Frequency offset estimation using the phase rotation of channel estimates |
| KR970009688B1 (en) * | 1994-10-19 | 1997-06-17 | 엘지정보통신 주식회사 | Circuit for depreesing jitter |
| JP3351642B2 (en) * | 1994-12-20 | 2002-12-03 | 富士通株式会社 | Phase jitter extraction circuit and phase jitter cancellation circuit |
| EP0748093A1 (en) * | 1995-06-08 | 1996-12-11 | Laboratoires D'electronique Philips S.A.S. | Digital transmission system using decision means for selecting the synchronisation mode |
| JP3568284B2 (en) * | 1995-08-22 | 2004-09-22 | 松下電器産業株式会社 | Demodulation method and demodulation device |
| FR2746994B1 (en) * | 1996-03-29 | 1998-04-30 | Alcatel Telspace | ROBUST PHASE ESTIMATOR AND RECOVERY FOR DIGITAL SIGNALS AFFECTED IN PARTICULAR BY PHASE JIT |
| US5828255A (en) * | 1996-11-15 | 1998-10-27 | International Business Machines Corporation | Phase locked loop having adaptive jitter reduction |
| FR2792794B1 (en) * | 1999-04-23 | 2002-10-31 | Telediffusion Fse | METHOD FOR DEPLOYING A PHASE SIGNAL, LINEAR PHASE DEPLOYING SYSTEM AND CARRIER RECOVERY DEVICE |
| US6658065B1 (en) * | 2000-02-29 | 2003-12-02 | Skyworks Solutions, Inc. | System of and method for reducing or eliminating the unwanted sideband in the output of a transmitter comprising a quadrature modulator followed by a translational loop |
| WO2003049391A1 (en) * | 2001-12-05 | 2003-06-12 | Nokia Corporation | Frequency offset correction based on the presence or absence of a received signal |
| US9160382B2 (en) | 2013-10-08 | 2015-10-13 | Blackberry Limited | Phase noise mitigation for wireless communications |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4320526A (en) * | 1980-03-03 | 1982-03-16 | Bell Telephone Laboratories, Incorporated | Adaptive phase-jitter tracker |
| US4495468A (en) * | 1981-01-02 | 1985-01-22 | Tau-Tron, Inc. | Controlled phase off-set digital test system |
| US4412299A (en) * | 1981-02-02 | 1983-10-25 | Teltone Corporation | Phase jitter detector |
| US4447910A (en) * | 1981-06-02 | 1984-05-08 | Harris Corporation | Phase tracking correction scheme for high frequency modem |
| CA1202702A (en) * | 1982-09-03 | 1986-04-01 | Gordon R. Lang | Means and method for reduction of phase jitter |
| US4631738A (en) * | 1984-12-06 | 1986-12-23 | Paradyne Corporation | Gain tracker for digital modem |
| US4683578A (en) * | 1985-07-05 | 1987-07-28 | Paradyne Corporation | Automatic gain control using the extreme points of a constellation |
| US4689804A (en) * | 1985-08-14 | 1987-08-25 | Racal Data Communications Inc. | Method and apparatus for reduction of sinusoidal phase jitter in a high speed data modem |
| JPH0640627B2 (en) * | 1987-01-28 | 1994-05-25 | 日本電気株式会社 | Adaptive Zittaki Yancera |
| US4856031A (en) * | 1988-04-28 | 1989-08-08 | General Datacomm, Inc. | Adaptive multiharmonic phase jitter compensation |
-
1988
- 1988-07-27 JP JP63185415A patent/JP2658221B2/en not_active Expired - Lifetime
-
1989
- 1989-07-26 CA CA000606715A patent/CA1318360C/en not_active Expired - Fee Related
- 1989-07-27 US US07/385,469 patent/US5128968A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US5128968A (en) | 1992-07-07 |
| JP2658221B2 (en) | 1997-09-30 |
| JPH0236640A (en) | 1990-02-06 |
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