CA1321004C - Integrated telecommunication system with improved digital voice response - Google Patents
Integrated telecommunication system with improved digital voice responseInfo
- Publication number
- CA1321004C CA1321004C CA000613290A CA613290A CA1321004C CA 1321004 C CA1321004 C CA 1321004C CA 000613290 A CA000613290 A CA 000613290A CA 613290 A CA613290 A CA 613290A CA 1321004 C CA1321004 C CA 1321004C
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- CA
- Canada
- Prior art keywords
- interface
- high speed
- circuits
- microprocessor
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0407—Selecting arrangements for multiplex systems for time-division multiplexing using a stored programme control
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/42—Systems providing special services or facilities to subscribers
- H04M3/50—Centralised arrangements for answering calls; Centralised arrangements for recording messages for absent or busy subscribers ; Centralised arrangements for recording messages
Abstract
INTEGRATED TELECOMMUNICATION SYSTEM
WITH IMPROVED DIGITAL VOICE RESPONSE
Abstract Of The Disclosure An integrated telecommunication system for multiple telephone line response and processing having a plurality of interface circuits, each of which is adapted to control the physical connection to a plurality of telephone line channels, control communication on a group of telephone line channels connected thereto. Each interface circuit includes a high speed interface microprocessor and a first data storage associated therewith. A first bus system interconnects the plurality of interface processor circuits to signal processor circuits. Each signal processor module includes a cross point switch and a high speed digital signal microprocessor for analyzing the incoming signals and compressing the data therein, a second data storage associated therewith, and one or more of a plurality of telecommunication function circuits controlled thereby. A multi-bus system connects each of the plurality of interface processors to each of the plurality of signal processor circuits and to a main system control processor and a third data storage. The high speed processing requirements of each group of telephone lines is performed by the respective interface control processor and a digital signal microprocessor and main system control processor selectively controls the storage of data in the first, second and third data storages and intercommunication functions between the plurality of interface processor circuits and the plurality of signal processor circuits and the function circuits controlled thereby.
WITH IMPROVED DIGITAL VOICE RESPONSE
Abstract Of The Disclosure An integrated telecommunication system for multiple telephone line response and processing having a plurality of interface circuits, each of which is adapted to control the physical connection to a plurality of telephone line channels, control communication on a group of telephone line channels connected thereto. Each interface circuit includes a high speed interface microprocessor and a first data storage associated therewith. A first bus system interconnects the plurality of interface processor circuits to signal processor circuits. Each signal processor module includes a cross point switch and a high speed digital signal microprocessor for analyzing the incoming signals and compressing the data therein, a second data storage associated therewith, and one or more of a plurality of telecommunication function circuits controlled thereby. A multi-bus system connects each of the plurality of interface processors to each of the plurality of signal processor circuits and to a main system control processor and a third data storage. The high speed processing requirements of each group of telephone lines is performed by the respective interface control processor and a digital signal microprocessor and main system control processor selectively controls the storage of data in the first, second and third data storages and intercommunication functions between the plurality of interface processor circuits and the plurality of signal processor circuits and the function circuits controlled thereby.
Description
1321~04 INTFGRATED TELECOMMUNICATION SYSTEM
W~TH IMPROVED DIGITAL ~OICE RESPONSE
BACKGROUND AND BRIEF DESCRIPTION OF THE INVENTION:
The pre~nt lnv~ntlon reletea to an lntegr~ted volce response aystems for hundling large numbera of telephone linea. Th~ integruted telecommunic~tion system provides ~
multlple telephone line reaponae ~nd procesaing syatem which provide~ a "soft" platform for the integrntlon o all ~Jor nspecta of the voice indu~try including: voice response, apeak~r dependent and independent voice recognition, text-to-speech ~nd volce ldentific~tion. In addition, it connecta to the telephone Tl digltal networ~ ~uch as provided by MCI, AT6T, Sprint, etc. It providea simultaneou~ voice ~nd d~tQ trafic and has the ability to be configured in mediu~ to large applicationa. The syatem disclosed herein i8 able to ~-hendle up to 192 lines but lt is obvlou~ thut it can be configured to h~ndle much l~rger ayatems.
The in~ention i~ comprised of several layera of proces~ors, ooch wlth lta own program ond communicotion p~th.
Each lnterAce proceasor include~ one or more Tl connection int-recQ clrcuita and a control microprocessor and each digltol aignal proceasor circuit includes a crosa-point switch or llne datn inter~cing purpoae~ and its own digital signal proceasor or perorming aignal analyai~ ~nd d~ta compreaslon.
Thl~ dat~ ia communic~ted to the main system 13~1 00~
control mlcroprocessor which buffers it and signals the host system (whlch may be a conventional PC-AT small systems type computer) that data is present and then transfers that data to the ho~e. Additionally, a control microprocessor in the interface circuit provides the Tl handshaking and call progress monitoring in con~unctlon with the lnterface clrcuit which handles the physlcal connectlons to the Tl and all lts attendant traffic management.
Ob~ects of the invention include the provision of an improved integrated telecommunlcatlons system with the abillty to handle all ma~or aspect~ of volce industry.
Therefore in accordance with the present lnvention there 18 provided an integrated telecommunication system for multiple telephone line re~ponse and processlng comprising a plurality of interface processor circuitq, each of which i8 adapted to control the physical connection to a plurallty of telephone line channels and control communication on a group of said telephone line channels connected thereto, each said interface circuit including a high speed lnterface control microprocessor and a first data storage associated therewithr a plurality of signal processor circuit means, each said signal processor circuit mean~ including crosspoint switch means for receiving multiple line multlple channel inputs and producing corresponding ~ultiple line multiple channel outputs, and a hlgh speed digital signal microprocessor for analyzing the incoming slgnals and compressing the data therein, and a second data storage assoclated therewlth, for controlllng one or more telecommunication function clrcuits, a main system control mlcroprocessor, a first bus system for connectlng sald plurallty of lnterface processor circuits to said plurality of slgnal processor circuit means, and a second bus system for connectlng each of sald plurality of interface processor circuits to each - ~
21~
of ~aid plurality of ~ignal processor circuit means and to said main system control microprocessor, whereby the high ~peed processing requirements of each said group of telephone lines i~ performed by said interface processor circuits and sa~d digital signal microprocessor and said main system control microprocessor controls the storage of data in said first and second data storages and intercommunication functions between said plurality of interface processor circuits and said plurality of signal processor circuit means and said one or more telecommunication function circuits controlled thereby.
The above and other ob~ects, advantages and feature~ of the invention will become more apparent when considered with the following ~pecification and accompanying drawlngs wherein:
Figures 1-4 prov~de in broad perspective an overview of the functional aspects of the system in which:
FIG. 1 is a functional block diagram of an automated multiple telephone line response and processing system incorporating the invention, FIG. 2 is a functional block diagram of the Tl interface processor shown in FIG. 1, FIG. 3 is a functional block diagram of the digital signal processor shown ln FIG. 1, FIG. 4 is a functional block diagram of the control processor shown in FIG. 1.
Figure~ 5-8 are more detailed diagrams of the system wherein:
1~21~0~
FIG 5 correspondA to FIG 1 ~nd la ~ more det~ d e~pos~tlon o~ the over~ll system, FIG 6 ahows the lnterconnectlon between the dlgital lnterf~clng ~nd the dlglt~l sl gnRl proceaaor clrcultry components, FIG 7 i~ ~ functional lllustration of the syatem me~ory whlch la controlled by the maln sy~tem ~icroprocea~or illuatr ting th~ particul~r locotion of esch of theae roapective elements in the interf~ce clrcultry and in the dlgit~l switch clrcuitry and the sddltlon~l memory shown in FIG 1, ~nd FIG 8 ia ~ det~iled block diagr~ of n aingle digit~l algnal proceaaor module illuatruted ln FIG
DETAILED DESC~IPTION OF THE INVENTION
Referrlng now to FIGS 1-4, the system ln lt~ bro~der nspects ia od~pted and designed to meet aeveral requirements including provlding a ''aoft" ~l~tform for the inte~r~tion of all the ma~or a~pecta of the voice industry such as volce re~ponae, ape~ker dependent and independent voice recognition, t-xt-to-~peech ond volce identiflcotion, connectlon to ths Tl digital network, the provlalon o ~imult~noou~ volce ~nd doto tr~1c control ond the obility to be con~igured in medium to larg- scole opplic~tiona It ia ~lao cap~ble o beh~ving aa ~n on~log or digltol witch for each Tl channel In FIG 1, aQverol l~yera o procesaora each with ita own program ond communicotion p~ths ~re illustrated Each Tl element <or ' T-span) conQtltutes multiple telephone channels or lines. (Each "T-span" coming from the phone company may be four wires or optical fiber havlng 24 channels (or more) encoded thereon - or 24 simultaneous conversatlons or data exchanges). In thls embodlment there are two T-spans or Tl telephone lines, each having 24 channels 80 that there are 48 channels handled by each lnterface processor 10-1, 10-2, 10-3...10-N. Each interface processor 10 18 illustrated in a functional block diagram shown in FIG. 2 and include a Tl interface microclrcuit chip which in this embodiment is a Mitel 89760* (the details of which are given in the "Microelectronics Data book" published by the Mitel Corporation, copyright 1988). Each proces~or includes a high speed microprocessor which, in this case, is an Intel 80188* (which is described in the Intel Manual) and includes 64K of randsm access memory for storing data and program informatlon. This high speed microprocessor detects a phone ringing on one of the channels and signals the main system microprocessor, which, in turn, signals a partlcular digital signal processor module 13 to handle the call, which then signals the lnterface circuit that it has been assigned to handle the call and to connect the ringing channel to it for proces~ing and - responding to any ~ignals ~including voice) thereon. It also include~ a serial diagnostic port.
It should be noted that the multibus for conveying address and data information between the various units is *Trade Mark i' ';
:
132100~
lllu~trated in FIG. 1 ~a element No. 11. At the ~sme time, second~ry bu~ 12 lnterconnecta the lnter~ce proce~aora 10-1 ~nd the dlglt~l ~lgn~l processor~ 13-1, 13-2, 13-3...13-N. The bu~ 12 1~ lndlc~ted ln FIG. 1 ln ~ block form but i~ ~hown ln greater detsil wlth the v~rioua interconnectiona between the units shown in FIG. 6. Aa shown in FIG. 6, bu~ 12 hus a plursl$ty of lines, ln this embodiment 8, which are design~ted a8 15-1, 15-2...15-8 with the output of e~ch interf~ce unit 10-1 being connected to two of the lines. The dif~erent channels on each T-span which ~re labeled T-span 0, T-spAn 1 T-span 2...T-span 7~ each with 24 individual channels, is provided wlth a communication p~th to the T2 bus and thence to the individual digital aign~l proceaaor clrcuits 1~-1, 13-2.
lt ahould be noted that eoch of the digit~l aign~l proceaaing circuits is connected to ~ll of the lines of bu~ 12 80 that ~ny dlglt~l ~lgnul processlng circuitry 13-1, 13-2...1 -N c~n be uaed to process the aign~ls on ~ny of the channel~ of the T-ap~na connected to the interfsce circuits 10-1...10-N.
Referrlng ag~in to FIG. 2, it wlll be noted that the bus 12 1~ indlc~ted ~a belng ~ high speed dat~ hlghway to the digital ~ign~l procossors. The functions performed by the lnter~ce procè~sors 10 i~ set out in the table of unctions llated on FIG. 2. The 24 channels on e~ch of the Tl inputs typically is tlme division multiplexed and is demultiplexed by thi- proc-s40r. E~ch of theae ~unctions is performed by the program stored in ~ programmable read-only memory 54 <shown in FIG. 5) whlch m~y be ln e flrmw~re module ~inc ~ 4 in~tallable ROM c~rtridges). Each o the dlgital aignel procea~ors 13 ia ahown in detall in FIG. 8 ~nd wlll be deacribed in gre~ter detail in connection with th~t flgure.
However, lt should be noted thMt broadly, this circuit includes the digital sign~l procesoor chipa ~nd it recei~es packet~o data or Mnalysi~ from the lnterface clrcults 10. Each digital aignal proce~or 13, which is multit~sked, then perform~ the anqlysia and dat~ compreaaion on the~e packets o~ dato ~nd communicates t~e compreased data or the dual tone ~requency modulatlona (DTMF) to the ho~t computer ~ystem 74 which, in thi~ case, may be n PC-AT computer. It aign~l~ dot~ i8 present -nd transer~ th~t dut~ to the hoat computer syatem 74.
Additionally, a high ~peed control microprocessor 63 (in the interace circuit~ 10 shown in FIG. 5> provldes the handshRking und c~ll progre~ monitoring in conJunction with the line interface circuit. The functions performed by o~ch of the digit~l ~ignal processor elementa 13 are ahown in the table at the right in FIG. 3.
The control proce~sor 15 contains the main microproce~sor 60 and 18 ~hown in detail in FIG. 5. The functional block dlsgr~m shown in FIG. 4 o~ the control processor ill~strates a high ~peed (20mHz Intell 80386)*microprocesaor 60 which i~
c~p~bie o controlling up to 16 meg~byte~ o r~ndom ~ccea~
memory. The~e 16 meg~byte~ o~ r~ndom ~cceaa memory ~re illu~tr~ted diagr~mmatic~lly in FIG. 7 where the .~ystem memory *Trade Mark 6 ,, ' .
~ 3210~4 model la dlagrammatlcelly lllustrated. It wlll be noted that each o the dlgital aignal proce~aors 13 haa lts memory lndlcated aa belng controlled by the maln ayBtem control ~lcroproc~aor 1~, each p~ogr~m ~AM 20 and each dsta ~AM ~1 ln the dlgltal sign~l proceaaora 13 ia shown ~a belng p~rt of the ~omory controlled by the Maln processor. At the ~me tlmej the random acceaa memorlea and the ROMa in the lnterface unita 10 are likewise ~llu~tr~ted as being p~rt of the memory addresaable or being controlled by the main microprocea~or 60.
It al80 addresaea it~ own ~emories 70 and 71. In other words, up to 16 megabytes of memory whether physlcally atored in ~ither the lnterface clrcults 10 or the digital aignal processor clrcuits 13 or in the hoat computer 74 i~ ~cceaalble or control by the maln mlcroprocesaor CPU ayatem 15 ~la the main multi-bus 11. In FIG. 4, a connectlon i8 provided ~or the SCSI bu~ to the hoat processor ~nd a aerial diagnostic connect~on to a seri~l diagnostic port ia likewise provided for ~yutom dlngnosis.
The table to the rlght in FIG. 4 liats the functiona whlch ~re performed by the main control proceasor 15. These include cnll progreaa and a~aignment, speech dat~ management, host aystem lnterface mansgement, loc~l and remote external dlagno4tic~, automatic aelf-di~gnostica and ayatem wide ~t~tl~tlcs and monitoring. It wlll be appreci~ted that the read-only memory shown in FIG. 6 may contaln theae programa whlch are down-loaded upon initiating operation of the ayatem 132~04 to thereby control the oper~tlon of th~ centr~l proces~or through theae programa. Various ones of the program8 may be aelected or c~lled-up from the ROM or may be separately loaded through the SCSI from the permanent atorage 76.
The overall aspecta of the system disclosed i~ to prov$de a aoft platform or the integration o all the ma~or aspec~s of the voice reaponae sy~tem a8 deacribed above. The system i8 compriaed of aeveral layers of mlcroprocesaors each with lts own program and communication pntha but each of which are controlled, by a ~in centr~l microprocesaor 60. At the Tl connectlona, co~mercially available microproce~or chipa are utilized to handle the physic~l connectlon to the Tla ~the telecom~unication channels) und all its attendunt trafflc ~anagement. It then provldea the packets o dat~ to the dlgital signal proces~or for analyais. The digltal signal proceaaor then performs signAl analyala and dato compresslon and oommunicates the compreased data or the ~TFMa to the main ~yatem control microprocesaor which bu~fera lt and aignala the host ~y~tem that data is present and transfers thnt data to the hoat. Additionally, the microproceaaor in the interace procos~or provides the telephone channel handahaking ~nd c~ll progrea~ monitoring in con~unction with the interfacing provided by the mlcroproce~sor interf~clng chlps.
Thia ay~tem thus providea an efective meana o dl~tributlng the high speed processing requirements of handling of the 192 ch~nnela of T1 dat~ circuita that per~orm those l32lao~
requlred functlons e~fecti~ely while leevlng the d~tq storege ~nd communlcetlon function~ to the ~ingle msln ~ystem mlcroprocesaor whlch c~n effectl~ely address l~rge volune~ of d~t~ snd ~nsge the ho~t lnterfece.
~ eferrlng now to FIG. 5, s more detsiled sy~tem block d~sgrn~ is shown in whlch the interf~ce proceasora lO, digit~l sign~l processor~ 13 ~nd m~ln control proceasor syatem 15 ~re ~hown ln their interrelated Qrr~ngements with the preferred microelectronic circuit chipa with their m~nufscturer identified ~e.g., Mitel 89760, i~ ~ Mitel circuit component or interf~cing to 4 Tl telephone chennel ~nd i8 described, or ex~mple, in det~il beginning ot p~ge~ 4-263 through 4-288 of the Mitel "Microelectronics Dsts Book" ia~ue No. 5, copyright 1988 by the Mitel Corporation). The coupling of the lndl~ldual telephone line channels to the Mitel circult element i~ con~entional and is ~llustrated at page 4-286 of ~aid Mitel Manual and hence need not be shown in detail herein.
As deacribed ubo~e, the control mlcroprocessor 50 <~n Intel 80188) ia respon~ible for the control ~nd monitoring of the line lnterf~ce controller 51 <e Mitel 89760) and the ~asoci4ted circuitry. Specific411y, it h~ndles the SF or ESF
bit oriented AB aign~lling per ch~nnel; the F~L UI r~me for perform~nce reporting: the ISDN D-ch~nnel sign~lling l~yer 2 ~nd l~yer 3: the multi-bus interf~ce for communic~tiona to the m~in centr41 processor 60 in ayaten~ centr~l processing unit lS
g 1321~4 and lt does the lnltlali%~tion qnd diagnostlc testlng functions for thia unit.
The call progrea~ interace unit 52 ~a Mitel 8920)*ia coupled to the DS1 line interace unit S1 and i8 controlled by control microprocea~or 50. Control microproceaaor 50 ia initially louded with its progrom from read-only ~e~ory 54~
The line interface ele~ent 51 ia alao coupled to the acility duta link 55 ~a hltel 8952*unlt) conventionally ~ervea as the ocility data link controller. Finally, the line interf~ce unit 51 i8 olao coupled via the parallel input~output port 56 which are likewiae controlled by the high ~peed control processor 50. The coupling between multi-bua 11 and the high speed control processor 50 in the interace circuitry i8 buffered by a random accea~s ~emory 56 which storea both data and program which is coupled to and from the central procesaor nicroprocessor 60 via the multi-bua 11.
The bus 1~ is generally indicated ag having three lines but it will be apprecieted that theae are multi-lines for inputa/outputa ~nd the thlrd line is a aynchronizing line.
Thua, in the digital aignal proceasor 13, line 60 is a ~ynchronizing line and linea 61 und 62 can constitute input lines und output lines, respectively. Synchronizing line 60 is connected to synchronize the operation of high speed microproces~or 6~ (~n Intel 30C~5 unit) by synchronizing line *Trade Mark , --1321~0~
A crosa-point awltch 65 (which ia ahown and deacribed ln gre~ter det~ n relation to FIG. 8), la controlled by hlgh speed ~lcroprocesaor 63 and BUppl ies dlglt~ gnala to a dAta rendom eccea~ memory 66 ~nd progr~m random acceaa memory 67 which, ~8 deacribed e~rlier herein, ~re controlled by the ~oln central procea~or 60. The high apeed digitMl a~gn~l procesaor 63 ia progrnmmed for an~lyzing and encodlng and decodlng functions on data paased to it from the interace clrcuitry 10 in the main centrol mlcroprocessor lS. E~ch of these circuits 13 ia responsible or proce~sing ~ix chonnela of the T1 telephone circulta wlth ~ compliment of four dlgital aign~l procesaora 13 required to proces~ all 24 channels of the telephone llne component Tl.
Hlgh speed mlcroprocessor 63 iA thus reapon~ible to handle communlc~tiona of dat~ to ~nd from the llne lnterfac~ ~ .
syatem 10, the perormance of ADPCM to PCM and PCM to ADPCM
compres0ion, perform~nce of the DTMF and MF recognltion, perormance o the DTMF and MF tone generation, dat~ buffer mQnagement, watch dog unctiona, cnll progreaa monitoring, ~y~tem houaekeeping functlons and the perormance o channel ~onogemont unctions. All o thea~ functions ore achieved under progr~m control which i8 received from the central proceasor by the program RAM 67.
The moln centrul proceaslng unit 15 ia illustr~ted 08 ho~lng centrol proce~or 60, a random access memory 70, a read-only memory 71 (whlch may be in a flrmwore module ~32~ ~04 lncluding lnstolleble ROM certridges), n seri~l lnput~output port 72 ~nd o ~11 computer systems lnteruce <SCSI) 73 whlch couples to o ho~t system 7~ which moy lnclude o further amoll computer systems lnterace 75, lerge or mssa permenent ~tor~ge 76 (for record or orchl~ol purposes) and the a~ull host computer (PC-AT) referred to eorller M~in centr~l procesaor 60 include progrons for performing aupervisory control function~ over the digitel slgn~l proce~aors ~nd the lnterf~ce circuitry 10 nd its high speed ~icroprocessor 50 end communlcetion~ to the host syatem 74 und the meaory mQnugeaent functions <~8 noted e~rlier, ~11 of the different memory elerent~ idontiied hereln ~re controllable ~rom the centrol nlcroproces~or 60), aerial communications to o debugger~nonltor end wotch dog unctions Specl1c~11y, thls centrsl mlcroproces~or m~n~gea int-rections between the two hlgh speed mlcroprocea~ora 50 end 63 ~lo buaea 11 nnd 12 end the host oy-ten 74 ~io the SCSI bus) It ol~o m~noges ita loc~l mRnOry, lo~ding phroses rom the host PC 74, trnnaerring r-corded peech to the host PC ond determining where in nemory to otore this doto It al80 maneges the mess~ge queue to ond rom tho hoot co~putor 7~ driv-r Moreo~er, it hondles mon~gem-nt o~ coll progress d~ta from the two high speed microproce-40r4 SO ~nd 63 ~nd it hondle4 c~ll os4ignment when the hlgh opeed microprocesoor 50 ~ignol~ on incoming coll by ~ooigning it to o porticulor hlgh speed computer 63 in the bunk o digit~l aignol procesaora 13-1, 13-2 13-N It monitor~
~32lao4 (e.g., providQs "watch dog" functions) o~ the st~tu~ o e~ch ch~nnel Rnd "w~kea up" locked up ch~nnels or t~ke~ them out of ~ervlce. In ~ddltlon, lt ia progr~mmed to h~ndle the physlc~l cont~ol o~ the SCSI l~ter~ce 73 with the SCSI drlver. It ~lao c~n hAndle uni~ers~l ~synchronous receive~tr~nsmit ~UART) communic~tlons with the front psnel and proce~aea lnstruction~
rom the host computer 74 (e.g., send DTMF, record in minutes, play A phr~se, etc.). The hoat computer 74 c~n provide functionul control over the entire system bec~use it down lo~da p~rnmeter in~orm~tion at ~t~rt up ~nd communic~tea individu~l lnstructions.
Reerring now to FIG. 8, a det~il circuit di~grAm o a single dlgit~l sign~l processing module incorpor~ting the invention is llluatr~ted. E~ch of the individu~l lnterconnectlng llnea in FIG. 8 hsa ~ number wlth a alash beside it which indic~tea the number o linea or channela of information. Cro~a point switch 65 ls u~ed to provide 8-line byte 32 ch~nnel inputs to the digltal aign~l proceaaor 13 and connect to bus 12. Dlgit~l aignsl proceasor circuitry 13 h~s ~our modulea, e~ch one of which includes of lta own code memory 67, d~t~ memory 68, cro~ point swltch 65 ~nd high speed mlcroproce~or 63. The inputs to the code memory 67 ~nd d~t~
momory 68 ~re controlled by ~ddreas multiplexers 80 ~nd 81, r~p~ctively, which receive inputs rom the high apeed mlcroproce~or 63 ~nd the multi-bus ~ddress lines 83A. High ~peed microproceaaor 63 i~ n TI TMS 320C25 chip which hA~ Mn executlon cycle tlne of 120NS in order to ~lt in a dual port ~e~ory wlthout buo arb~tr~tlon It hua a 16-bit oxternnl bua ~lndic~ted) with a 32-blt internol bua (not shown), a 5~ word data r~ndom acceos memory with a capability of accesaing 64K
words of dat~ memory and 64K words of code memory and it has a 16-bit ~ultiplier and ~ ~erial port tlmer The dat~ ~e~or~ 68 la ~ dual port memory end the main central proceaaor 60 (FIG.
5) c~n down load d~ta to the date ~emory 68 and set~a ~lag in the momory to signal the high peed momory 63 tho compl~tion of the data tran~fer The first hal of tho 120NS cycle ia allocat~d for the dota memory acceos and the ~ocond half of the cycl- 1- used by the ~ain nicroproceaaor 60 In thia way, the bu~ contention problema will novor occur and consoquently, no bu- arbitratlon ia required A- an example, ~our 32K X 8 RAM
chipa with ~SNS access and cycle time may be uaed The total 64K 16-bit word data memory is thus provided Tho digital aignal proco~sor cod~ momory 67 i8 alao a dual port memory However, the data in this ca~e c~n only be lo~dod by the ~ain centr~l ~icroproceasor 60 when the high a~-od ne~ory 63 i~ ln halt ~nd thus lt la as~um-d that the code memory 67 n--d only b- loaded during initlaliz~tlon ~ total o 64K 16~b~t word cod- m-mory ia thua provlded Data flow ~rom the multi-bua d~to lines 8~D to the data rando~ acce4a ~emory 68 ia vla conventional data coupling circuita 82 ~the de~ignatlons are shown or this exemplory Qmbodiment~ and to the code random accoss 67 vi~ dat~ coupling circuit 83D, both - .
of whlch ~re lllu~tr~ted as beck-to-b~ck ~i-dlrectlon~l couplers, there belng one auch clrcult for e~ch of the lndlvldul 16 llnea shown. Moreover, the hlgh speed mlcr~pr~a~ monit~r~ th~ operetion of these unlts vl~
convention~l d~t~ coupllng unita 84 ~nd 85 (their chlp deslgn~tion~ ~r~ F244X2) which ~ufer the d~t~ ~nd code inform~tion flow with re~pect to the high apeed microprocessor 6~.
In aumm~ry, ths invention prov$dea ~ aot pl~tform for the integrstlon of all the mQ~or ~apecta of the voice induatry lncl~ding volce reaponae, ape~ker dependent ~nd lndependent voice recognitlon, text to speech Rnd volce identi1c~tion. It el80 provldes connectlon to the Tl dlgltsl network, provl~ea almultsneoua volce snd d~t~ tr~ffic wlth the ~bil~ty to be conigured ln medium to large upplic~tiona. It ia compriaed o~
aever~ yera of microprocesaora e~ch wlth ita own progr~m ~nd communic~tion pass. Physic~l connectlon to the Tl telephone line ~nd ~11 ~ttend~nt tr~ffic man~gement ia controlled by interf~ce controllera. Ths interace ayatem providea p~cka of dat~ to a d,iglt~l signal proceaaor which h~a its own individu~l high ~peed microproceaaor for an lyais. The high apeed microprocQasor performa the sign~l ~n~lysis and d~t~
compresalon ~nd then communicatea the compreaaed d~t~ to ~ m~in or centr~1 microproceasor which buffers it Rnd signala the host ayatem th~t the d~t~ is preaent ~nd then tr~naera th~t dst~ to the hoat. The ~yatem provides ~n effect me~ns of diatributing -1~210~
the high apeed procesaing requirements for the hondllng of 92 chonnela of Tl telephone dato to chips that perform the requlred functions effectively wh~le leaYlng the dot~ atoroge and communicatlon functions to a alngle centrol microprocea~or which can effectively Addreas l~rge volumes of d~to ~nd m~nage the SCSI interfoce.
While there haa been ahown and de~cribed a preerred embodiment of the lnvention, it will be appreclated th~t variou~ modlficationa Hnd ad~ptat~ons o the inventlon wlll become readily apparent to those skilled in the art and it 18 intended thot auch ob~ious modificotions ond odoptationa be encomp~ssed within the cl~ima ~ppended hereto.
WHAT IS CLAIMED IS:
W~TH IMPROVED DIGITAL ~OICE RESPONSE
BACKGROUND AND BRIEF DESCRIPTION OF THE INVENTION:
The pre~nt lnv~ntlon reletea to an lntegr~ted volce response aystems for hundling large numbera of telephone linea. Th~ integruted telecommunic~tion system provides ~
multlple telephone line reaponae ~nd procesaing syatem which provide~ a "soft" platform for the integrntlon o all ~Jor nspecta of the voice indu~try including: voice response, apeak~r dependent and independent voice recognition, text-to-speech ~nd volce ldentific~tion. In addition, it connecta to the telephone Tl digltal networ~ ~uch as provided by MCI, AT6T, Sprint, etc. It providea simultaneou~ voice ~nd d~tQ trafic and has the ability to be configured in mediu~ to large applicationa. The syatem disclosed herein i8 able to ~-hendle up to 192 lines but lt is obvlou~ thut it can be configured to h~ndle much l~rger ayatems.
The in~ention i~ comprised of several layera of proces~ors, ooch wlth lta own program ond communicotion p~th.
Each lnterAce proceasor include~ one or more Tl connection int-recQ clrcuita and a control microprocessor and each digltol aignal proceasor circuit includes a crosa-point switch or llne datn inter~cing purpoae~ and its own digital signal proceasor or perorming aignal analyai~ ~nd d~ta compreaslon.
Thl~ dat~ ia communic~ted to the main system 13~1 00~
control mlcroprocessor which buffers it and signals the host system (whlch may be a conventional PC-AT small systems type computer) that data is present and then transfers that data to the ho~e. Additionally, a control microprocessor in the interface circuit provides the Tl handshaking and call progress monitoring in con~unctlon with the lnterface clrcuit which handles the physlcal connectlons to the Tl and all lts attendant traffic management.
Ob~ects of the invention include the provision of an improved integrated telecommunlcatlons system with the abillty to handle all ma~or aspect~ of volce industry.
Therefore in accordance with the present lnvention there 18 provided an integrated telecommunication system for multiple telephone line re~ponse and processlng comprising a plurality of interface processor circuitq, each of which i8 adapted to control the physical connection to a plurallty of telephone line channels and control communication on a group of said telephone line channels connected thereto, each said interface circuit including a high speed lnterface control microprocessor and a first data storage associated therewithr a plurality of signal processor circuit means, each said signal processor circuit mean~ including crosspoint switch means for receiving multiple line multlple channel inputs and producing corresponding ~ultiple line multiple channel outputs, and a hlgh speed digital signal microprocessor for analyzing the incoming slgnals and compressing the data therein, and a second data storage assoclated therewlth, for controlllng one or more telecommunication function clrcuits, a main system control mlcroprocessor, a first bus system for connectlng sald plurallty of lnterface processor circuits to said plurality of slgnal processor circuit means, and a second bus system for connectlng each of sald plurality of interface processor circuits to each - ~
21~
of ~aid plurality of ~ignal processor circuit means and to said main system control microprocessor, whereby the high ~peed processing requirements of each said group of telephone lines i~ performed by said interface processor circuits and sa~d digital signal microprocessor and said main system control microprocessor controls the storage of data in said first and second data storages and intercommunication functions between said plurality of interface processor circuits and said plurality of signal processor circuit means and said one or more telecommunication function circuits controlled thereby.
The above and other ob~ects, advantages and feature~ of the invention will become more apparent when considered with the following ~pecification and accompanying drawlngs wherein:
Figures 1-4 prov~de in broad perspective an overview of the functional aspects of the system in which:
FIG. 1 is a functional block diagram of an automated multiple telephone line response and processing system incorporating the invention, FIG. 2 is a functional block diagram of the Tl interface processor shown in FIG. 1, FIG. 3 is a functional block diagram of the digital signal processor shown ln FIG. 1, FIG. 4 is a functional block diagram of the control processor shown in FIG. 1.
Figure~ 5-8 are more detailed diagrams of the system wherein:
1~21~0~
FIG 5 correspondA to FIG 1 ~nd la ~ more det~ d e~pos~tlon o~ the over~ll system, FIG 6 ahows the lnterconnectlon between the dlgital lnterf~clng ~nd the dlglt~l sl gnRl proceaaor clrcultry components, FIG 7 i~ ~ functional lllustration of the syatem me~ory whlch la controlled by the maln sy~tem ~icroprocea~or illuatr ting th~ particul~r locotion of esch of theae roapective elements in the interf~ce clrcultry and in the dlgit~l switch clrcuitry and the sddltlon~l memory shown in FIG 1, ~nd FIG 8 ia ~ det~iled block diagr~ of n aingle digit~l algnal proceaaor module illuatruted ln FIG
DETAILED DESC~IPTION OF THE INVENTION
Referrlng now to FIGS 1-4, the system ln lt~ bro~der nspects ia od~pted and designed to meet aeveral requirements including provlding a ''aoft" ~l~tform for the inte~r~tion of all the ma~or a~pecta of the voice industry such as volce re~ponae, ape~ker dependent and independent voice recognition, t-xt-to-~peech ond volce identiflcotion, connectlon to ths Tl digital network, the provlalon o ~imult~noou~ volce ~nd doto tr~1c control ond the obility to be con~igured in medium to larg- scole opplic~tiona It ia ~lao cap~ble o beh~ving aa ~n on~log or digltol witch for each Tl channel In FIG 1, aQverol l~yera o procesaora each with ita own program ond communicotion p~ths ~re illustrated Each Tl element <or ' T-span) conQtltutes multiple telephone channels or lines. (Each "T-span" coming from the phone company may be four wires or optical fiber havlng 24 channels (or more) encoded thereon - or 24 simultaneous conversatlons or data exchanges). In thls embodlment there are two T-spans or Tl telephone lines, each having 24 channels 80 that there are 48 channels handled by each lnterface processor 10-1, 10-2, 10-3...10-N. Each interface processor 10 18 illustrated in a functional block diagram shown in FIG. 2 and include a Tl interface microclrcuit chip which in this embodiment is a Mitel 89760* (the details of which are given in the "Microelectronics Data book" published by the Mitel Corporation, copyright 1988). Each proces~or includes a high speed microprocessor which, in this case, is an Intel 80188* (which is described in the Intel Manual) and includes 64K of randsm access memory for storing data and program informatlon. This high speed microprocessor detects a phone ringing on one of the channels and signals the main system microprocessor, which, in turn, signals a partlcular digital signal processor module 13 to handle the call, which then signals the lnterface circuit that it has been assigned to handle the call and to connect the ringing channel to it for proces~ing and - responding to any ~ignals ~including voice) thereon. It also include~ a serial diagnostic port.
It should be noted that the multibus for conveying address and data information between the various units is *Trade Mark i' ';
:
132100~
lllu~trated in FIG. 1 ~a element No. 11. At the ~sme time, second~ry bu~ 12 lnterconnecta the lnter~ce proce~aora 10-1 ~nd the dlglt~l ~lgn~l processor~ 13-1, 13-2, 13-3...13-N. The bu~ 12 1~ lndlc~ted ln FIG. 1 ln ~ block form but i~ ~hown ln greater detsil wlth the v~rioua interconnectiona between the units shown in FIG. 6. Aa shown in FIG. 6, bu~ 12 hus a plursl$ty of lines, ln this embodiment 8, which are design~ted a8 15-1, 15-2...15-8 with the output of e~ch interf~ce unit 10-1 being connected to two of the lines. The dif~erent channels on each T-span which ~re labeled T-span 0, T-spAn 1 T-span 2...T-span 7~ each with 24 individual channels, is provided wlth a communication p~th to the T2 bus and thence to the individual digital aign~l proceaaor clrcuits 1~-1, 13-2.
lt ahould be noted that eoch of the digit~l aign~l proceaaing circuits is connected to ~ll of the lines of bu~ 12 80 that ~ny dlglt~l ~lgnul processlng circuitry 13-1, 13-2...1 -N c~n be uaed to process the aign~ls on ~ny of the channel~ of the T-ap~na connected to the interfsce circuits 10-1...10-N.
Referrlng ag~in to FIG. 2, it wlll be noted that the bus 12 1~ indlc~ted ~a belng ~ high speed dat~ hlghway to the digital ~ign~l procossors. The functions performed by the lnter~ce procè~sors 10 i~ set out in the table of unctions llated on FIG. 2. The 24 channels on e~ch of the Tl inputs typically is tlme division multiplexed and is demultiplexed by thi- proc-s40r. E~ch of theae ~unctions is performed by the program stored in ~ programmable read-only memory 54 <shown in FIG. 5) whlch m~y be ln e flrmw~re module ~inc ~ 4 in~tallable ROM c~rtridges). Each o the dlgital aignel procea~ors 13 ia ahown in detall in FIG. 8 ~nd wlll be deacribed in gre~ter detail in connection with th~t flgure.
However, lt should be noted thMt broadly, this circuit includes the digital sign~l procesoor chipa ~nd it recei~es packet~o data or Mnalysi~ from the lnterface clrcults 10. Each digital aignal proce~or 13, which is multit~sked, then perform~ the anqlysia and dat~ compreaaion on the~e packets o~ dato ~nd communicates t~e compreased data or the dual tone ~requency modulatlona (DTMF) to the ho~t computer ~ystem 74 which, in thi~ case, may be n PC-AT computer. It aign~l~ dot~ i8 present -nd transer~ th~t dut~ to the hoat computer syatem 74.
Additionally, a high ~peed control microprocessor 63 (in the interace circuit~ 10 shown in FIG. 5> provldes the handshRking und c~ll progre~ monitoring in conJunction with the line interface circuit. The functions performed by o~ch of the digit~l ~ignal processor elementa 13 are ahown in the table at the right in FIG. 3.
The control proce~sor 15 contains the main microproce~sor 60 and 18 ~hown in detail in FIG. 5. The functional block dlsgr~m shown in FIG. 4 o~ the control processor ill~strates a high ~peed (20mHz Intell 80386)*microprocesaor 60 which i~
c~p~bie o controlling up to 16 meg~byte~ o r~ndom ~ccea~
memory. The~e 16 meg~byte~ o~ r~ndom ~cceaa memory ~re illu~tr~ted diagr~mmatic~lly in FIG. 7 where the .~ystem memory *Trade Mark 6 ,, ' .
~ 3210~4 model la dlagrammatlcelly lllustrated. It wlll be noted that each o the dlgital aignal proce~aors 13 haa lts memory lndlcated aa belng controlled by the maln ayBtem control ~lcroproc~aor 1~, each p~ogr~m ~AM 20 and each dsta ~AM ~1 ln the dlgltal sign~l proceaaora 13 ia shown ~a belng p~rt of the ~omory controlled by the Maln processor. At the ~me tlmej the random acceaa memorlea and the ROMa in the lnterface unita 10 are likewise ~llu~tr~ted as being p~rt of the memory addresaable or being controlled by the main microprocea~or 60.
It al80 addresaea it~ own ~emories 70 and 71. In other words, up to 16 megabytes of memory whether physlcally atored in ~ither the lnterface clrcults 10 or the digital aignal processor clrcuits 13 or in the hoat computer 74 i~ ~cceaalble or control by the maln mlcroprocesaor CPU ayatem 15 ~la the main multi-bus 11. In FIG. 4, a connectlon i8 provided ~or the SCSI bu~ to the hoat processor ~nd a aerial diagnostic connect~on to a seri~l diagnostic port ia likewise provided for ~yutom dlngnosis.
The table to the rlght in FIG. 4 liats the functiona whlch ~re performed by the main control proceasor 15. These include cnll progreaa and a~aignment, speech dat~ management, host aystem lnterface mansgement, loc~l and remote external dlagno4tic~, automatic aelf-di~gnostica and ayatem wide ~t~tl~tlcs and monitoring. It wlll be appreci~ted that the read-only memory shown in FIG. 6 may contaln theae programa whlch are down-loaded upon initiating operation of the ayatem 132~04 to thereby control the oper~tlon of th~ centr~l proces~or through theae programa. Various ones of the program8 may be aelected or c~lled-up from the ROM or may be separately loaded through the SCSI from the permanent atorage 76.
The overall aspecta of the system disclosed i~ to prov$de a aoft platform or the integration o all the ma~or aspec~s of the voice reaponae sy~tem a8 deacribed above. The system i8 compriaed of aeveral layers of mlcroprocesaors each with lts own program and communication pntha but each of which are controlled, by a ~in centr~l microprocesaor 60. At the Tl connectlona, co~mercially available microproce~or chipa are utilized to handle the physic~l connectlon to the Tla ~the telecom~unication channels) und all its attendunt trafflc ~anagement. It then provldea the packets o dat~ to the dlgital signal proces~or for analyais. The digltal signal proceaaor then performs signAl analyala and dato compresslon and oommunicates the compreased data or the ~TFMa to the main ~yatem control microprocesaor which bu~fera lt and aignala the host ~y~tem that data is present and transfers thnt data to the hoat. Additionally, the microproceaaor in the interace procos~or provides the telephone channel handahaking ~nd c~ll progrea~ monitoring in con~unction with the interfacing provided by the mlcroproce~sor interf~clng chlps.
Thia ay~tem thus providea an efective meana o dl~tributlng the high speed processing requirements of handling of the 192 ch~nnela of T1 dat~ circuita that per~orm those l32lao~
requlred functlons e~fecti~ely while leevlng the d~tq storege ~nd communlcetlon function~ to the ~ingle msln ~ystem mlcroprocesaor whlch c~n effectl~ely address l~rge volune~ of d~t~ snd ~nsge the ho~t lnterfece.
~ eferrlng now to FIG. 5, s more detsiled sy~tem block d~sgrn~ is shown in whlch the interf~ce proceasora lO, digit~l sign~l processor~ 13 ~nd m~ln control proceasor syatem 15 ~re ~hown ln their interrelated Qrr~ngements with the preferred microelectronic circuit chipa with their m~nufscturer identified ~e.g., Mitel 89760, i~ ~ Mitel circuit component or interf~cing to 4 Tl telephone chennel ~nd i8 described, or ex~mple, in det~il beginning ot p~ge~ 4-263 through 4-288 of the Mitel "Microelectronics Dsts Book" ia~ue No. 5, copyright 1988 by the Mitel Corporation). The coupling of the lndl~ldual telephone line channels to the Mitel circult element i~ con~entional and is ~llustrated at page 4-286 of ~aid Mitel Manual and hence need not be shown in detail herein.
As deacribed ubo~e, the control mlcroprocessor 50 <~n Intel 80188) ia respon~ible for the control ~nd monitoring of the line lnterf~ce controller 51 <e Mitel 89760) and the ~asoci4ted circuitry. Specific411y, it h~ndles the SF or ESF
bit oriented AB aign~lling per ch~nnel; the F~L UI r~me for perform~nce reporting: the ISDN D-ch~nnel sign~lling l~yer 2 ~nd l~yer 3: the multi-bus interf~ce for communic~tiona to the m~in centr41 processor 60 in ayaten~ centr~l processing unit lS
g 1321~4 and lt does the lnltlali%~tion qnd diagnostlc testlng functions for thia unit.
The call progrea~ interace unit 52 ~a Mitel 8920)*ia coupled to the DS1 line interace unit S1 and i8 controlled by control microprocea~or 50. Control microproceaaor 50 ia initially louded with its progrom from read-only ~e~ory 54~
The line interface ele~ent 51 ia alao coupled to the acility duta link 55 ~a hltel 8952*unlt) conventionally ~ervea as the ocility data link controller. Finally, the line interf~ce unit 51 i8 olao coupled via the parallel input~output port 56 which are likewiae controlled by the high ~peed control processor 50. The coupling between multi-bua 11 and the high speed control processor 50 in the interace circuitry i8 buffered by a random accea~s ~emory 56 which storea both data and program which is coupled to and from the central procesaor nicroprocessor 60 via the multi-bua 11.
The bus 1~ is generally indicated ag having three lines but it will be apprecieted that theae are multi-lines for inputa/outputa ~nd the thlrd line is a aynchronizing line.
Thua, in the digital aignal proceasor 13, line 60 is a ~ynchronizing line and linea 61 und 62 can constitute input lines und output lines, respectively. Synchronizing line 60 is connected to synchronize the operation of high speed microproces~or 6~ (~n Intel 30C~5 unit) by synchronizing line *Trade Mark , --1321~0~
A crosa-point awltch 65 (which ia ahown and deacribed ln gre~ter det~ n relation to FIG. 8), la controlled by hlgh speed ~lcroprocesaor 63 and BUppl ies dlglt~ gnala to a dAta rendom eccea~ memory 66 ~nd progr~m random acceaa memory 67 which, ~8 deacribed e~rlier herein, ~re controlled by the ~oln central procea~or 60. The high apeed digitMl a~gn~l procesaor 63 ia progrnmmed for an~lyzing and encodlng and decodlng functions on data paased to it from the interace clrcuitry 10 in the main centrol mlcroprocessor lS. E~ch of these circuits 13 ia responsible or proce~sing ~ix chonnela of the T1 telephone circulta wlth ~ compliment of four dlgital aign~l procesaora 13 required to proces~ all 24 channels of the telephone llne component Tl.
Hlgh speed mlcroprocessor 63 iA thus reapon~ible to handle communlc~tiona of dat~ to ~nd from the llne lnterfac~ ~ .
syatem 10, the perormance of ADPCM to PCM and PCM to ADPCM
compres0ion, perform~nce of the DTMF and MF recognltion, perormance o the DTMF and MF tone generation, dat~ buffer mQnagement, watch dog unctiona, cnll progreaa monitoring, ~y~tem houaekeeping functlons and the perormance o channel ~onogemont unctions. All o thea~ functions ore achieved under progr~m control which i8 received from the central proceasor by the program RAM 67.
The moln centrul proceaslng unit 15 ia illustr~ted 08 ho~lng centrol proce~or 60, a random access memory 70, a read-only memory 71 (whlch may be in a flrmwore module ~32~ ~04 lncluding lnstolleble ROM certridges), n seri~l lnput~output port 72 ~nd o ~11 computer systems lnteruce <SCSI) 73 whlch couples to o ho~t system 7~ which moy lnclude o further amoll computer systems lnterace 75, lerge or mssa permenent ~tor~ge 76 (for record or orchl~ol purposes) and the a~ull host computer (PC-AT) referred to eorller M~in centr~l procesaor 60 include progrons for performing aupervisory control function~ over the digitel slgn~l proce~aors ~nd the lnterf~ce circuitry 10 nd its high speed ~icroprocessor 50 end communlcetion~ to the host syatem 74 und the meaory mQnugeaent functions <~8 noted e~rlier, ~11 of the different memory elerent~ idontiied hereln ~re controllable ~rom the centrol nlcroproces~or 60), aerial communications to o debugger~nonltor end wotch dog unctions Specl1c~11y, thls centrsl mlcroproces~or m~n~gea int-rections between the two hlgh speed mlcroprocea~ora 50 end 63 ~lo buaea 11 nnd 12 end the host oy-ten 74 ~io the SCSI bus) It ol~o m~noges ita loc~l mRnOry, lo~ding phroses rom the host PC 74, trnnaerring r-corded peech to the host PC ond determining where in nemory to otore this doto It al80 maneges the mess~ge queue to ond rom tho hoot co~putor 7~ driv-r Moreo~er, it hondles mon~gem-nt o~ coll progress d~ta from the two high speed microproce-40r4 SO ~nd 63 ~nd it hondle4 c~ll os4ignment when the hlgh opeed microprocesoor 50 ~ignol~ on incoming coll by ~ooigning it to o porticulor hlgh speed computer 63 in the bunk o digit~l aignol procesaora 13-1, 13-2 13-N It monitor~
~32lao4 (e.g., providQs "watch dog" functions) o~ the st~tu~ o e~ch ch~nnel Rnd "w~kea up" locked up ch~nnels or t~ke~ them out of ~ervlce. In ~ddltlon, lt ia progr~mmed to h~ndle the physlc~l cont~ol o~ the SCSI l~ter~ce 73 with the SCSI drlver. It ~lao c~n hAndle uni~ers~l ~synchronous receive~tr~nsmit ~UART) communic~tlons with the front psnel and proce~aea lnstruction~
rom the host computer 74 (e.g., send DTMF, record in minutes, play A phr~se, etc.). The hoat computer 74 c~n provide functionul control over the entire system bec~use it down lo~da p~rnmeter in~orm~tion at ~t~rt up ~nd communic~tea individu~l lnstructions.
Reerring now to FIG. 8, a det~il circuit di~grAm o a single dlgit~l sign~l processing module incorpor~ting the invention is llluatr~ted. E~ch of the individu~l lnterconnectlng llnea in FIG. 8 hsa ~ number wlth a alash beside it which indic~tea the number o linea or channela of information. Cro~a point switch 65 ls u~ed to provide 8-line byte 32 ch~nnel inputs to the digltal aign~l proceaaor 13 and connect to bus 12. Dlgit~l aignsl proceasor circuitry 13 h~s ~our modulea, e~ch one of which includes of lta own code memory 67, d~t~ memory 68, cro~ point swltch 65 ~nd high speed mlcroproce~or 63. The inputs to the code memory 67 ~nd d~t~
momory 68 ~re controlled by ~ddreas multiplexers 80 ~nd 81, r~p~ctively, which receive inputs rom the high apeed mlcroproce~or 63 ~nd the multi-bus ~ddress lines 83A. High ~peed microproceaaor 63 i~ n TI TMS 320C25 chip which hA~ Mn executlon cycle tlne of 120NS in order to ~lt in a dual port ~e~ory wlthout buo arb~tr~tlon It hua a 16-bit oxternnl bua ~lndic~ted) with a 32-blt internol bua (not shown), a 5~ word data r~ndom acceos memory with a capability of accesaing 64K
words of dat~ memory and 64K words of code memory and it has a 16-bit ~ultiplier and ~ ~erial port tlmer The dat~ ~e~or~ 68 la ~ dual port memory end the main central proceaaor 60 (FIG.
5) c~n down load d~ta to the date ~emory 68 and set~a ~lag in the momory to signal the high peed momory 63 tho compl~tion of the data tran~fer The first hal of tho 120NS cycle ia allocat~d for the dota memory acceos and the ~ocond half of the cycl- 1- used by the ~ain nicroproceaaor 60 In thia way, the bu~ contention problema will novor occur and consoquently, no bu- arbitratlon ia required A- an example, ~our 32K X 8 RAM
chipa with ~SNS access and cycle time may be uaed The total 64K 16-bit word data memory is thus provided Tho digital aignal proco~sor cod~ momory 67 i8 alao a dual port memory However, the data in this ca~e c~n only be lo~dod by the ~ain centr~l ~icroproceasor 60 when the high a~-od ne~ory 63 i~ ln halt ~nd thus lt la as~um-d that the code memory 67 n--d only b- loaded during initlaliz~tlon ~ total o 64K 16~b~t word cod- m-mory ia thua provlded Data flow ~rom the multi-bua d~to lines 8~D to the data rando~ acce4a ~emory 68 ia vla conventional data coupling circuita 82 ~the de~ignatlons are shown or this exemplory Qmbodiment~ and to the code random accoss 67 vi~ dat~ coupling circuit 83D, both - .
of whlch ~re lllu~tr~ted as beck-to-b~ck ~i-dlrectlon~l couplers, there belng one auch clrcult for e~ch of the lndlvldul 16 llnea shown. Moreover, the hlgh speed mlcr~pr~a~ monit~r~ th~ operetion of these unlts vl~
convention~l d~t~ coupllng unita 84 ~nd 85 (their chlp deslgn~tion~ ~r~ F244X2) which ~ufer the d~t~ ~nd code inform~tion flow with re~pect to the high apeed microprocessor 6~.
In aumm~ry, ths invention prov$dea ~ aot pl~tform for the integrstlon of all the mQ~or ~apecta of the voice induatry lncl~ding volce reaponae, ape~ker dependent ~nd lndependent voice recognitlon, text to speech Rnd volce identi1c~tion. It el80 provldes connectlon to the Tl dlgltsl network, provl~ea almultsneoua volce snd d~t~ tr~ffic wlth the ~bil~ty to be conigured ln medium to large upplic~tiona. It ia compriaed o~
aever~ yera of microprocesaora e~ch wlth ita own progr~m ~nd communic~tion pass. Physic~l connectlon to the Tl telephone line ~nd ~11 ~ttend~nt tr~ffic man~gement ia controlled by interf~ce controllera. Ths interace ayatem providea p~cka of dat~ to a d,iglt~l signal proceaaor which h~a its own individu~l high ~peed microproceaaor for an lyais. The high apeed microprocQasor performa the sign~l ~n~lysis and d~t~
compresalon ~nd then communicatea the compreaaed d~t~ to ~ m~in or centr~1 microproceasor which buffers it Rnd signala the host ayatem th~t the d~t~ is preaent ~nd then tr~naera th~t dst~ to the hoat. The ~yatem provides ~n effect me~ns of diatributing -1~210~
the high apeed procesaing requirements for the hondllng of 92 chonnela of Tl telephone dato to chips that perform the requlred functions effectively wh~le leaYlng the dot~ atoroge and communicatlon functions to a alngle centrol microprocea~or which can effectively Addreas l~rge volumes of d~to ~nd m~nage the SCSI interfoce.
While there haa been ahown and de~cribed a preerred embodiment of the lnvention, it will be appreclated th~t variou~ modlficationa Hnd ad~ptat~ons o the inventlon wlll become readily apparent to those skilled in the art and it 18 intended thot auch ob~ious modificotions ond odoptationa be encomp~ssed within the cl~ima ~ppended hereto.
WHAT IS CLAIMED IS:
Claims (5)
1. An integrated telecommunication system for multiple telephone line response and processing comprising:
a plurality of interface processor circuits, each of which is adapted to control the physical connection to a plurality of telephone line channels and control communication on a group of said telephone line channels connected thereto, each said interface circuit including a high speed interface control microprocessor and a first data storage associated therewith, a plurality of signal processor circuit means, each said signal processor circuit means including crosspoint switch means for receiving multiple line multiple channel inputs and producing corresponding multiple line multiple channel outputs, and a high speed digital signal microprocessor for analyzing the incoming signals and compressing the data therein, and a second data storage associated therewith, for controlling one or more telecommunication function circuits, a main system control microprocessor, a first bus system for connecting said plurality of interface processor circuits to said plurality of signal processor circuit means, and a second bus system for connecting each of said plurality of interface processor circuits to each of said plurality of signal processor circuit means and to said main system control microprocessor, whereby the high speed processing requirements of each said group of telephone lines is performed by said interface processor circuits and said digital signal microprocessor and said main system control microprocessor controls the storage of data in said first and second data storages and intercommunication functions between said plurality of interface processor circuits and said plurality of signal processor circuit means and said one or more telecommunication function circuits controlled thereby.
a plurality of interface processor circuits, each of which is adapted to control the physical connection to a plurality of telephone line channels and control communication on a group of said telephone line channels connected thereto, each said interface circuit including a high speed interface control microprocessor and a first data storage associated therewith, a plurality of signal processor circuit means, each said signal processor circuit means including crosspoint switch means for receiving multiple line multiple channel inputs and producing corresponding multiple line multiple channel outputs, and a high speed digital signal microprocessor for analyzing the incoming signals and compressing the data therein, and a second data storage associated therewith, for controlling one or more telecommunication function circuits, a main system control microprocessor, a first bus system for connecting said plurality of interface processor circuits to said plurality of signal processor circuit means, and a second bus system for connecting each of said plurality of interface processor circuits to each of said plurality of signal processor circuit means and to said main system control microprocessor, whereby the high speed processing requirements of each said group of telephone lines is performed by said interface processor circuits and said digital signal microprocessor and said main system control microprocessor controls the storage of data in said first and second data storages and intercommunication functions between said plurality of interface processor circuits and said plurality of signal processor circuit means and said one or more telecommunication function circuits controlled thereby.
2. The integrated telecommunication system defined in claim 1 wherein each of said plurality of interface processor circuits includes a telephone line interface circuit chip, a call progress interface chip and a facility data link chip and means connecting said interface circuit chip, call progress interface chip and said facility data link chip to said high speed interface control microprocessor, and means to supply a program to said high speed interface control microprocessor.
3. The integrated telecommunication system defined in claim 1 including a permanent data storage means and means connecting said permanent data storage means to said main system control microprocessor.
4. An integrated telecommunication system for multiple telephone line response and processing comprising:
a plurality of interface processor circuits, each of which is adapted to control the physical connection to a plurality of telephone line channels, and control communication on a group of said telephone line channels connected thereto, and each interface processor circuit including a high speed interface control microprocessor, respectively, a plurality of signal processor circuit means, each said signal processor circuit means including crosspoint switch means for receiving multiple line multiple channel inputs and producing corresponding multiple line multiple channel outputs, and a high speed digital signal microprocessor for analyzing the incoming signals and compressing the data therein, and one or more telecommunication function circuit means controlled thereby, a main system control microprocessor, and data storage means connected thereto, a first bus system for connecting said plurality of interface processor circuits to said plurality of signal processor circuit means, and a second bus system for connecting each of said plurality of interface processor circuits to each of said plurality of signal processor circuit means and to said main system control microprocessor, whereby the high speed processing requirements of said group of telephone line channels is performed by said interface processor circuits and said digital signal microprocessor and said main system control microprocessor controls the storage of data in said data storage means and intercommunication functions between said plurality of interface processor circuits and said plurality of signal processor circuit means and said telecommunication function circuit means controlled thereby.
a plurality of interface processor circuits, each of which is adapted to control the physical connection to a plurality of telephone line channels, and control communication on a group of said telephone line channels connected thereto, and each interface processor circuit including a high speed interface control microprocessor, respectively, a plurality of signal processor circuit means, each said signal processor circuit means including crosspoint switch means for receiving multiple line multiple channel inputs and producing corresponding multiple line multiple channel outputs, and a high speed digital signal microprocessor for analyzing the incoming signals and compressing the data therein, and one or more telecommunication function circuit means controlled thereby, a main system control microprocessor, and data storage means connected thereto, a first bus system for connecting said plurality of interface processor circuits to said plurality of signal processor circuit means, and a second bus system for connecting each of said plurality of interface processor circuits to each of said plurality of signal processor circuit means and to said main system control microprocessor, whereby the high speed processing requirements of said group of telephone line channels is performed by said interface processor circuits and said digital signal microprocessor and said main system control microprocessor controls the storage of data in said data storage means and intercommunication functions between said plurality of interface processor circuits and said plurality of signal processor circuit means and said telecommunication function circuit means controlled thereby.
5. The integrated telecommunication system defined in claim 4 wherein each of said plurality of interface processor circuits includes a telephone line interface circuit chip, a call progress interface chip and a facility data link chip and means connecting said interface circuit chip, call progress interface chip and said facility data link chip to said high speed interface control microprocessor, and means to supply a program to said high speed interface control microprocessor.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/253,470 | 1988-10-05 | ||
| US07/253,470 US4955054A (en) | 1988-10-05 | 1988-10-05 | Integrated telecommunication system with improved digital voice response |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1321004C true CA1321004C (en) | 1993-08-03 |
Family
ID=22960405
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000613290A Expired - Fee Related CA1321004C (en) | 1988-10-05 | 1989-09-26 | Integrated telecommunication system with improved digital voice response |
Country Status (12)
| Country | Link |
|---|---|
| US (1) | US4955054A (en) |
| EP (1) | EP0437515B1 (en) |
| JP (1) | JPH04502839A (en) |
| AU (1) | AU622072B2 (en) |
| BR (1) | BR8907697A (en) |
| CA (1) | CA1321004C (en) |
| DE (1) | DE68928550T2 (en) |
| DK (1) | DK60591A (en) |
| ES (1) | ES2016188A6 (en) |
| FI (1) | FI911619A0 (en) |
| IL (1) | IL91810A (en) |
| WO (1) | WO1990004298A1 (en) |
Families Citing this family (48)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5420852A (en) * | 1988-09-29 | 1995-05-30 | American Tel-A-Systems, Inc. | Digital switching system connecting buses with incompatible protocols and telephone answering system and private automatic branch exchange with integrated voice and textual message recording |
| US5341368A (en) * | 1992-05-05 | 1994-08-23 | American Tel-A-Systems, Inc. | Digital switching system interconnecting buses with imcompatible protocols |
| US5029199A (en) * | 1989-08-10 | 1991-07-02 | Boston Technology | Distributed control and storage for a large capacity messaging system |
| US5165095A (en) * | 1990-09-28 | 1992-11-17 | Texas Instruments Incorporated | Voice telephone dialing |
| US5193110A (en) * | 1990-10-09 | 1993-03-09 | Boston Technology, Incorporated | Integrated services platform for telephone communication system |
| US5260937A (en) * | 1990-10-29 | 1993-11-09 | Dsc Communications Corporation | Power conserving technique for a communications terminal time slot interchanger |
| US5239542A (en) * | 1991-08-23 | 1993-08-24 | Redcom Laboratories, Inc. | Time division multiplex switching system for interconnecting telephone circuits which operate in accordance with different signalling systems and call formats |
| US5274738A (en) * | 1991-12-31 | 1993-12-28 | Dictaphone Corporation | Modular digital voice processing system |
| US5404455A (en) * | 1991-12-31 | 1995-04-04 | Dictaphone Corporation | Time division multiplexer chip for supporting alternating communication between a pair of RAMs and two different interfaces |
| CA2138170C (en) * | 1992-06-15 | 1998-11-10 | Martin Owen Watts | Service platform |
| US5321744A (en) * | 1992-09-29 | 1994-06-14 | Excel, Inc. | Programmable telecommunication switch for personal computer |
| JP2516317B2 (en) * | 1992-10-13 | 1996-07-24 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Data processing system and method for loading digital signal processor. |
| US5625845A (en) * | 1992-10-13 | 1997-04-29 | International Business Machines Corporation | System for facilitating continuous, real-time, unidirectional, and asynchronous intertask and end-device communication in a multimedia data processing system using open architecture data communication modules |
| US5440740A (en) * | 1992-10-13 | 1995-08-08 | Chen; Fetchi | System and method for managing devices on multiple digital signal processors |
| CA2111653A1 (en) * | 1993-02-10 | 1994-08-11 | Ellis K. Cave | Method and system for unified voice telephone services |
| US5467372A (en) * | 1993-07-21 | 1995-11-14 | Rohm Co., Ltd. | Multi channel ADPCM compression and expansion device |
| GB2280820A (en) * | 1993-07-29 | 1995-02-08 | Ibm | Distributed system for call processing |
| US5347512A (en) * | 1993-09-17 | 1994-09-13 | Rockwell International Corporation | Telecommunication system with delay data buffer and method |
| US5442789A (en) * | 1994-03-31 | 1995-08-15 | International Business Machines Corporation | System and method for efficiently loading and removing selected functions on digital signal processors without interrupting execution of other functions on the digital signal processors |
| US5793845A (en) * | 1994-08-01 | 1998-08-11 | British Telecommunications Public Limited Company | Service node for a telephony network |
| US5875234A (en) | 1996-02-14 | 1999-02-23 | Netphone, Inc. | Computer integrated PBX system |
| US6252944B1 (en) * | 1997-06-11 | 2001-06-26 | Estech Systems, Inc. | Telephone call/voice processing system |
| US7421066B1 (en) * | 1996-06-12 | 2008-09-02 | Estech Systems, Inc. | Telephone call/voice processing system |
| US6724751B1 (en) * | 1996-12-21 | 2004-04-20 | International Business Machines Corporation | Distributed voice processing system |
| GB2320642A (en) * | 1996-12-21 | 1998-06-24 | Ibm | Distributed voice processing system |
| US6198753B1 (en) | 1997-05-20 | 2001-03-06 | Alcatel Usa Sourcing, L.P. | Method and apparatus for facilitating an interface to a digital signal processor |
| US5961627A (en) * | 1997-06-18 | 1999-10-05 | Gigalabs, Inc | High speed switch for high speed connection between computers and peripheral devices |
| WO1999026233A2 (en) * | 1997-11-14 | 1999-05-27 | Koninklijke Philips Electronics N.V. | Hardware sharing in a speech-based intercommunication system |
| US6208657B1 (en) * | 1998-01-07 | 2001-03-27 | Mci Communications Corporation | Programmable gateway for a virtual bearer channel platform |
| US6763017B1 (en) | 1998-09-30 | 2004-07-13 | Cisco Technology, Inc. | Method and apparatus for voice port hunting of remote telephone extensions using voice over packet-data-network systems (VOPS) |
| US6584108B1 (en) | 1998-09-30 | 2003-06-24 | Cisco Technology, Inc. | Method and apparatus for dynamic allocation of multiple signal processing resources among multiple channels in voice over packet-data-network systems (VOPS) |
| US6535505B1 (en) * | 1998-09-30 | 2003-03-18 | Cisco Technology, Inc. | Method and apparatus for providing a time-division multiplexing (TDM) interface among a high-speed data stream and multiple processors |
| US6611531B1 (en) | 1998-09-30 | 2003-08-26 | Cisco Technology, Inc. | Method and apparatus for routing integrated data, voice, and video traffic |
| US7339924B1 (en) * | 1998-09-30 | 2008-03-04 | Cisco Technology, Inc. | Method and apparatus for providing ringing timeout disconnect supervision in remote telephone extensions using voice over packet-data-network systems (VOPS) |
| US7009962B1 (en) | 1998-09-30 | 2006-03-07 | Cisco Technology, Inc. | Method and apparatus for providing forwarding on ring-no-answer for remote telephone extensions using voice over packet-data-network systems (VOPS) |
| US6560196B1 (en) | 1998-11-19 | 2003-05-06 | Cisco Technology, Inc. | Method and apparatus for controlling the transmission of cells across a network |
| US7068594B1 (en) | 1999-02-26 | 2006-06-27 | Cisco Technology, Inc. | Method and apparatus for fault tolerant permanent voice calls in voice-over-packet systems |
| US6657970B1 (en) | 1999-02-26 | 2003-12-02 | Cisco Technology, Inc. | Method and apparatus for link state determination in voice over frame-relay networks |
| US7006493B1 (en) | 1999-03-09 | 2006-02-28 | Cisco Technology, Inc. | Virtual voice port configured to connect a switched voice call to a permanent voice call |
| US6778555B1 (en) | 1999-05-28 | 2004-08-17 | Cisco Technology, Inc. | Voice over packet system configured to connect different facsimile transmission protocols |
| US6775372B1 (en) | 1999-06-02 | 2004-08-10 | Dictaphone Corporation | System and method for multi-stage data logging |
| US6246752B1 (en) | 1999-06-08 | 2001-06-12 | Valerie Bscheider | System and method for data recording |
| US6252947B1 (en) | 1999-06-08 | 2001-06-26 | David A. Diamond | System and method for data recording and playback |
| US6252946B1 (en) | 1999-06-08 | 2001-06-26 | David A. Glowny | System and method for integrating call record information |
| US6249570B1 (en) | 1999-06-08 | 2001-06-19 | David A. Glowny | System and method for recording and storing telephone call information |
| US6977898B1 (en) | 1999-10-15 | 2005-12-20 | Cisco Technology, Inc. | Method for supporting high priority calls on a congested WAN link |
| US7073094B1 (en) * | 2002-05-09 | 2006-07-04 | Winbond Electronics Corporation | Method and systems for programming and testing an embedded system |
| WO2004080091A1 (en) * | 2003-03-03 | 2004-09-16 | Andrew Corporation | Independently acquiring and tracking wireless communication system signaling channel assignments on communication links |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4726014A (en) * | 1983-01-11 | 1988-02-16 | U.S. Holding Company, Inc. | Cellular mobile radio service telephone system |
| JPS59191992A (en) * | 1983-04-15 | 1984-10-31 | Fujitsu Ltd | Information processing exchange system |
| US4627046A (en) * | 1984-04-26 | 1986-12-02 | Data General Corp. | Programmable feature card |
| US4640992A (en) * | 1984-09-10 | 1987-02-03 | At&T Information Systems Inc. | Speech response interface circuit |
| US4656621A (en) * | 1984-12-28 | 1987-04-07 | Gte Laboratories Incorporated | Digital switching system |
| US4719617A (en) * | 1985-02-25 | 1988-01-12 | U.S. Holding Company | Full service voice/data system |
| US4747130A (en) * | 1985-12-17 | 1988-05-24 | American Telephone And Telegraph Company, At&T Bell Laboratories | Resource allocation in distributed control systems |
| CA1254981A (en) * | 1986-02-18 | 1989-05-30 | Lester Kirkland | Communications switching system |
| US4971639A (en) * | 1989-02-28 | 1990-11-20 | Sampson Machine Company | Method and apparatus for joining polymeric substrates such as vinyl frames |
| JPH091992A (en) * | 1995-06-23 | 1997-01-07 | Kimoto & Co Ltd | Marking sheet and manufacture of multi-color mark using that |
-
1988
- 1988-10-05 US US07/253,470 patent/US4955054A/en not_active Expired - Lifetime
-
1989
- 1989-09-26 CA CA000613290A patent/CA1321004C/en not_active Expired - Fee Related
- 1989-09-27 IL IL91810A patent/IL91810A/en not_active IP Right Cessation
- 1989-10-03 BR BR898907697A patent/BR8907697A/en not_active IP Right Cessation
- 1989-10-03 JP JP1510883A patent/JPH04502839A/en active Pending
- 1989-10-03 DE DE68928550T patent/DE68928550T2/en not_active Expired - Fee Related
- 1989-10-03 EP EP89911738A patent/EP0437515B1/en not_active Expired - Lifetime
- 1989-10-03 WO PCT/US1989/004236 patent/WO1990004298A1/en active IP Right Grant
- 1989-10-03 AU AU44092/89A patent/AU622072B2/en not_active Ceased
- 1989-10-04 ES ES8903337A patent/ES2016188A6/en not_active Expired - Fee Related
-
1991
- 1991-04-04 FI FI911619A patent/FI911619A0/en not_active Application Discontinuation
- 1991-04-05 DK DK060591A patent/DK60591A/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| BR8907697A (en) | 1991-07-30 |
| WO1990004298A1 (en) | 1990-04-19 |
| ES2016188A6 (en) | 1990-10-16 |
| IL91810A (en) | 1993-08-18 |
| US4955054A (en) | 1990-09-04 |
| DE68928550T2 (en) | 1998-07-23 |
| DK60591A (en) | 1991-06-03 |
| AU622072B2 (en) | 1992-03-26 |
| FI911619A0 (en) | 1991-04-04 |
| IL91810A0 (en) | 1990-06-10 |
| JPH04502839A (en) | 1992-05-21 |
| EP0437515B1 (en) | 1998-01-14 |
| EP0437515A4 (en) | 1993-05-12 |
| DE68928550D1 (en) | 1998-02-19 |
| DK60591D0 (en) | 1991-04-05 |
| EP0437515A1 (en) | 1991-07-24 |
| AU4409289A (en) | 1990-05-01 |
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