CA1321838C - Apparatus and method for flexible control of digital signal processing devices - Google Patents

Abstract

ABSTRACT
Control apparatus for use with a digital signal processing device. is described in which the control apparatus determines, along with the electrical configuration of the digital signal processing apparatus, the application of members of the signal array to be processed to and the removal of the members of the signal array having been processed from the digital signal processing device. The control apparatus controls the location of data exchanged between the digital signal processing device and associated memory units. The control apparatus permits the digital signal processing apparatus to operate in a normal mode for performing a predetermined processing operation on the members of a signal array, a recursive mode for performing a series of operations on the signal array by a single digital signal processing unit, and a sequential mode for performing a series of processing operations by plurality of digital signal processing units coupled in a series arrangement. The control apparatus has provision for automatic accommodation of predetermined latency in a signal member path, resulting from pipelined computation and from pipelined memory accesses, as well as accommodating preselected signal array sizes and preselected signal array overlap.

Description

~21838 APPARATUS AND MET~OD FOR FLEXIBLE CONTROL
OF DIGITAL 8IGNAL PR~CE8SIN~ DEVICE~
R~hATED APPLI~ATION
This application i~ related to the following Canadian Patent Application.
A HIGH-PERFORMANCE ~ECTOR ARRAY SIGNAL invented by Surendar S. Magar, Michael E. Fleming, Shannon N.
Shen, Kevin M. Rishavy, Christopher D. Furman and Kenneth N. Murphy; having Canadian Serial No. ~90,954 filed on February 14, 1989 and assigned to the assignee of the present Canadian Patent Application.

s~cRGRouND OF THE INVENTION
1. Field o~ the Invention This invention relates generally to the digital processing of signal arrays and more particularly to the control of digital signal processing devices. By appropriate control of the associated digital signal processing apparatus, flexibility and enhanced processing of the signal arrays can be achieved.

2. Description of the Related Art In the related art, the digital processing of signal arrays employing complex algorithms, such as the fast ~ourier transform, has been performed generally using two techniques. In the first technique, the digital signal processing equipment has been a general purpose digital processing unit operating under the control of an appropriate software program. This processing technique is relatively slow and compromises the frequent requirement that the signal processing be performed in real time. The second technique involves the coupling of components in an appropriate manner to perform the requisite processing function. The use of component implementation of the apparatus requires relatively lengthy signal paths and can result in processing that can be unacceptably slow.
Recently, a device fabricated on a single semiconductor substrate has been developed that permits '~
. . . , , . , .; - . ~ , ~: : .. ": :

13~38 the execution of the processing operations implementing a radix-4 fast Fourier transform algorithm and a mixed radix-4/radix-2 fast fourier transform algorithm.
Because these algorithms permit rapid execution of the t 5 fast Fourier transform computations, the ability to process high frequency digital signals in real time is now possible. However, because of the great variability ,-in the processing tasks, e.g., the number of members in an array to be processed, the control functions could 10 not easily be included in components fabricated on the processor semiconductor substrate.

FEATUP~ES OF T~IE INVENTION
It is an object of the present invention to provide '~
improved apparatus for processing of arrays of digital 15 signals. ?,~
It is a feature of the present invention to provide control apparatus for controlling the processing of digital signal arrays.
It is another feature of the present invention to 20 provide control apparatus for controlling the processing of digital signal arrays in which a plurality of address -generator units can have address signals applied to a plurality of associated memory units.
It is yet another feature of the present invention i 2~ to provide a digital signal processing system that can ' execute digital processing procedures in a recursive j manner.
It is a further feature of the present invention to provide a digital signal processing system that can 30 execute processing procedures on signal arrays alone or as a member of a sequence of signal processing units.
It is yet a further feature of the present invention to accommodate easily changes in the digital signal p:rocessing system latency.
35It is still another feature of the present ¦ invention to provide an improved system for performing a .: . .. . - . . . .

~32~ 838 radix-4 fast Fourier transform on an array of signal groups.
It is still a further feature of the present invention to provide a digital signal processing system that can accommodate overlap of signal group arrays being processed.

SUMM~RY OF THE INVENTION f The aforementioned and other features are accomplished, according to the present invention, by 10 control apparatus that can control the processing of an array of signals by a dedicated digital signal processing device and associated memory units.
The control apparatus executes an instruction sequence previously entered in the control apparatus by 15 a microprocessor and/or a dedicated memory device. Each instruction includes a field that is used to determine the configuration of the associated digital signal processing device and the configuration of the associated memory system, therefore controlling the 20 implementation of the algorithm being executed. Each instruction identifies a memory unit in which a signal array to be processed by the associated digital signal processing device and initiates operation of an address sequencing apparatus for the memory array in which the ~5 signal array to be processed is stored and initiates address sequencing apparatus for the memory array into which the processed signal array is to be stored. By controlling the memory array to which the signal array ; addresses are directed, the function of the memory array can be controlled. In this manner, a single appropriately configured digital signal processing device, in conjunction with the control apparatus of the present invention, can execute a multi-step program implementing, for example, a radix-4 fast Fourier 35 transform algorithm. When selected control signals are exchanged between a p urality of digital signal processing systems using the control device the systems ~ 3 ~
can be coupled in a sequential or cascaded manner to expedite signal array processing. The control apparatus includes the ability to access coupled digital signal processing systems thereby controlling the flow of signals being processed among the data processing systems. This control permits simultaneous processing of a plurality of data arrays. ~he control apparatus also includes registers storing information relating to array size, latency and overlap size among data groups which permit flexibility in handling of signal array processing.
These and other features of the invention will be understood upon reading of the following description along with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS
Figure lA illustrates the transformation of a 64 element array using a radix-4 fast Fourier transform, Figure lB illustrates the general relationship between the order of the original signal and the order of the transformed signals, and Figure lC illustrates the radix-4 fast Fourier transformation performed by the digital signal processing unit.
Figure 2 is a functional block diagram of the apparatus for controlling the digital signal processing device of the present invention.
Figure 3 illustrates the format for the control apparatus instruction.
Figure 4A and Figure 4B illustrate system 'configurations for performing recursive processing ¦30 functions implementing a digital signal processing algorithm in which associated memories have reallocated functions.
Figure 4C and 4D illustrate double buffered input-output system configurations for performing recursive processing functions in which associated memory units reallocated functions.

: :. L

- '' ` ~ . " ' :' ' , `' ` ~ : ,, , ` . ~ . :, ' :13?.~3~
Figure 4E illustrates a minimum configuration using the apparatus of the present invention.
Figure 5A and 5B illustrate the operation of a plurality of sequential digital signal processing systems using the present invention.
Figure 6A and Figure 15B illustrate the use of the latency register in the control apparatus of Fig. 2.
Figure 7 is a flow diagram of the use of the present invention for digital signal filtering in the 10 frequency domain. ?`
Figure 8 illustrates the overlap between arrays and the signals discarded after processing the arrays.
Figure 9 illustrates a digital signal processing system using the present invention that can execute the process illustrated in Fig. 8.

DESCRIPTION OF THE PREFERRED EMBODIMENT
1. Detailed DescriPtion of the Fiaures l~-Referring to Fig. lA, the flow diagram for -~
performing a radix-4 fast Fourier transform, using the decimation in frequency transform methodology, on a 64 element array of complex quantities. The numbers 0-64 associated with the left hand column refer to the ordering of the array elements. The numbers 0-64 associated with the right hand column similarly designate ordering of the transformed array elements relative to the initial ordering. The transformation of a 64 element array involves three processing procedures.
-~ Processing procedure 1 involves the combination of ` elements extending over the entire 643 element array.
The processing procedure ~ involves the combination of ; array elements within each of 4 groups of 8 array elements. The processing procedure 3 involves the combination of elements in each of 16 groups of 4 array elements. As will be clear to those skilled in the art, the combination of array elements includes the use of the scaling constants and includes the combination of ~2 ~ ~38 quantities from a plurality (4 for the radix-4 transformation) of array elements.
Referring to Fig. lB, the relationship of the array elements actually combined in the each procedure of the fast Fourier transform is illustrated. For example, in procedure 1 illustrated in Fig. lA, the transformed complex number q(O) will include components from p(O), '-p(l6), p(32) and p(48). I~ Fig. 2B, n=O, 1,...,(N/4-1) and N=64.
Referring to Fig. lC, the effact of the operation of the digital signal processing apparatus on four complex variables and the four complex scaling factors are illustrated. Fig. lC can best be understood in the following manner. j 15 The Input Variables are: -rZ + jiZ; where Z=0-3. `
The Scaling Factors are: /
cZ + jsZ; where Z = 0-3. -The Intermediate Variables are:
aZ + jyZ; where Z=0-3 or:
aO + jbO = [(rO + r2) + (rl + r3)] + j[(io + i2) + (il + i3)]
al + jbl = [(rO - r2) + (il - i3)] + j[(iO - i2) - (rl - r3)]
a2 + jb2 = [(ro + r2) + (rl + r3)] + j[(10 + i2) - (il + i3)]
a3 + jb3 = [(rO - r2) + (il - i3)] + j[(iO - i2) + (rl - r3)]. `~
25 The Output Variables are:
xZ + jyZ; where Z = 0-3 or xO + jyO = (aO + jbO) * (cO + jsO) xl + jyl = (al + jbl) * (cl + jsl) x2 + jy2 = (a2 + jb2) * (c2 + js2) x3 + jy3 = (a3 + jb3) * (c2 + js3) In these equations, j = (-1)1/2 and * denotes complex ; multiplication. The foregoing equations describe the processing capability of the digital signal processing apparatus. To perform the radix-4 fast Fourier transform, the values cO = 1 and sO = O must be set.
Referring now to Fig. 2, the functional block diagram of the digital signal processing device control ~ ; : :

~32~$3~
apparatus 20 of the present invention is shown. The control apparatus 20 includes an instruction processor 203 that controls the execution of instructions stored in instruction memory 202. In the preferred embodiment, the instruction memory can store 32 words. Under control of the instruction processor 203, an instruction from memory register 202 is placed in instruction register 201. The instruction register 201 applies programmable output signals (i.e., control signals) to the associated digital signial processing device and to associated memory apparatus. The instruction register 201 provides control signals controlling the address generators including: the input address sequencer (IAS) 211, the read address sequencer (RAS) 212, the auxiliary address sequencer (XAS 213), the write address sequencer (214), (214) and the output address sequencer (OAS).
Control signals from the instruction register 201 control the application of the five address generators 211-215 to one of five selected (i.e., by the control signals) memory units ADRA, ADRB, ADRX, ADRC and ADRD by bus multiplexer 204. The control apparatus 20 has a plurality of registers 220 that contain data required for the processing members of the array. Register 221 stores the value describing the array size; register 222 stores information describing the latency of signals both within the associated digital signal processor, and also in the associated (e.g., memory) apparatus;
register 223 contains values describing the number of signal array members that are included as members of two arrays for purposes of processing the arrays; and control registers 224 which store information permitting additional flexibility in the digital signal processing.
The control apparatus 20 can have external instruction directly entered into the instruction register. Input control signals can be used to initialize (boot) the control apparatus 20 and can load instructions into the instruction memory 202 and can load parameters into the register bank 220. The control apparatus receives ' ' ', ` ,;' ' , .

. . .

~l32:l8~8 system clock signals, CLKIN signals,and can receive clock signals related to the signal arrays being entered into the signal processing system (ICLK signals), clock signals related to the apparatus receiving the processed j~
signal arrays (OCLK signals) and clock signals related to initialization of the control apparatus (HCLK
signals).
Referring to Fig. 3, the instruction format of the preferred embodiment is shown. The instructions include bit positions. The bit positions 0-7 have the programmable output signals stored therein. These output signals are used to control the associated digital signal processing device and other apparatus associated with the control apparatus. Bit positions 8-11 control the configuration of the bus multiplexer 204, thereby determining to which memory unit the signals ~
from each address generator is applied. The bit ~-positions 12-13 provide a scaling constant for the i-groups of address signals, ADRX signals, which address the auxiliary memory. The data groups in this memory are the weighting factors in processing operations and the scaling factors can permit one group of data for different sized arrays. The bit position 14 determines a parameter of the processing algorithm. In the preferred embodiment, this parameter denoted the use of a mixed radix operation in a fast Fourier transform.
Bit positions 15-19 define the type of addressing to be performed on the signal array, i.e., controls the sequences employed by the address generators 211-215.
Referring next to Figure 4A, the configuration of the system for the recursive execution of a digital signal processing algorithm is shown. The signal array to be processed is entered into memory unit B 41, i.e., the DATA IN signals are applied to memory unite B under control of the control apparatus 20. The signa array, once stored in memory unit B 41, is thereafter applied to the digital signal processing device 40 in response to address signals ADRB provided by the RAS address . .: :. ::, : . ,~ :, :: , .

:, : ::: :~: . i:.,. - . .; ". : , 13~1838 sequencer. Signal groups from the memory unit X 42 are simultaneously applied to the digital signal processing device 40 under control of the ADRX signals from the XAS
address generator of the control apparatus 20. The signals stored in the memory unit X 42 ar~ the weighting factors (typically referre~ to as twiddle factors in reference to fast Fourier transform algorithms) in the processing execution of t:he fast Fourier transform procedures. The configuration of the digital signal processing device 40 is determined by control signals (Programmable Output Signals) from the control apparatus 20. The processed signals from the digital signal processing device 40 are applied to memory unit C 43 under control of the ADRC signals from the WAS write address generator of contrGl apparatus 20. Control signals from the control apparatus 20 are applied to the digital signal processing device for controlling the implementation of the processing procedures. The bus 401 of the digital signal processing unit 40 controllably couples the input ports of the digital signal processing unit to the output ports in the preferred embodiment.
Referring to Fig. 4B, the configuration of the system for recursive digital signal processing is illustrated. The system is similar to Fig. 4A except that the array signals being applied to the digital signal processing device 40 are stored in the memory unit C 43, e.g., after being processed by the ccnfiguration shown in Fig. 4A. The (intermediate) array signals are applied to an input port of the digital signal processing device 40, which functions as an input port in the operation described in Fig. 4A, under control of the ADRC address signals generated by the RAS signal generator of control apparatus 20. The - 35 output signal from the digital signal processing device 40 are applied through an input port under control of the ADRB address signals generated by the WAS address generator of control apparatus 20. The ability to - -. ~ -::: : :, ,,: , .
. . . .

~'32~3~
reverse the flow of the recursive processing of signal arrays is the result of the apparatus in the digital signal processing device to control the function of the normally designated input port and output port. At the end of the processing operation, the processed data signals are extracted from memory unit C 43.
Referring next to Fig. 4C, the system configuration of Fig. 4A and Fig. 4B have been consolidated in a single Figure and the memory unit A 45 and memory unit D
44 added. The execution of digital signal processing algorithm in a recursive manner is accomplished between the memory unit B, for which the ADRB address signals re provided alternatively by the RAS and the WAS address generator, and memory unit C, for which the ADRC address signals are provided by the WAS and the RAS address generator. The digital signals are exchanged between memory unit B 41 and memory unit C 43 and are processed by the digital signal processing device 40 under control -~ of the control apparatus 20 to implement a predetermined algorithm. The processing typically includes combining the signal groups in the memory units with signal groups from memory unit X, the data in memory unit X being determined by ADRX address signals from the XAS address generator. The additional memory unit A 45, in response to ADRA address signal provided by the IAS address generator, permit the entry of DATA IN signals even though a previous entered signal array is currently being processed. Similarly, the memory unit D 44, in response to ADRD address signals generated by the OAS
address generator, permits a formerly processed signal array to be extracted from the system.
Referring next to Fig. 4D, when the digital signal processing system illustrated in Fig. 4C has completed processing of the signal array stored in memory unit B
42 and memory unit C 43, then the bus multiplexer of control apparatus 20 causes the memory unit C 43 to receive ADRC address signals from the OAS address generator unit and to apply the DATA OUT signals to - :, . , . ,:. ., ,., ::,. . : .: .

~32 ~8~8 external apparatus. The memory unit B 41 receives ADRB
address signals from the IAS address generator and DATA
IN signals of the signal array to be processed are entered in memory unit B 41. Simultaneously, the signal array now stored in memory unit A 41 (as a consequence of the system configuration of Fig. 4C) is now processed by transferring the signa:L array through the digital signal processing dPvice 40 to memory ~nit D 44 in response to appropriately applied address signals from the RAS address generator and the WAS address generator.
The processing algorithm c2m therefore be executed in a recursive manner by repeated processing of signal array alternatively stored memory unit A 45 and memory unit D
44. The signal array that had been processed previously and is stored in memory unit C 43 is now applied to external apparatus through the application of OAS
address signals to the memory unit C 43. The now empty and unused memory unit B 41 can now have the IAS address signals entered therein during the processing of the current array.
Referring to Fig. 4E, the minimum system configuration is shown for processing digital signal arrays according to the present invention. In this configuration, the digital signal processing unit 40 has only memory unit A 45 associated therewith in addition to the memory unit X 43. Thus, the ADRA address signal must be provided by the IAS address generator (for entering data into the system), by the RAS address generator (for reading signal groups into the digital signal processing device), by the WAS address generator (for writing signal groups back into the memory unit A
45) and the OAS address generator (for applying processed signals to external apparatus). The presence of a single memory (in addition to the auxiliary memory) is made possible by the internal bus 401 of digital signal processing device 40, which permits processed signal groups to be applied to the input port and the bus multiplexer of control apparatus 20 which permits ': :
..

- : . , ,.:

-` 13218~8 any address signals to be applied to the memory unit.
It will be clear that the simplicity of the system is achieved at the cost of processing speed. Because the input and output signals of the digital signal processing unit pass through the same (input) port and cannot be simultaneously applied, the speed of the system will be compromised as compared to a system with at least one additional memory unit.
Referring next to Fig. 5A and 5B, the operation of a plurality of sequential or cascaded digital signal processing systems using the control apparatus of the present invention is shown. In the illustrated embodiment, three systems, system A 51, system B 52 and system C 53 are used. However, it will be clear that any number of sequential or cascaded systems can be used. Digital signal processing system A 51, B 52 and C
53 include a digital processing device 40A, 40B and 40C;
a memory unit B 41A, 41B and 41C; a memory unit X 42A, 42B, and 42C, a memory unit C 43A, 43B and 43C; and control apparatus 20A, 20B and 20C; respectively. In addition, first (in the sequence) system A 51 includes memory unit A 45A, while the final (in the sequence) system C 53 includes a memory unit D 44C. In Fig. 5A, the DATA IN signals of the signal array to be processed are entered in memory unit A 45A in response to IAS
address signals from control apparatus 20A. The previous signal array stored in memory unit B 4lA in locations determined by the RAS address signals are processed (and typically combined with weighting factors or other constants in memory unit X 42A at locàtions determined by the XAS-address signals) in digital signal processing device 40A and the resulting array is stored in memory unit C 43A at locations determined by the WAS
address signals, the RAS, XAS and WAS signals being generated in control apparatus 2OA. In system B, the previous, partially processed signal array stored in memory unit B 4lB at memory locations determined by the RAS addrless signals are processed (and typically ., ,. ' ~ ' :' ~, .

~321838 combined with wei.ghting factors or other constants in memory unit X 42B from locations determined by the XAS
address signals) in digital signal processing device 40B
and stored in memory unit C 43B, the RAS, XAS and WAS
S address signals being generated in control apparatus 2OB. In system C 53, the previous, partially processed signal array in memory unit B 4lC at memory locations determined by RAS address signals are processed (and typically combined with ~eighting factors or other constants in memory unit X ~12C from locations determined by the XAS address signals) in digital signal processing device 40C and stored in memory unit C 43C at locations determined by WAS address signals, the RAS, XAS and WAS
address signals being generated in control apparàtus 20C. In addition, the signal array stored in memory unit D 44C are removed from the system C 53 as DATA OUR
signals under control of the OAS address signals from control apparatus 20C. After completion of the - processing by the systems A 51, B 52 and C 53, the configuration of the sequential systems is changed as shown in Fig. 5B. In system A 51, the DATA IN signals are stored in memory unit 41A at locations determined by IAS address signals from control apparatus 20A, memory unit B 41A being available after completion of the processing of the array previously stored therein. The signal array in memory unit A 45A is applied to the digital processing unit 40A in response to RAS address signals from control apparatus 20A. The digital signal processing unit 40A processes the applied signal array in response to control signals from control apparatus 20A, the processing including use of signal groups in memory unit X 42A in response to control apparatus 2OA
XAS address signals with preselected instructions, and stores the processed signal array in memory unit B 4lB
at locations determined by the WAS address signals generated by control apparatus 2OB. The signal array stored in memory unit C 43A is applied to digital signal processing unit 40B in response to RAS address signals .

- , : , . .: :, - ~ ,.. ~ ,.- ,~ , . , ~21838 generated in control apparatus 2OA. The applied signal array is processed in digital signal processing device 40B in response to control signals from control apparatus 20B, the processing including use of signal groups in memory unit X 42:B in response to XAS address generated in control apparatus 20B, and applied to memory unit B 41C in repone to WAS address signals generated by control appariatus 20C. The signal array stored in memory unit C 43B is applied to digital signal processing unit 40C in response to address signals generated in control apparatus 2OB. The signal array is processed by digital signal processing unit 40C in response to control signals from control apparatus 20C, the processing including use of signal groups in memory unit X 42C in response to control apparatus 20C XAS
address signals, and stores the processed signals in memory unit D 45C in response to WAS address signals from control apparatus 20C. The signal array stored in memory unit C 44C is transferred from system C 52 in response to OAS address signal from control apparatus 20C. A SYNC (END OF PASS) signal and a GO (~EGINNING OF
PASS) signal are provided by control apparatus A, B and C to synchronize signal transfer among the processing units.
Referring next to Fig. 6A, the factors contributing to the latency of the digital signal processing of the present invention is illustrated. The RAS address signals, generated in the control apparatus can be of such a frequency that to insure accuracy of the addressing of memory unit B 41, an address latch 412 is inserted in the address signal path. Similarly, the XAS
address signals are applied to a latch circuit 422 before being applied to memory unit X 42. The data signals at the address identified by the RAS address signals stored in latch circuit 412 are temporarily stored in data latch circuit 411 prior to being applied to digital signal processing device 40 and the data signals stored in the location determined by the XAS

,, " ~

.~3~83~
address signals stored in address latch 422 are temporarily stored in data latch 421 prior to being entered in the digital signal processing device 40.
Once the data signals are applied to digital processing unit 40, the digital signal processing device causes a delay in the propagation of signals. The delay is illustrated in Fig. 6A by l~ltch #1 491 through latch #n 499. The latches 491-499 can be a representation of the various stages of a pipeline implement digital signal processing device. After the signals are processed by the digital signal processing deviGe 40, the output signals are temporarily stored in data latch circuit 431. The output signal are then stored in memory unit C 43 in a location determined by the WAS
address signals stored in address latch 432, the WAS
address signals having been generated by control apparatus 20. In this configuration, each latch circuit typically result in a one system clock cycle delay of the signal propagated therethrough. Similarly, the extraction of data signals from a memory unit typically requires one clock cycle. Thus, after RAS address signals are generated in the control apparatus 20, the data cycles are applied to the digital signal processing unit 40 delayed by two system clock cycles. Similarly, the delay between the generation of the XAS address signals and the application of the data signals identified by these address signals is also two system clock cycles. The digital signal processing unit has delay, the delay typically determined by the processing operations that the device is -re~uired to perform. In the preferred embodiment, the digital signal processing unit is designed such that a four system clock cycle delay separates the application of the data signals to the input port and the application of the processed data signals to the output port of the digital signal processing unit. The output signal are delayed one system clock cycle prior to being applied to the memory unit C 43. The WAS address signals are delay~d one ~l3~1838 system clock cycle prior to applying the address signals to memory unit C determining the memory location into which the data signals are stored.
In Fig. 6B, the effects of the delays of the apparatus, resulting in latency, are shown. The system latency for the digital signal processing device and associated apparatus begins when instruction register causes the RAS and the XAS signals to be generated and ends when the data signals are applied to the memory lo unit (C). The latency of the system includes the time periods for the data signals to be processed in the digital signal processing device. In the illustrated embodiment, the delay in providing the data signals from the memory unit B and from memory unit X are equal.
While this is not requirement, the equality of these delays is typically employed for design simplification.
The system latency is used to ensure that the storage of the processed data signals is synchronized with the application of the unprocessed data signals to the digital signal processing device. Control apparatus automatically compensates for these delays, permitting a user to enter appropriate configuration signals into a control register.
Referring next to Fig. 7, the process of digital filtering in the frequency domain employing the digital signal processing system of the present invention is illustrated. In process 71, the DATA IN signals are stored so that an overlap of sequential data arrays is achieved. In step 72, window data is combined with the array data in a multiply operation. Using stored weighting factors, a fast Fourier transform is performed resulting in an array of signals in the frequency domain in step 73. In step 74, the stored frequency response of the filter is combined with the frequency domain array signals. Using the stored weighting factors, the inverse fast Fourier transform in performed on the signal array transforming the array into a time domain signal array in step 75. The signals of the array that 1~2~83~

were the result of the array overlap are deleted in step 76, resulting in the DATA OUT.
In the process illustrated in Fig. 7 and in similar processes, the lengthy sequence is divided up into segments of data, referred herein to arrays of data.
The arrays of data are constrained to overlap as illustrated in Fig. 8, to minimize the effects of processing a long series of signals as a shorter series of signals. The portions of the arrays that overlap are discarded after processing and are not included among the DATA OUT signals.
Referring next to Figure 9, the use of the apparatus of the present invention to execute, in a recursive manner, the procedure illustrated in Fig. 7 is shown. The digital signal processing device performs the processing functions under control of the control apparatus 20. As in the configuration illustrated in Fig. 4C and 4D, the recursive configuration includes two memory units A and B, 45 and 41 coupled to the input port of the digital signal processing device 40 while two memory units C and D, 43 and 44, are coupled to the output port of the digital signal processing device 40.
In addition, an overlap memory unit A 455 is associated with memory unit A 45 and an overlap memory unit B 415 is associated with memory unit B. Also, memory unit X
(window) 425 and memory unit X (filter parameters) 426 have been added in addition to memory unit X to provide extended sets of numerical values to be used during the processing of the array and filter data. The additional input memory units 455 and 415 provide for the storage of signals of the arrays that are to be used in the overlap computation. By appropriate addressing of the input memory unit arrays, the overlap signals can be combined with the next sequential array and processed therewith. Similarly, by appropriate addressing of the output signals, the overlap processed signals can be eliminated. The amount of the overlap is stored in the overlap register 223 of Fig. 2 which controls the :- : . :: - , . . . ..

~ 32~8~8 addressing for the signal arrays with overlap signals and the elimination of the overlap processed signals.
2. Operation of the Preferred Embodiment The present invention provides for flexible control of a digital signal processing device. In the preferred embodiment, the digital signal processing unit can be configured into performing a radix-4 fast Fourier transform on for applied complex signal groups, a radix-2 fast Fourier transform on two sets of two applied complex signal groups, a fast Fourier transform of N
complex signal groups to provide 2N real signal groups, and fast Fourier transform of N complex signal groups into N real signal groups. In addition, the digital signal processing device of the preferred embodiment can execute a mixed radix-4/radix-~ procedure and can perform a multiplicity of arithmetic and logical operations on applied complex signal groups.
The separation of the processing and control functions in the implementation of the digital processing apparatus permits flexibility in the resulting digital signal processing system. In this manner, the digital processing device used in the system can be redesigned to meet different or unforeseen processing procedures -without disrupting the programs that control the operation of the control apparatus.
Similarly, in the event of an unforeseen control requirement wherein the processing algorithm is unchanged, only the control apparatus need be redesigned. The address generating apparatus; IAS, RAS, XAS, WAS and OAS; are implemented by sequencing apparatus in the preferred embodiment. For the fast Fourier transform operations, the only variable of significance is the signal group array size. Of course, the size of the signal group array determines the weighting factors used in a transformation. Because this quantity is known and is in fact stored in a register in the present invention, then the addressing sequences can be fixed (hardwired) in the control ~ 3~838 apparatus. For the pr~cessing of arrays of signals, the data groups to be processed have periodic addresses in the array, a characteristic that lends itself to the use of address sequencers to address the array. The periodicity and the size of the array are sufficient to specify the sequence for typical signal array processing. As is well known to those familiar with the processing of digital signal arrays, especially the fast Fourier transform, the output signal group having the lo sequential position as the input signal group can correspond to a different address. This different address can be accommodated by a procedure referred to as digit reversing in which groups of logic signal representing the address can be reversed to provide the correct sequential address.
Referring again to Fig. 3, the bit position 14 of the control apparatus instruction format designates a mixed radix algorithm. In the fast Fourier transform algorithms, the radix-2 butterfly procedure operates on an array of 2N members. The radix-4 butterfly procedure operates on an array of 4M members. However, the radix-4 butterfly procedures require fewer computations (M~
and are therefore the preferred procedures in the fast Fourier transforms. Therefore, when the array is of such a size that the array can be decomposed into an even plurality of radix-4 arrays, the mixed radix algorithm provides for the entire array to processed, first, by using the radix-2 procedure. Then each of the radix-4 arrays comprising the initial array are processed using the radix-4 procedures.
The flexibility imparted to the digital system processing system by incorporation of bus multiplexer 204 of control apparatus 20 is illustrated in Figs. 4A-4E and 5A-5B. The bus multiplexer 204 permits the function of the memory units to be changed in response to instructions placed in control apparatus 20. Thus, for example, during the execution of a recursive algorithm, the configuration of the bus multiplexer 204 . . : :- . :: ..................... - .
~- '' ;., - ;, ,, .,: .

13~1838 determines whether a memory unit is entering a signal array into the digital processing unit or receiving signals from the digital signal processing unit. In the cascaded or sequential coupling of systems, the address signals control the entry from and to adjacent systems.
In the preferred embodiment:, the system clock signal, CLKIN, has associated therewith a periodic synchroni~ation signal which can be used to synchronize operation between the plurality of digital signal lo processing systems. The CLKIN signal also has GO
control signal which is used to produce the FND OF PASS
and BEGINNING OF PASS control signals. As suggested by the name, the BEGINNING OF PASS indicates the beginning of the processing of a signal array by the associated digital signal processing device and is used as a SYNC
signal. Similarly, the END OF PASS signal designates the completion of application of a signal array to the associated digital signal processing unit. By applying a single GO control signal to the plurality of digital signal processing systems, the control apparatus of the associated digital signal processing system can initiate activity in a timely manner.
The us of the present invention in a recursive mode of operation is illustrated in Figs. 4A-4B and in a cascaded or sequential mode of operation is illustrated in Figs. 5A and 5B. It will be clear that these two modes of operation are not exclusive, but can be combined in appropriate situations. Any system in the sequence can perform a plurality of operations prior to transferring the signal groups to the next sequential system.
The foregoing description is included to illustrate the operation of the preferred embodiment and is not meant to limit the scope of the invention. The scope of the invention is to be limited only by the following claims. From the foregoing description, many variations will be apparent to those skilled in the art that would ~32~38 yet be encompassed by the spirit and scope of the invention.

Claims (20)

1. An apparatus for controlling a digital signal processing device that is capable of performing a fast-Fourier transform (FFT) on a signal array and a plurality of memory units associated with the digital signal processing device where at least one of the memory units is capable of storing a signal array, comprising:
first means for determining which of a plurality of FFT address sequences should be generated and applied to the plurality of memory units in order for the digital signal processing device to achieve a digital signal processing function, said first means including means for processing a plurality of instructions, a first memory for storing said plurality of instructions, and a second memory for storing a delay associated with transferring information between the digital signal processing device and the memory units and with the processing of a signal arrayby the digital signal processing device, wherein the contents of said second memory can be altered to accommodate configurations of the digital signal processing device and the plurality of memory units that have a different delay;and second means, responsive to said first means, for generating the addresses of locations in the memory units that are necessary to accomplish the digital signal processing function and applying the addresses to the memory units.

2. An apparatus, as claimed in claim 1, wherein:
each instruction, when processed by said first means, results in more than one element of a signal array being processed by the digital signal processing device.

3. An apparatus, as claimed in claim 1, wherein:
each instruction, when processed by said first means, results in all of the elements of a signal array being processed by the digital signal processing device.

4. An apparatus, as claimed in claim 1, wherein:

said means for processing includes a vector processor.

5. An apparatus, as claimed in claim 1, wherein:
said plurality of instructions remaining in the same locations in said first memory during the processing of a signal array.

6. An apparatus, as claimed in claim 1, wherein:
said first means includes means for bypassing said first memory to provide an instruction that is external to said first memory.

7. An apparatus, as claimed in claim 1, wherein:
said first means includes a third memory for storing the amount that adjacent signal arrays to be processed by the digital signal processing device overlap, wherein the contents of said third memory can be altered to accommodate digital signal processing applications that require different amounts of signal array overlap.

8. An apparatus, as claimed in claim 7, wherein:
the amount of overlap allows said first means to generate the addresses necessary to discard the portions of the signal array output by the digital signal processing device that overlap.

9. An apparatus, as claimed in claim 1, wherein:
said first means includes a fourth memory for storing the size of the signal array to be processed by the digital signal processing device, wherein the contents of said fourth memory can be altered to accommodate digital signal processing applications that require signal arrays of different sizes to be processed.

10. An apparatus, as claimed in claim 1, wherein:
said first means includes means for coordinating the operation of the apparatus with the operation of another apparatus that is associated with another digital signal processing device and associated memory units.

11. An apparatus, as claimed in claim 1, wherein:
at least one of the instructions capable of being processed by said means for processing includes a FFT of N complex-points into two separate N real-pointFFTs.

12. An apparatus, as claimed in claim 1, wherein:
at least one of said plurality of instructions capable of being processed by said means for processing includes one of the following functions:
a mixed radix and a FFT of N complex-points into a FFT of 2N
real-points.

13. An apparatus, as claimed in claim 1, wherein:
said second means includes a plurality of address generators, wherein each of said plurality of address generators produces the addresses for one of the memory units.

14. An apparatus, as claimed in claim 13, wherein:
said second means includes a multiplexer for use in selecting which memory unit each of said plurality of address generators provides with addresses.

15. An apparatus, as claimed in claim 1 wherein:
said second means includes a first address generator for producing the addresses of the memory unit that receives a signal array to be processed by thedigital signal processing device in the future, a second address generator for simultaneously producing the addresses for the memory unit that provides the digital signal processing device with a signal array for processing, a third address generator for simultaneously producing the addresses of the memory unit that receives the signal array processed by the digital signal processing device, anda fourth address generator for simultaneously producing the addresses for the memory unit that outputs a signal array previously processed by the digital signal processing device.

16. An apparatus, as claimed in claim 1, wherein:
said second means includes hardwired means for use in generating the addresses.

17. An apparatus, as claimed in claim 1, wherein:
said second means includes a third means for selecting which memory units receive the addresses generated by said second means.

18. An apparatus, as claimed in claim 1, wherein:
said first means and said second means are fabricated on a single semiconductor substrate.

19. A method for adaptively controlling a digital signal processing device that is capable of performing a fast-Fourier transform (FFT) digital signal processing function on a signal array and a plurality of memory units, wherein at least oneof the plurality of memory units is capable of exchanging signal array information with the digital signal processing device, comprising:
providing a controller for determining which of a plurality of address sequences should be generated and applied to the plurality of memory units;
combining a plurality of digital signal processing instructions to produce a first program;
transmitting said program to said controller;
storing said program in said controller;
determining the delay associated with both transferring information between one of the memory units and the digital signal processing device and with the digital signal processing device in processing a signal array;
transmitting the delay to said controller;
storing the delay in said controller;
executing said program, wherein said controller produces the address sequences required by said plurality of digital signal processing instructions and the delay;
performing at least one of the following actions:
reconfiguring said digital signal processing device and said plurality of memory units into a configuration having a different delay;
and combining a plurality of digital signal processing instructions to produce a second program redetermining, according to said step of performing, said different delay;
transmitting, according to said step of performing, at least one of said different delay and said second program to said controller and storing same in said controller;
and executing one of the following:
said first program and said second program, wherein said controller produces the address sequences required by the plurality of digital signal processing instructions and the delay.

20. A method, as claimed in claim 19, further including:
determining the amount of overlap of adjacent signal arrays to be processed by the digital signal processing device;
transmitting the overlap to said controller;
storing the overlap in said controller;
and repeating said steps of determining the amount of overlap, transmitting the overlap, and storing the overlap when the overlap changes.