CA1324684C - Variable length data processing apparatus - Google Patents
Variable length data processing apparatusInfo
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- CA1324684C CA1324684C CA000604840A CA604840A CA1324684C CA 1324684 C CA1324684 C CA 1324684C CA 000604840 A CA000604840 A CA 000604840A CA 604840 A CA604840 A CA 604840A CA 1324684 C CA1324684 C CA 1324684C
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- 238000012545 processing Methods 0.000 title claims description 34
- 238000001514 detection method Methods 0.000 claims description 17
- 230000004044 response Effects 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 description 7
- 101150089655 Ins2 gene Proteins 0.000 description 5
- 101100072652 Xenopus laevis ins-b gene Proteins 0.000 description 5
- 230000000875 corresponding effect Effects 0.000 description 5
- 101100179596 Caenorhabditis elegans ins-3 gene Proteins 0.000 description 4
- 238000013500 data storage Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002674 ointment Substances 0.000 description 1
- 235000012976 tarts Nutrition 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/04—Addressing variable-length words or parts of words
Abstract
Abstract of the Disclosure Variable length data stored in a RAM are sequen-tially read out by designating their addresses. It is detected whether or not the readout data is a code indi-cating a delimitation of, e.g., a word block, record block, file block, or the like. If it is detected that the readout data is a code indicating a delimitation, an address at that time is latched, thus forming an address table based on the latched address. The address table thus formed is utilized upon retrieval of data in the RAM, thus allowing high-speed data access.
Description
The present inventlon relates to an apparatus for processing variable length data ln which words, records, flles, and the like are dellmited by delimiter codes.
When data processing is performed in a variable length data format, processed variable length data are delimited by word and record delimiter codes in units of words and records, and are sequentially arrayed and stored on a memory. When processing is performed for the variable length data string arrayed and stored on the memory, the variable length data string is sequen-tially read out from the memory and the word and record delimiter codes are retrieved. For example, when a second word in each record in the memory is extracted to perform updating processing, a record dellmlter code in the memory is retrieved, and a flrst word dellmlter code from the retrieved record dellmlter code ls retrieved to extract the second word (because the second word is arrayed to follow the flrst word). In order to extract the second word ln each record, the above retrleval processlng must be repetitlvely executed.
In this manner, ln the conventional system, every tlme processlng ls performed for the varlable length data strlng whlch ls dellmited by various dellmlter data such as dellmlter codes, the above-mentioned retrieval processing must be executed, resultlng in a time-consuming operatlon.
This also applles to a case whereln a word to be processed ln each record is predetermined, e.g., a varl-able word ls a second word and other words are flxed words. The retrleval processlng must be executed every time processing for the word to be processed ls performed.
It is an object of the present lnvention to provlde a variable length data processing apparatus wherein a table is formed based on addresses of delimiter codes of variable length data stored in a memory, and is referred to upon data access to allow high-speed access of corre-sponding variable length data.
In order to achieve the above ob~ect, according to the present lnvention, there is provided a data process-lng apparatus whlch accesses storage means storlng vari-able length data dellmlted by dellmiter codes to perform data processlng, comprising:
controlling means, connected to sald storage means through an address bus, for deslgnating an address through said address bus every time one clock is generated, reading out data stored at the designated address onto a data bus, and incrementing the address every time the data is read out;
detecting means, connected to said data bus, for detecting in response to every clock whether or not the data on said data bus coincldes with the delimiter code .
, :
indicating a delimitation of a data block;
latching means, connected to said address bus, for, when said detecting means detects a colncldence, latch-lng the address on said address bus;
table means for storing address data based on the address latched in said latching means; and processing means for designating a start address of each data block stored in said storage means with refer-ence to the address data stored in said table means and performing processing for each data block.
According to the present invention, a table based on addresses indicating dslimiter positions of variable length data stored ln a memory can be easlly formed.
When deslred data ln the memory ls read out and pro-cessing, e.g., updating of the readout data ls to be performed, hlgh-speed access can be performed by utlllz-lng the table.
Thls lnvention can be more fully understood from the following detailed description when taken in con~unction with the accompanylng drawings, in which:
Flg. 1 is a block dlagram for explalning an embodi-ment of the present lnventlon;
Flg. 2 ls a vlew showlng a flrst example of an address table:
Flgs. 3A through 3H show first timing charts;
Flg. 4 ls a vlew showing a second example of the address table;
Figs. 5A through 5F show second timing charts; and Fig. 6 is a view showing a third example of the address table.
s Fig. 1 is a block diagram of a variable length data processing apparatus according to an embodiment of the present invention.
The variable length data processing apparatus pro-cesses variable length data in whlch words and records are delimited by delimiter codes. The apparatus pro-cesses varlable length data stored in a RAM 3 in accor-dance wlth a program prestored in a ROM 2 under the control of a CPU 1. The RAM 3 is connected to the CPU 1 and the ROM 2 through an address bus AB and a data bus DB. The address bus AB and the data bus DB are con-nected to a magnetic disk 4 for storing a large volume of varlable length data and a DMA controller 5 for directly transferring a portion of the varlable length data stored ln the magnetlc dlsk 4.
The address bus AB and the data bus DB are also connected to a dellmlter detectlon unlt 6. The dell-mlter detectlon unlt 6 detects varlous dellmiter codes, l.e., a dellmlter code "," lndlcatlng a dellmltatlon of a word, a delimlter cnde "(" lndlcatlng a dellmltatlon of a record, a dellmlter code " " a dellmitatlon of a flle, and the llke, on the data bus DB, reads out an address ln the RAM 3 in whlch the detected dellmlter code is store~, and performs varlous processlng opera-tions such as creation of an address table based on the readout address under the control of a controller 61.
The delimiter detection unit 6 includes an address gen-erator 62 and an address latch circuit 63 which are con-nected to both the data bus DB and the address bus AB, and a designated field register 64, an instruction code register 65, a delimiter type register 66, a read buffer 67, and a detector 68 which are connected to the data bus DB. The designated fleld reglster 64 is connected to a comparator 69. The comparator 69 is connected to a counter 70. The instructlon code register 65 is con-nected to an instruction decoder 71. A decoded output from the lnstructlon decoder is supplied to the control-ler 61.
The circuits of the delimiter detection unit 6 willbe described below in detail.The address generator 62 has a read address regis-ter RA and a write address register WA. Upon reception of a start signal S2 from the controller 61, the gener-ator 62 starts a cyclic operation consisting of a read cycle and a write cycle on the basis of a clock slgnal generated by a clock generator ~not shown). In the read cycle, the generator 62 outputs the content of the read address reglster RA onto the address bus AB. Upon com-pletion of the read cycle, the generator 62 increments the content of the read address register by "1". when .
the generator 62 receives a latch completion slgnal S8 from the controller 61, it outputs the content of the wrlte address register WA onto the address bus AB, and increments the content of the write address reglster WA
by "1" after the lapse of a predetermined period of time from the outputting.
Upon reception of an address latch slgnal S6 from the controller 61, the address latch circuit 63 fetches the address data present on the address bus AB at that time, increments the data by "1", and outputs it onto the data bus DB.
The designated field register 64 stores data indi-cating the order of words to be designated on one record. When this data is supplied to the comparator 69, lt ls decremented by "1" and is compared with the content of the counter 70.
The lnstructlon code reglster 65 stores an instruc-tlon code determlnlng the operation of the dellmiter detectlon unlt 6. The reglster 65 causes the instruc-tlon decoder 71 to decode a table formatlon lnstructioncode INSl, a speclflc fleld table formatlon lnstructlon code INS2, a data transfer instructlon code INS3, or the llke ln accordance wlth the lnstructlon code, thus determlnlng the control operatlon of the controller 61.
The dellmlter codes ",", "(", " ", and the llke are preset ln the dellmlter type reglster 66, and are supplied to the detector 68. The detector 68 is a cir-cuit for detecting whether or not the content of the read buffer 67 for temporarlly storlng data read out from the RAM 3 onto the data bus DB coincides with any one of the delimiter codes preset in the delimiter type register 66. When a coincldence is detected, the detec-tor outputs a detection signal of the corresponding delimiter code to the controller 61. When a noncoinci-dence is detected, the detector outputs no detection lo signal.
The controller 61 performs a control operation in accordance with the instruction code set in the instruc-tion code register 65. For example, when the specific field table formation instructlon code INS2 is set ln the instructlon code register 65, the controller 61 per-forms slgnal I/O control as follows.
(l) when the controller 61 receives a processing start slgnal Sl from the CPU 1, it outputs a start slg-nal S2 to the address generator 62.
When data processing is performed in a variable length data format, processed variable length data are delimited by word and record delimiter codes in units of words and records, and are sequentially arrayed and stored on a memory. When processing is performed for the variable length data string arrayed and stored on the memory, the variable length data string is sequen-tially read out from the memory and the word and record delimiter codes are retrieved. For example, when a second word in each record in the memory is extracted to perform updating processing, a record dellmlter code in the memory is retrieved, and a flrst word dellmlter code from the retrieved record dellmlter code ls retrieved to extract the second word (because the second word is arrayed to follow the flrst word). In order to extract the second word ln each record, the above retrleval processlng must be repetitlvely executed.
In this manner, ln the conventional system, every tlme processlng ls performed for the varlable length data strlng whlch ls dellmited by various dellmlter data such as dellmlter codes, the above-mentioned retrieval processing must be executed, resultlng in a time-consuming operatlon.
This also applles to a case whereln a word to be processed ln each record is predetermined, e.g., a varl-able word ls a second word and other words are flxed words. The retrleval processlng must be executed every time processing for the word to be processed ls performed.
It is an object of the present lnvention to provlde a variable length data processing apparatus wherein a table is formed based on addresses of delimiter codes of variable length data stored in a memory, and is referred to upon data access to allow high-speed access of corre-sponding variable length data.
In order to achieve the above ob~ect, according to the present lnvention, there is provided a data process-lng apparatus whlch accesses storage means storlng vari-able length data dellmlted by dellmiter codes to perform data processlng, comprising:
controlling means, connected to sald storage means through an address bus, for deslgnating an address through said address bus every time one clock is generated, reading out data stored at the designated address onto a data bus, and incrementing the address every time the data is read out;
detecting means, connected to said data bus, for detecting in response to every clock whether or not the data on said data bus coincldes with the delimiter code .
, :
indicating a delimitation of a data block;
latching means, connected to said address bus, for, when said detecting means detects a colncldence, latch-lng the address on said address bus;
table means for storing address data based on the address latched in said latching means; and processing means for designating a start address of each data block stored in said storage means with refer-ence to the address data stored in said table means and performing processing for each data block.
According to the present invention, a table based on addresses indicating dslimiter positions of variable length data stored ln a memory can be easlly formed.
When deslred data ln the memory ls read out and pro-cessing, e.g., updating of the readout data ls to be performed, hlgh-speed access can be performed by utlllz-lng the table.
Thls lnvention can be more fully understood from the following detailed description when taken in con~unction with the accompanylng drawings, in which:
Flg. 1 is a block dlagram for explalning an embodi-ment of the present lnventlon;
Flg. 2 ls a vlew showlng a flrst example of an address table:
Flgs. 3A through 3H show first timing charts;
Flg. 4 ls a vlew showing a second example of the address table;
Figs. 5A through 5F show second timing charts; and Fig. 6 is a view showing a third example of the address table.
s Fig. 1 is a block diagram of a variable length data processing apparatus according to an embodiment of the present invention.
The variable length data processing apparatus pro-cesses variable length data in whlch words and records are delimited by delimiter codes. The apparatus pro-cesses varlable length data stored in a RAM 3 in accor-dance wlth a program prestored in a ROM 2 under the control of a CPU 1. The RAM 3 is connected to the CPU 1 and the ROM 2 through an address bus AB and a data bus DB. The address bus AB and the data bus DB are con-nected to a magnetic disk 4 for storing a large volume of varlable length data and a DMA controller 5 for directly transferring a portion of the varlable length data stored ln the magnetlc dlsk 4.
The address bus AB and the data bus DB are also connected to a dellmlter detectlon unlt 6. The dell-mlter detectlon unlt 6 detects varlous dellmiter codes, l.e., a dellmlter code "," lndlcatlng a dellmltatlon of a word, a delimlter cnde "(" lndlcatlng a dellmltatlon of a record, a dellmlter code " " a dellmitatlon of a flle, and the llke, on the data bus DB, reads out an address ln the RAM 3 in whlch the detected dellmlter code is store~, and performs varlous processlng opera-tions such as creation of an address table based on the readout address under the control of a controller 61.
The delimiter detection unit 6 includes an address gen-erator 62 and an address latch circuit 63 which are con-nected to both the data bus DB and the address bus AB, and a designated field register 64, an instruction code register 65, a delimiter type register 66, a read buffer 67, and a detector 68 which are connected to the data bus DB. The designated fleld reglster 64 is connected to a comparator 69. The comparator 69 is connected to a counter 70. The instructlon code register 65 is con-nected to an instruction decoder 71. A decoded output from the lnstructlon decoder is supplied to the control-ler 61.
The circuits of the delimiter detection unit 6 willbe described below in detail.The address generator 62 has a read address regis-ter RA and a write address register WA. Upon reception of a start signal S2 from the controller 61, the gener-ator 62 starts a cyclic operation consisting of a read cycle and a write cycle on the basis of a clock slgnal generated by a clock generator ~not shown). In the read cycle, the generator 62 outputs the content of the read address reglster RA onto the address bus AB. Upon com-pletion of the read cycle, the generator 62 increments the content of the read address register by "1". when .
the generator 62 receives a latch completion slgnal S8 from the controller 61, it outputs the content of the wrlte address register WA onto the address bus AB, and increments the content of the write address reglster WA
by "1" after the lapse of a predetermined period of time from the outputting.
Upon reception of an address latch slgnal S6 from the controller 61, the address latch circuit 63 fetches the address data present on the address bus AB at that time, increments the data by "1", and outputs it onto the data bus DB.
The designated field register 64 stores data indi-cating the order of words to be designated on one record. When this data is supplied to the comparator 69, lt ls decremented by "1" and is compared with the content of the counter 70.
The lnstructlon code reglster 65 stores an instruc-tlon code determlnlng the operation of the dellmiter detectlon unlt 6. The reglster 65 causes the instruc-tlon decoder 71 to decode a table formatlon lnstructioncode INSl, a speclflc fleld table formatlon lnstructlon code INS2, a data transfer instructlon code INS3, or the llke ln accordance wlth the lnstructlon code, thus determlnlng the control operatlon of the controller 61.
The dellmlter codes ",", "(", " ", and the llke are preset ln the dellmlter type reglster 66, and are supplied to the detector 68. The detector 68 is a cir-cuit for detecting whether or not the content of the read buffer 67 for temporarlly storlng data read out from the RAM 3 onto the data bus DB coincides with any one of the delimiter codes preset in the delimiter type register 66. When a coincldence is detected, the detec-tor outputs a detection signal of the corresponding delimiter code to the controller 61. When a noncoinci-dence is detected, the detector outputs no detection lo signal.
The controller 61 performs a control operation in accordance with the instruction code set in the instruc-tion code register 65. For example, when the specific field table formation instructlon code INS2 is set ln the instructlon code register 65, the controller 61 per-forms slgnal I/O control as follows.
(l) when the controller 61 receives a processing start slgnal Sl from the CPU 1, it outputs a start slg-nal S2 to the address generator 62.
(2) When the controller 61 receives the delimiter code "(" indicating a record delimitation from the detector 68, it outputs a reset signal S3 to the counter 70.
(3) When the controller 61 receives the dellmlter code "," lndlcatlng a word dellmitation from the detec-tor 68, lt outputs a comparlson slgnal S4 to the comparator 69, and, after the lapse of a predetermined period of time, outputs a count-up slgnal S7 to the counter 70.
(4) When the controller 61 recelves the dellmlter code " ~' lndicating a file delimltation from the detec-tor 68, it outputs a processlng end signal S9 to the CPU1.
(5) When the controller 61 receives a colncidence signal S5 from the comparator 69, it outputs a latch signal S6 to the address latch circuit 63, and then outputs a latch completion slgnal S8 to the address generator 62.
When the data transfer instruction code INS3 is set in the instruction code register 65, the controller 61 performs slgnal I/O control as follows.
(1) When the controller 61 receives a processing start signal Sl from the CPU 1, lt outputs a start slg-nal S10 to the DMA controller 5.
(2) When the controller 61 recelves the dellmiter code "(" or "," indlcating a record or word dellmi-tatlon from the detector 6a, lt outputs a latchsignal S6 to the address latch clrcult 63, and then outputs an lnterruptlon slgnal Sll to the DMA con-troller 5.
(3) When the controller 61 recelves the dellmlter code " " lndicatlng a flle dellmitatlon from the detec-tor 68, lt outputs an end slgnal S14 to the DMA con-troller 5, and outputs a processlng end slgnal S9 to . -! `, ..
-` 1 324684 the CPU 1.
(4) When the controller 61 receives an lnterrupted signal S12 from the DMA controller 5, lt outputs a lat~h complation signal S8 to the address generator 62, and then outputs an interruption completion signal S13 to the DMA controller 5.
The DMA controller 5 will now be described.
The DMA controller 5 has an address counter AC.
When the controller 5 receives the start signal S10 from the controller 61, it starts a data transfer operation on the basis of a clock signal from a clock generator (not shown). The controller 5 reads out unit data from the magnetic disk 4 onto the data bus DB, and outputs the content of the address counter AC onto the address bus AB to deslgnate an address of the RAM 3. Then, the controller 5 transfers the unit data on the data bus DB
to the deslgnated address position in the RAM 3. The controller 5 repeats this operation in response to every clock signal, so that each unit data in the magnetic disk 4 is transferred to the RAM 3 at high speed. The address counter AC is incremented by "1" every time the unit data ls transferred. When the DMA controller 5 receives the interruption signal Sll from the controller 61, it lnterrupts the data transfer operation (stops a clock operation)~ and then sends the interrupted signal S12 to the controller 61. Upon reception of the inter-ruption completlon slgnal S13 from the controller 61, . .~.
the DMA controller 5 restarts the interrupted data transfer operation. Upon reception of an end slgnal S14, the controller 5 ends a series of data transfer operatlons.
The operation of the embodlment of the present lnvention will be described hereinafter.
A case will be described below wherein an address table of designated words is formed, e.g., wherein the address table of second words in records is formed, as shown in Flg. 2.
Fig. 2 shows a case wherein the start address of a second word of each record stored in an area starting from address ~1" in the RAM 3 is written in a table area of the RAM 3, i.e., a table area starting from address "lO0", thereby forming an address table. Since the start address of the second word of the first record is "5", the address "5" data is written at address "100".
Since the start address of the second word of the second record ls "16n, the address "16" data ls written at address "101". Slnce the start address of the second word of the third record is "2s", the address ll25ll data ls wrltten at address "102". Slmllarly, the start addresses of the second words of the followlng records are wrltten ln an area after address "103", thus formlng the address table.
In thls manner, when the address table of the deslgnated words ls formed, lf an lnstruction for adding all the second words of the records ls lnput, the addresses of the second words of the records can be dlrectly detected wlth reference to thls address table, and an access speed can be lncreased. There-fore, word addltlon processing can be performed athlgh speed.
An operation for formlng the address table shown in Fig. 2 using the block circuit shown in Fig. 1 will be described in detail below with reference to the timing chart shown in Fig. 3.
Various registers are initiallzed prior to address table formatlon processlng. More speclflcally, the CPU
1 sets data "1" and ~'100" as initial values in the read address register RA and the write address register WA, and sets data "2" in the designated field register 64.
The CPU 1 then sets the delimiter codes '',ll, ''(ll~ and n 1l in the delimiter type register 66, and sets the specific field table formation instruction code INS2 in the instructlon code register 65.
After these settlng operations, the CPU 1 outputs the processlng start signal Sl to the controller 61, and transfers all the control to the controller 61.
Upon reception of the processing start signal Sl from the CPU 1, the controller 61 outputs the start signal S2 to the address generator 62. More specifi-cally, the address generator 62 outputs address data stored in the read address register RA onto the address , . . .
bus AB ln a first read cycle, and reads out data stored in the corresponding address area in the RAM 3 onto the data bus Ds. The data read out onto the data bus DB is fetched ln the read buffer 67, and the detector 68 ~udges whether or not the fetched data coincides with any one of the delimiter codes set in the deli-miter type register 66. Since data stored in the address area "1" in the RAM 3 is the delimiter code lts detection signal is output to the controller 61.
When the controller 61 receives the detection signal of the delimiter code ''(ll~ it outputs the reset signal S3 to the counter 70 to reset the content of the counter 70 to "1". Slnce no address latch operatlon ls performed ln this read cycle, the address generator 62 does not output address data stored in the wrlte address reglster WA onto the address bus AB in the followlng wrlte cycle, and no write access to the RAM 3 is performed. Upon completion of the read cycle, the value of the read address reglster RA ls lncremented by "1", l.e., to "2".
Thereafter, ln the next read cycle, the content of the read address reglster RA ls output onto the address bus AB, and data, l.e., "x" stored ln the correspondlng address area ln the RAM 3 iS read out onto the data bus DB. Thls data ls fetched ln the read buffer 67. Slnce thls data ls not a dellmlter code, the detector 68 does not output a detectlon slgnal, and hence, no wrlte t 324684 access to the RAM 3 ls performed in the followlng wrlte cycle.
In the next read cyclet slnce data "x" ls output onto the data bus DB, no wrlte access to the RAM 3 ls performed, elther, in the following wrlte cycle.
In the fourth read cycle, slnce the dellmlter code "," ls output onto the data bus DB, this code is detected by the detector 68, and lts detectlon signal is output to the controller 61. Upon reception of the detectlon slgnal of the dellmlter code ",", the con-troller 61 outputs the comparlson signal S4 to the comparator 69, so that a value "1" obtained by decre-menting data "2" stored in the designated field register 64 is compared wlth a count value stored in the counter 70. In this case, slnce the data "1" is set in the counter 70, the comparator 69 detects a coincidence between the two data, and supplies the coincldence signal S5 to the controller 61. When the controller 61 recelves the coincidence signal S5, it outputs the latch slgnal S6 to the address latch circuit 63. Thus, the address latch circuit 6~ latches address data at that tlme, i.e., "4". Thereafter, the controller 61 outputs the count-up signal S7 to the counter 70 to update the value of the counter 70 to "2". The controller 61 outputs the latch completion signal S8 to the address generator 62. The address generator 62 outputs address data, i.e., "100", stored in the write address register WA onto the address bus AB to designate the correspond-ing address area in the RAM 3. In thls case, data obtained by incrementing the address data latched ln the address latch circuit 63 by "1", l.e., "5", ls supplled onto the data bus DB . The data ~5" on the data bus DB
ls stored at address ~'loo" ln the RAM 3. After the data storage operation, the address generator 62 increments the value of the write address register WA by "1".
In the fifth read cycle, since data "x" is detected on the data bus DB, a detection operation by the detec-tor 68 ls not performed, and hence, no data storage processlng ls performed ln the following write cycle.
In the sixth read cycle, since the delimiter code "," ls detected on the data bus DB, thls code ls detected by the detector 68, and its detection result ls supplied to the controller 61. Upon receptlon of thls detectlon signal, the controller 61 outputs the comparlson slgnal S4 to the comparator 69, so that a value "1" obtained by decrementing data stored in the deslgnated fleld reglster 64 by "1" ls compared wlth a count value stored ln the counter 70. In thls case, slnce the counter 70 stores data H2", the comparator 69 does not output the coincldence slgnal S5. As a result, the controller 61 does not output the latch slgnal Sfi to the address latch clrcult 63, and hence, no data storage processlng 19 performed ln the followlng wrlte cycle.
In thls read cycle, the controller 61 outputs the . .
.
count-up signal S7 to the counter 70 to update the value of the counter 70 to "3".
Simllarly, the data readout processing is sequentially performed. When the delimiter code "~" is read out onto the data bus DB in the 13th read cycle, this code is detected by the detector 68, and its detec-tion result is supplied to the controller 61. Upon reception of this detection signal, tha controller 61 outputs the reset signal S3 to the counter 70 to reset the content of the counter 70 to "1".
In the 14th read cycle, since data "x" is output onto the data bus DB~ the detector 68 does not output the detection signal.
In the 15th read cycle, the delimiter code "," is output onto the data bus DB, and this code is detected by the detector 68. The controller 61 then supplles the comparison signal S4 to the comparator 69, so that a value "1" obtained by decrementlng data stored in the deslgnated fleld register 64 by "1" is compared with a count value stored in the counter 70. In this case, slnce the counter 70 stores data "1", the comparator 69 outputs the coincldence slgnal S5, and the controller 61 outputs the latch slgnal S6 to the address latch clrcuit 63 to cause lt to latch address data at that tlme, i.e., "15". Thereafter, the controller 61 outputs the count-up signal S7 to the counter 70, and outputs the latch completlon slgnal S8 to the address generator 62. The address generator 62 outputs address data, l.e., "101"
stored ln the write address reglster WA onto the address bus As in the following wrlte cycle. In thls case, data obtained by incrementing the address data latched ln the address latch clrcuit 63 by "1", i.e., data "16" ls sup-plied onto the data bus DB. Thls data "16" ls stored at address "101" ln the RAM 3.
In this manner, the data stored in the RAM 3 are sequentially read out, and are sub~ected to delimiter detection in the detector 68. If the dellmiter code indicating the record delimitation is detected, the counter 70 is detected. If the dellmiter code 'l,ll indi-cating a word delimitation is detected, the comparator 69 checks if this code is a code stored immedlately before the deslgnated word in one record, l.e., a deli-miter code stored immedlately before the second word.
If it is determined that the detected code is the deli-mlter code stored immediately before the second word, the address ln the RAM 3 at which this delimlter code is stored ls latched ln the address latch circult 63.
Data obtalned by incrementing this address value by "1" is sequentially stored ln the table area in the RAM 3.
When the detector 68 detects the delimiter code " " lndicating a file dellmltatlon, the controller 61 ends the address table formation processing, and outputs the end signal S9 to the CPU 1, thus transferrlng all the control to the CPu 1.
With the series of processing operatlons descrlbed above, the start addresses of the second words of the records in a predetermined file in the RAM 3 are stored in the designated address table area in the RAM 3.
Therefore, the CPU 1 refers to the address table to directly detect the start addresses of the second words of the records in the file, and updatlng process-ing or the llke for one file can be performed at high speed.
Since the address table formation processing is performed by a special-purpose circuit, it can be per-formed at very high speed.
A case will be described below wherein an address table of words is formed simultaneously when varlable length data stored ln the magnetic disk 4 are DMA-transferred into the RAM 3.
Fig. 4 shows a case whereln varlable-length word data stored ln the magnetlc dlsk 4 are sequentlally transferred to and stored in an area starting from address "11" in the RAM 3, and at the same time, the ~tart address of the words stored in the RAM 3 in this manner are stored ln the table area in the RAM 3, i. e., in an area starting from address "100", thus forming an address table. Slnce the start addresses of the words are "12", "15", ~17", "21~, "24", "26",..., they are stored at addresses "100", "101", "102",... to form the - la -address table.
In this manner, the data are transferred from the magnetic disk 4 to the RAM 3, and at the same tlme, the address table storlng the start addresses of the words stored in the RAM 3 is formed. Therefore, after the above-mentioned data transfer, a deslred word can be directly accessed based on the address table, and updat-ing processing of words, or the like can be performed at high speed.
The data transfer operation shown in Fig. 4 and the operation for formlng the address table using the block circuit shown in Fig. 1 will be described in detail below with reference to the timing chart in Fig. 5.
Prior to data transfer processing, various initial-lzation operations are performed. More specifically,the CPU 1 sets data "100" as an initial value in the write address register WA, and sets data "11" as an inltlal value in the address counter AC of the DMA
controller 5. The CPU 1 sets the dellmlter codes ",", "~", and " " ln the dellmiter type reglster 66, and sets the data transfer instruction code INS3 in the lnstructlon code register 65.
After these setting operations, the CPU 1 outputs the processing start signal Sl to the controller 61, thus transferrlng all the control to the controller 61.
Upon receptlon of the processing start slgnal Sl from the CPU 1, the controller 61 outputs the start signal S10 to the DMA controller 5. More speclflcally, the DMA controller 5 outputs the address data stored ln the address counter AC onto the address bus AB, and at the same tlme, reads out unlt data from the magnetlc disk 4. Since the address counter AC stores the data "11" as the initlal value, address "11" of the RAM 3 is designated, and data stored at the start address of the magnetic disk 4, i.e., the delimiter code llt'' is read out onto the data bus DB. The readout code is stored at address "11" of the RAM 3. The data read out onto the data bus DB is fetched in the read buffer 67 at the same time, and it ls checked lf the fetched code colncldes wlth the delimiter code set ln the dellmlter type regis-ter 66. In thls case, since the readout data ls thedelimiter code ll(ll~ lts detectlon signal ls output to the controller 61. Upon receptlon of the detectlon signal, the controller 61 outputs the latch signal S6 to the address latch clrcuit 63 to cause it to latch address data at that time, i.e., "11". After the data transfer is completed, the DMA controller 5 lncrements the value of the address counter AC by "1" to "12".
Thereafter, the controller 61 outputs the interruption slgnal Sll to the DMA controller 5. Upon reception of the interruption signal Sll, the DMA controller 5 tem-porarily interrupts the readout operation of the data from the magnetic disk 4, and outputs the interrupted signal S12 to the controller 61. when the controller 61 receives the interrupted signal S12, lt outputs the latch completion signal S8 to the address generator 62.
The address generator 62 outputs address data stored in the write address register WA, i.e., "100'l onto the address bus As, and designates the corresponding address in the RAM 3. At this time, data obtained by increment-ing address data latched in the address latch circuit 63 by "1", i.e., data "12" is supplied onto the data bus DB. The data "12" on the data bus DB is stored at address "100" in the RAM 3. After the storage opera-tlon, the address generator 62 increments the value of the write address register WA by "1~. Thereafter, the controller 61 outputs the interruption completion slgnal S13 to the DMA controller 5. Upon reception of the lnterruption completion slgnal S13, the DMA controller 5 restarts the data readout operation.
When the DMA controller 5 restarts the data readout operatlon, it outputs address data stored in the address 2~ counter AC onto the address bus AB ln synchronlsm wlth the clock, and at the same tlme, reads out unlt data from the magnetlc dlsk 4. Slnce the address counter AC
stores data "12", address "12" of the RAM 3 ls deslg-nated, and the second data stored ln the magnetlc dlsk 4, l.e., data "x" ls read out onto the data bus DB, and ls stored at address "12~ of the RAM 3. The data read out onto the data bus DB ls fetched ln the read buffer 67 at the same time, and the detector 68 ~udges whether or not the fetched data is the delimiter code set in the delimiter type register 66. In this case, slnce the readout data ls not a dellmlter code, the detector 68 outputs no detectlon signal, and only the data transfer operation is performed. After the data storage operatlon ln the RAM 3, the value of the address counter AC ls lncremented by "1" to "13".
In synchronism with the next clock, the thlrd unit data stored in the magnetic disk 4 is transferred to address "13" of the RAM 3. Slnce this data is not a delimiter code, either, only the data transfer operatlon is performed.
In synchronlsm wlth the next clock, the fourth unlt data stored ln the magnetlc dlsk 4 ls transferred to address "14" of the RAM 3. Since this data is the delimiter code ",", the detector 68 outputs a detection signal. Upon reception of the detection signal, the controller 61 outputs the latch signal S6 to the address latch circuit 63 to cause it to latch address data at that tlme, l.e., "14". The latched address data ls incremented by "1", and the incremented data "15" ls stored at an address designated by the address generator 62, i.e., address "101" ln the RAM 3.
Similarly, when data stored in the magnetic disk 4 is transferred to the RAM 3, this data is simultane-ously detected by the detector 68. If the data to be transferred to the RAM 3 is the delimiter code, an address next to that of the RAM 3 at whlch this dell-miter code is stored is read out as data, and ls sequentially stored in the table area in the RAM 3.
When the detector 68 detects the dellmlter code " ~ indicating a flle delimitation, the controller 61 outputs an operatlon end signal S14 to the DMA control-ler 5, thus stopplng the data transfer operation of the DMA controller 5. The controller 61 outputs the end signal S9 to the CPU 1 to transfer all the control to the CPU 1.
With the series of operations described above, variable length data for one file stored in the magnetic disk 4 are transferred to the RAM 3, and the storage position of each transferred word in the RAM 3, i.e., the start address of each word is stored in the prede-termined address table area in the RAM 3.
Therefore, after the data is transferred from the magnetlc disk 4 to the RAM 3, the CPU 1 can refer to the address table to directly detect the storage position of a word, and perform high-speed word access.
In the above embodiment, the operations based on the specific field table formation instruction code INS2 and the data transfer lnstruction code INS3 have been described. An operation based on the table formation lnstructlon code INSl is performed in the same manner as described above. More specifically, the operation based :
.
on the table formation lnstructlon code INSl corresponds to a partlal modiflcation of the operation based on the lnstruction code INS2. That ls, when the detector 68 detects the dellmiter code ~'," or "~', the latch slgnal S6 is output based on thls detection. Therefore, in this case, the start addresses of all the words are stored in the address table. Fig. 6 shows this state.
In the above embodiment, when a delimiter code is detected and an address at that time is latched, a value obtained by incrementing the address data by "1" is stored in the address table. However, the latched address itself may be stored in the address table.
If a delimiter code to be set in the delimiter type register 66 is appropriately selected, an address table indlcatlng only a delimitatlon position of each word, an address table lndlcatlng only a delimitation positlon of each record, and an address table indicating only a dellmltatlon position of each file, can be arbitrarily formed.
When the data transfer instruction code INS3 is set in the instruction code register 65, the controller 61 performs slgnal I/O control as follows.
(1) When the controller 61 receives a processing start signal Sl from the CPU 1, lt outputs a start slg-nal S10 to the DMA controller 5.
(2) When the controller 61 recelves the dellmiter code "(" or "," indlcating a record or word dellmi-tatlon from the detector 6a, lt outputs a latchsignal S6 to the address latch clrcult 63, and then outputs an lnterruptlon slgnal Sll to the DMA con-troller 5.
(3) When the controller 61 recelves the dellmlter code " " lndicatlng a flle dellmitatlon from the detec-tor 68, lt outputs an end slgnal S14 to the DMA con-troller 5, and outputs a processlng end slgnal S9 to . -! `, ..
-` 1 324684 the CPU 1.
(4) When the controller 61 receives an lnterrupted signal S12 from the DMA controller 5, lt outputs a lat~h complation signal S8 to the address generator 62, and then outputs an interruption completion signal S13 to the DMA controller 5.
The DMA controller 5 will now be described.
The DMA controller 5 has an address counter AC.
When the controller 5 receives the start signal S10 from the controller 61, it starts a data transfer operation on the basis of a clock signal from a clock generator (not shown). The controller 5 reads out unit data from the magnetic disk 4 onto the data bus DB, and outputs the content of the address counter AC onto the address bus AB to deslgnate an address of the RAM 3. Then, the controller 5 transfers the unit data on the data bus DB
to the deslgnated address position in the RAM 3. The controller 5 repeats this operation in response to every clock signal, so that each unit data in the magnetic disk 4 is transferred to the RAM 3 at high speed. The address counter AC is incremented by "1" every time the unit data ls transferred. When the DMA controller 5 receives the interruption signal Sll from the controller 61, it lnterrupts the data transfer operation (stops a clock operation)~ and then sends the interrupted signal S12 to the controller 61. Upon reception of the inter-ruption completlon slgnal S13 from the controller 61, . .~.
the DMA controller 5 restarts the interrupted data transfer operation. Upon reception of an end slgnal S14, the controller 5 ends a series of data transfer operatlons.
The operation of the embodlment of the present lnvention will be described hereinafter.
A case will be described below wherein an address table of designated words is formed, e.g., wherein the address table of second words in records is formed, as shown in Flg. 2.
Fig. 2 shows a case wherein the start address of a second word of each record stored in an area starting from address ~1" in the RAM 3 is written in a table area of the RAM 3, i.e., a table area starting from address "lO0", thereby forming an address table. Since the start address of the second word of the first record is "5", the address "5" data is written at address "100".
Since the start address of the second word of the second record ls "16n, the address "16" data ls written at address "101". Slnce the start address of the second word of the third record is "2s", the address ll25ll data ls wrltten at address "102". Slmllarly, the start addresses of the second words of the followlng records are wrltten ln an area after address "103", thus formlng the address table.
In thls manner, when the address table of the deslgnated words ls formed, lf an lnstruction for adding all the second words of the records ls lnput, the addresses of the second words of the records can be dlrectly detected wlth reference to thls address table, and an access speed can be lncreased. There-fore, word addltlon processing can be performed athlgh speed.
An operation for formlng the address table shown in Fig. 2 using the block circuit shown in Fig. 1 will be described in detail below with reference to the timing chart shown in Fig. 3.
Various registers are initiallzed prior to address table formatlon processlng. More speclflcally, the CPU
1 sets data "1" and ~'100" as initial values in the read address register RA and the write address register WA, and sets data "2" in the designated field register 64.
The CPU 1 then sets the delimiter codes '',ll, ''(ll~ and n 1l in the delimiter type register 66, and sets the specific field table formation instruction code INS2 in the instructlon code register 65.
After these settlng operations, the CPU 1 outputs the processlng start signal Sl to the controller 61, and transfers all the control to the controller 61.
Upon reception of the processing start signal Sl from the CPU 1, the controller 61 outputs the start signal S2 to the address generator 62. More specifi-cally, the address generator 62 outputs address data stored in the read address register RA onto the address , . . .
bus AB ln a first read cycle, and reads out data stored in the corresponding address area in the RAM 3 onto the data bus Ds. The data read out onto the data bus DB is fetched ln the read buffer 67, and the detector 68 ~udges whether or not the fetched data coincides with any one of the delimiter codes set in the deli-miter type register 66. Since data stored in the address area "1" in the RAM 3 is the delimiter code lts detection signal is output to the controller 61.
When the controller 61 receives the detection signal of the delimiter code ''(ll~ it outputs the reset signal S3 to the counter 70 to reset the content of the counter 70 to "1". Slnce no address latch operatlon ls performed ln this read cycle, the address generator 62 does not output address data stored in the wrlte address reglster WA onto the address bus AB in the followlng wrlte cycle, and no write access to the RAM 3 is performed. Upon completion of the read cycle, the value of the read address reglster RA ls lncremented by "1", l.e., to "2".
Thereafter, ln the next read cycle, the content of the read address reglster RA ls output onto the address bus AB, and data, l.e., "x" stored ln the correspondlng address area ln the RAM 3 iS read out onto the data bus DB. Thls data ls fetched ln the read buffer 67. Slnce thls data ls not a dellmlter code, the detector 68 does not output a detectlon slgnal, and hence, no wrlte t 324684 access to the RAM 3 ls performed in the followlng wrlte cycle.
In the next read cyclet slnce data "x" ls output onto the data bus DB, no wrlte access to the RAM 3 ls performed, elther, in the following wrlte cycle.
In the fourth read cycle, slnce the dellmlter code "," ls output onto the data bus DB, this code is detected by the detector 68, and lts detectlon signal is output to the controller 61. Upon reception of the detectlon slgnal of the dellmlter code ",", the con-troller 61 outputs the comparlson signal S4 to the comparator 69, so that a value "1" obtained by decre-menting data "2" stored in the designated field register 64 is compared wlth a count value stored in the counter 70. In this case, slnce the data "1" is set in the counter 70, the comparator 69 detects a coincidence between the two data, and supplies the coincldence signal S5 to the controller 61. When the controller 61 recelves the coincidence signal S5, it outputs the latch slgnal S6 to the address latch circuit 63. Thus, the address latch circuit 6~ latches address data at that tlme, i.e., "4". Thereafter, the controller 61 outputs the count-up signal S7 to the counter 70 to update the value of the counter 70 to "2". The controller 61 outputs the latch completion signal S8 to the address generator 62. The address generator 62 outputs address data, i.e., "100", stored in the write address register WA onto the address bus AB to designate the correspond-ing address area in the RAM 3. In thls case, data obtained by incrementing the address data latched ln the address latch circuit 63 by "1", l.e., "5", ls supplled onto the data bus DB . The data ~5" on the data bus DB
ls stored at address ~'loo" ln the RAM 3. After the data storage operation, the address generator 62 increments the value of the write address register WA by "1".
In the fifth read cycle, since data "x" is detected on the data bus DB, a detection operation by the detec-tor 68 ls not performed, and hence, no data storage processlng ls performed ln the following write cycle.
In the sixth read cycle, since the delimiter code "," ls detected on the data bus DB, thls code ls detected by the detector 68, and its detection result ls supplied to the controller 61. Upon receptlon of thls detectlon signal, the controller 61 outputs the comparlson slgnal S4 to the comparator 69, so that a value "1" obtained by decrementing data stored in the deslgnated fleld reglster 64 by "1" ls compared wlth a count value stored ln the counter 70. In thls case, slnce the counter 70 stores data H2", the comparator 69 does not output the coincldence slgnal S5. As a result, the controller 61 does not output the latch slgnal Sfi to the address latch clrcult 63, and hence, no data storage processlng 19 performed ln the followlng wrlte cycle.
In thls read cycle, the controller 61 outputs the . .
.
count-up signal S7 to the counter 70 to update the value of the counter 70 to "3".
Simllarly, the data readout processing is sequentially performed. When the delimiter code "~" is read out onto the data bus DB in the 13th read cycle, this code is detected by the detector 68, and its detec-tion result is supplied to the controller 61. Upon reception of this detection signal, tha controller 61 outputs the reset signal S3 to the counter 70 to reset the content of the counter 70 to "1".
In the 14th read cycle, since data "x" is output onto the data bus DB~ the detector 68 does not output the detection signal.
In the 15th read cycle, the delimiter code "," is output onto the data bus DB, and this code is detected by the detector 68. The controller 61 then supplles the comparison signal S4 to the comparator 69, so that a value "1" obtained by decrementlng data stored in the deslgnated fleld register 64 by "1" is compared with a count value stored in the counter 70. In this case, slnce the counter 70 stores data "1", the comparator 69 outputs the coincldence slgnal S5, and the controller 61 outputs the latch slgnal S6 to the address latch clrcuit 63 to cause lt to latch address data at that tlme, i.e., "15". Thereafter, the controller 61 outputs the count-up signal S7 to the counter 70, and outputs the latch completlon slgnal S8 to the address generator 62. The address generator 62 outputs address data, l.e., "101"
stored ln the write address reglster WA onto the address bus As in the following wrlte cycle. In thls case, data obtained by incrementing the address data latched ln the address latch clrcuit 63 by "1", i.e., data "16" ls sup-plied onto the data bus DB. Thls data "16" ls stored at address "101" ln the RAM 3.
In this manner, the data stored in the RAM 3 are sequentially read out, and are sub~ected to delimiter detection in the detector 68. If the dellmiter code indicating the record delimitation is detected, the counter 70 is detected. If the dellmiter code 'l,ll indi-cating a word delimitation is detected, the comparator 69 checks if this code is a code stored immedlately before the deslgnated word in one record, l.e., a deli-miter code stored immedlately before the second word.
If it is determined that the detected code is the deli-mlter code stored immediately before the second word, the address ln the RAM 3 at which this delimlter code is stored ls latched ln the address latch circult 63.
Data obtalned by incrementing this address value by "1" is sequentially stored ln the table area in the RAM 3.
When the detector 68 detects the delimiter code " " lndicating a file dellmltatlon, the controller 61 ends the address table formation processing, and outputs the end signal S9 to the CPU 1, thus transferrlng all the control to the CPu 1.
With the series of processing operatlons descrlbed above, the start addresses of the second words of the records in a predetermined file in the RAM 3 are stored in the designated address table area in the RAM 3.
Therefore, the CPU 1 refers to the address table to directly detect the start addresses of the second words of the records in the file, and updatlng process-ing or the llke for one file can be performed at high speed.
Since the address table formation processing is performed by a special-purpose circuit, it can be per-formed at very high speed.
A case will be described below wherein an address table of words is formed simultaneously when varlable length data stored ln the magnetic disk 4 are DMA-transferred into the RAM 3.
Fig. 4 shows a case whereln varlable-length word data stored ln the magnetlc dlsk 4 are sequentlally transferred to and stored in an area starting from address "11" in the RAM 3, and at the same time, the ~tart address of the words stored in the RAM 3 in this manner are stored ln the table area in the RAM 3, i. e., in an area starting from address "100", thus forming an address table. Slnce the start addresses of the words are "12", "15", ~17", "21~, "24", "26",..., they are stored at addresses "100", "101", "102",... to form the - la -address table.
In this manner, the data are transferred from the magnetic disk 4 to the RAM 3, and at the same tlme, the address table storlng the start addresses of the words stored in the RAM 3 is formed. Therefore, after the above-mentioned data transfer, a deslred word can be directly accessed based on the address table, and updat-ing processing of words, or the like can be performed at high speed.
The data transfer operation shown in Fig. 4 and the operation for formlng the address table using the block circuit shown in Fig. 1 will be described in detail below with reference to the timing chart in Fig. 5.
Prior to data transfer processing, various initial-lzation operations are performed. More specifically,the CPU 1 sets data "100" as an initial value in the write address register WA, and sets data "11" as an inltlal value in the address counter AC of the DMA
controller 5. The CPU 1 sets the dellmlter codes ",", "~", and " " ln the dellmiter type reglster 66, and sets the data transfer instruction code INS3 in the lnstructlon code register 65.
After these setting operations, the CPU 1 outputs the processing start signal Sl to the controller 61, thus transferrlng all the control to the controller 61.
Upon receptlon of the processing start slgnal Sl from the CPU 1, the controller 61 outputs the start signal S10 to the DMA controller 5. More speclflcally, the DMA controller 5 outputs the address data stored ln the address counter AC onto the address bus AB, and at the same tlme, reads out unlt data from the magnetlc disk 4. Since the address counter AC stores the data "11" as the initlal value, address "11" of the RAM 3 is designated, and data stored at the start address of the magnetic disk 4, i.e., the delimiter code llt'' is read out onto the data bus DB. The readout code is stored at address "11" of the RAM 3. The data read out onto the data bus DB is fetched in the read buffer 67 at the same time, and it ls checked lf the fetched code colncldes wlth the delimiter code set ln the dellmlter type regis-ter 66. In thls case, since the readout data ls thedelimiter code ll(ll~ lts detectlon signal ls output to the controller 61. Upon receptlon of the detectlon signal, the controller 61 outputs the latch signal S6 to the address latch clrcuit 63 to cause it to latch address data at that time, i.e., "11". After the data transfer is completed, the DMA controller 5 lncrements the value of the address counter AC by "1" to "12".
Thereafter, the controller 61 outputs the interruption slgnal Sll to the DMA controller 5. Upon reception of the interruption signal Sll, the DMA controller 5 tem-porarily interrupts the readout operation of the data from the magnetic disk 4, and outputs the interrupted signal S12 to the controller 61. when the controller 61 receives the interrupted signal S12, lt outputs the latch completion signal S8 to the address generator 62.
The address generator 62 outputs address data stored in the write address register WA, i.e., "100'l onto the address bus As, and designates the corresponding address in the RAM 3. At this time, data obtained by increment-ing address data latched in the address latch circuit 63 by "1", i.e., data "12" is supplied onto the data bus DB. The data "12" on the data bus DB is stored at address "100" in the RAM 3. After the storage opera-tlon, the address generator 62 increments the value of the write address register WA by "1~. Thereafter, the controller 61 outputs the interruption completion slgnal S13 to the DMA controller 5. Upon reception of the lnterruption completion slgnal S13, the DMA controller 5 restarts the data readout operation.
When the DMA controller 5 restarts the data readout operatlon, it outputs address data stored in the address 2~ counter AC onto the address bus AB ln synchronlsm wlth the clock, and at the same tlme, reads out unlt data from the magnetlc dlsk 4. Slnce the address counter AC
stores data "12", address "12" of the RAM 3 ls deslg-nated, and the second data stored ln the magnetlc dlsk 4, l.e., data "x" ls read out onto the data bus DB, and ls stored at address "12~ of the RAM 3. The data read out onto the data bus DB ls fetched ln the read buffer 67 at the same time, and the detector 68 ~udges whether or not the fetched data is the delimiter code set in the delimiter type register 66. In this case, slnce the readout data ls not a dellmlter code, the detector 68 outputs no detectlon signal, and only the data transfer operation is performed. After the data storage operatlon ln the RAM 3, the value of the address counter AC ls lncremented by "1" to "13".
In synchronism with the next clock, the thlrd unit data stored in the magnetic disk 4 is transferred to address "13" of the RAM 3. Slnce this data is not a delimiter code, either, only the data transfer operatlon is performed.
In synchronlsm wlth the next clock, the fourth unlt data stored ln the magnetlc dlsk 4 ls transferred to address "14" of the RAM 3. Since this data is the delimiter code ",", the detector 68 outputs a detection signal. Upon reception of the detection signal, the controller 61 outputs the latch signal S6 to the address latch circuit 63 to cause it to latch address data at that tlme, l.e., "14". The latched address data ls incremented by "1", and the incremented data "15" ls stored at an address designated by the address generator 62, i.e., address "101" ln the RAM 3.
Similarly, when data stored in the magnetic disk 4 is transferred to the RAM 3, this data is simultane-ously detected by the detector 68. If the data to be transferred to the RAM 3 is the delimiter code, an address next to that of the RAM 3 at whlch this dell-miter code is stored is read out as data, and ls sequentially stored in the table area in the RAM 3.
When the detector 68 detects the dellmlter code " ~ indicating a flle delimitation, the controller 61 outputs an operatlon end signal S14 to the DMA control-ler 5, thus stopplng the data transfer operation of the DMA controller 5. The controller 61 outputs the end signal S9 to the CPU 1 to transfer all the control to the CPU 1.
With the series of operations described above, variable length data for one file stored in the magnetic disk 4 are transferred to the RAM 3, and the storage position of each transferred word in the RAM 3, i.e., the start address of each word is stored in the prede-termined address table area in the RAM 3.
Therefore, after the data is transferred from the magnetlc disk 4 to the RAM 3, the CPU 1 can refer to the address table to directly detect the storage position of a word, and perform high-speed word access.
In the above embodiment, the operations based on the specific field table formation instruction code INS2 and the data transfer lnstruction code INS3 have been described. An operation based on the table formation lnstructlon code INSl is performed in the same manner as described above. More specifically, the operation based :
.
on the table formation lnstructlon code INSl corresponds to a partlal modiflcation of the operation based on the lnstruction code INS2. That ls, when the detector 68 detects the dellmiter code ~'," or "~', the latch slgnal S6 is output based on thls detection. Therefore, in this case, the start addresses of all the words are stored in the address table. Fig. 6 shows this state.
In the above embodiment, when a delimiter code is detected and an address at that time is latched, a value obtained by incrementing the address data by "1" is stored in the address table. However, the latched address itself may be stored in the address table.
If a delimiter code to be set in the delimiter type register 66 is appropriately selected, an address table indlcatlng only a delimitatlon position of each word, an address table lndlcatlng only a delimitation positlon of each record, and an address table indicating only a dellmltatlon position of each file, can be arbitrarily formed.
Claims (9)
1. A data processing apparatus which accesses storage means storing variable length data delimited by delimiter codes to perform data processing, com-prising:
controlling means, connected to said storage means through an address bus, for designating an address through said address bus every time one clock is generated, reading out, from said storage means, data stored at the designated address onto a data bus, and incrementing the address every time the data is read out;
detecting means, connected to said data bus, for detecting in response to every clock whether or not the data on said data bus coincides with the delimiter code indicating a delimitation of a data block;
latching means, connected to said address bus, for, when said detecting means detects a coincidence, latching the address on said address bus;
table means for storing address data based on the address latched in said latching means; and processing means for designating a start address of each data block stored in said storage means with refer-ence to the address data stored in said table means and performing processing for each data block.
controlling means, connected to said storage means through an address bus, for designating an address through said address bus every time one clock is generated, reading out, from said storage means, data stored at the designated address onto a data bus, and incrementing the address every time the data is read out;
detecting means, connected to said data bus, for detecting in response to every clock whether or not the data on said data bus coincides with the delimiter code indicating a delimitation of a data block;
latching means, connected to said address bus, for, when said detecting means detects a coincidence, latching the address on said address bus;
table means for storing address data based on the address latched in said latching means; and processing means for designating a start address of each data block stored in said storage means with refer-ence to the address data stored in said table means and performing processing for each data block.
2. The apparatus according to claim 1, wherein said storage means stores variable length data delimited by various delimiter codes, and said detecting means detects whether or not the data on said data bus coin-cides with a specific delimiter code indicating a delimitation of a desired data block.
3. The apparatus according to claim 2, wherein the specific delimiter is a code indicating a delimitation of variable length word data block.
4. The apparatus according to claim 2, wherein the specific delimiter code is a code indicating a delimita-tion of variable length record data block.
5. The apparatus according to claim 2, wherein the specific delimiter code is a code indicating a delimita-tion of variable length file data block.
6. The apparatus according to claim 2, wherein said detecting means includes a register for storing the spe-cific delimiter code.
7. The apparatus according to claim 3, further comprising:
a counter which is reset upon detection of a delimiter code indicating a record block delimitation, and is incremented upon detection of a delimiter code indicating a word block delimitation;
a register for storing a predetermined designated value; and comparison means for comparing a value of said counter with a value of said register, wherein said latching means includes means for, when a coincidence signal is obtained from said com-parison means, latching the address on said address bus.
a counter which is reset upon detection of a delimiter code indicating a record block delimitation, and is incremented upon detection of a delimiter code indicating a word block delimitation;
a register for storing a predetermined designated value; and comparison means for comparing a value of said counter with a value of said register, wherein said latching means includes means for, when a coincidence signal is obtained from said com-parison means, latching the address on said address bus.
8. An apparatus for forming an address table for storage means for storing data as an object to be processed, comprising:
a read address register for storing an address indicating a readout start position of the variable length data;
a write address register for storing an address indicating a write position of said address table;
reading out means, connected to said storage means through an address bus, for designating an address of said storage means on the basis of an address stored in said read address register in response to every clock, and reading out corresponding stored data:
detecting means, connected to said storage means through a data bus, for detecting whether or not the data read out by said reading out means coincides with a delimiter code;
latching means, connected to said address bus, for, when said detecting means detects a coincidence, latching an address on said address bus;
writing means, connected to said address table through said address bus, for designating the address of said address table on the basis of the address stored in said write address register every time the address is latched in said latching means, and writing address data based on the address latched in said latching means in a corresponding storage area; and incrementing means for incrementing the address of said read address register every time the data is read out by said reading out means, and for incrementing the address of said write address register every time the address data is written by said writing means.
a read address register for storing an address indicating a readout start position of the variable length data;
a write address register for storing an address indicating a write position of said address table;
reading out means, connected to said storage means through an address bus, for designating an address of said storage means on the basis of an address stored in said read address register in response to every clock, and reading out corresponding stored data:
detecting means, connected to said storage means through a data bus, for detecting whether or not the data read out by said reading out means coincides with a delimiter code;
latching means, connected to said address bus, for, when said detecting means detects a coincidence, latching an address on said address bus;
writing means, connected to said address table through said address bus, for designating the address of said address table on the basis of the address stored in said write address register every time the address is latched in said latching means, and writing address data based on the address latched in said latching means in a corresponding storage area; and incrementing means for incrementing the address of said read address register every time the data is read out by said reading out means, and for incrementing the address of said write address register every time the address data is written by said writing means.
9. A data processing apparatus for processing data on the basis of first storage means and second storage means for storing data, comprising:
controlling means, connected to said first and second storage means through a data bus and an address bus, for controlling, in response to every clock, said first storage means so that data is read out onto said data bus, and said second storage means so that an address is designated through said address bus, the data on said data bus being written in a storage area corresponding to the designated address, and the address being incremented upon every write access;
detecting means, connected to said address bus, for detecting in response to every clock whether or not the data on said data bus coincides with a delimiter code indicating a delimitation of a data block;
latching means, connected to said address bus, for, when said detecting means detects a coincidence, latching an address on said address bus;
table means for storing address data based on the address latched in said latching means; and processing means for designating a start address of each data block written in said second storage means with reference to the address data stored in said table means and performing processing for each data block.
controlling means, connected to said first and second storage means through a data bus and an address bus, for controlling, in response to every clock, said first storage means so that data is read out onto said data bus, and said second storage means so that an address is designated through said address bus, the data on said data bus being written in a storage area corresponding to the designated address, and the address being incremented upon every write access;
detecting means, connected to said address bus, for detecting in response to every clock whether or not the data on said data bus coincides with a delimiter code indicating a delimitation of a data block;
latching means, connected to said address bus, for, when said detecting means detects a coincidence, latching an address on said address bus;
table means for storing address data based on the address latched in said latching means; and processing means for designating a start address of each data block written in said second storage means with reference to the address data stored in said table means and performing processing for each data block.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17511188A JPH0225922A (en) | 1988-07-15 | 1988-07-15 | Data detector |
| JP63-175111 | 1988-07-15 | ||
| JP63-311347 | 1988-12-09 | ||
| JP31134788A JPH02157934A (en) | 1988-12-09 | 1988-12-09 | Variable length data processor |
| JP31134688A JPH02157933A (en) | 1988-12-09 | 1988-12-09 | Variable length data processor |
| JP63-311346 | 1988-12-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1324684C true CA1324684C (en) | 1993-11-23 |
Family
ID=27324044
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000604840A Expired - Fee Related CA1324684C (en) | 1988-07-15 | 1989-07-05 | Variable length data processing apparatus |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5115490A (en) |
| EP (1) | EP0350929B1 (en) |
| KR (1) | KR0152979B1 (en) |
| CA (1) | CA1324684C (en) |
| DE (1) | DE68924377T2 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA1328027C (en) * | 1988-07-14 | 1994-03-22 | Toshio Kashio | Data processing apparatus |
| JPH0795269B2 (en) * | 1988-11-04 | 1995-10-11 | 富士通株式会社 | Instruction code decoding device |
| JP2746734B2 (en) * | 1990-06-08 | 1998-05-06 | 富士通株式会社 | Access processing method for stream file |
| US5510785A (en) * | 1993-03-19 | 1996-04-23 | Sony Corporation | Method of coding a digital signal, method of generating a coding table, coding apparatus and coding method |
| JP3433978B2 (en) * | 1993-07-30 | 2003-08-04 | 富士通株式会社 | I / O control unit |
| US5586253A (en) * | 1994-12-15 | 1996-12-17 | Stratus Computer | Method and apparatus for validating I/O addresses in a fault-tolerant computer system |
| JPH1021012A (en) * | 1996-06-28 | 1998-01-23 | Toshiba Corp | Magnetic disk device and command processing method for the same |
| DE60107523T2 (en) * | 2000-03-03 | 2005-12-15 | Koninklijke Philips Electronics N.V. | Data carrier with means for synchronization with the received data stream |
| US6901481B2 (en) | 2000-04-14 | 2005-05-31 | Stratus Technologies Bermuda Ltd. | Method and apparatus for storing transactional information in persistent memory |
| US6802022B1 (en) | 2000-04-14 | 2004-10-05 | Stratus Technologies Bermuda Ltd. | Maintenance of consistent, redundant mass storage images |
| US6862689B2 (en) | 2001-04-12 | 2005-03-01 | Stratus Technologies Bermuda Ltd. | Method and apparatus for managing session information |
| US7137108B1 (en) * | 2000-10-26 | 2006-11-14 | International Business Machines Corporation | Identifying non-externalized text strings that are not hard-coded |
| US6948010B2 (en) * | 2000-12-20 | 2005-09-20 | Stratus Technologies Bermuda Ltd. | Method and apparatus for efficiently moving portions of a memory block |
| US6886171B2 (en) * | 2001-02-20 | 2005-04-26 | Stratus Technologies Bermuda Ltd. | Caching for I/O virtual address translation and validation using device drivers |
| US6766413B2 (en) | 2001-03-01 | 2004-07-20 | Stratus Technologies Bermuda Ltd. | Systems and methods for caching with file-level granularity |
| US6874102B2 (en) * | 2001-03-05 | 2005-03-29 | Stratus Technologies Bermuda Ltd. | Coordinated recalibration of high bandwidth memories in a multiprocessor computer |
| US6996750B2 (en) * | 2001-05-31 | 2006-02-07 | Stratus Technologies Bermuda Ltd. | Methods and apparatus for computer bus error termination |
| DE10324014A1 (en) * | 2003-05-27 | 2005-01-13 | Micronas Gmbh | Address generator, method of operation therefor, and data processing system using the same |
| KR100963140B1 (en) * | 2008-11-27 | 2010-06-16 | 한국과학기술원 | Direct memory access device and direct memory access method |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5235264B2 (en) * | 1971-09-29 | 1977-09-08 | ||
| JPS5413306B2 (en) * | 1974-01-24 | 1979-05-30 | ||
| CA1071332A (en) * | 1974-05-01 | 1980-02-05 | Toshio Kashio | Data processing system |
| JPS5524134B2 (en) * | 1974-11-15 | 1980-06-27 | ||
| JPS586979B2 (en) * | 1974-11-15 | 1983-02-07 | カシオケイサンキ カブシキガイシヤ | JIYO HOUYOMI DASHI SOUCHI |
| JPS5522821B2 (en) * | 1974-11-15 | 1980-06-19 | ||
| JPS5250132A (en) * | 1975-10-21 | 1977-04-21 | Casio Comput Co Ltd | Information processing control unit |
| JPS5272125A (en) * | 1975-12-12 | 1977-06-16 | Casio Comput Co Ltd | Manual input device for information |
| JPS5279628A (en) * | 1975-12-25 | 1977-07-04 | Casio Comput Co Ltd | Information reading processing equipment |
| JPS5346689A (en) * | 1976-10-12 | 1978-04-26 | Sumitomo Electric Ind Ltd | Oil removing method and device empolyed when welding of cable |
| JPS5350953A (en) * | 1976-10-20 | 1978-05-09 | Casio Comput Co Ltd | Comparison/array system for variable length information |
| US4376933A (en) * | 1979-02-22 | 1983-03-15 | Xerox Corporation | Circuit for compacting data |
| US4306287A (en) * | 1979-08-31 | 1981-12-15 | Bell Telephone Laboratories, Incorporated | Special address generation arrangement |
| FR2472231B1 (en) * | 1979-12-20 | 1986-02-21 | Cii Honeywell Bull | DEVICE FOR ADDRESSING INFORMATION ELEMENTS IN A MULTI-INPUT TABLE, RECORDED IN A MEMORY |
| FR2486926A1 (en) * | 1980-07-21 | 1982-01-22 | Saint Gobain Vitrage | OVEN FOR HEATING SUSPENDED GLASS SHEETS IN VERTICAL POSITION |
| JPS5845920B2 (en) * | 1980-09-19 | 1983-10-13 | 荏原インフイルコ株式会社 | Biochemical treatment method for organic waste liquid |
| JPS5846735A (en) * | 1981-09-15 | 1983-03-18 | Anritsu Corp | Storage device of 2-channel waveform |
| JPS5853384A (en) * | 1981-09-25 | 1983-03-29 | Toshiba Corp | Laser seam welding machine |
| JPS59116870A (en) * | 1982-12-23 | 1984-07-05 | Casio Comput Co Ltd | Data storage device |
-
1989
- 1989-06-24 KR KR1019890008774A patent/KR0152979B1/en not_active IP Right Cessation
- 1989-07-03 US US07/375,386 patent/US5115490A/en not_active Expired - Fee Related
- 1989-07-05 CA CA000604840A patent/CA1324684C/en not_active Expired - Fee Related
- 1989-07-13 DE DE68924377T patent/DE68924377T2/en not_active Expired - Fee Related
- 1989-07-13 EP EP89112869A patent/EP0350929B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0350929A3 (en) | 1991-01-30 |
| DE68924377T2 (en) | 1996-03-07 |
| EP0350929A2 (en) | 1990-01-17 |
| KR900002170A (en) | 1990-02-28 |
| KR0152979B1 (en) | 1998-11-16 |
| US5115490A (en) | 1992-05-19 |
| DE68924377D1 (en) | 1995-11-02 |
| EP0350929B1 (en) | 1995-09-27 |
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