CA2002213A1 - High Performance Integrated Circuit Chip Package and Method of Making Same - Google Patents

High Performance Integrated Circuit Chip Package and Method of Making Same

Info

Publication number
CA2002213A1
CA2002213A1 CA2002213A CA2002213A CA2002213A1 CA 2002213 A1 CA2002213 A1 CA 2002213A1 CA 2002213 A CA2002213 A CA 2002213A CA 2002213 A CA2002213 A CA 2002213A CA 2002213 A1 CA2002213 A1 CA 2002213A1
Authority
CA
Canada
Prior art keywords
face
heat sink
chip package
support substrate
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2002213A
Other languages
French (fr)
Other versions
CA2002213C (en
Inventor
Iwona Turlik
Arnold Reisman
Deepak Nayak
Lih-Tyng Hwang
Giora Dishon
Scott L. Jacobs
Robert Francis Darveaux
Neil M. Poley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nortel Networks Ltd
MCNC
International Business Machines Corp
Original Assignee
Northern Telecom Ltd
MCNC
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Northern Telecom Ltd, MCNC, International Business Machines Corp filed Critical Northern Telecom Ltd
Publication of CA2002213A1 publication Critical patent/CA2002213A1/en
Application granted granted Critical
Publication of CA2002213C publication Critical patent/CA2002213C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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Abstract

A high performance integrated circuit chip package includes a support substrate having conductors extending from one face to the opposite face thereof and a multilayer wiring substrate on the opposite face of the support substrate for connecting chips mounted thereon to one another and to the conductors. A heat sink includes microchannels at one face thereof, with thermally conductive cushions connecting the one face of the heat sink with the exposed back sides of the chips, to provide a high density chip package with high heat dissipation.
The multilayer wiring substrate may be formed by a self-aligned thin film wiring method, with a self-aligned lift off method being employed to form internal wiring planes. The support substrate and heat sink may be formed of blocks of material having thermal expansion matching silicon. The cushions are a low melting point solder, preferably pure indium, and are sufficiently thick to absorb thermal stresses, but sufficiently thin to efficiently conduct heat from the chips to the heat sink.
CA002002213A 1988-11-10 1989-11-03 High performance integrated circuit chip package and method of making same Expired - Fee Related CA2002213C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US27072988A 1988-11-10 1988-11-10
US270,729 1988-11-10

Publications (2)

Publication Number Publication Date
CA2002213A1 true CA2002213A1 (en) 1990-05-10
CA2002213C CA2002213C (en) 1999-03-30

Family

ID=23032548

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002002213A Expired - Fee Related CA2002213C (en) 1988-11-10 1989-11-03 High performance integrated circuit chip package and method of making same

Country Status (5)

Country Link
US (1) US5325265A (en)
EP (1) EP0368743A3 (en)
JP (1) JPH02257664A (en)
KR (1) KR900008659A (en)
CA (1) CA2002213C (en)

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JP2917909B2 (en) * 1996-05-07 1999-07-12 日本電気株式会社 Method for manufacturing multilayer wiring board
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