CA2002402A1 - Tabcircuit electrical connector supporting multiple components thereon - Google Patents

Tabcircuit electrical connector supporting multiple components thereon

Info

Publication number
CA2002402A1
CA2002402A1 CA002002402A CA2002402A CA2002402A1 CA 2002402 A1 CA2002402 A1 CA 2002402A1 CA 002002402 A CA002002402 A CA 002002402A CA 2002402 A CA2002402 A CA 2002402A CA 2002402 A1 CA2002402 A1 CA 2002402A1
Authority
CA
Canada
Prior art keywords
support
periphery
traces
components
electrical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002002402A
Other languages
French (fr)
Inventor
Gerold Firl
Stuart D. Asakawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of CA2002402A1 publication Critical patent/CA2002402A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01Ink jet
    • B41J2/135Nozzles
    • B41J2/14Structure thereof only for on-demand ink jet heads
    • B41J2/14016Structure of bubble jet print heads
    • B41J2/14072Electrical connections, e.g. details on electrodes, connecting the chip to the outside...
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387Flexible insulating substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • H05K3/241Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
    • H05K3/242Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0393Flexible materials
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/17Post-manufacturing processes
    • H05K2203/175Configurations of connections suitable for easy deletion, e.g. modifiable circuits or temporary conductors for electroplating; Processes for deleting connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0044Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/005Punching of holes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0044Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49121Beam lead frame or beam lead device
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • Y10T29/49156Manufacturing circuit on or in base with selective destruction of conductive paths

Abstract

TABCIRCUIT ELECTRICAL CONNECTOR
SUPPORTING MULTIPLE COMPONENTS THEREON

ABSTRACT OF THE DISCLOSURE

A flexible interconnect circuit having at least two connected components within its periphery is formed with electrically conductive traces on a nonconductive plastic support. The components are interconnected to each other, and to external locations, with the interconnect circuit. As part of the manufacturing process, the conductive traces are typically electroplated with gold. The traces must be contacted as electrodes during electrodeposition, and the contacting is done using bus connectors along the periphery of the support. Isolated traces, not contacting the periphery and typically extending only between the components within the periphery, are contacted by providing removable bus connectors on the nonconductive support. When plating is complete, the removable bus connectors are removed, preferably by die cutting away portions of those portions of the support having the unneeded bus connectors.

Description

TABCIRCUIT ELECTRICAL CONNECTOR
SUPPORTING MULTIPLE COMPONENTS THEREON

BACKGROUND OF T~E INVENTION

This lnvention relates to connectors for 5 making electrical connections to electrical components, and, more particular, to a flexible interconnact circult havlng electrical traces supported on an electrically insulatlng substrate.

One of the continulng trends ln the 10 electronlcs an~ electromechanlcal appara-tus industrles has been reducing the size of many components and types of apparatus. There are many reasons to strlve for reduced slze, but generally miniaturization increases the speed of operation of electronic 15 devices, reduces the cost of components and apparatus, and increases the numbers of functions that they can perform.
As the si~e of the components is reduced, the difficulty in providlng electrical interconnections 20 between components and to components becomes greater.
Assuming that the number of required external connections for any particular component remains approximately constant even as the size is reduced, the space around the periphery of the device that is 25 availa~le to make the connectlons becomes smaller.
Thus, for e~ample, a 10 fold reductlon ln component size also reduces the available length of periphery by 10 fold.
Slnce the linear length and space required to 30 make e~ternal connec~ons typically does not scale downwardly, the reductlons in component size have prompted many approaches to lmproYed connectability.
In one, a flexible connector material called a TAB
(for Tape Automated ~onding~ flexible interconnect circuit material has been introduced. A TAB circuit electrical connector material includes a flexible insulating support layer, typically made of a plastic material, and particularly a polyimlde such as 5 Kapton. Traces of electrically conducting material are formed on the surface of the support layer. The traces are normally made of copper which is electroplated with gold to reduce oxidation.
The TAB circuit bonding approach is widely 10 used -to make various types of devices. For example, US Patents 3,689,991 and 4,649,415, whlch are incorporated by reference, describe the use of flexible circuit bonding to semiconductor components.
US Patent 4,635,073, which is incorporated by 15 reference~ describes the use of flexible circuit bonding for thermal ink ~et printer print heads. This approach of i'lexible TAB circuit bondlng is particularly suited for manufacturing large numbers of identlcally configured circuits because the bonding 20 material is manufactured in long strips or rolls and the bonding operation is automated.
In use, the custom flexible interconnect circuit is fabricated, and then it is attached to the component for which it ls designed. The component 25 typically is placed within the periphery of the interconnect circuit, either within an aperture cut through the lnterconnect circuit or mounted directly upon the plastic support of the interconnect circuit.
One end of each trace of the in-terconnect circuit is 30 bonded to the appropriate bonding point of the leads o~ the component, and the other end provides external access.
Although its use has greatly increased the efflciency of many manufacturing operations, the 35 flexible circuit bonding approach has drawbacks in practice. I-t is difficult to place more than one component within the periphery of a flexible circuit, Z4()~

due to manufacturing problems that are encountered ln formlng the traces that run between the components on the flexible circuit. Accordingly, there is a need for an improved manufacturing approach to producing 5 ~lexible interconnect circu~t material, which permits the placing of more than one component on the circuit. The present invention fulfills this need, and further provides related advantages.

SUMMARY OF THE INVENTION
10 The present invention provldes a method for manufacturing a flexible interconnect circuit, wherein the traces are plated with a protectiYe layer, for use in devices having more than one component to be connected within the periphery o~ the circuit. Such 15 an approach greatly increases the versatilit~ of the circuits and devices made therewith, by permitting processing on the circuit itsel~ using multiple components. In a typical use, a primary component is supported by secondary components that perform some or 20 all of the processing functions, with both the primary and secondary components mounted on a single flexible interconnect circuit.
In accordance with the inventlon, a method for forming an electrical device having at least two 25 components in-terconnected by a flexible electrical connector material having conduc-tive traces supported on a nonconductive support, the components being disposed within the periphery of the nonconductive support comprises the steps of providing a composite 30 of an electrical conductor material on a nonconductive support; removing a portion of the electrlcal conductor material to form a pattern of traces and plating bus connections, the bus connections providlng an electrically continuous path from each trace to the periphery of the support; electrodepositing a metalllc coating over the electrical conductor material, utllizing as one electrodeposition contact the plating bus at the periphery of the support; removing the 5 pla-ting bus connections at the periphery of the support; removing those plating internal bus connections extending from the perlphery of the support to those traces that interconnect the components wlthout otherwise extending to the 10 periphery o~ the electrically insulating support; and connecting the electrical connector locations on the electrical components to the appropriate traces o~ -the ~lexible electrlcal connector.
Where -two or more components of the device 15 are to be lnterconnected by the same flexible interconnect circuit, or TABcircuit, there will be some traces that run to the periphery of the circuit for external connectlon, an~ other traces that run from one component to another component. Those traces 20 that run to the perlphery of the circuit are readily electrodeposited with gold or other oxidatlon and corrosion resistant metal using bus bar connection points that run along the periphery of the circuit.
Those traces that run between components have 25 no continuous electrical connection with the periphery of the circuit, and therefore cannot be electroplated readil~. Such isolated traces are sometimes called "orphan traces". In the present approach, additional internal bus bar electrical connections are etched 30 into the metallic layer at the same time the traces are etched. The internal bus bar connections extend ~rom the orphan traces to the periphery of the circuit, to connect with the bus at the periphery.
Platlng is conducted, and then the periphery bus 35 connections and the internal bus connectlons are removed. The internal bus connections made to the orphan traces are within the interlor of the ~lexible ~Z~

circuit, and are preferably removed by dle cutting or punching, leaving a cleanl~ defined aperture through the flexible circuit.
The present invention is preferably used in 5 con~unction with the flexible interconnect circuits of thermal ink ~et printer print heads. In such application, there is a primary component served by the flexible interconnect circuit, the ink e~ector.
The flexible interconnect circuit is mounted on the 10 ink e~ector support, and the necessary electrical connectlons made. Addi-tionally, it may be desirable to provide other ac-tive components, such as a multiplexer, mounted on the circuit support within the periphery of the in-terconnect circuit. Some traces 15 run from the periphery of the circuit to the e~ector, some traces run from the periphery to the multlplexer, and some from the multiplexer to the e~ector. The traces from the multiplexer to the e~ector are the isolated or orphan traces, and can proi~itably utilize 20 the internal bus connectors of the present invention.
In accordance with this more specific aspect of the invention, a method for forming an electrical device having at least two components interconnected by a flexible electrical connector material having 25 conductive traces supported on a nonconductive support, the components being disposed within the periphery of the nonconductlve support with at least one of the components be~ng mounted on the nonconductive support and at least one of the 30 components being wlthin an aperture through the support comprises the steps of providing a composite of an electrical conductor material on a nonconductive support; removing a portion of the electrical conductor material to form a pattern of traces and 35 plating bus connections, the bus connections providing an electrically continuous path from those traces that interconnect between the two components within the ~OX~2 periphery of the support, to the perlphery of the support; electrodepositing a metallic coating oYer the electrical conductor material, utilizing as one electrodeposition contact the plating bus at the 5 periphery of the support; removing the plating bus connections at the periphery of the support; removing those plating internal bus connections extending from the periphery of the support to those traces that interconnect the components without otherwise 10 extending to the periphery of the electrically insulating support; and connecting the electrical connector locations on the electrical components to the appropriate traces of the flexible electr-lcal connector.
The invention also extends to the method of making the flexible interconnect clrcuit itself. In accordance with this aspect of the invention, a method for preparing a flexible electrical connector material having conductive traces supported on a nonconductive 20 support, at least some of the traces having no contlnuous connection to the periphery of the support, comprises the steps of providing a composite of an electrical conductor materlal on a nonconductive support; removing a port~on of the electrical 25 conductor material to form a pattern of traces and plating bus connections, the bus connections providing as electrically continuous path from each trace to the periphery of the support; electrodepositing a metallic coating over the electrical conductor material, 30 utilizing as one electrodeposition contact the plating bus at the perlphery of the support; removing the platlng bus connections at the periphery of the support; and removing those portions of the electrical bus connections e~tending from the 35 periphery of the support to those traces having no continuous connection to the periphery.
2~0~

The present invention therefore provides a manufacturing process that is readily introduced into large scale fabrication of devices. The cost of the device is increased only marginally, if at all. The 5 versatility afforded device designers is significantly increased by permitting them -to incorporate two or more components onto a single flexible interconnect clrcuit. Other features and advantages of the invention will be apparent from the following more 10 detailed description of the preferred embodiment, taken in con~unction with the accompanying drawings, which lllustrate, by way of example, the principles of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a perspective view of a thermal ink ~et print head assembly;
Figure 2 is an exploded perspective view of the thermal ink ~et print head assembly of Figure l;
Figure 3 ls a plan view of a portion of the 20 flexible interconnect circuit shown in Figure 2 during fabrication, with some traces and bus connections not shown for clarity; and Figure 4 is a plan view similar to Figure 3, e~cept at an earlier stage of fabrication, with the 25 additional bus connections to the orphan traces shown.

DETAILED DESCRIPTION OF THE INVENTION
AND THE_P~EFE~RED EMBODIMENTS

The presently prei`erred application of the present invention is in con~unction with a thermal ink 30 ~et printhead assembly 10, used to eJect microdroplets of ink toward a print medium in a precisely controlled-C)2 -8~

array. Such a prlnthead assembly ls disclosed in US
Patent 4,~35,073.
Briefly, and referring to Figure 1, the printhead assembly 10 includes an e~ector 12 having a 5 silicon substrate 14 with an elongated slot 1~ therein which serves as an lnk intake port for provldlng lnk to a plurallty of lnk reservolrs (not shown) and to correspondlng ink e~ectlon orlflces 18 in an orlfice plate 20 overlylng the substrate 14. Ink is e~ected 10 through the orifices 18 by localized heating of the silicon substrate 14. To effect such heating, thé
silicon substrate 14 has a plurality of tantalum-aluminum alloy reslstors (not shown), one located ad~acent each oriflce 18. Electrical current 15 is provided to each reslstor through a lead 22 deposited upon the silicon substrate 14, each lead 22 terminating near the edge of the substrate 14 in a bonding location 24. A current delivered to a particular resistor causes the ink ad~acent the 20 resistor to be heated and vaporized, e~ecting a microdroplet of ink through the orifice 18 ad~acent the resistor. The present inventlon deals with the approach for providing electrical interconnections, not directly with the e~ector 12 or its mode of 25 operation. The structure and operation of ink e~ectors is described more completely ln the Hewlett Packard Journal, Volume 36, Number 5, May 1985, which disclosure is herein incorporated by reference.
The e~ector 12 is mounted in a recess 2~ in 30 ~he top of a central raised portion 28 of a plastic or metal manifold 30 to place it close to the print medium, as may best be seen in the exploded view oi`
Flgure 2. The raised portion 28 has slanted side walls 32. The raised portion also has end tabs 34, 35 whlch facilitate its handling and attachment to a carriage mechanism (not shown) in the printer.

~z~z ~ lectrical current ls supplied to the bonding locations 24 on the sillcon substrate 1~ through a flexible interconnect circuit 36, also sometimes known as a T~Bcircuit, illustrated in schematic plan view in 5 Figures 3 and ~. The general features and structure of such flexible interconnect circuits 36, and the method of their fabrication, are described in US
Patent 3,689,991. The presen-t invention deals with a modified form of construction of the flexible 10 interconnect circuit 36.
Generally, the flexible interconnect circuit 36 is manu~actured as a flat piece and then molded to fit over the raised portion 28 and down the side walls 32 of -the manifold 30. Electrical traces on the 15 flexible interconnect circuit 36 are bonded at the end ad~acent the substrate 1~ to the bonding locations 24, and at the other end to external current leads (not shown). Electrical current is introduced into the respective resistors of the e~ector 12 through the 20 individual traces of the flexible interconnect circuit 36.
In manufacturlng the lnterconnect circult 3~, a thin layer of electrically conductive metal, preferably copper, is deposited upon a continuous 25 layer support 40 of flexible polyimide plastic such as Kapton, forming a composite of metal on a nonmetallic support. The electrically conductive metal may be deposited in any of several ways, the two most common belng electrolytic deposition from solution and 3~ ~dhe~lve bonding of a thin sheet of metal to the substrate. The layer of conductive metal ls patterned by standard photoresist techniques to produce lndlvldual conductive traces 38 in the proper pattern to deliver current to the intended locations. The 35 electrical connectlon to the bonding locations on the substrate is provided by extending the traces in a cantilevered fashion from the edge of the plastic 2~0ZA~

support in a pattern that places them over the respect~ve bonding locations 24 when the flexible interconnect circuit 36 is assembled to the manifold 30. (See Figure 6 of US Patent 3,689,991 and the text 5 at col. 3, line 53-col. 4, line 4.) The cantilevered traces are soldered -to the bonding locations using a combination of heat and pressure, which bends the can-tilevered traces downwardly to contact the bonding locations.
In a more ad~anced form of the printhead assembly 10, a multiplexer 4~ is supported on the flexible interconnect circuit 36. Like the e~ector 12, the multiplexer 42 is within the periphery 44 of the circuit 36. The multiplexer 42 is required 15 because of an increased number of orifices 1~, which require an equal number of resistors to heat the ink and e;ect droplets.
Figure 3 illustrates the relationship between the e~ector 12, the multiplexer 42, and the traces.
20 Some traces 46 run from the periphery 44 to the multiplexer 42, and some traces 48 run from the periphery 42 to the eJector 12. (In Figures 3 and 4, only a few illustrative traces are shown for clarlty.
In an actual circuit, there may be several hundred 25 individual traces.) ~11 of these traces 46 and 48 extend to the periphery, and during the manufacturing step lllustrated in Figure 3 connect directly with a periphery bus connector 50 that runs along the edge of the clrcult 36. The traces 46 and 48 are readily 30 electroplated during manufacturing, as wlth gold, by applying the proper voltage and current to the bus connector ~0.
However, some traces 52 ("orphan traces") run from the multlplexer 42 to the e~ector 12. Durlng 35 manufacturlng, no platlng voltage and current can be applled dlrectly to the traces 52 from a connectlon at the perlphery 44 of the circuit 36, because there ls ~z~

no contlnuous curre~t path to the traces 52. The multiplexer 42 and e~ector 12 are not present during the early stages of the manufacturing operation, when plating is performed, and their structure cannot aid 5 in the plating. Thus, at the plating stage, the traces 52 are otherwise isolated from the periphery 44 and the periphery bus connector 50, and could not be plated but for the approach of the invention.
To accomplish elec-trodeposition of gold on 10 the orphan traces 52 by electroplating, internal bus connectors 54 are prov~ded, as illustrated in Figure 4. The internal bus connectors 54 extend from the periphery bus connector 50 to the orphan traces 52, so that an electrical voltage and current may be applied 15 to the ~races 52 ~rom the periphery 44 of the circuit 36.
The internal bus connectors 54 are formed during the same etching step that forms the traces 38 (more specifically, the traces 46, 48, and 52) and the 20 periphery bus connector 50. A sheet of conductive materlal is deposited upon the support 40, and patterned by a photolithography technique. In this technique, a mask materlal is applied to the conductive sheet and the appropriate portions of the 25 photoresistive mask removed to expose the portions of the conductive sheet that are to be removed. The patterning is accomplished by photolithographic procedures well established in the art. The portions to be removed are etched away to leave a pattern of 30 traces and bus connectors, as illustrated in Figure 4.
Electroplating of the traces 38 (including traces 46, 48, and 52) and bus connectors 50 and 54 is performed by connecting an electrode to the periphery bus connector 50, making the conductive parts 35 cathodic. All traces 46, 48, and 52 may be made cathodic by applying a voltage to the perlphery bus conductor 50, because ei-ther the traces (46 and 48) ~o~z contact the periphery bus conductor 50 dlrectly, or the traces (52) contact the perlphery bus conductor 50 lndirectly through the internal bus connector 54. The partlally fabricated circuit 36 is placed into an 5 electrolyte containing the ions to be electroplated, preferably gold, and deposition is contlnued as long as necessary to achleve the required thlckness. The plated circuit 3h is removed and excess electrolyte washed away.
The internal bus connectors 54 must be partially or totally removed, as their presence in the finished circuit 36 would provide an unintended current path. The internal bus connectors 54 are removed to avoid unintended cross connections between 15 the orphan traces 52, and also between the traces 52 and other components and the periphery bus connector (which is normally later removed). Preferably, the bus 54 is configured so that it is located at least partially in an area of the support 40 which is to be 20 removed in any event. For example, in the preferred embodiment of the printhead assembly 10, a central portion 56 of the support 40 is necessarily removed so that the support fits over the substrate 14 for electrical connection purposes. The lnternal bus 25 connector 54 arrangement is therefore designed to be primarily located in the central portion 56 of the support 40, so that opening of an aperture through the support 40 to receive the substrate 14 simultaneously removes a sufficient amount of the bus connector 54 to 30 avoid later short circuits when the multiplexer 42 and substrate 14 are bonded to the traces 38. The central portlon 56 is removed to form an aperture entirely through the support 40 by cutting along a line 58, preferably with a die punch. Alternatively, any 35 breaklng of the current path along the internal bus connectors 54 between each current carrler that is to remain is sufficient to avoid the presence of an x~

unwanted current path ln the finished devlce. ~emoval of most of the bus connector 54 is preferred, because precious plated me-tal can be recovered, and the chances o~ later failure due to the presence of the 5 unused metal can be reduced.
To complete the fabrlcation of the prlnthead assembly 10 device, the multiplexer 42 ls fastened with adhesive to the open area on -the support 40, and the electrical contacts on the multiplexer 42 are 10 connected to the appropriate traces 38 by thermosonic bonding, welding, TABbonding, or other well known technique. The flexible interconnect circuit 3~ is bent to the proper shape to fit over the manifold 30, as shown in Figure 2, and then attached thereto by 15 adhesive. Electrical contacts are made from the traces 38 to the bonding locations 24 with one of the same types of techniques.
The preferred use of the present invention is with ink ~et printer assemblies, but its use is not so 20 limited. In many integra-ted circuit applications, active components are mounted within the periphery of a TABclrcuit interconnect structure. Orphan traces that are to run between the components within the periphery are formed in the conductive metal, and must 25 be plated during the manufac-turing operation. The present approach of using removable internal bus connectors permits the orphan traces to be plated by contact to the periphery bus connector through internal bus connectors, which are then removed in 30 whole or in part to avoid unintended interconnec-tions ln the final part.
The present approach permits two or more components to be assembled into a device within the perlphery of a single flexible interconnect circult.
35 Special signal processing chips or components can therefore be added to the device, wlthout the need for separate packaging. The newly added components are ~oz~

located in close proximity to the other components, cutting costs and reducing the signal travel times.
The present approach does not require any new processlng steps, e~cept the final dle cuttlng in 5 those cases which dld not previously requlre a flnal die cuttlng. Such die cuttlng procedures are well known, and add little to the final costs.
Al-though particular embodiments of the invention have been descrlbed in detail for purposes 10 of illustration, various modifications may be made without departing from the spirit and scope of the invention. Accordingly, ~he invention is not to be limited except as by the appended claims.

Claims (17)

1. A method for preparing a flexible electrical connector material having conductive traces supported on a nonconductive support, at least some of the traces having no continuous connection to the periphery of the support, comprising the steps of:
providing a composite of an electrical conductor material on a nonconductive support;
removing a portion of the electrical conductor material to form a pattern of traces and plating bus connections, the bus connections providing an electrically continuous path from each trace to the periphery of the support;
electrodepositing a metallic coating over the electrical conductor material, utilizing as one electrodeposition contact the plating bus at the periphery of the support;
removing the plating bus connections at the periphery of the support; and removing those portions of the electrical bus connections extending from the periphery of the support to those traces having no continuous connection to the periphery.
2. The method of claim 1, wherein the step of removing a portion of the internal bus connectors is accomplished by punching out a portion of the nonconductive support having the bus connections thereon.
3. The method of claim 1, wherein the nonconductive support material is a polyimide.
4. The method of claim 1, wherein the electrical conductor support material is copper.
5. The method of claim 1, wherein the plated metallic coating is gold.
6. A flexible electrical connector material prepared by the method of claim 1.
7. A method for forming an electrical device having at least two components interconnected by a flexible electrical connector material having conductive traces supported on a nonconductive support, the components being disposed within the periphery of the nonconductive support, the method comprising the steps of:
providing a composite of an electrical conductor material on a nonconductive support;
removing a portion of the electrical conductor material to form a pattern of traces and plating bus connections, the bus connections providing an electrically continuous path from each trace to the periphery of the support;
electrodepositing a metallic coating over the electrical conductor material, utilizing as one electrodeposition contact the plating bus at the periphery of the support;
removing the plating bus connections at the periphery of the support;
removing those plating internal bus connections extending from the periphery of the support to those traces that interconnect the components without otherwise extending to the periphery of the electrically insulating support;
and connecting the electrical connector locations on the electrical components to the appropriate traces of the flexible electrical connector.
8. The process of claim 7, wherein at least one of the electrical components is mounted upon the flexible electrical connector.
9. The method of claim 7, wherein the step of removing those plating internal bus connections is accomplished by punching out a portion of the nonconductive support having the bus connections thereon.
10. The method of claim 7, wherein the nonconductive support material is a polyimide.
11. The method of claim 7, wherein the electrical conductor support material is copper.
12. The method of claim 7, wherein the plated metallic coating is gold.
13. The method of claim 7, wherein at least one of the components is an integrated circuit.
14. The method of claim 7, wherein at least one of the components is a thermal ink Jet printer ejector.
15. An electrical device prepared by the method of claim 7.
16. A method for forming an electrical device having at least two components interconnected by a flexible electrical connector material having conductive traces supported on a nonconductive support, the components being disposed within the periphery of the nonconductive support with at least one of the components being mounted on the nonconductive support and at least one of the components being within an aperture through the support, the method comprising the steps of:
providing a composite of an electrical conductor material on a nonconductive support;
removing a portion of the electrical conductor material to form a pattern of traces and plating bus connections, the bus connections providing an electrically continuous path from those traces that interconnect between the two components within the periphery of the support, to the periphery of the support;
electrodepositing a metallic coating over the electrical conductor material, utilizing as one electrodeposition contact the plating bus at the periphery of the support;
removing the plating bus connections at the i periphery of the support;
removing those plating internal bus connections extending from the periphery of the support to those traces that interconnect the components without otherwise extending to the periphery of the electrically insulating support;
and connecting the electrical connector locations on the electrical components to the appropriate traces of the flexible electrical connector.
17. An electrical device prepared by the method of claim 16.
CA002002402A 1988-11-21 1989-11-07 Tabcircuit electrical connector supporting multiple components thereon Abandoned CA2002402A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US274,534 1988-11-21
US07/274,534 US4989317A (en) 1988-11-21 1988-11-21 Method for making tab circuit electrical connector supporting multiple components thereon

Publications (1)

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CA2002402A1 true CA2002402A1 (en) 1990-05-21

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CA002002402A Abandoned CA2002402A1 (en) 1988-11-21 1989-11-07 Tabcircuit electrical connector supporting multiple components thereon

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US (1) US4989317A (en)
EP (1) EP0370438B1 (en)
CA (1) CA2002402A1 (en)
DE (1) DE68912530T2 (en)

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Also Published As

Publication number Publication date
DE68912530T2 (en) 1994-08-18
US4989317A (en) 1991-02-05
EP0370438A1 (en) 1990-05-30
EP0370438B1 (en) 1994-01-19
DE68912530D1 (en) 1994-03-03

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