CA2003926C - Method of processing data - Google Patents
Method of processing dataInfo
- Publication number
- CA2003926C CA2003926C CA002003926A CA2003926A CA2003926C CA 2003926 C CA2003926 C CA 2003926C CA 002003926 A CA002003926 A CA 002003926A CA 2003926 A CA2003926 A CA 2003926A CA 2003926 C CA2003926 C CA 2003926C
- Authority
- CA
- Canada
- Prior art keywords
- data
- data transfer
- designated
- memory
- main memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
Abstract
Abstract of the Disclosure In a data processing method of this invention, data having an amount of a designated total data transfer length is transferred from a data buffer in a data mover to a designated start address of a control memory at a data transfer rate of a control data transfer control unit.
Data having an amount of a designated block data transfer length is transferred from the buffer in the data mover to a designated start address of a high-speed arithmetic memory at a data transfer rate of a high-speed data transfer control unit.
Data having an amount of a designated block data transfer length is transferred from the buffer in the data mover to a designated start address of a high-speed arithmetic memory at a data transfer rate of a high-speed data transfer control unit.
Description
. 7 ~ ~
;~00:~92fi Specification Title of the Invention Method of Processing Data Background of the Invention The present invention relates to a method of controlling data transfer between a high-speed arithmetic memory used by a high-speed arithmetic processor and an input/output device.
In general, a supercomputer has a capability for performing arithmetic processing at very high speed as compared with general purpose computers. The supercomputers allow high-speed solutions of various equations which represent natural phenomena using a large amount of data to achieve various technical studies and developments in scientific and technological fields.
For example, in an aircraft manufacturer, a supercomputer is used to analyze an air whirl formed around each wing. This analysi# ha3 been conventionally performed by experiments using a wind tunnel.
In such a supercomputer for performing a large amount of scientific and t`echnological calculations, many problems are involved, and a very large amount of data are required.
A large amount of data, thereore, are stored in a secondary memory device such as a magnetic disk unit, and the data are input/output between the magnetic disk and a ~ ~ :
200392fi high-speed arithmetic memory, as needed, thus performing calculations.
More specifically, the larger a ratio of a transfer period of time between the secondary memory device and the high-speed arithmetic memory is, as compared with a transfer period of time executed between an arithmetic processor and the high-speed arithmetic memory at high speed, the larger an adverse effect to an execution performance of an entire program becomes.
Conventionally, a supercomputer of this type includes a system control unit, an input/output processor connected to the system control unit, a control processor, a control memory mainly used for these processors, a high-speed arithmetic processor, and a high-speed 15 arithmetic memory mainly used for the high-speed arithmetic ;
processor. ~ ;
In a data transfer operation between the secondary memory device and the high-speed arithmetic memory in a conventional data processing apparatus of this type, the control processor serves as a main unit, and the data contents transferred from the input~output processor to the control memory are transferred to the high-speed arithmetic memory, or the contents are directly transferred from the input/output processor to the high-speed arithmetic memory.
In this method, however, a rate of tran~fer to the high-speed arithmetic me ry is undesirably limited by ~
;.. ~ ' :, .
~ ' - -''"' a rate of transfer from the control processor or the input/output processor to the control memory.
In general, the rate of transfer from the control processor or the input/output processor to the control memory iB considerably lower than that between the high-speed arithmetic processor and the high-speed - -arithmetic memory. As a result, a ratio of an input/output period of time between the secondary memory device and the high-speed arithmetic memory is undesirably larger than a transfer period of time between the high-speed arithmetic processor and the high-speed arithmetic memory.
More specifically, in the above-mentioned conventional data processing apparatus, a transfer period of time between the secondary memory device and the high-speed arithmetic memory is undesirably longer than that between the high-speed arithmetic processor and the high-speed arithmetic memory, and an execution period of time of the entire program may also be increased, thus degrading performance of the apparatus.
SummarY of the Invention The present invention has bqen made in consideation of the above situation, and ha6 as its principal object to provide a data processing apparatus in ~, ~ : . .. .
~-~ ` which an execution period of time of an entirè program i6 `25 decreased, and performance thereof is improved.
According to the~present invention, there is provided à method of performing data proce6sing in a data ~-~
; , , 2~03926 proces~ing apparatus including a system control unit, a fir~t proce~sor group lncluding processors connected to sald system control unit, a second processor group includlng a plurallty of arithmetic processors, a flrst main memory unlt malnly used hy said first proces~or group, a second main memory unit mainly used by said second processor group, and data transfer control means :~
for enabllng data tran~fer between sald first and second maln memory units which is designated by each of said processor~
included in æaid first processor group, co~prlslng the steps of, transferrlng data havlng an amount of a designated total data - ~
transfer length between a data buffer in ~aid data transfer ~ .
control means and a deslgnated start address of said first main meDory unlt, at a first data transfer rate the ~ame as that between said flrst processor group and said fir~t main memory .~ :
unlt~ and transferrlng data havlng an amount or a designated total data transfer length between said buffer in sald data transfer control means and a de~ignated start address of ~aid ~econd main ..
memory unit, at a second data tran6fer rate the same as that . ;~.
between said second proces~or group and said second main memory unit. .
Aacording to the present invention, there is further .. ;~
provided a method of performlng data proce~ing in a data .
proces~ing apparAtus including a ~ystem control unit, a first proces~or group includlng proce~sors connected to said system control unit, a ~econd proce~sor group including a plurallty of arithmetic processors, a fir~t ~aln memory unlt malnly u~ed by ;.
sald flrst proce~sor group, a second maln memory unit mainly u~ed 4 ~
: :, B; :~:
. .
by said second processor group, and data transfer control means for enabling data transfer between said flrst and second maln memory units which is designated by each of said processors included in said first processor group, comprising the steps of, transferring data having an amount of a designated total data transfer length between a designated start address of said first main memory unit and a data buffer in said data transfer control --means, at a first data transfer rate the same as that between said first processor group and ~aid first main memory unit; and sequentlally transferrlng data having an amount o$ a designated block data transfer length between said buffer in said data transfer control mean~ and a deslgnated start address of said second main memory unit in accordance with a designated : :
interelement distance, or data having an amount of a designated total data transfer length between sald buffer ln sald data transfer control means and the deslgnated start address of sald ~econd maln memory unlt, at a second data transfer rate the ~ame as that between sald second processor group and sald second maln memory unlt.
Brlef De~crlDtlon of th~e Drawing~
Flgure 1 18 a block dlagram showlng flrst and ~econd embodlments oL thc pre~ent lnventlon1 . ....
,.
`''': '.
Bi . -.
r, ~
2{~39~6 Fig. 2 is a view showing instruction specifications instructed to a mover in the first embodiment;
; Fig. 3 is a diagram of data tran~fer from an input/output device to a high-speed arithmetic memory shown in the first and second embodiments;
Fig. 4 is a view showing a data transfer image in the first embodiment;
Fig. 5 is a view showing instruction specifications instructed to a mover in the æecond embodiment; and -Fig. 6 is a view showing a data transfer image in -the ~econd embodiment.
I Detailed Description of the Preferred Embodiments ¦ 15 Preferred embodiments of the present invention ~ will be described hereinafter with reference to the ¦ accompanying drawings.
~First Embodiment) Referring to Fig. 1, a data processing apparatus according to the present invention includes a system ¦ controller 6, input/output processors 11 and 12 for t~ controlling an input/output operation of a system connected ~- to the system controller 6, secondary memory devices 13 and 14, high-speed arithmetic processors 8 and 9 for executing a user program, in which vector calculation is ffiainly `~ performed at very high speed, a control processor 10, a control data transfer control unit 3 for controlling data ~, .. .
- 6 - :
: : .
1,`~ ~. .
20039;26 transfer between the input/output processors 11 and 12 or the control processor 10 and a control memory 1, a high-speed data transfer control unit 7 for controlling data transfer between the high-speed arithmetic processors 8 and 9 and a high-speed arithmetic memory 2, a control unit 5 for controlling data communication between the high-speed arithmetic processor side and the control processor side and data communication between the processors, and a data mover 4 for enabling data transfer between the control memory 1 and the high-speed arithmetic memory 2, which is designated by the control processor 10 or the input/output processors 11 and 12.
In addition, the data mover 4 sequentially transfers data each having a designated total data transfer length from a data buffer 4a in the data mover 4 to the designated start address of the control memory 1 at a transfer rate of the control data transfer control unit 3.
This transfer operation is controlled by the data mover 4.
The data mover 4 sequentially transfers, at high speed, 20 data having a designated total data tran~fer length from : :
the data buffer 4a in the data mover 4 to the designated start address of the high-speed arithmetic memory 2 at a data transfer rate of the high-~peed data transfer control ~.
unit 7.
An operation of this embodiment will be described ~w. ~
- 7 - .
~ ' ,.
An operation performed when data must be transferred from the secondary memory device 13 to the high-speed arithmetic memory 2 will be described hereinafter.
The high-speed arithmetic processor 8 stores in the control memory 1 a channel program which includes data required for data transfer, and signals this storage to the control processor 10 through communication between the processors. ,:
The control processor 10 which received data of this storage starts the input/output processor 11. Then, the inputtoutput processor 11 reads out the channel program from the control memory 1, and signals the start of data transfer to the secondary memory device 13. Desired data is read out from the secondary memory device 13, and is stored in the buffer in the control memory 1. ~.
After all the designated data are transferred from the secondary memory device 13 to the control memory 1, the end of the data transfer by the I/0 start is ,' ': .
signaled from the input/output processor 11 to the control processor 10.
The control processor 10 which received data :,, .
representing the ,end of the data transfer reads out the channel program stored in the control memory 1, and ' ~
; 25 produces data for starting the data mover 4. ' Fig. 2 shows contents of data for starting the ~
.data mover 4. A transfer target designates a data tranufer '~ ~ .
: 8~ :.':,.
20039;~6 direction between the control memory 1 and the high-speed arithmetic memory 2.
An output format represents that a request source for starting the data mover 4 is the control processor 10 or the input/output processors 11 and 12, and that a transfer scheme is synchronous or asynchronous.
A control memory address represents that a start address or a logical/physical address of the control memory 1 is a target for data transfer.
In this embodiment, the control memory address is defined by 8-byte boundaries.
A high-speed arithmetic memory address represents that a start address or a logical/physical address of the high-speed arithmetic memory is a target for data transfer.
In this embodiment, the high-speed arithmetic memory address is defined by 8-byte boundaries.
The total data transer length repxesents a total number of transfer data when each 8-byte transfer data is defined as one element.
In this embodiment, the control processor 10 sequentially designates the above-mentioned data shown in Fig. 2 to the data mover 4. Finally, the data mover 4 is started.
In this embodiment, the started data mover 4 ; 2S read8 out data from the start address of the control in the large-capacity buffer 4a in the data mover 4 memory l in accordance with the data uhown in Fig. 2. -. - ~ .,:, In this embodiment, the total data tran6fer length does not exceed the capacity of the large-capacity buffer 4a. If the total data transfer length exceeds the capacity of the buffer 4a, the data mover 4 divides the total data transfer length into some data to control data transfer of the control memory 1 and the high-speed arit~metic memory 2.
Data transfer from the control memory 1 to the large-capacity buffer 4a in the data mover 4 is performed at a data transfer rate of the control data transfer control unit 3.
Then, data transfer is executed from the large-capacity data buffer 4a in the data mover 4 to the high-speed arithmetic memory 2 under the control of thè -data mover 4. At this time, the transfer operation is controlled in accordance with the data shown in Fig. 2 such as the high-speed arithmetic memory address and the total data transfer length.
In this embodiment, data transfer from the large-capacity buffer 4a in the data mover 4 to the high-speed arithmetic memory 2 is executed at a transfer rate of the high-speed data tran~fer control unit 4. If a well-balanced ratio can be achieved from a point of view as , .:
a system, this transfer rate may be l/n (n is an integer) the data transfer raté between the high-speed arithmetic processor 8 and the high-speed arithmetic memory 2.
..
. .
- 1 0 - : ' :' ' ' ~ ~ , '' . .
2~03g26 When the data mover 4 completes transfer of all the data according to the above-mentioned procedures, the data representing the end of transfer is supplied from the data mover 4 to the control processor 10 serving as the request source, and the data representing the end of transfer is supplied from the control processor 10 to the high-speed arithmetic processor 8 through communication between the processors. Therefore, the data transfer from the secondary memory device to the high-speed data memory is completed.
Although the high-speed arithmetic processor 8 and the secondary memory device 13 are used in this embodiment, another high-speed arithmetic processor and another secondary memory device can be similarly used.
Fig. 3 shows a transfer operation from the input/output device to the high-speed arithmetic memory in the first embodiment of the pre~ent invention.
Fig. 4 shows a data transfer image.
(Second Embodiment) , , .
2Q A second embodiment will be described below with reference to Fig. 1, in the same manner as in the first . .
; embodiment.
i~ . , : .
` In the second embodiment, the data mover 4 ,; ~ . .
equentially transfers data each having a designated total 25~ ata transfer length ~rom a data buffer 4a in the data .~.~ .. ~ . .
mover 4~to the designated~start address of the control ~memory 1 at a transfer~rate of~the control data transfer 200;:'~9;~6 control unit 3. This transfer operation is controlled by the data mover 4. The data mover 4 sequentially transfers, at high speed, data having a designated block data transfer length from the data buffer 4a in the data mover 4 to the designated start address of the high-speed arithmetic memory 2 at a data transfer rate of the high-speed data transfer control unit 7, in accordance with a designated interelement distance.
Note that when the interelement distance is "0l-, data each having a designated total data transfer length are sequentially transferred in the same manner as in the first embodiment.
An operation of this embodiment i8 the same as that in the first embodiment.
Fig. 5 shows contents of data for ætarting the data mover 4. A transfer target designates a data transfer direction between the aontrol memory 1 and the high-speed arithmetic memory 2.
An output format represents that a request source for starting the data mover 4 is the control processor 10 or the input/output proces80rs 11 and 12, and that a transfer s~heme is synchronous or asynchronous.
A control memory address represents that a start address or a logical/physical address of the control memory 1 is a target for data transfer.
In this embodimént, the control memory address is defined by 4-byte boundaries.
.
- 12 - ~
:: . ..
200;~9~
A high-speed arithmetic memory addre~s represents that a start address or a logical/physical address of the high-speed arithmetic memory is a target for data transfer.
In this embodiment, the high-speed arithmetic memory address is defined as 4-byteiboundaries.
The total data transfer length represents a total number of-transfer data when each 4-byte transfer data is defined as one element.
The interelement distance designatès the distance between the block data in units of bytes.
The block data transfer length represents the length of data processed as block data by the number of elements obtained when 4-byte data i8 defined as one element in this embodiment.
15In this embodiment, the control processor 10 sequentially designates the above-mentioned data shown in Fig. 5 to the data mover 4, in the same manner as in the first embodiment. Finally, the data mover 4 is started.
In this embodiment, the started data mover 4 reads out data from the start addres~ of the control memory 1 in the large-capacity buf$er 4a in the data mover 4 in accordance with the data 8hown in Fig. 5.
- In this embodiment, the total data transfex length does not exceed the capacity of the large-capacity buffer 4a. If the total data transfer length exceeds the ; capacity of the buffer 4a, the data mover 4 divides the ` ~ total data transfer length into some data to control data . .
~ ~ - 13~-,. . .. .
20039Z~i transfer between the control memory 1 and the high-speed arithmetic memory 2.
Data transfer from the control memory 1 to the large-capacity buffer 4a in the data mover 4 is performed at a data transfer rate of the control data transfer control unit 3. -Then, data transfer is executed from the large-capacity data buffer 4a in the data mover 4 to the high-speed arithmetic memory 2 under the control of the data mover 4, as shown in Fig. 6. At this time, the transfer operation i8 controlled in accordance with the data shown in Fig. 5 such as the high-speed arithmetic memory address, the total data transfer length, the interelement distance, and the block data transfer length.
As described above, in this invention, data transfer between the control memory and the high-speed arithmetic memory designated by the control processor to the data mover is performed as follows. Data having a designated amount i~ transferred from the large-capacity buffer in the data mover to the designated start address of the control memory at a data transfer rate of the control memory and the control processor. In addition, the data having a designated transfer amount i~ transferred, at high speed, from the buffer in the data mover to the designated 8tart address of the high-speed arithmetic memory at a data ~. . . .
transfer rate between the high-speed arithmetic memory and the high-speed arithmetic processor. Therefore, a ratio of .
: -. .
. ~
ZOO~9~i a transfer period of time between the secondary memorydevice and the high-speed arithmetic memory to that of a transfer period of time between the high-speed arithmetic processor and the high-speed arithmetic memory can be decreased, and an execution period of time of the entire program can be decreased, thus effectively improving the performance.
In addition, according to the present invention, data each having a designated block data transfer length are sequentially transferred from the buffer in the data mover to the designated start address of the high-speed arithmetic memory in accordance with the designated interelement distance. Furthermore, data each having a designated total data length are sequentially transferred, at high speed, from the buffer in the data mover to the designated start address of the high-speed arithmetic memory at a data transfer rate between the high-speed arithmetic memory and the high-speed arithmetic processor.
Therefore, a ratio of a transfer period of time between the secondary memory device and the high-speed arithmetic memory to that of a transfer period of time between the arithmetic processor and the high-speed arithmetic memory can be decreased, and the execution period of time of the entire program can be decreased, thus effectively improving the Ferformance. Moreover, data can be optimally developed from the secondary memory~device so that a high-speed arithmetia operation can be directly performed in the ::
,'~; -,'' .~
- 15 - - :
:- ..
- Z00~9~:6 -.
high-speed arithmetic memory, and the execution period of time for the program can be effectively reduced. .
,:
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;~00:~92fi Specification Title of the Invention Method of Processing Data Background of the Invention The present invention relates to a method of controlling data transfer between a high-speed arithmetic memory used by a high-speed arithmetic processor and an input/output device.
In general, a supercomputer has a capability for performing arithmetic processing at very high speed as compared with general purpose computers. The supercomputers allow high-speed solutions of various equations which represent natural phenomena using a large amount of data to achieve various technical studies and developments in scientific and technological fields.
For example, in an aircraft manufacturer, a supercomputer is used to analyze an air whirl formed around each wing. This analysi# ha3 been conventionally performed by experiments using a wind tunnel.
In such a supercomputer for performing a large amount of scientific and t`echnological calculations, many problems are involved, and a very large amount of data are required.
A large amount of data, thereore, are stored in a secondary memory device such as a magnetic disk unit, and the data are input/output between the magnetic disk and a ~ ~ :
200392fi high-speed arithmetic memory, as needed, thus performing calculations.
More specifically, the larger a ratio of a transfer period of time between the secondary memory device and the high-speed arithmetic memory is, as compared with a transfer period of time executed between an arithmetic processor and the high-speed arithmetic memory at high speed, the larger an adverse effect to an execution performance of an entire program becomes.
Conventionally, a supercomputer of this type includes a system control unit, an input/output processor connected to the system control unit, a control processor, a control memory mainly used for these processors, a high-speed arithmetic processor, and a high-speed 15 arithmetic memory mainly used for the high-speed arithmetic ;
processor. ~ ;
In a data transfer operation between the secondary memory device and the high-speed arithmetic memory in a conventional data processing apparatus of this type, the control processor serves as a main unit, and the data contents transferred from the input~output processor to the control memory are transferred to the high-speed arithmetic memory, or the contents are directly transferred from the input/output processor to the high-speed arithmetic memory.
In this method, however, a rate of tran~fer to the high-speed arithmetic me ry is undesirably limited by ~
;.. ~ ' :, .
~ ' - -''"' a rate of transfer from the control processor or the input/output processor to the control memory.
In general, the rate of transfer from the control processor or the input/output processor to the control memory iB considerably lower than that between the high-speed arithmetic processor and the high-speed - -arithmetic memory. As a result, a ratio of an input/output period of time between the secondary memory device and the high-speed arithmetic memory is undesirably larger than a transfer period of time between the high-speed arithmetic processor and the high-speed arithmetic memory.
More specifically, in the above-mentioned conventional data processing apparatus, a transfer period of time between the secondary memory device and the high-speed arithmetic memory is undesirably longer than that between the high-speed arithmetic processor and the high-speed arithmetic memory, and an execution period of time of the entire program may also be increased, thus degrading performance of the apparatus.
SummarY of the Invention The present invention has bqen made in consideation of the above situation, and ha6 as its principal object to provide a data processing apparatus in ~, ~ : . .. .
~-~ ` which an execution period of time of an entirè program i6 `25 decreased, and performance thereof is improved.
According to the~present invention, there is provided à method of performing data proce6sing in a data ~-~
; , , 2~03926 proces~ing apparatus including a system control unit, a fir~t proce~sor group lncluding processors connected to sald system control unit, a second processor group includlng a plurallty of arithmetic processors, a flrst main memory unlt malnly used hy said first proces~or group, a second main memory unit mainly used by said second processor group, and data transfer control means :~
for enabllng data tran~fer between sald first and second maln memory units which is designated by each of said processor~
included in æaid first processor group, co~prlslng the steps of, transferrlng data havlng an amount of a designated total data - ~
transfer length between a data buffer in ~aid data transfer ~ .
control means and a deslgnated start address of said first main meDory unlt, at a first data transfer rate the ~ame as that between said flrst processor group and said fir~t main memory .~ :
unlt~ and transferrlng data havlng an amount or a designated total data transfer length between said buffer in sald data transfer control means and a de~ignated start address of ~aid ~econd main ..
memory unit, at a second data tran6fer rate the same as that . ;~.
between said second proces~or group and said second main memory unit. .
Aacording to the present invention, there is further .. ;~
provided a method of performlng data proce~ing in a data .
proces~ing apparAtus including a ~ystem control unit, a first proces~or group includlng proce~sors connected to said system control unit, a ~econd proce~sor group including a plurallty of arithmetic processors, a fir~t ~aln memory unlt malnly u~ed by ;.
sald flrst proce~sor group, a second maln memory unit mainly u~ed 4 ~
: :, B; :~:
. .
by said second processor group, and data transfer control means for enabling data transfer between said flrst and second maln memory units which is designated by each of said processors included in said first processor group, comprising the steps of, transferring data having an amount of a designated total data transfer length between a designated start address of said first main memory unit and a data buffer in said data transfer control --means, at a first data transfer rate the same as that between said first processor group and ~aid first main memory unit; and sequentlally transferrlng data having an amount o$ a designated block data transfer length between said buffer in said data transfer control mean~ and a deslgnated start address of said second main memory unit in accordance with a designated : :
interelement distance, or data having an amount of a designated total data transfer length between sald buffer ln sald data transfer control means and the deslgnated start address of sald ~econd maln memory unlt, at a second data transfer rate the ~ame as that between sald second processor group and sald second maln memory unlt.
Brlef De~crlDtlon of th~e Drawing~
Flgure 1 18 a block dlagram showlng flrst and ~econd embodlments oL thc pre~ent lnventlon1 . ....
,.
`''': '.
Bi . -.
r, ~
2{~39~6 Fig. 2 is a view showing instruction specifications instructed to a mover in the first embodiment;
; Fig. 3 is a diagram of data tran~fer from an input/output device to a high-speed arithmetic memory shown in the first and second embodiments;
Fig. 4 is a view showing a data transfer image in the first embodiment;
Fig. 5 is a view showing instruction specifications instructed to a mover in the æecond embodiment; and -Fig. 6 is a view showing a data transfer image in -the ~econd embodiment.
I Detailed Description of the Preferred Embodiments ¦ 15 Preferred embodiments of the present invention ~ will be described hereinafter with reference to the ¦ accompanying drawings.
~First Embodiment) Referring to Fig. 1, a data processing apparatus according to the present invention includes a system ¦ controller 6, input/output processors 11 and 12 for t~ controlling an input/output operation of a system connected ~- to the system controller 6, secondary memory devices 13 and 14, high-speed arithmetic processors 8 and 9 for executing a user program, in which vector calculation is ffiainly `~ performed at very high speed, a control processor 10, a control data transfer control unit 3 for controlling data ~, .. .
- 6 - :
: : .
1,`~ ~. .
20039;26 transfer between the input/output processors 11 and 12 or the control processor 10 and a control memory 1, a high-speed data transfer control unit 7 for controlling data transfer between the high-speed arithmetic processors 8 and 9 and a high-speed arithmetic memory 2, a control unit 5 for controlling data communication between the high-speed arithmetic processor side and the control processor side and data communication between the processors, and a data mover 4 for enabling data transfer between the control memory 1 and the high-speed arithmetic memory 2, which is designated by the control processor 10 or the input/output processors 11 and 12.
In addition, the data mover 4 sequentially transfers data each having a designated total data transfer length from a data buffer 4a in the data mover 4 to the designated start address of the control memory 1 at a transfer rate of the control data transfer control unit 3.
This transfer operation is controlled by the data mover 4.
The data mover 4 sequentially transfers, at high speed, 20 data having a designated total data tran~fer length from : :
the data buffer 4a in the data mover 4 to the designated start address of the high-speed arithmetic memory 2 at a data transfer rate of the high-~peed data transfer control ~.
unit 7.
An operation of this embodiment will be described ~w. ~
- 7 - .
~ ' ,.
An operation performed when data must be transferred from the secondary memory device 13 to the high-speed arithmetic memory 2 will be described hereinafter.
The high-speed arithmetic processor 8 stores in the control memory 1 a channel program which includes data required for data transfer, and signals this storage to the control processor 10 through communication between the processors. ,:
The control processor 10 which received data of this storage starts the input/output processor 11. Then, the inputtoutput processor 11 reads out the channel program from the control memory 1, and signals the start of data transfer to the secondary memory device 13. Desired data is read out from the secondary memory device 13, and is stored in the buffer in the control memory 1. ~.
After all the designated data are transferred from the secondary memory device 13 to the control memory 1, the end of the data transfer by the I/0 start is ,' ': .
signaled from the input/output processor 11 to the control processor 10.
The control processor 10 which received data :,, .
representing the ,end of the data transfer reads out the channel program stored in the control memory 1, and ' ~
; 25 produces data for starting the data mover 4. ' Fig. 2 shows contents of data for starting the ~
.data mover 4. A transfer target designates a data tranufer '~ ~ .
: 8~ :.':,.
20039;~6 direction between the control memory 1 and the high-speed arithmetic memory 2.
An output format represents that a request source for starting the data mover 4 is the control processor 10 or the input/output processors 11 and 12, and that a transfer scheme is synchronous or asynchronous.
A control memory address represents that a start address or a logical/physical address of the control memory 1 is a target for data transfer.
In this embodiment, the control memory address is defined by 8-byte boundaries.
A high-speed arithmetic memory address represents that a start address or a logical/physical address of the high-speed arithmetic memory is a target for data transfer.
In this embodiment, the high-speed arithmetic memory address is defined by 8-byte boundaries.
The total data transer length repxesents a total number of transfer data when each 8-byte transfer data is defined as one element.
In this embodiment, the control processor 10 sequentially designates the above-mentioned data shown in Fig. 2 to the data mover 4. Finally, the data mover 4 is started.
In this embodiment, the started data mover 4 ; 2S read8 out data from the start address of the control in the large-capacity buffer 4a in the data mover 4 memory l in accordance with the data uhown in Fig. 2. -. - ~ .,:, In this embodiment, the total data tran6fer length does not exceed the capacity of the large-capacity buffer 4a. If the total data transfer length exceeds the capacity of the buffer 4a, the data mover 4 divides the total data transfer length into some data to control data transfer of the control memory 1 and the high-speed arit~metic memory 2.
Data transfer from the control memory 1 to the large-capacity buffer 4a in the data mover 4 is performed at a data transfer rate of the control data transfer control unit 3.
Then, data transfer is executed from the large-capacity data buffer 4a in the data mover 4 to the high-speed arithmetic memory 2 under the control of thè -data mover 4. At this time, the transfer operation is controlled in accordance with the data shown in Fig. 2 such as the high-speed arithmetic memory address and the total data transfer length.
In this embodiment, data transfer from the large-capacity buffer 4a in the data mover 4 to the high-speed arithmetic memory 2 is executed at a transfer rate of the high-speed data tran~fer control unit 4. If a well-balanced ratio can be achieved from a point of view as , .:
a system, this transfer rate may be l/n (n is an integer) the data transfer raté between the high-speed arithmetic processor 8 and the high-speed arithmetic memory 2.
..
. .
- 1 0 - : ' :' ' ' ~ ~ , '' . .
2~03g26 When the data mover 4 completes transfer of all the data according to the above-mentioned procedures, the data representing the end of transfer is supplied from the data mover 4 to the control processor 10 serving as the request source, and the data representing the end of transfer is supplied from the control processor 10 to the high-speed arithmetic processor 8 through communication between the processors. Therefore, the data transfer from the secondary memory device to the high-speed data memory is completed.
Although the high-speed arithmetic processor 8 and the secondary memory device 13 are used in this embodiment, another high-speed arithmetic processor and another secondary memory device can be similarly used.
Fig. 3 shows a transfer operation from the input/output device to the high-speed arithmetic memory in the first embodiment of the pre~ent invention.
Fig. 4 shows a data transfer image.
(Second Embodiment) , , .
2Q A second embodiment will be described below with reference to Fig. 1, in the same manner as in the first . .
; embodiment.
i~ . , : .
` In the second embodiment, the data mover 4 ,; ~ . .
equentially transfers data each having a designated total 25~ ata transfer length ~rom a data buffer 4a in the data .~.~ .. ~ . .
mover 4~to the designated~start address of the control ~memory 1 at a transfer~rate of~the control data transfer 200;:'~9;~6 control unit 3. This transfer operation is controlled by the data mover 4. The data mover 4 sequentially transfers, at high speed, data having a designated block data transfer length from the data buffer 4a in the data mover 4 to the designated start address of the high-speed arithmetic memory 2 at a data transfer rate of the high-speed data transfer control unit 7, in accordance with a designated interelement distance.
Note that when the interelement distance is "0l-, data each having a designated total data transfer length are sequentially transferred in the same manner as in the first embodiment.
An operation of this embodiment i8 the same as that in the first embodiment.
Fig. 5 shows contents of data for ætarting the data mover 4. A transfer target designates a data transfer direction between the aontrol memory 1 and the high-speed arithmetic memory 2.
An output format represents that a request source for starting the data mover 4 is the control processor 10 or the input/output proces80rs 11 and 12, and that a transfer s~heme is synchronous or asynchronous.
A control memory address represents that a start address or a logical/physical address of the control memory 1 is a target for data transfer.
In this embodimént, the control memory address is defined by 4-byte boundaries.
.
- 12 - ~
:: . ..
200;~9~
A high-speed arithmetic memory addre~s represents that a start address or a logical/physical address of the high-speed arithmetic memory is a target for data transfer.
In this embodiment, the high-speed arithmetic memory address is defined as 4-byteiboundaries.
The total data transfer length represents a total number of-transfer data when each 4-byte transfer data is defined as one element.
The interelement distance designatès the distance between the block data in units of bytes.
The block data transfer length represents the length of data processed as block data by the number of elements obtained when 4-byte data i8 defined as one element in this embodiment.
15In this embodiment, the control processor 10 sequentially designates the above-mentioned data shown in Fig. 5 to the data mover 4, in the same manner as in the first embodiment. Finally, the data mover 4 is started.
In this embodiment, the started data mover 4 reads out data from the start addres~ of the control memory 1 in the large-capacity buf$er 4a in the data mover 4 in accordance with the data 8hown in Fig. 5.
- In this embodiment, the total data transfex length does not exceed the capacity of the large-capacity buffer 4a. If the total data transfer length exceeds the ; capacity of the buffer 4a, the data mover 4 divides the ` ~ total data transfer length into some data to control data . .
~ ~ - 13~-,. . .. .
20039Z~i transfer between the control memory 1 and the high-speed arithmetic memory 2.
Data transfer from the control memory 1 to the large-capacity buffer 4a in the data mover 4 is performed at a data transfer rate of the control data transfer control unit 3. -Then, data transfer is executed from the large-capacity data buffer 4a in the data mover 4 to the high-speed arithmetic memory 2 under the control of the data mover 4, as shown in Fig. 6. At this time, the transfer operation i8 controlled in accordance with the data shown in Fig. 5 such as the high-speed arithmetic memory address, the total data transfer length, the interelement distance, and the block data transfer length.
As described above, in this invention, data transfer between the control memory and the high-speed arithmetic memory designated by the control processor to the data mover is performed as follows. Data having a designated amount i~ transferred from the large-capacity buffer in the data mover to the designated start address of the control memory at a data transfer rate of the control memory and the control processor. In addition, the data having a designated transfer amount i~ transferred, at high speed, from the buffer in the data mover to the designated 8tart address of the high-speed arithmetic memory at a data ~. . . .
transfer rate between the high-speed arithmetic memory and the high-speed arithmetic processor. Therefore, a ratio of .
: -. .
. ~
ZOO~9~i a transfer period of time between the secondary memorydevice and the high-speed arithmetic memory to that of a transfer period of time between the high-speed arithmetic processor and the high-speed arithmetic memory can be decreased, and an execution period of time of the entire program can be decreased, thus effectively improving the performance.
In addition, according to the present invention, data each having a designated block data transfer length are sequentially transferred from the buffer in the data mover to the designated start address of the high-speed arithmetic memory in accordance with the designated interelement distance. Furthermore, data each having a designated total data length are sequentially transferred, at high speed, from the buffer in the data mover to the designated start address of the high-speed arithmetic memory at a data transfer rate between the high-speed arithmetic memory and the high-speed arithmetic processor.
Therefore, a ratio of a transfer period of time between the secondary memory device and the high-speed arithmetic memory to that of a transfer period of time between the arithmetic processor and the high-speed arithmetic memory can be decreased, and the execution period of time of the entire program can be decreased, thus effectively improving the Ferformance. Moreover, data can be optimally developed from the secondary memory~device so that a high-speed arithmetia operation can be directly performed in the ::
,'~; -,'' .~
- 15 - - :
:- ..
- Z00~9~:6 -.
high-speed arithmetic memory, and the execution period of time for the program can be effectively reduced. .
,:
~ . .
. ........................................................................ .
~ 25 .~:c~
;s.
, ~ , ~ 16 ~
Claims (2)
1. A method of performing data processing in a data processing apparatus including a system control unit, a first processor group including processors connected to said system control unit, a second processor group including a plurality of arithmetic processors, a first main memory unit mainly used by said first processor group, a second main memory unit mainly used by said second processor group, and data transfer control means for enabling data transfer between said first and second main memory units which is designated by each of said processors included in said first processor group, comprising the steps of:
transferring data having an amount of a designated total data transfer length between a data buffer in said data transfer control means and a designated start address of said first main memory unit, at a first data transfer rate the same as that between said first processor group and said first main memory unit; and transferring data having an amount of a designated total data transfer length between said buffer in said data transfer control means and a designated start address of said second main memory unit, at a second data transfer rate the same as that between said second processor group and said second main memory unit.
transferring data having an amount of a designated total data transfer length between a data buffer in said data transfer control means and a designated start address of said first main memory unit, at a first data transfer rate the same as that between said first processor group and said first main memory unit; and transferring data having an amount of a designated total data transfer length between said buffer in said data transfer control means and a designated start address of said second main memory unit, at a second data transfer rate the same as that between said second processor group and said second main memory unit.
2. A method of performing data processing in a data processing apparatus including a system control unit, a first processor group including processors connected to said system control unit, a second processor group including a plurality of arithmetic processors, a first main memory unit mainly used by said first processor group, a second main memory unit mainly used by said second processor group, and data transfer control means for enabling data transfer between said first and second main memory units which is designated by each of said processors included in said first processor group, comprising the steps of:
transferring data having an amount of a designated total data transfer length between a designated start address of said first main memory unit and a data buffer in said data transfer control means, at a first data transfer rate the same as that between said first processor group and said first main memory unit; and sequentially transferring data having an amount of a designated block data transfer length between said buffer in said data transfer control means and a designated start address of said second main memory unit in accordance with a designated interelement distance, or data having an amount of a designated total data transfer length between said buffer in said data transfer control means and the designated start address of said second main memory unit, at a second data transfer rate the same as that between said second processor group and said second main memory unit.
transferring data having an amount of a designated total data transfer length between a designated start address of said first main memory unit and a data buffer in said data transfer control means, at a first data transfer rate the same as that between said first processor group and said first main memory unit; and sequentially transferring data having an amount of a designated block data transfer length between said buffer in said data transfer control means and a designated start address of said second main memory unit in accordance with a designated interelement distance, or data having an amount of a designated total data transfer length between said buffer in said data transfer control means and the designated start address of said second main memory unit, at a second data transfer rate the same as that between said second processor group and said second main memory unit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63299423A JPH07122868B2 (en) | 1988-11-29 | 1988-11-29 | Information processing equipment |
| JP299423/88 | 1988-11-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2003926A1 CA2003926A1 (en) | 1990-05-29 |
| CA2003926C true CA2003926C (en) | 1994-03-22 |
Family
ID=17872375
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002003926A Expired - Fee Related CA2003926C (en) | 1988-11-29 | 1989-11-27 | Method of processing data |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5301351A (en) |
| EP (1) | EP0375959B1 (en) |
| JP (1) | JPH07122868B2 (en) |
| AU (1) | AU622240B2 (en) |
| CA (1) | CA2003926C (en) |
| DE (1) | DE68928602T2 (en) |
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- 1989-11-27 CA CA002003926A patent/CA2003926C/en not_active Expired - Fee Related
- 1989-11-28 EP EP89121900A patent/EP0375959B1/en not_active Expired - Lifetime
- 1989-11-28 DE DE68928602T patent/DE68928602T2/en not_active Expired - Fee Related
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1993
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Also Published As
| Publication number | Publication date |
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| CA2003926A1 (en) | 1990-05-29 |
| DE68928602D1 (en) | 1998-04-16 |
| JPH02146665A (en) | 1990-06-05 |
| AU4534189A (en) | 1990-06-07 |
| JPH07122868B2 (en) | 1995-12-25 |
| US5301351A (en) | 1994-04-05 |
| EP0375959A3 (en) | 1992-02-26 |
| AU622240B2 (en) | 1992-04-02 |
| EP0375959B1 (en) | 1998-03-11 |
| EP0375959A2 (en) | 1990-07-04 |
| DE68928602T2 (en) | 1998-10-15 |
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