CA2008902A1 - Reconfigurable signal processor - Google Patents

Reconfigurable signal processor

Info

Publication number
CA2008902A1
CA2008902A1 CA2008902A CA2008902A CA2008902A1 CA 2008902 A1 CA2008902 A1 CA 2008902A1 CA 2008902 A CA2008902 A CA 2008902A CA 2008902 A CA2008902 A CA 2008902A CA 2008902 A1 CA2008902 A1 CA 2008902A1
Authority
CA
Canada
Prior art keywords
pes
neighbors
ports
tree
lattice
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2008902A
Other languages
French (fr)
Other versions
CA2008902C (en
Inventor
Allen Louis Gorin
Patrick Anthony Makofsky
Nancy Morton
Neal Conrad Oliver
Richard Robert Shively
Christopher Anthony Stanziola
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Publication of CA2008902A1 publication Critical patent/CA2008902A1/en
Application granted granted Critical
Publication of CA2008902C publication Critical patent/CA2008902C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
    • G06F11/2007—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication media
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • G06F15/17343—Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
    • G06F11/2005—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication controllers

Abstract

RECONFIGURABLE SIGNAL PROCESSOR
Abstract An interconnection scheme among the processing elements ("PEs") of a multiprocessor computing architecture realizes, through PE reconfiguration, bothfault tolerance and a wide variety of different processing topologies including binary trees and linear systolic arrays. By using a novel variant on a tree expansion scheme, the invention also allows for arbitrary up-sizing of the PE count to build virtually any size of tree network, with each size exhibiting the same high degree of fault tolerance and reconfigurability.
The invention may be practiced with 4-port PEs arrayed in a module comprising a 4X4 board-mounted PE lattice. Each PE has four physical ports, which connect to the similar ports of its lattice neighbors. Each PE has an internal capability to be configured to route signals to or from ally of its neighbors. Thus, for tree topologies, any of the four neighbors of a given PE may be selected as the parent of the given PE; and any or all of the remaining three neighboring PEs may be selected as the child(ren) PEs.
The PE ports are configured under the control of a remote Host, which establishes an initial desired PE topology. The operability of the PEs is tested, and information on faulty PEs or communications paths is used to enable or disable nodes as necessary by revising the PE port configurations. The nodes thus are reorganized and can run or continue running, on a degraded basis.
CA002008902A 1989-03-31 1990-01-30 Reconfigurable signal processor Expired - Fee Related CA2008902C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/331,411 US5020059A (en) 1989-03-31 1989-03-31 Reconfigurable signal processor
US331,411 1989-03-31

Publications (2)

Publication Number Publication Date
CA2008902A1 true CA2008902A1 (en) 1990-09-30
CA2008902C CA2008902C (en) 1994-05-31

Family

ID=23293844

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002008902A Expired - Fee Related CA2008902C (en) 1989-03-31 1990-01-30 Reconfigurable signal processor

Country Status (4)

Country Link
US (1) US5020059A (en)
JP (1) JP2647227B2 (en)
CA (1) CA2008902C (en)
GB (4) GB2231985B (en)

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Also Published As

Publication number Publication date
GB9301714D0 (en) 1993-03-17
GB2262174A (en) 1993-06-09
JP2647227B2 (en) 1997-08-27
CA2008902C (en) 1994-05-31
GB2231985B (en) 1993-12-15
GB9006712D0 (en) 1990-05-23
GB2262175A (en) 1993-06-09
GB2231985A (en) 1990-11-28
GB9301712D0 (en) 1993-03-17
US5020059A (en) 1991-05-28
GB2262173B (en) 1993-12-15
GB9301713D0 (en) 1993-03-17
GB2262173A (en) 1993-06-09
JPH02287668A (en) 1990-11-27

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